A preparation method of a GaN HEMT device and a GaN HEMT device

Abstract

The present application provides a method for manufacturing a GaN HEMT device and a GaN HEMT device. The manufacturing method includes the following steps: forming a substrate of a second-doped-type SIC material; forming a first-doped-type SIC epitaxial wafer grown separately along the C axis; forming a first-doped-type electric field termination layer on the front surface of the SIC epitaxial wafer; wherein, the doping concentration of the electric field termination layer is greater than that of the substrate; forming a release layer at a position below the electric field termination layer in the SIC epitaxial wafer; wherein, the portion of the SIC epitaxial wafer located between the electric field termination layer and the release layer serves as an electric field bearing layer; bonding the front surface of the electric field termination layer and the front surface of the substrate together; performing peeling at the release layer; the substrate is above the electric field termination layer, and the electric field bearing layer is above the electric field termination layer. The present application solves the technical problem caused by the high cost of traditional GaN HEMT devices.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and specifically, to a method for manufacturing a GaN HEMT device and a GaN HEMT device. Background Art

[0002] Gallium nitride high electron mobility transistor (GaN HEMT) devices are emerging semiconductor devices that have been widely used in many fields due to their excellent performance. Compared with traditional silicon-based devices, GaN HEMTs have higher switching speeds and higher breakdown voltages, making them perform excellently in high-frequency, high-power, and high-temperature environments.

[0003] In recent years, the technology of GaN HEMT devices has developed rapidly. Many semiconductor companies and research institutions have increased their research and production investments in GaN materials. Compared with early technologies, current GaN HEMT devices have made significant progress in terms of cost, stability, and production processes. With the maturity of manufacturing processes, the market applications of GaN HEMT devices have become more and more extensive, and the prices have gradually decreased, promoting their popularization in various fields.

[0004] ‌GaN on SiC HEMT devices: Specifically refer to GaN HEMT devices fabricated on a silicon carbide (SiC) substrate. GaN on SiC HEMT devices usually have a high-resistance SiC substrate, and above the high-resistance SiC substrate is the epitaxial structure of the GaN HEMT device.

[0005] Figure 1 It is a schematic diagram of an existing GaN on SiC HEMT device. Figure 1 From the literature "A Review of GaN on SiC High Electron-Mobility Power Transistors and MMICs". As Figure 1 shown, Substrate Via (i.e., substrate via 1-1) is opened from the back of the device to the front to achieve grounding.

[0006] While the existing GaN on SiC HEMT is developing, it also faces the problem of the high price of the silicon carbide substrate. Epitaxially growing gallium nitride material on a silicon carbide substrate has a lower defect density and higher crystal quality than epitaxially growing gallium nitride material on a silicon or sapphire substrate. Therefore, high-performance GaN HEMT devices commonly use SiC material as the substrate. The existing SiC substrate technology for manufacturing GaN HEMT devices in the industry is generally a high-resistance SiC substrate grown along the C-axis. The GaN epitaxial layer grown on the high-resistance SiC substrate grown along the C-axis has lower defects and dislocations, and the material quality is good.

[0007] The substrates commonly used in large-scale power devices are single-crystal SIC substrates, D-level wafers (test wafer level) or polycrystalline SIC substrates with a lower price and a low resistance that deviates from the C-axis by 4 degrees. However, the price of the high-resistance SiC substrate grown along the C-axis is much higher than that of the substrate grown with a low resistance deviating from the C-axis by 4 degrees. This results in the substrate cost accounting for the main part of the complete cost of the GaN HEMT device. At the same time, since GaN HEMT devices often undergo back thinning and back metallization, the several-hundred-micron-thick high-resistance SiC substrate grown along the C-axis used as the substrate will be thinned to a thickness of several tens to several microns, and the excess SIC substrate will be removed by CMP technology and not utilized, causing waste of expensive substrate materials.

[0008] Therefore, the high cost of traditional GaN HEMT devices limits their application scenarios, which is a technical problem that needs to be urgently solved by those skilled in the art.

[0009] The above information disclosed in the background art is only used to strengthen the understanding of the background of the present application. Therefore, it may contain information on prior art that is not known to those of ordinary skill in the art. Summary of the Invention

[0010] The present application provides a method for manufacturing a GaN HEMT device and a GaN HEMT device to solve the technical problem that the high cost of traditional GaN HEMT devices limits their application scenarios.

[0011] The present application provides a method for manufacturing a GaN HEMT device, including the following steps:

[0012] Form a substrate of a second-doped-type SIC material;

[0013] Form a separate first-doped-type SIC epitaxial wafer grown along the C-axis;

[0014] Form a first-doped-type electric field termination layer on the front surface of the SIC epitaxial wafer; wherein, the doping concentration of the electric field termination layer is greater than that of the substrate.

[0015] A release layer is formed at a position below the electric field termination layer in the SIC epitaxial wafer; wherein, a portion of the SIC epitaxial wafer between the electric field termination layer and the release layer serves as an electric field pressure-bearing layer;

[0016] Bond the front side of the electric field termination layer and the front side of the substrate together;

[0017] Perform peeling at the release layer; wherein, the electric field termination layer is above the substrate, and the electric field pressure-bearing layer is above the electric field termination layer;

[0018] Wherein, an epitaxial structure of a GaN HEMT device is above the electric field pressure-bearing layer.

[0019] This application also provides a GaN HEMT device, including:

[0020] A substrate of SIC material of the second doping type;

[0021] An electric field termination layer of SIC grown along the C-axis of the first doping type, formed above the substrate;

[0022] An electric field pressure-bearing layer of SIC grown along the C-axis of the first doping type, formed above the electric field termination layer 11.

[0023] Due to the adoption of the above technical solutions in this application, the following technical effects are achieved:

[0024] The substrate of this application has a larger thickness, and after the entire GaN HEMT device is completed, the back side of the substrate needs to be thinned. The substrate with a lower cost adopted in this application serves as a support basis on the one hand and an object to be thinned on the other hand.

[0025] Compared with the thickness lost in the thinning process in the prior art, the thickness of the release layer lost in the preparation method of the GaN HEMT device of this application is very small. The electric field termination layer and the electric field pressure-bearing layer in this application play the roles of pressure-bearing and electric field termination. Therefore, the substrate, the electric field termination layer, and the electric field pressure-bearing layer as a whole can correspond to the high-resistance SiC substrate in the background art.

[0026] The growth of the SIC epitaxial wafer grown along the C-axis is a process with a higher cost and complex control. The SIC epitaxial wafer grown along the C-axis formed by one-time growth can be used multiple times. Each time it is used to prepare one or a batch of GaN HEMT devices, which can also reduce the preparation cost of the GaN HEMT device and the complexity of the preparation method. Description of the Drawings

[0027] The accompanying drawings described herein are used to provide a further understanding of the present application and form a part of the present application. The schematic embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation of the present application. In the drawings:

[0028] Figure 1 Schematic diagram of a prior art GaN on SiC HEMT device;

[0029] Figure 2-A Flow chart of the preparation method of the GaN HEMT device of the present application;

[0030] Figure 2-B Schematic diagram of the preparation method of the GaN HEMT device of the present application when step S1 is completed;

[0031] Figure 2-C Schematic diagram of the preparation method of the GaN HEMT device of the present application when step S3 is completed;

[0032] Figure 2-D Schematic diagram of the preparation method of the GaN HEMT device of the present application when step S4 is completed;

[0033] Figure 2-E Schematic diagram of the preparation method of the GaN HEMT device of the present application when step S5 is completed;

[0034] Figure 2-F Schematic diagram of the preparation method of the GaN HEMT device of the present application when step S6 is executed;

[0035] Figure 2-G Schematic diagram of the preparation method of the GaN HEMT device of the present application when step S6 is completed;

[0036] Figure 3 Schematic diagram of one implementation of the GaN HEMT device of the present application;

[0037] Figure 4 Schematic diagram of another implementation of the GaN HEMT device of the present application;

[0038] Figure 5 Schematic diagram of yet another implementation of the GaN HEMT device of the present application;

[0039] Figure 6 Schematic diagram of the preparation method of the GaN HEMT device of the present application when step S7 is completed;

[0040] Figure 7 Schematic diagram of the preparation method of the GaN HEMT device of the present application when step S8 is completed;

[0041] Figure 8 Schematic diagram of completing step S9 in the preparation method of the GaN HEMT device of this application;

[0042] Figure 9 Schematic diagram of completing step S10 in the preparation method of the GaN HEMT device of this application;

[0043] Figure 10 Schematic diagram of completing step S11 in the preparation method of the GaN HEMT device of this application;

[0044] Figure 11 Schematic diagram of completing step S12 in the preparation method of the GaN HEMT device of this application;

[0045] Figure 12 Schematic diagram of completing step S13 in the preparation method of the GaN HEMT device of this application;

[0046] Figure 13 Schematic diagram of completing step S14 in the preparation method of the GaN HEMT device of this application.

[0047] Reference numerals:

[0048] In the background art:

[0049] Substrate through-hole 1-1;

[0050] In this application:

[0051] Substrate 10, SIC epitaxial wafer 12-0, electric field termination layer 11, electric field pressure-bearing layer 12, stripping layer 13;

[0052] SIC connection area 20, first connection area 21,

[0053] AlN layer 22, AlN layer base 220, GaN buffer layer 23, GaN buffer layer base 230,

[0054] GaN layer 24, GaN layer base 240, AlGaN layer 25, AlGaN layer base 250,

[0055] Gate metal 26, SiN layer 27, SiN layer base 270, drain 28-1, source 28-2,

[0056] Metal silicide layer 29, source metal 31, backside ground metal 32, second connection area 33. Detailed implementation manners

[0057] In order to make the technical solutions and advantages in this application clearer and more understandable, the following further elaborates on the exemplary embodiments of this application with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, rather than an exhaustive list of all embodiments. It should be noted that, without conflict, the embodiments in this application and the features in the embodiments can be combined with each other. Embodiment 1

[0058] As Figure 2-A shown, a method for fabricating a GaN HEMT device of this application includes the following steps:

[0059] As Figure 2-B shown, step S1: Form a substrate 10 of a second-doped-type SIC material;

[0060] Step S2: Form a first-doped-type SIC epitaxial wafer 12-0 grown along the C-axis alone;

[0061] As Figure 2-C shown, step S3: Form a first-doped-type electric field termination layer 11 on the front surface of the SIC epitaxial wafer 12-0; wherein, the doping concentration of the electric field termination layer 11 is greater than the doping concentration of the substrate 10;

[0062] As Figure 2-D shown, step S4: Form a release layer 13 at a position below the electric field termination layer 11 in the SIC epitaxial wafer 12-0; wherein, the portion of the SIC epitaxial wafer 12-0 between the electric field termination layer 11 and the release layer 13 serves as an electric field bearing layer 12;

[0063] As Figure 2-E shown, step S5: Bond the front surface of the electric field termination layer 11 and the front surface of the substrate 10 together;

[0064] As Figure 2-F shown, step S6: Perform peeling at the release layer 13; wherein, as Figure 2-G shown, the electric field termination layer 11 is above the substrate 10, and the electric field bearing layer 12 is above the electric field termination layer 11;

[0065] Wherein, an epitaxial structure of a GaN HEMT device is above the electric field bearing layer 12.

[0066] The method for fabricating a GaN HEMT device of this application includes the following steps:

[0067] Step S1: Form a substrate 10 of a second-doped type SIC material. Specifically, it can be to form a substrate 10 of a second-doped type SIC material that grows at an angle of 4 degrees off the C-axis alone. The cost of the substrate 10 of the second-doped type that grows at an angle of 4 degrees off the C-axis is relatively low.

[0068] Step S2: Form a first-doped type SIC epitaxial wafer 12-0 that grows along the C-axis alone. Note that at this time, the SIC epitaxial wafer 12-0 that grows along the C-axis is not directly formed on the substrate 10 that grows at an angle of 4 degrees off the C-axis, because a SIC epitaxial wafer that grows along the C-axis cannot be grown on the substrate 10 that grows at an angle of 4 degrees off the C-axis.

[0069] Step S3: Form a first-doped type electric field termination layer 11 on the front surface of the SIC epitaxial wafer 12-0; wherein, the doping concentration of the electric field termination layer 11 is greater than the doping concentration of the substrate 10.

[0070] Step S4: Form a peeling layer 13 at a position below the electric field termination layer 11 in the SIC epitaxial wafer 12-0; wherein, the part of the SIC epitaxial wafer 12-0 between the electric field termination layer 11 and the peeling layer 13 serves as an electric field bearing layer 12.

[0071] Step S5: Invert the entire SIC epitaxial wafer 12-0, and bond the front surface of the electric field termination layer 11 and the front surface of the substrate 10 together.

[0072] Step S6: Peeling is performed at the peeling layer 13; wherein, the electric field termination layer 11 is on the substrate 10, and the electric field bearing layer 12 is on the electric field termination layer 11. At this time, the part of the SIC epitaxial wafer 12-0 at the peeling layer 13 position and above it is peeled off, and the electric field termination layer 11 and the electric field bearing layer 12 are sequentially arranged from bottom to top on the substrate 10.

[0073] Since then, the substrate 10, the electric field termination layer 11, and the electric field bearing layer 12 as a whole serve as the basis for the epitaxial structure of the GaN HEMT device. That is, the substrate 10, the electric field termination layer 11, and the electric field bearing layer 12 as a whole correspond to the high-resistance SiC substrate in the background art.

[0074] The thickness of the substrate 10 of the present application that grows at an angle of 4 degrees off the C-axis is relatively large, and after the entire GaN HEMT device is completed, the back surface of the substrate 10 needs to be thinned. The substrate 10 of the present application that grows at an angle of 4 degrees off the C-axis with a relatively low cost serves as a support basis on the one hand and an object to be thinned on the other hand.

[0075] Due to its own characteristics, the substrate 10 of the SIC material grown at a 4-degree angle off the C-axis cannot be directly used as the basis for the epitaxial structure of the GaN HEMT device. If directly grown on the substrate 10 grown at a 4-degree angle off the C-axis, only an epitaxy deviated from the C-axis by 4 degrees can be grown, and the epitaxy deviated from the C-axis by 4 degrees cannot be directly used as the basis for the epitaxial structure of the GaN HEMT device either.

[0076] Therefore, in this application, through the methods of SIC epitaxial wafers, electric field termination layer 11, electric field pressure-bearing layer 12, inversion, front bonding, and peeling, the electric field termination layer 11 and the electric field pressure-bearing layer 12 on the substrate 10 are realized. The cost of the electric field termination layer 11 and the electric field pressure-bearing layer 12 is relatively high, but their thickness in the GaN HEMT device of this application is small, and it is not necessary to thin the electric field termination layer 11 and the electric field pressure-bearing layer 12 during the entire manufacturing process of the GaN HEMT device, so the relatively high-cost electric field termination layer 11 and electric field pressure-bearing layer 12 will not be damaged. During the whole process, only a peeling layer 13 is lost. Compared with the thickness lost by the thinning process in the prior art, the thickness of the peeling layer 13 lost by the manufacturing method of the GaN HEMT device in this application is very small. The electric field termination layer 11 and the electric field pressure-bearing layer 12 in this application play the roles of pressure-bearing and electric field termination. Therefore, the substrate 10, the electric field termination layer 11, and the electric field pressure-bearing layer 12 as a whole can correspond to the high-resistance SiC substrate in the background technology.

[0077] In addition, the first-doped type SIC epitaxial wafer 12-0 grown along the C-axis can be grown with a relatively large thickness at one time. The peeling layer 13, the electric field termination layer 11, and the electric field pressure-bearing layer 12 in the manufacture of a single GaN HEMT device will consume a certain thickness of the SIC epitaxial wafer 12-0, and the remaining part of the SIC epitaxial wafer 12-0 can still be used as the SIC epitaxial wafer in the manufacture of other GaN HEMT devices. In this way, the first-doped type SIC epitaxial wafer 12-0 grown along the C-axis can be grown once and used multiple times. The growth of the SIC epitaxial wafer 12-0 grown along the C-axis is a process with relatively high cost and complex control. The SIC epitaxial wafer 12-0 grown along the C-axis formed by one-time growth can be used multiple times, and each time it is used to manufacture one or a batch of GaN HEMT devices, which can also reduce the manufacturing cost of the GaN HEMT device and the complexity of the manufacturing method.

[0078] In implementation, the step of forming the first-doped type electric field termination layer 11 on the front surface of the SIC epitaxial wafer 12-0 is specifically:

[0079] Form the first-doped type electric field termination layer 11 on the front surface of the SIC epitaxial wafer 12-0 by ion implantation;

[0080] Alternatively, a field termination layer 11 of a first doping type is formed on the front surface of the SIC epitaxial wafer 12-0 by epitaxial growth.

[0081] In implementation, the step of forming the release layer 13 at a position below the field termination layer 11 in the SIC epitaxial wafer 12-0 is specifically:

[0082] The release layer 13 is formed at a position below the field termination layer 11 in the SIC epitaxial wafer 12-0 by hydrogen ion implantation.

[0083] In implementation, the step of bonding the front surface of the field termination layer 11 and the front surface of the substrate 10 together is specifically:

[0084] The front surface of the field termination layer 11 and the front surface of the substrate 10 are connected together by low-temperature bonding.

[0085] The bonding method can be the Smartcut bonding method.

[0086] In implementation, the step of bonding the front surface of the field termination layer 11 and the front surface of the substrate 10 together is specifically:

[0087] The front surface of the field termination layer 11 and the front surface of the substrate 10 are connected together by low-temperature bonding;

[0088] The step of peeling the SIC epitaxial wafer 12-0 at the position of the release layer 13 is specifically:

[0089] Peeling is performed at the release layer 13 by thermal reaction, high-temperature thermal annealing is used to strengthen the bonding, and the surface of the newly peeled electric field bearing layer 12 is smoothed by CMP process (chemical mechanical polishing process).

[0090] In the preparation method of the GaN HEMT device of the present application, ion implantation, bonding, peeling, high-temperature annealing to strengthen bonding, and CMP process are all common and mature processes, without additional process development costs, making the implementation of the preparation method of the GaN HEMT device of the present application more convenient and with lower implementation difficulty.

[0091] In implementation, the substrate 10 is a single-crystal or polycrystalline SIC material substrate;

[0092] Or a D-level wafer (test wafer level) of the SIC substrate.

[0093] In implementation, the substrate 10 is a high-resistance substrate or a low-resistance substrate.

[0094] Specifically, the GaN HEMT device of the present application further includes steps for preparing other structures.

[0095] Specifically, the first doping type is P-type and the second doping type is N-type.

[0096] In implementation, the substrate 10 is a low-resistance substrate;

[0097] The upper surface of the electric field bearing layer 12 is divided into a first region of the electric field bearing layer and a second region of the electric field bearing layer; the manufacturing method further includes the following steps:

[0098] Form a grounded backside ground metal 32 on the back side of the substrate 10;

[0099] Form a first connection region base of the first doping type downward in the first region of the electric field bearing layer. From the upper surface of the first connection region base, etch downward to form a first through hole, and fill the first through hole with SIC of the second doping type to form a SIC connection region 20 of the second doping type; wherein, the unetched part of the first connection region base forms a first connection region 21.

[0100] Wherein, the backside ground metal 32, the substrate 10 and the SIC connection region 20 are connected to connect the zero potential to the position on the upper surface of the GaN HEMT device located in the SIC connection region 20.

[0101] In implementation, it further includes the following steps:

[0102] Perform implantation on the inner wall of the first through hole to form a second connection region 33, and the second connection region 33:

[0103] In the vertical direction, the second connection region 33 is connected below the first connection region 21, and the bottom end of the SIC connection region 20 enters the electric field termination layer 11 or the bottom end of the SIC connection region 20 is connected to the upper surface of the substrate 10;

[0104] In the horizontal direction, the second connection region 33 is formed on the outer peripheral surface of the SIC connection region 20;

[0105] The doping concentration of the second connection region 33 is greater than the doping concentration of the electric field termination layer 11.

[0106] The electric field termination layer 11 and the electric field bearing layer 12 formed on the substrate 10 are necessary structures of the GaN HEMT device. The upper surface of the electric field bearing layer is divided into a first region of the electric field bearing layer and a second region of the electric field bearing layer, and the GaNHEMT front structure is formed on the first region of the electric field bearing layer.

[0107] The first through-hole is formed by etching downward from the second region of the electric field pressure-bearing layer, and the bottom end of the first through-hole enters the substrate 10. That is, the starting point of the etching for forming the first through-hole is the second region of the electric field pressure-bearing layer, and the end point is to enter the substrate 10. The etching for forming the first through-hole only needs to penetrate through the thickness of the electric field termination layer 11 of the SIC material and the electric field pressure-bearing layer 12 and go a little deeper into the substrate 10. The total thickness of the electric field termination layer 11 and the electric field pressure-bearing layer 12 is generally only a few micrometers. Therefore, the etching depth for forming the first through-hole is very small.

[0108] The N-type SIC connection region 20 is formed by filling N-type polycrystalline SIC in the first through-hole, and the lower end of the SIC connection region 20 enters the substrate 10. In this way, the back-side ground metal 32, the N-type substrate 10, and the N-type SIC connection region 20 are connected.

[0109] The GaN HEMT front-side structure is formed on the first region of the electric field pressure-bearing layer. The distance between the back-side ground metal 32 and the upper surface of the GaN HEMT front-side structure is the total thickness of the GaN HEMT device of this application. Therefore, the etching for forming the first through-hole is an etching with a small depth for the SIC material with relatively high etching difficulty, and it is also much smaller than the thickness of the GaN HEMT device of this application. Therefore, the etching for forming the first through-hole does not need to adopt the TSV through-hole process, and only the semi-through-hole etching process needs to be adopted to form it. The etching process is simple, and the process implementation difficulty is small.

[0110] The depth of the first through-hole is small. Correspondingly, the diameter of the first through-hole is also small, and further, the area occupied by the first through-hole is also small.

[0111] The back-side ground metal 32 is grounded and the conductive carriers are electrons. The substrate uses an N-type low-resistance substrate 10, that is, the majority carriers of the substrate 10 are electrons and there are many electrons in the substrate 10. Since the back-side ground metal 32 and the N-type low-resistance substrate 10 each have many electrons as conductive carriers, the electrical connection at the connection between the N-type low-resistance substrate 10 and the back-side ground metal 32 is good and the resistance is low.

[0112] Both the N-type substrate 10 and the N-type SIC connection region 20 are N-type, and the majority carriers are electrons. In this way, by controlling the doping concentration of the N-type substrate 10 and the N-type SIC connection region 20, it is possible to achieve good electrical connection and low resistance at the connection between the N-type substrate 10 and the N-type SIC connection region 20.

[0113] As a result, the back-side grounding metal 32, the N-type substrate 10, and the N-type SIC connection region 20 are connected and have good electrical connection with relatively low resistance. Since the back-side grounding metal 32 is grounded, through the connection of the back-side grounding metal 32, the N-type substrate 10, and the N-type SIC connection region 20, the zero potential of the grounded back-side grounding metal 32 has been connected to the upper surface of the SIC connection region 20 (corresponding to the height of the upper surface of the second region of the epitaxial layer), that is, the zero potential has been connected inside the GaN HEMT device of the present application and at the middle position in the thickness direction, providing conditions for the front-side grounding of the GaN HEMT device of the present application. In this way, the structural form of the GaN HEMT device of the present application realizes that the front-side grounding no longer needs to penetrate the entire thickness of the device, and thus no longer requires the TSV via process.

[0114] The manufacturing process of the GaN HEMT device of the present application, in chronological order, on the basis of Figure 2-A - Figure 6 also includes the following steps:

[0115] Step S7: As shown in Figure 6 , form the back-side grounding metal 32 on the back side of the N-type low-resistance substrate 10, and form an epitaxial layer of P-type SIC material from the upper surface of the substrate 10. The epitaxial layer includes a P-type field termination layer 11 and a field pressure-bearing layer 12 from bottom to top;

[0116] Step S8: As shown in Figure 7 , form a P-type first connection region base by implantation, form a first via by etching downward from the upper surface of the first connection region base, and fill the first via with N-type polycrystalline SIC to form the N-type SIC connection region 20; at this time, form the first connection region 21;

[0117] Step S9: As shown in Figure 8 , sequentially form an AlN layer base 220, a GaN buffer layer base 230, a GaN layer base 240, an AlGaN layer base 250, and a SiN layer base 270 from bottom to top above the field pressure-bearing layer 12, the N-type SIC connection region 20, and the first connection region 21;

[0118] Step S10: As shown in Figure 9 , etch downward from the upper surface of the SiN layer base 270 to expose the first connection region 21 and the N-type SIC connection region 20;

[0119] Step S11: As shown in Figure 10 , form a metal silicide layer 29 above the first connection region 21 and the N-type SIC connection region 20;

[0120] Step S12: As shown in Figure 11 , form a gate metal 26 on the SiN layer base 270;

[0121] Step S13: As Figure 12 shown, a first contact hole 30 is formed on the metal silicide layer 29, and a source electrode 28-1 and a drain electrode 28-2 are formed; thus, an AlN layer 22, a GaN buffer layer 23, a GaN layer 24, an AlGaN layer 25, and a SiN layer 27 are formed.

[0122] Step S14: As Figure 13 shown, a source electrode metal 31 and a drain electrode metal are formed. Embodiment 2

[0123] The GaN HEMT device of the present application includes:

[0124] A substrate 10 of a second-doped type SIC material;

[0125] An electric field termination layer 11 of a first-doped type SIC grown along the C axis, formed on the substrate 10;

[0126] An electric field pressure-bearing layer 12 of a first-doped type SIC grown along the C axis, formed on the electric field termination layer 11.

[0127] Specifically, the substrate 10 can adopt a substrate 10 of a second-doped type grown at an angle of 4 degrees off the C axis.

[0128] For the GaN HEMT device of the present application, the substrate 10, the electric field termination layer 11, and the electric field pressure-bearing layer 12 as a whole serve as the basis of the epitaxial structure of the GaN HEMT device, with a relatively low overall cost and a relatively simple preparation process. The substrate 10, the electric field termination layer 11, and the electric field pressure-bearing layer 12 as a whole correspond to the high-resistance SiC substrate in the background art.

[0129] The substrate 10 of the present application grown at an angle of 4 degrees off the C axis has a relatively large thickness, and after the entire GaN HEMT device is completed, the back surface of the substrate 10 needs to be thinned. The relatively low-cost substrate 10 of the present application grown at an angle of 4 degrees off the C axis serves as a support basis on the one hand and an object to be thinned on the other hand.

[0130] The electric field termination layer 11 and the electric field pressure-bearing layer 12 have a relatively high cost, but have a relatively small thickness in the GaN HEMT device of the present application, and there is no need to thin the electric field termination layer 11 and the electric field pressure-bearing layer 12 during the preparation process of the entire GaN HEMT device, so the relatively high-cost electric field termination layer 11 and electric field pressure-bearing layer 12 will not be damaged. The electric field termination layer 11 and the electric field pressure-bearing layer 12 in the present application play the roles of pressure bearing and electric field termination. Therefore, the substrate 10, the electric field termination layer 11, and the electric field pressure-bearing layer 12 as a whole can correspond to the high-resistance SiC substrate in the background art.

[0131] In implementation, the substrate 10 is a low-resistance substrate 10;

[0132] The upper surface of the electric field bearing layer 12 is divided into a first region of the electric field bearing layer and a second region of the electric field bearing layer;

[0133] The GaN HEMT device further includes:

[0134] A grounded backside ground metal 32 formed on the back side of the substrate 10;

[0135] A first through hole formed downward from the first region of the electric field bearing layer, and the bottom end of the first through hole enters the substrate 10;

[0136] An N-type SIC connection region 20 formed by filling the first through hole with N-type polycrystalline SIC, and the lower end of the SIC connection region 20 enters the substrate 10;

[0137] A GaN HEMT front structure formed above the second region of the electric field bearing layer;

[0138] Wherein, the backside ground metal 32, the N-type substrate 10 and the N-type SIC connection region 20 are connected to connect the zero potential to the position of the upper surface of the GaN HEMT device and the SIC connection region 20.

[0139] The patent application with the publication number CN118016691A discloses a gallium nitride heterostructure based on a large-size silicon-based composite substrate and a manufacturing method thereof.

[0140] Compared with the patent application with the publication number CN118016691A, the present application has the following differences:

[0141] The patent application with the publication number CN118016691A is a silicon-based composite substrate, which uses Si and SiC substrates for bonding. The thermal conductivities and lattice constants of these two heterogeneous materials are different. Therefore, there will inevitably be problems such as thermal mismatch and lattice mismatch during bonding, and stress will be generated at the bonding interface. In order to relax the stress, a certain amount of dislocations will be formed at the interface, and even extend upward to affect the SiC material, and subsequently affect the performance of the gallium nitride material and the device. To form a good interface, it is necessary to strictly control the bonding process and quality, resulting in increased costs. The thermal conductivity of silicon material is much lower than that of SiC and GaN materials, and the heat dissipation is very slow, which poses great limitations to the high-temperature and high-power applications of power devices.

[0142] Moreover, the silicon-based composite substrate cannot be applied to the structure in which the substrate is connected by using the SiC connection layer in this application. Due to the hetero-junction structure formed by the SiC material and the Si material, there may be defects, dangling bonds, interface states, etc. at the interface, which affect the transmission of electrons from the SiC connection layer to the Si material, thereby affecting the performance of the GaN device.

[0143] This application bonds the epitaxial wafer of the SiC material to the SiC substrate. Since they are homogeneous materials, there are no problems of thermal mismatch and lattice mismatch at the bonding interface, and there are no special requirements for the bonding process, which will not increase the cost. At the same time, the SiC connection layer and the substrate are made of the same material, and the device performance will not be affected.

[0144] In implementation, the value range of the depth at which the lower end of the N-type SIC connection region 20 enters the substrate 10 is greater than or equal to 0.1 μm. This can ensure a good connection between the N-type SIC connection region 20 and the substrate 10.

[0145] In implementation, the value range of the thickness of the substrate 10 is greater than or equal to 5 μm and less than or equal to 300 μm;

[0146] The value range of the resistivity of the substrate 10 is greater than or equal to 0.1 mohm cm and less than or equal to 1000 ohm cm.

[0147] The logic for selecting the resistivity of the substrate is that this device needs to conduct electricity through the substrate to the back. According to the current technology, the thickness of the back substrate is about 100 μm. For a lower ground resistance, for a 10 mm 2 device, according to the resistivity of 100 ohm cm, the ground resistance is 10 ohm. If it is greater than this value, the device performance will not be good. The thickness and resistivity of the substrate jointly determine the parasitic resistance.

[0148] In implementation, as Figure 3 、 Figure 4 、 Figure 5 shown, the GaN HEMT device of this application further includes:

[0149] A metal silicide layer 29, which is formed on the N-type SIC connection region 20;

[0150] A first contact hole 30, which is formed on the metal silicide layer 29; the upper end of the first contact hole 30 is connected to the source metal 31 of the GaN HEMT front structure;

[0151] Among them, the source metal 31 of the front structure of the GaN HEMT is connected to the first contact hole 30, the metal silicide layer 29, the N-type SIC connection region 20, the N-type substrate 10, and the grounded backside ground metal 32.

[0152] In this way, the source metal 31 of the front structure of the GaN HEMT is grounded from the front of the GaN HEMT device of the present application through the first contact hole 30, the metal silicide layer 29, the N-type SIC connection region 20, the N-type substrate 10, and the grounded backside ground metal 32. That is, the source of the GaN HEMT device of the present application is grounded through the front grounding structure.

[0153] The first contact hole 30 is formed by a contact hole process, and the metal of the first contact hole 30 is tungsten. Therefore, the preparation process of the first contact hole 30 is simple and the cost is low.

[0154] In this way, the front grounding structure of the GaN HEMT device of the present application includes:

[0155] The source metal 31, the first contact hole 30, the metal silicide layer 29, the N-type SIC connection region 20 (filled in the first through hole), the N-type substrate 10, the grounded backside ground metal 32, and the first connection region 21.

[0156] Adopting a two-end structure, the metal silicide layer 29 and the structure below it (the N-type SIC connection region 20 (filled in the first through hole), the N-type substrate 10, the grounded backside ground metal 32, and the first connection region 21) are one section, and the structure above the metal silicide layer 29 (the source metal 31, the first contact hole 30) is one section. Both the first contact hole 30 and the first through hole are relatively short, far less than the overall thickness of the GaN HEMT device of the present application. Moreover, the first contact hole 30 adopts a contact hole process and the first through hole adopts a semi-through hole process. That is, the preparation process of the front grounding structure of the GaN HEMT device of the present application does not require a TSV process, and the deficiencies brought by the TSV process are not present in the present application either.

[0157] In implementation, as Figure 3 、 Figure 4 、 Figure 5 shown, the GaN HEMT device of the present application further includes:

[0158] A P-type connection region is formed downward from the first region of the epitaxial layer within the epitaxial layer, and the P-type connection region is connected to the outer peripheral surface of the N-type SIC connection region 20; and the metal silicide layer 29 is formed above the N-type SIC connection region 20 and the P-type connection region;

[0159] Among them, the metal silicide layer 29 is respectively connected to the N-type SIC connection region 20 and the P-type connection region.

[0160] In this way, the backside ground metal 32, the N-type substrate 10, the N-type SIC connection region 20, and the metal silicide layer 29 are connected; and the P-type epitaxial layer, the P-type connection region, and the metal silicide layer 29 are connected.

[0161] Through the connection of the backside ground metal 32, the N-type substrate 10, the N-type SIC connection region 20, and the metal silicide layer 29, the zero potential of the grounded backside ground metal 32 has been connected to the metal silicide layer 29. Through the metal silicide layer 29, the P-type connection region, and the P-type epitaxial layer that have been connected to the zero potential, the P-type epitaxial layer has been connected to the zero potential.

[0162] Regarding the structure of the epitaxial layer:

[0163] As a first optional method, the epitaxial layer includes:

[0164] A P-type electric field termination layer 11 formed on the substrate 10.

[0165] As a second optional method, in implementation, as Figure 3 、 Figure 4 、 Figure 5 shown, the epitaxial layer includes:

[0166] A P-type electric field termination layer 11 formed on the substrate 10;

[0167] A P-type electric field bearing layer 12 formed on the electric field termination layer 11.

[0168] Setting both the P-type electric field termination layer 11 and the P-type electric field bearing layer 12 simultaneously is a preferred implementation method. In this way, the parameters of the P-type electric field bearing layer 12 with a lower doping concentration are used to meet the requirements of the breakdown voltage of the GaN HEMT device, and the parameters of the P-type electric field termination layer 11 with a higher doping concentration are used to meet the requirements of the electric field cut-off of the GaN HEMT device. Therefore, the breakdown voltage of the GaN HEMT device of the present application can meet the requirements, and at the same time, the electric field can be cut off within the electric field termination layer 11, and the thickness of the entire GaN HEMT device remains small.

[0169] In implementation, as Figure 3 、 Figure 4 、 Figure 5 shown, the GaN HEMT device further includes:

[0170] The first P-type connection region 21 is formed downward from the upper surface of the epitaxial layer and is connected to the outer peripheral surface of the N-type SIC connection region 20. The first connection region 21 occupies a part of the epitaxial layer in the lateral direction.

[0171] Wherein, the metal silicide layer 29 is also formed on the first connection region 21, and the metal silicide layer 29 is connected to the first connection region 21 and the N-type SIC connection region 20 respectively.

[0172] The P-type SiC material epitaxial layer, the P-type first connection region 21, and the metal silicide layer 29 are connected and have good electrical connection. Since the zero potential has been connected to the metal silicide layer 29, the epitaxial layer is thus connected to the zero potential.

[0173] During implementation, as Figure 3 、 Figure 4 、 Figure 5 shown, the P-type connection region includes the P-type first connection region 21, and the first connection region 21:

[0174] In the vertical direction, the first connection region 21 is formed downward from the upper surface of the electric field bearing layer 12, and the lower surface of the first connection region 21 is higher than the lower surface of the electric field bearing layer 12;

[0175] In the lateral direction, the first connection region 21 is connected to the outer peripheral surface of the N-type SIC connection region 20 and occupies a part of the electric field bearing layer 12;

[0176] The doping concentration of the first connection region 21 is greater than the doping concentration of the electric field bearing layer 12;

[0177] Wherein, the metal silicide layer 29 is also formed on the first connection region 21, and the metal silicide layer 29 is connected to the first connection region 21 and the N-type SIC connection region 20 respectively.

[0178] The doping concentration of the P-type first connection region 21 is greater than the doping concentration of the P-type electric field bearing layer 12. In this way, the P-type electric field bearing layer 12, the P-type first connection region 21, and the metal silicide layer 29 that has been connected to the zero potential are electrically connected, and the P-type electric field bearing layer 12 is connected to the zero potential.

[0179] The metal silicide layer 29 is respectively connected to the first connection region 21 and the N-type SIC connection region 20. Through the backside ground metal 32, the N-type substrate 10, the N-type SIC connection region 20, and the metal silicide layer 29, the zero potential of the grounded backside ground metal 32 has been connected to the metal silicide layer 29. The P-type electric field bearing layer 12, the P-type first connection region 21, and the metal silicide layer 29 that has been connected to the zero potential are electrically connected, realizing the connection of the P-type electric field bearing layer 12 to the zero potential.

[0180] The first region of the epitaxial layer corresponds to the first region of the electric field bearing layer, and the second region of the epitaxial layer corresponds to the second region of the electric field bearing layer.

[0181] As an alternative, as Figure 4 shown, the first connection region 21 is located below the first region of the electric field bearing layer and partially below the second region of the electric field bearing layer. That is, the first connection region 21 extends in the lateral direction under the GaN HEMT front structure.

[0182] Since the doping concentration of the first connection region 21 is greater than that of the electric field bearing layer 12, the electric field generated by the GaN HEMT front structure is rapidly reduced at the position of the first connection region 21, playing a role in balancing the electric field.

[0183] As another alternative, as Figure 5 shown, the P-type connection region further includes a P-type second connection region 33:

[0184] In the vertical direction, the second connection region 33 is connected below the first connection region 21, and the bottom end of the N-type SIC connection region 20 enters the electric field termination layer 11 or the bottom end of the N-type SIC connection region 20 is connected to the upper surface of the substrate 10;

[0185] In the lateral direction, the second connection region 33 is formed on the outer peripheral surface of the N-type SIC connection region 20;

[0186] The doping concentration of the second connection region 33 is greater than that of the electric field termination layer 11.

[0187] Since the doping concentration of the second connection region 33 is greater than that of the electric field termination layer 11 and the doping concentration of the first connection region 21 is greater than that of the electric field bearing layer 12, the connection of the P-type electric field termination layer 11, the second connection region 33, the first connection region 21, and the metal silicide layer 29 is better, and the connection of the N-type electric field bearing layer 12, the second connection region 33, the first connection region 21, and the metal silicide layer 29 is also better.

[0188] The epitaxial layer of the P-type SiC material, the P-type second connection region 33, and the metal silicide layer 29 are connected and have good electrical connection, which is also to better connect the epitaxial layer to the zero potential.

[0189] The reason for forming the first connection region 21 and the second connection region 33 in two structures by two processes respectively is that. Limited by the implantation process, the depth formed by the first connection region 21 cannot be too deep at present, and the first connection region 21 cannot directly enter the electric field termination layer 11. Therefore, a method of forming the second connection region 33 by ion implantation on the side wall of the through hole is also adopted.

[0190] The higher the doping concentration of the first connection region 21 and the second connection region 33, the better. In actual preparation, the doping concentrations of the first connection region 21 and the second connection region 33 are limited by the ion implantation process.

[0191] In implementation, the value range of the doping concentration of the first connection region 21 is greater than or equal to 1×10 17 cm -3 less than or equal to 1×10 22 cm -3 , and the doping concentration of the first connection region 21 is at least 2 orders of magnitude higher than the doping concentration of the electric field bearing layer 12;

[0192] The value range of the doping concentration of the second connection region 33 is 1×10 17 cm -3 less than or equal to 1×10 22 cm -3 , and the doping concentration of the second connection region 33 is at least 2 orders of magnitude higher than the doping concentration of the electric field termination layer 11.

[0193] Specifically, as Figure 3 , Figure 4 , and Figure 5 shown, the front structure of the GaN HEMT includes:

[0194] The AlN layer 22 is formed on the second region of the electric field bearing layer;

[0195] The GaN buffer layer 23 is formed on the AlN layer 22;

[0196] The GaN layer 24 is formed on the GaN buffer layer 23;

[0197] The AlGaN layer 25 is formed on the GaN layer 24;

[0198] The SiN layer 27 is formed on the AlGaN layer 25;

[0199] The gate metal 26 is formed on the SiN layer 27 and is connected to the AlGaN layer 25 through a contact hole passing through the SiN layer 27;

[0200] The source 28-1 and the drain 28-2 each penetrate the SiN layer 27 and the AlGaN layer 25 and enter the GaN layer 24, and are respectively connected to both ends of the GaN layer 24;

[0201] The source metal 31 is connected on the source 28-1.

[0202] Among them, AlN is aluminum nitride; GaN is gallium nitride; AlGaN is aluminum gallium nitride; SiN is silicon nitride.

[0203] AlGaN / GaN forms a heterojunction, and the two-dimensional electron gas (2DEG) generated by the heterojunction is the basis for the operation of all GaN HEMT devices. The AlGaN layer 25 and the GaN layer 24 form a heterojunction, and the on and off of the two-dimensional electron gas 2DEG generated by the heterojunction are controlled by the gate metal 26.

[0204] The electric field termination layer 11 and the electric field bearing layer 12 are required to grow along the C-axis because the performance of the front structure of the GaN HEMT is better in this way.

[0205] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0206] The present application is described with reference to the flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram can be implemented by computer program instructions, and the combination of the processes and / or blocks in the flowchart and / or block diagram can also be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing devices generate a device for realizing the functions specified in Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks.

[0207] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to work in a particular manner, such that the instructions stored in the computer-readable memory produce a manufacture including an instruction device that implements the function specified in one process or a plurality of processes and / or one block or a plurality of blocks in the flow. Figure 1 in one process or a plurality of processes and / or Figure 1 one block or a plurality of blocks.

[0208] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus, so that a series of operation steps are executed on the computer or other programmable apparatus to generate a computer-implemented process, and thus the instructions executed on the computer or other programmable apparatus provide steps for implementing the function specified in one process or a plurality of processes and / or one block or a plurality of blocks in the flow. Figure 1 in one process or a plurality of processes and / or Figure 1 one block or a plurality of blocks.

[0209] Although the preferred embodiments of the present application have been described, those skilled in the art can make additional changes and modifications once they learn the basic creative concepts. Therefore, the appended claims are intended to be construed to include the preferred embodiments as well as all changes and modifications falling within the scope of the present application.

[0210] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these modifications and variations.

Claims

1. A preparation method of a GaN HEMT device, characterized in that, Comprising: A substrate (10) made of SIC material of a second doping type; Forming a separate first-doped SIC epitaxial wafer (12-0) grown along the C-axis; Forming a first-doped electric field termination layer (11) on the front surface of the SIC epitaxial wafer (12-0); wherein, the doping concentration of the electric field termination layer (11) is greater than that of the substrate (10); Forming a peeling layer (13) at a position below the electric field termination layer (11) in the SIC epitaxial wafer (12-0); wherein, the portion of the SIC epitaxial wafer (12-0) between the electric field termination layer (11) and the peeling layer (13) serves as an electric field bearing layer (12); Bonding the front surface of the electric field termination layer (11) and the front surface of the substrate (10) together; Performing peeling at the position of the peeling layer (13); wherein, above the substrate (10) are successively the electric field termination layer (11) and the electric field bearing layer (12); The substrate (10) is a low-resistance substrate; The upper surface of the electric field bearing layer (12) is divided into an electric field bearing layer first region and an electric field bearing layer second region; the manufacturing method further includes the following steps: Forming a grounded back surface ground metal (32) on the back side of the substrate (10); Forming a first-doped first connection region base downward in the electric field bearing layer second region, forming a first through hole downward by etching from the upper surface of the first connection region base, and filling the first through hole with SIC of a second doping type to form a second-doped SIC connection region (20); wherein, the unetched portion of the first connection region base forms a first connection region (21).

2. The manufacturing method of the GaN HEMT device according to claim 1, characterized in that, The step of forming a first-doped electric field termination layer (11) on the front surface of the SIC epitaxial wafer (12-0) is specifically: Forming a first-doped electric field termination layer (11) on the front surface of the SIC epitaxial wafer (12-0) by ion implantation; Or forming a first-doped electric field termination layer (11) on the front surface of the SIC epitaxial wafer (12-0) by epitaxial growth.

3. The manufacturing method of the GaN HEMT device according to claim 2, characterized in that, The step of forming a peeling layer (13) at a position below the electric field termination layer (11) in the SIC epitaxial wafer (12-0) is specifically: Forming a peeling layer (13) at a position below the electric field termination layer (11) in the SIC epitaxial wafer (12-0) by hydrogen ion implantation.

4. The manufacturing method of the GaN HEMT device according to claim 3, characterized in that, The step of bonding the front surface of the electric field termination layer (11) and the front surface of the substrate (10) together is specifically: Bonding the front surface of the electric field termination layer (11) and the front surface of the substrate (10) together by low-temperature bonding; The step of peeling the SIC epitaxial wafer (12-0) at the position of the peeling layer (13) is specifically: Performing peeling at the peeling layer (13) by thermal reaction, strengthening the bonding by high-temperature thermal annealing, and performing CMP surface smoothing treatment on the just-peeled surface of the electric field bearing layer (12).

5. The manufacturing method of the GaN HEMT device according to any one of claims 1 to 4, characterized in that, The substrate (10) is a single-crystal or polycrystalline substrate, and the substrate is a high-resistance substrate or a low-resistance substrate; The steps of forming the substrate (10) of the second-doped type SIC material are specifically as follows: Forming a substrate (10) of the second-doped type SIC material grown at an angle of 4 degrees off the C-axis.

6. The manufacturing method of the GaN HEMT device according to claim 1, characterized in that, It further includes the following steps: Injecting to form a second connection region (33) on the inner wall of the first through hole, and the second connection region (33): In the vertical direction, the second connection region (33) is connected below the first connection region (21), and the bottom end of the SIC connection region (20) enters into the electric field termination layer (11) or the bottom end of the SIC connection region (20) is connected to the upper surface of the substrate (10); In the horizontal direction, the second connection region (33) is formed on the outer peripheral surface of the SIC connection region (20).

7. A GaN HEMT device, characterized in that, It includes: A substrate (10) of the second-doped type SIC material; An electric field termination layer (11) of the first-doped type SIC grown along the C-axis, formed on the substrate (10); An electric field pressure-bearing layer (12) of the first-doped type SIC grown along the C-axis, formed on the electric field termination layer (11); The substrate (10) is a low-resistance substrate; The upper surface of the electric field pressure-bearing layer (12) is divided into an electric field pressure-bearing layer first region and an electric field pressure-bearing layer second region; The GaN HEMT device further includes: A grounded backside ground metal (32), formed on the back side of the substrate (10); A first through hole, formed downward from the electric field pressure-bearing layer first region, and the bottom end of the first through hole enters into the substrate (10); An N-type SIC connection region (20), formed by filling the first through hole with N-type polycrystalline SIC, and the lower end of the SIC connection region (20) enters into the substrate (10); A GaN HEMT front structure, formed on the electric field pressure-bearing layer second region; Wherein, the backside ground metal (32), the N-type substrate (10) and the N-type SIC connection region (20) are connected and connected to the GaN HEMT device.

8. The GaN HEMT device according to claim 7, wherein It further includes: A metal silicide layer (29), the metal silicide layer (29) is formed on the N-type SIC connection region (20); A first contact hole (30), formed on the metal silicide layer (29); the upper end of the first contact hole (30) is connected to the source metal (31) of the GaN HEMT front structure; Wherein, the source metal (31) of the GaN HEMT front structure, the first contact hole (30) and the metal silicide layer (29) are connected.

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