Method of manufacturing semiconductor device

Abstract

The invention relates to a method of manufacturing a semiconductor device. The reliability of the semiconductor device is improved. A field plate electrode FP is formed inside the trench TR via an insulating film IF1. The other portion of the field plate electrode FP selectively retracts toward the bottom of the trench TR such that a portion of the field plate electrode FP remains as an extraction portion FPa. A silicon oxide film OX1 is formed on the upper surface of the field plate electrode FP by thermal oxidation. The insulating film IF1 and the silicon oxide film OX1 on the upper surface TS of the semiconductor substrate SUB are removed, and the insulating film IF1 is retracted so that the position of the upper surface of the insulating film IF1 is lower than the position of the upper surface of the field plate electrode FP.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The disclosure of Japanese Patent Application No. 2023-121756 filed on July 26, 2023 including the specification, drawings and abstract is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a method for manufacturing a semiconductor device, for example, a method for manufacturing a semiconductor device provided with a gate electrode and a field plate electrode inside a trench. Background Art

[0004] In a semiconductor device equipped with a semiconductor element such as a power MOSFET (metal oxide semiconductor field effect transistor), a trench gate structure having a gate electrode embedded inside a trench is applied. As a type of trench gate structure, a split gate structure is known, in which a field plate electrode is formed at the bottom of the trench and a gate electrode is formed at the top of the trench. A source potential is supplied from a source electrode to the field plate electrode. By extending a depletion layer in a drift region through the field plate electrode, the concentration in the drift region can be increased, thereby reducing the resistance of the drift region.

[0005] For example, a MOSFET having a split gate structure is disclosed in Patent Document 1. The field plate electrode and the gate electrode of Patent Document 1 are formed as follows: First, after forming the field plate electrode inside the trench, the upper surface of the field plate electrode is recessed. Next, a conductive film for the gate electrode is deposited on the semiconductor substrate to fill the inside of the trench on the field plate electrode. Then, by performing anisotropic etching on the conductive film, a gate electrode is formed on the top of the trench.

[0006] The disclosed techniques are listed below.

[0007] [Patent Document 1] Japanese Patent Application Publication No. 2011-199109 Summary of the invention

[0008] Inside the trench, a portion of the gate electrode may be formed in a protruding manner. When such an area exists, the electric field tends to concentrate, causing the insulation resistance between the gate electrode and the field plate electrode to deteriorate and making leakage current more likely to occur.

[0009] In addition, the field plate electrode includes a lead-out portion for electrically connecting to the source electrode. The field plate electrode of the lead-out portion is formed not only at the bottom of the trench but also at the top. Anisotropic etching is performed on the conductive film for the gate electrode, but the conductive film may remain as a residue on the side of the lead-out portion. This may lead to a problem that the insulation resistance between the lead-out portion and the semiconductor substrate cannot be maintained.

[0010] The main purpose of the present application is to improve the reliability of semiconductor devices by ensuring the insulation resistance between the gate electrode and the field plate electrode and between the lead-out portion and the semiconductor substrate. Other purposes and novel features will become apparent from the description and drawings of this specification.

[0011] Typical embodiments among the embodiments disclosed in the present application will be briefly described as follows.

[0012] A manufacturing method for a semiconductor device according to an embodiment includes the following steps: (a) providing a semiconductor substrate of a first conductivity type having an upper surface and a lower surface; (b) after (a), forming a trench in the semiconductor substrate to reach a predetermined depth from the upper surface of the semiconductor substrate toward the lower surface of the semiconductor substrate; (c) after (b), forming a first insulating film on the upper surface of the semiconductor substrate and inside the trench; (d) after (c), forming a first conductive film on the first insulating film to fill the inside of the trench;

[0013] (e) after (d), the first conductive film located outside the trench is removed to form the first conductive film remaining inside the trench as a field plate electrode; (f) after (e), a portion of the field plate electrode is retained as a lead-out portion, and the other portion of the field plate electrode is selectively retracted toward the bottom of the trench; (g) after (f), a first silicon oxide film is formed on the upper surface of the field plate electrode by thermal oxidation; (h) after (g), the first insulating film and the first silicon oxide film located on the upper surface of the semiconductor substrate are removed, and the first insulating film located inside the trench is retracted toward the bottom of the trench, so that in a cross-sectional view, the position of the upper surface of the first insulating film located inside the trench is lower than the position of the upper surface of the field plate electrode; (i) after (h), a gate insulating film is formed inside the trench on the first insulating film, and a second insulating film is formed to cover the field plate electrode exposed from the first insulating film;

[0014] (j) after (i), forming a second conductive film on the gate insulating film, the second insulating film and the first insulating film to fill the inside of the trench; and (k) after (j), removing the second conductive film located outside the trench to form the second conductive film remaining inside the trench as a gate electrode on the field plate electrode. The second conductive film formed on the first insulating film and the second insulating film in contact with the lead-out portion by (j) is removed by (k).

[0015] According to one embodiment, the reliability of a semiconductor device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a plan view showing the semiconductor device in the first embodiment.

[0017] Figure 2is a plan view showing the semiconductor device in the first embodiment.

[0018] Figure 3 is a main part plan view showing the semiconductor device in the first embodiment.

[0019] Figure 4 is a main part plan view showing the semiconductor device in the first embodiment.

[0020] Figure 5 is a cross-sectional view showing the semiconductor device in the first embodiment.

[0021] Figure 6 is a cross-sectional view illustrating a manufacturing process of the semiconductor device in the first embodiment.

[0022] Figure 7 It's a picture. Figure 6 Cross-sectional view of the subsequent manufacturing process.

[0023] Figure 8 It's a picture. Figure 7 Cross-sectional view of the subsequent manufacturing process.

[0024] Fig. 9 It's a picture. Figure 8 Cross-sectional view of the subsequent manufacturing process.

[0025] Fig.10 It's a picture. Fig. 9 Cross-sectional view of the subsequent manufacturing process.

[0026] Fig.11 It's a picture. Fig.10 Cross-sectional view of the subsequent manufacturing process.

[0027] Fig.12 It's a picture. Fig.11 Cross-sectional view of the subsequent manufacturing process.

[0028] Fig.13 It's a picture. Fig.12 Cross-sectional view of the subsequent manufacturing process.

[0029] Fig.14 It's a picture. Fig.13 Cross-sectional view of the subsequent manufacturing process.

[0030] Fig.15 It's a picture. Fig.14 Cross-sectional view of the subsequent manufacturing process.

[0031] Fig.16 It's a picture. Fig.15 Cross-sectional view of the subsequent manufacturing process.

[0032] Fig.17 It's a picture. Fig.16 Cross-sectional view of the subsequent manufacturing process.

[0033] Fig.18 It's a picture. Fig.17 Cross-sectional view of the subsequent manufacturing process.

[0034] Fig.19 It's a picture. Fig.18 Cross-sectional view of the subsequent manufacturing process.

[0035] Fig. 20 It's a picture. Fig.19 Cross-sectional view of the subsequent manufacturing process.

[0036] Fig.21 It's a picture. Fig. 20 Cross-sectional view of the subsequent manufacturing process.

[0037] Fig. 22 is a plan view of a semiconductor device in a first modified example.

[0038] Fig.23 2 is a cross-sectional view illustrating a manufacturing process of the semiconductor device in the second modified example.

[0039] Fig.24 : is a cross-sectional view illustrating a manufacturing process of the semiconductor device in the third modified example.

[0040] Fig.25 : is a cross-sectional view illustrating a manufacturing process of the semiconductor device in the fourth modified example.

[0041] Fig.26 It shows Fig.25 A cross-sectional view of a subsequent manufacturing process of a semiconductor device.

[0042] Fig. 27 is a main portion cross-sectional view of the semiconductor device in Inspection Example 1.

[0043] Fig.28 is a main portion cross-sectional view of the semiconductor device in Inspection Example 1.

[0044] Fig.29 is a main portion cross-sectional view of the semiconductor device in Inspection Example 2. DETAILED DESCRIPTION

[0045] Hereinafter, the embodiments are described in detail with reference to the accompanying drawings. In all the drawings used to explain the embodiments, components having the same function are represented by the same reference numerals, and their repeated descriptions are omitted. In the following embodiments, the description of the same or similar parts is not repeated in principle unless otherwise required.

[0046] In addition, the X direction, Y direction, and Z direction described in the present application intersect each other and are orthogonal to each other. In the present application, the Z direction is described as the vertical direction, height direction, or thickness direction of a specific structure. In addition, the expression "plan view" used in the present application means that the plane formed by the X direction and the Y direction is a "plane", and the "plane" is viewed from the Z direction.

[0047] <About inspection examples>

[0048] Next, use Figures 27 to 29 , a detailed explanation is given about the problems of the semiconductor devices in Inspection Examples 1 and 2 studied by the inventors of the present application based on Patent Document 1, etc. It should be noted that the problems identified from Inspection Examples 1 and 2 are unknown in the public domain, but are new insights obtained by the inventors of the present application. Fig. 27 and 28 The semiconductor device of Inspection Example 1 is shown. Fig.29 The semiconductor device of Inspection Example 2 is shown.

[0049] In Check Example 1, if Fig. 27 As shown in FIG. 1 , an insulating film IF1 and a field plate electrode FP are formed inside the trench TR. Fig.28 As shown, the insulating film IF1 inside the trench TR is recessed by isotropic etching. Then, by performing thermal oxidation, the gate insulating film GI and the insulating film IF2 are formed inside the trench TR.

[0050] Next, a conductive film CF2 is deposited to fill the inside of the trench TR, and a gate electrode GE is formed on the upper portion of the trench TR by anisotropically etching the conductive film CF2. A portion of the gate electrode GE is also formed as an embedded portion GEa between the field plate electrode FP and the semiconductor substrate SUB.

[0051] In Inspection Example 1, the isotropic etching of the insulating film IF1 is performed from Fig. 27 The starting point 11 is shown. Therefore, Fig.28 As shown, the position of the portion of the upper surface of the insulating film IF1 located inside the trench TR that contacts the field plate electrode FP is retracted downward from the position of the portion that contacts the side surface of the semiconductor substrate SUB. That is, the position of the portion that contacts the field plate electrode FP is retracted toward the bottom of the trench TR.

[0052] Since the embedded portion GEa of the gate electrode GE is formed along the shape of the upper surface of the insulating film IF1, the shape of the lower end of the embedded portion GEa tends to protrude. Therefore, the electric field tends to be concentrated on Fig.28 At the protruding point 20 shown, the insulation withstand voltage between the gate electrode GE and the field plate electrode FP is degraded, so that leakage current is more likely to occur.

[0053] Furthermore, although the insulating film IF2 is formed by thermal oxidation, oxygen is difficult to reach near the protruding point 20, so that the thickness of the insulating film IF2 is locally thinned. Therefore, it is more difficult to ensure the insulation withstand voltage between the gate electrode GE and the field plate electrode FP.

[0054] In Check Example 2, if Fig.29 As shown, the field plate electrode FP includes a lead portion FPa for electrically connecting to the source electrode. The field plate electrode FP of the lead portion FPa is formed not only at the bottom of the trench TR but also at the top of the trench TR.

[0055] During the formation of the conductive film CF2, the conductive film CF2 is also deposited in the space surrounded by the insulating films IF1, IF2 and the gate insulating film GI. During the anisotropic etching process for forming the gate electrode GE, preferably, all the conductive film CF2 present in the above space is removed, but a portion of the conductive film CF2 may be left as a residue RS.

[0056] During operation of the MOSFET, a source voltage Vs of, for example, 0 V is supplied to the lead portion FPa, and a drain voltage Vd of, for example, 100 V is supplied to the drift region NV (semiconductor substrate SUB). Typically, an insulation withstand voltage between the lead portion FPa and the drift region NV is maintained by the thickness of the insulating film IF1.

[0057] However, when there is an electrically floating residue RS, such as Fig.29 As shown, the capacitance between the lead portion FPa and the residue RS and the capacitance between the residue RS and the drift region NV form a series capacitance. Since a voltage of 100V is applied to the series capacitance, there is a problem that the insulation withstand voltage between the lead portion FPa and the drift region NV cannot be maintained.

[0058] Specifically, when the thickness of the insulating film IF1 is increased to improve the insulation withstand voltage, the isotropic etching process takes longer to recess the insulating film IF1, making it easier for the residue RS to be formed at a deeper position. Moreover, since the space between the gate insulating film GI and the insulating film IF2 becomes wider, it is more likely to form a larger residue RS.

[0059] As described above, by alleviating the electric field concentration at the protruding point 20 , the insulation withstand voltage between the gate electrode GE and the field plate electrode FP can be ensured, and a technique for ensuring the insulation withstand voltage between the lead portion FPa and the drift region NV by suppressing the generation of the residue RS is desired.

[0060] (First embodiment)

[0061] <Structure of semiconductor device>

[0062] The following will use Figures 1 to 5 The structure of the semiconductor device 100 in the first embodiment is described. The semiconductor device 100 includes a MOSFET having a trench gate structure as a semiconductor element. The MOSFET of the first embodiment has a split gate structure provided with a gate electrode GE and a field plate electrode FP.

[0063] The main feature of the present application lies in the manufacturing process of forming the silicon oxide film OX1 on the upper surface of the field plate electrode FP and the manufacturing processes before and after it, which will be described in detail in the following section “Manufacturing method of semiconductor device”.

[0064] Figure 1 and 2 is a plan view of a semiconductor chip serving as the semiconductor device 100 . Figure 3 and 4 Is magnification Figure 1 and 2 A plan view of the main parts of area 1A is shown. Figure 2 and 4 Shows Figure 1 and 3 The structure below is mainly a trench gate structure formed in the semiconductor substrate SUB. Figure 3 The positions of the holes CH1, CH2, and CH3 shown by the dotted lines in FIG. Figure 4 The positions of the holes CH1, CH2, and CH3 shown coincide. Figure 5 It is along Figure 3 and 4 Cross-sections along lines AA and BB are shown.

[0065] Figure 1 The wiring pattern formed above the semiconductor substrate SUB is mainly shown. The semiconductor device 100 has a cell region CR and a peripheral region OR surrounding the cell region CR in a plan view. In the cell region CR, main semiconductor elements such as a plurality of MOSFETs are formed. The peripheral region OR is used to connect the gate wiring GW to the gate electrode GE and is used as a termination region, etc.

[0066] like Figure 1 and 2As shown, most of the cell region CR is covered by the source electrode SE. In a plan view, the gate wiring GW surrounds the source electrode SE. Although not shown here, the source electrode SE and the gate wiring GW are covered by a protective film such as a polyimide film. Some parts of the protective film have openings, and the source electrode SE and the gate wiring GW exposed at these openings become the source pad SP and the gate pad GP. By connecting an external connection member to the source pad SP and the gate pad GP, the semiconductor device 100 is electrically connected to other semiconductor chips, lead frames or wiring substrates, etc. The external connection member is, for example, a wire made of aluminum, gold or copper or a clip made of a copper plate.

[0067] like Figure 4 As shown, a plurality of trenches TR are formed in the semiconductor substrate SUB of the unit region CR. The plurality of trenches are formed in stripes, each trench extending in the Y direction and adjacent to each other in the X direction.

[0068] Likewise Figure 5 As shown in the AA cross section of FIG. 1 , inside the trench TR, a field plate electrode FP is formed at the bottom of the trench TR, and a gate electrode GE is formed at the top of the trench TR. The field plate electrode FP and the gate electrode GE extend in the Y direction along the trench TR.

[0069] Likewise Figure 5 As shown in the BB cross section of FIG. 1 , a portion of the field plate electrode FP in the cell region CR forms a lead portion FPa. Inside the trench TR, the field plate electrode FP forming the lead portion FPa is formed not only at the bottom of the trench TR but also at the top of the trench TR.

[0070] like Figure 2 As shown, a plurality of trenches TR formed in the peripheral region OR extend in the Y and X directions to surround the cell region CR in a plan view. Inside the trenches TR of the peripheral region OR, a field plate electrode FP constituting a lead-out portion FPa is formed.

[0071] In the cell region CR, a hole CH3 is formed on the lead portion FPa. The lead portion FPa is electrically connected to the source electrode SE through the hole CH3. Moreover, in the cell region CR, a hole CH1 is formed on the body region PB and the source region NS described later. The body region PB and the source region NS are electrically connected to the source electrode SE through the hole CH1. In the peripheral region OR, a hole CH2 is formed on the gate electrode GE. The gate electrode GE is electrically connected to the gate wiring GW through the hole CH2.

[0072] The following will use Figure 5 A cross-sectional structure of the semiconductor device 100 is described.

[0073] like Figure 5As shown, the semiconductor device 100 includes an n-type semiconductor substrate SUB having an upper surface TS and a lower surface BS. The semiconductor substrate SUB is made of n-type silicon. The semiconductor substrate SUB has a low-concentration n-type drift region NV. In the first embodiment, the n-type semiconductor substrate SUB itself constitutes the drift region NV. In addition, the semiconductor substrate SUB can be a stack of an n-type silicon substrate and an n-type semiconductor layer grown on an n-type silicon substrate by introducing phosphorus (P) through epitaxial growth. In this case, the low-concentration n-type semiconductor layer constitutes the drift region NV, and the high-concentration n-type silicon substrate constitutes the drain region ND.

[0074] In the semiconductor substrate SUB, an n-type drain region ND is formed to reach a predetermined depth from the lower surface BS of the semiconductor substrate SUB toward the upper surface TS. The drain region ND has a higher impurity concentration than the drift region NV. The drain electrode DE is formed on the lower surface BS of the semiconductor substrate SUB. The drain electrode DE is composed of a single-layer metal film such as an aluminum, titanium, nickel, gold or silver film or a laminated film made by appropriately laminating these metal films. The drain region ND and the drain electrode DE are formed across the cell region CR and the peripheral region OR. A drain potential is supplied from the drain electrode DE to the semiconductor substrate SUB (drain region ND, drift region NV).

[0075] In the semiconductor substrate SUB, a plurality of trenches TR are formed to reach a predetermined depth from the upper surface TS toward the lower surface BS of the semiconductor substrate SUB The depth of each trench TR is, for example, equal to or greater than 5 μm (5 micrometers) and equal to or less than 7 μm (7 micrometers).

[0076] like Figure 5 As shown in the AA cross section of FIG. 1 , inside the trench TR, a field plate electrode FP is formed at the bottom of the trench TR through the insulating film IF1 . The position of the upper surface of the insulating film IF1 is lower than the position of the upper surface of the field plate electrode FP.

[0077] The gate insulating film GI is formed inside the trench TR on the insulating film IF1. The insulating film IF2 is formed to cover the field plate electrode FP exposed from the insulating film IF1. The gate electrode GE is formed on the field plate electrode FP through the insulating film IF2. The field plate electrode FP and the gate electrode GE are respectively made of a polycrystalline silicon film, for example, n-type impurities have been introduced into the polycrystalline silicon film. In addition, the impurity concentration of the polycrystalline silicon film is higher than the impurity concentration of the semiconductor substrate SUB (drift region NV).

[0078] Furthermore, a portion of the gate electrode GE is formed in a space between the field plate electrode FP and the semiconductor substrate SUB and is surrounded by the insulating films IF1, IF2 and the gate insulating film GI. Such a portion of the gate electrode GE is referred to as an embedded portion GEa.

[0079] An insulating film IF1 is formed between the semiconductor substrate SUB and the field plate electrode FP. An insulating film IF2 is formed between the gate electrode GE and the field plate electrode FP. A gate insulating film GI is formed between the semiconductor substrate SUB and the gate electrode GE. By these films, the semiconductor substrate SUB, the gate electrode GE and the field plate electrode FP are electrically insulated from each other.

[0080] In addition, although the insulating film IF3 is formed on the gate electrode GE, when other semiconductor elements such as a resistor element are formed in a region different from the cell region CR, the insulating film IF3 is mainly used as a protective film for protecting the cell region CR. Therefore, if it is not necessary to form other semiconductor elements, it is not necessary to form the insulating film IF3.

[0081] The insulating films IF1, IF2, IF3 and the gate insulating film GI are made of, for example, a silicon oxide film. The thickness of the insulating film IF1 is greater than the thickness of each of the insulating film IF2 and the gate insulating film GI, and is, for example, equal to or greater than 400 nm and equal to or less than 600 nm. The thickness of each of the insulating film IF2 and the gate insulating film GI is, for example, equal to or greater than 50 nm and equal to or less than 70 nm. Note that these thicknesses are thicknesses inside the trench TR and in the X direction.

[0082] In the semiconductor substrate SUB, a p-type body region PB is formed to a certain depth from the upper surface TS of the semiconductor substrate SUB toward the lower surface BS of the semiconductor substrate SUB. The depth of the body region PB from the upper surface TS of the semiconductor substrate SUB is shallower than the depth of the trench TR from the upper surface TS of the semiconductor substrate SUB. In the body region PB, an n-type source region NS is formed. The source region NS has a higher impurity concentration than the drift region NV.

[0083] On the upper surface TS of the semiconductor substrate SUB, an interlayer insulating film IL is formed to cover the trench TR. The interlayer insulating film IL is made of, for example, a silicon oxide film. The thickness of the interlayer insulating film IL is, for example, equal to or greater than 700 nm and equal to or less than 900 nm.

[0084] In the interlayer insulating film IL, a hole CH1 is formed, which extends through the interlayer insulating film IL and the source region NS and reaches the body region PB. At the bottom of the hole CH1, a high concentration diffusion region PR is formed in the body region PB. The high concentration diffusion region PR has a higher impurity concentration than the body region PB. The high concentration diffusion region PR is provided mainly to reduce the contact resistance with the plug PG and prevent latch-up.

[0085] A source electrode SE is formed on the interlayer insulating film IL. The source electrode SE is electrically connected to the source region NS, the body region PB, and the high-concentration diffusion region PR through the hole CH1, and supplies a source potential to these impurity regions.

[0086] like Figure 5 As shown in the BB cross section of FIG. , a part of the field plate electrode FP constitutes the lead portion FPa of the field plate electrode FP. The upper surface of the insulating film IF1 in contact with the lead portion FPa is located higher than the upper surface of the insulating film IF1 in contact with the field plate electrode FP other than the lead portion FPa.

[0087] The insulating film IF2 is formed to cover the lead-out portion FPa exposed from the insulating film IF1. The insulating film IF3 is formed on the insulating film IF1, but as mentioned above, the insulating film IF3 does not need to be formed. Moreover, a body region PB is formed in the semiconductor substrate SUB adjacent to the lead-out portion FPa, but a source region NS is not formed in the body region PB.

[0088] In the interlayer insulating film IL, a hole CH3 is formed which extends through the interlayer insulating film IL, the insulating film IF3 and the insulating film IF2 and reaches the lead-out portion FPa. The source electrode SE is electrically connected to the lead-out portion FPa through the hole CH3 and supplies a source potential to the field plate electrode FP.

[0089] Although not shown here, in the interlayer insulating film IL, a hole CH2 is formed which extends through the interlayer insulating film IL and the insulating film IF3 and reaches the gate electrode GE. The gate wiring GW is electrically connected to the gate electrode GE through the hole CH2 and supplies a gate potential to the gate electrode GE.

[0090] Inside each of the holes CH1, CH2, and CH3, a plug PG is embedded. The plug PG is composed of, for example, a first barrier metal film and a first conductive film formed on the first barrier metal film. The first barrier metal film is composed of, for example, a laminated film of a titanium film and a titanium nitride film. The first conductive film is, for example, a tungsten film.

[0091] The source electrode SE and the gate wiring GW are composed of, for example, a second barrier metal film and a second conductive film formed on the second barrier metal film. The second barrier metal film is, for example, a titanium tungsten film. The second conductive film is, for example, an aluminum alloy film to which copper or silicon is added.

[0092] <Method for manufacturing semiconductor device>

[0093] The following uses Figures 6 to 21 Each manufacturing process included in the manufacturing method of the semiconductor device 100 is described.

[0094] First, an n-type semiconductor substrate SUB having an upper surface TS and a lower surface BS is prepared. As mentioned above, the semiconductor substrate SUB may be a stack of an n-type silicon substrate and an n-type semiconductor layer formed on the silicon substrate by epitaxial growth.

[0095] Next, a silicon oxide film is formed on the semiconductor substrate SUB by, for example, a CVD (chemical vapor deposition) method. Then, the silicon oxide film is patterned by using a photolithography technique and an anisotropic etching process to form a hard mask HM. Then, as shown in FIG. Figure 6 As shown, a trench TR is formed in the semiconductor substrate SUB by performing an anisotropic etching process using the hard mask HM as a mask to reach a predetermined depth from the upper surface TS to the lower surface BS of the semiconductor substrate SUB. Thereafter, the hard mask HM is removed by a wet etching process using a solution including hydrofluoric acid, for example.

[0096] Next, if Figure 7 As shown, an insulating film IF1 is formed inside the trench TR and on the upper surface TS of the semiconductor substrate SUB. The insulating film IF1 is, for example, a silicon oxide film formed by a thermal oxidation process. The thickness of the insulating film IF1 on the upper surface TS of the semiconductor substrate SUB is, for example, equal to or greater than 400 nm and equal to or less than 600 nm. In addition, the insulating film IF1 may be a laminated film consisting of a first silicon oxide film formed by a thermal oxidation process and a second silicon oxide film formed on the first silicon oxide film by film formation using a CVD method.

[0097] Next, a conductive film CF1 is formed on the insulating film IF1, for example, by film formation using a CVD method, to fill the inside of the trench TR. The conductive film CF1 is, for example, an n-type polysilicon film. In addition, the impurity concentration of the polysilicon film is higher than the impurity concentration of the semiconductor substrate SUB (drift region NV). In order to satisfactorily embed the conductive film CF1 inside the trench TR, the formation of the conductive film CF1 may be divided into multiple times, such as the formation of a first polysilicon film and the formation of a second polysilicon film.

[0098] Next, if Figure 8 As shown, by removing the conductive film CF1 located outside the trench TR, the conductive film CF1 remaining inside the trench TR is formed as the field plate electrode FP.

[0099] Specifically, first, the conductive film CF1 formed outside the trench TR is removed by polishing using, for example, a CMP (Chemical Mechanical Polishing) method. 6 The gas performs anisotropic etching, and the position of the upper surface of the conductive film CF1 inside the trench TR is retracted toward the bottom of the trench TR ( Figure 8 ). This forms the conductive film CF1 remaining inside the trench TR as the field plate electrode FP.

[0100] Next, if Fig. 9 As shown, another portion of the field plate electrode FP is selectively retracted so that a portion of the field plate electrode remains as the lead-out portion FPa.

[0101] Specifically, first, Fig. 9 As shown in the BB cross section of FIG. 1 , a resist pattern RP1 is formed to selectively cover a portion of the field plate electrode FP that will become the lead portion FPa. Then, using the resist pattern RP1 as a mask, by using, for example, SF 6 The gas performs anisotropic etching to remove the other portion of the field plate electrode FP that will not become the lead-out portion FPa. Fig. 9 As shown in the AA cross section, the other portion of the field plate electrode FP that will not become the lead-out portion FPa is selectively retracted toward the bottom of the trench TR ( Fig. 9 ). The unretracted portion of the field plate electrode FP becomes the lead-out portion FPa. Thereafter, the resist pattern RP1 is removed by ashing.

[0102] Next, if Fig.10 As shown, the silicon oxide film OX1 is formed on the upper surface of the field plate electrode FP by thermal oxidation treatment. The thermal oxidation treatment is a wet oxidation process performed using water vapor under the condition of at least 850 degrees Celsius but not more than 950 degrees Celsius. In addition, this thermal oxidation treatment increases the thickness of the insulating film IF1 formed above the field plate electrode FP.

[0103] The thermal oxidation process rounds the upper portion of the field plate electrode FP. In addition, the width of the upper portion of the field plate electrode FP is narrowed in the X direction in accordance with the thickness of the silicon oxide film OX1.

[0104] The upper portion of the field plate electrode FP includes the upper surface of the field plate electrode FP and a portion of the side surface of the field plate electrode FP continuous with the upper surface. In other words, the upper portion of the field plate electrode FP is a region of the field plate electrode FP exposed from the insulating film IF1.

[0105] also, Fig.10 The starting point 10 of the isotropic etching process performed on the insulating film IF1 and the silicon oxide film OX1 is shown. It should be noted that etching in the isotropic etching process is performed on the entire surface of the insulating film IF1 and the silicon oxide film OX1, but the starting point 10 described here refers to a position that particularly affects the shape of the insulating film IF1 at the location that eventually contacts the field plate electrode FP.

[0106] exist Fig.10 After the fabrication process, by performing isotropic etching, such as Fig.11 As shown, the silicon oxide film OX1 is removed, the thickness of the insulating film IF1 is reduced, and the upper part of the field plate electrode FP is exposed from the insulating film IF1. The isotropic etching process is, for example, a wet etching process using a solution including hydrofluoric acid. At this time, the insulating film IF1 on the upper surface TS of the semiconductor substrate SUB and inside the trench TR is not completely removed.

[0107] Next, isotropic etching is performed on the upper portion of the field plate electrode FP exposed from the insulating film IF1. This isotropic etching process is performed using CF 4 Gas chemical dry etching process. Fig.12 As shown, the upper portion of the field plate electrode FP is further rounded.

[0108] Furthermore, during this isotropic etching process, the thinned insulating film IF1 on the upper surface TS of the semiconductor substrate SUB and inside the trench TR serves as an etching stopper, and thus the semiconductor substrate SUB is not exposed to the isotropic etching process.

[0109] Next, the insulating film IF1 is isotropically etched using a solution including hydrofluoric acid. Fig.13 As shown, the insulating film IF1 located on the upper surface TS of the semiconductor substrate SUB is removed, and the insulating film IF1 located inside the trench TR is retracted toward the bottom of the trench TR ( Fig.13 In the first embodiment, as shown in the arrow in FIG. Fig.13 As shown, the insulating film IF1 located inside the trench TR is retracted toward the bottom of the trench TR so that the upper surface position of the insulating film IF1 located inside the trench TR is lower than the upper surface position of the field plate electrode FP in the cross-sectional view.

[0110] At this time, the position of the upper surface of the insulating film IF1 in contact with the field plate electrode FP other than the lead-out portion FPa is lower than the position of the lower surface of the insulating film IF1 in contact with the lead-out portion FPa.

[0111] It should be noted that Fig.11 and 12 The manufacturing process is not essential and can be omitted. Fig.10 After the manufacturing process, by performing Fig.13 In the manufacturing process, the insulating film IF1 and the silicon oxide film OX1 located on the upper surface TS of the semiconductor substrate SUB can be removed, and the insulating film IF1 located inside the trench TR can be retracted toward the bottom of the trench TR.

[0112] However, by executing Fig.11 and 12 In the manufacturing process shown, although the number of steps increases, the upper portion of the field plate electrode FP is further rounded, making it easier to make the electric field between the gate electrode GE and the field plate electrode FP uniform.

[0113] In addition, if Fig.10If the thermal oxidation process shown is a wet oxidation process, it is easier to ensure the thickness of the silicon oxide film OX1, but the thickness of the silicon oxide film OX1 may vary. In this case, after the silicon oxide film OX1 is removed, the surface of the field plate electrode FP becomes rough. By performing Fig.12 The isotropic etching process shown can further round the upper portion of the field plate electrode FP and make the surface of the field plate electrode FP smooth.

[0114] You can also Fig.10 The thermal oxidation process shown is performed as a dry oxidation process. The dry oxidation process is performed, for example, using oxygen gas under conditions equal to or greater than 1000 degrees Celsius and equal to or less than 1200 degrees Celsius. In the dry oxidation process, the uniformity of the thickness of the silicon oxide film OX1 is higher than that of the wet oxidation process. Therefore, after the silicon oxide film OX1 is removed, the surface of the field plate electrode FP is less likely to become rough. However, in the dry oxidation process, since the effect of accelerating oxidation is small, it is difficult to make the thickness of the silicon oxide film OX1 thicker than that of the wet oxidation process. Therefore, from the perspective of raising the position of the starting point 10, rounding the upper part of the field plate electrode FP, and narrowing the width of the upper part of the field plate circuit FP, the wet oxidation process is superior to the dry oxidation process.

[0115] Fig.11 The isotropic etching process shown in Fig.10 The starting point 10 is shown. Or, if omitted Fig.11 and 12 The manufacturing process shown is Fig.13 The isotropic etching process shown in Fig.10 In any case, Fig.13 At the end of the isotropic etching process shown in Fig.13 As shown in , the upper surface of the insulating film IF1 forms a curve which rises as it approaches the semiconductor substrate SUB and rises as it approaches the field plate electrode FP.

[0116] Next, if Fig.14 As shown, the gate insulating film GI is formed on the upper surface TS of the semiconductor substrate SUB and inside the trench TR located on the insulating film IF1, and the insulating film IF2 is formed to cover the field plate electrode FP exposed from the insulating film IF1.

[0117] The gate insulating film GI and the insulating film IF2 are formed by a thermal oxidation process such as dry oxidation. The dry oxidation process is performed, for example, using oxygen gas under conditions equal to or greater than 1000 degrees Celsius and equal to or less than 1200 degrees Celsius. In addition, the gate insulating film GI and the insulating film IF2 may be a laminated film of a third silicon oxide film formed by a dry oxidation process and a fourth silicon oxide film formed on the third silicon oxide film by a film formation process using CVD.

[0118] Next, if Fig.15 As shown, for example, by a film forming process using CVD, a conductive film CF2 is formed on the gate insulating film GI, the insulating film IF2, and the insulating film IF1 to fill the inside of the trench TR. The conductive film CF2 is, for example, an n-type polysilicon film. In addition, the impurity concentration of the polysilicon film is higher than the impurity concentration of the semiconductor substrate SUB (drift region NV).

[0119] Next, a polishing process is performed on the conductive film CF2 using a CMP method. As a result, the thickness of the conductive film CF2 is reduced, and the upper surface of the conductive film CF2 is flattened. Next, by performing anisotropic etching on the conductive film CF2, the conductive film CF2 located outside the trench TR is removed. Fig.16 As shown in FIG. 1 , the conductive film CF2 remaining inside the trench TR on the field plate electrode FP is formed as the gate electrode GE. Fig.16 As shown in the AA cross section of FIG. 1 , a part of the gate electrode GE is formed as the embedded portion GEa in a space surrounded by the insulating films IF1 , IF2 and the gate insulating film GI between the field plate electrode FP and the semiconductor substrate SUB.

[0120] Note that in order to completely remove the conductive film CF2 outside the trench TR, an anisotropic etching process is performed using overetching. Fig.16 As shown in the AA cross section of FIG. 1 , the position of the upper surface of the gate electrode GE becomes lower than the position of the upper surface TS of the semiconductor substrate SUB. Fig.16 As shown in the BB cross section of FIG. 1 , the conductive film CF2 formed on the insulating films IF1 and IF2 in contact with the lead-out portion FPa is removed by the anisotropic etching process.

[0121] <Main Features of First Embodiment>

[0122] Next, main features of the first embodiment are described in comparison with Examination Example 1 and Examination Example 2.

[0123] As mentioned above, in the inspection example 1, the isotropic etching process on the insulating film IF1 is performed from Fig. 27 The starting point 11 is shown. Therefore, Fig.28As shown in FIG. 1 , the position of the portion of the upper surface of the insulating film IF1 located inside the trench TR that contacts the field plate electrode FP is recessed downward compared to the position of the portion that contacts the side surface of the semiconductor substrate SUB. Subsequently, when the gate electrode GE is formed of the conductive film CF2, the shape of the lower end of the embedded portion GEa tends to protrude, making it easier for the electric field to be concentrated on the lower end of the embedded portion GEa. Fig.28 At the protruding point 20 shown. In addition, near the protruding point 20, oxygen becomes difficult to reach, so that the thickness of the insulating film IF2 is locally thinned. Therefore, in the inspection example 1, there is a problem in ensuring the insulation withstand voltage between the gate electrode GE and the field plate electrode FP.

[0124] In the first embodiment, by executing Fig.10 The thermal oxidation process shown forms a silicon oxide film OX1 on the upper surface of the field plate electrode FP. Therefore, the isotropic etching process performed on the insulating film IF1 and the silicon oxide film OX1 is performed from the starting point 10 which is higher than the starting point 11 of the inspection example 1.

[0125] Therefore, in Fig.13 At the end of the isotropic etching process shown in FIG. 1 , the upper surface of the insulating film IF1 forms a curved surface that rises as it approaches the semiconductor substrate SUB and also rises as it approaches the semiconductor substrate SUB. Fig.13 The X direction shown in FIG. 1 is approached to the field plate electrode FP. Note that when a film formation process using a CVD method is applied to form the insulating film IF1, the etching rate of the CVD film during the isotropic etching process is faster than that of the thermal oxidation treatment film, making it easier to form the above-mentioned curved surface. Fig.16 As shown in the AA cross section of FIG. 1 , even when the gate electrode GE is formed of the conductive film CF2, the shape of the lower end of the embedded portion GEa does not become protruding. Therefore, the problem that the electric field tends to concentrate at the protruding portion 20 (near the insulating film IF1) in the inspection example 1 is solved.

[0126] Even if the thickness of the insulating film IF2 is thin near the insulating film IF1, the thickness can be supplemented by the insulating film IF1. Therefore, the insulation withstand voltage between the gate electrode GE and the field plate electrode FP can be ensured, and the reliability of the semiconductor device 100 can be improved.

[0127] Moreover, by executing Fig.10 The upper portion of the field plate electrode FP is rounded by a thermal oxidation process. Fig.12 In the embodiment, by performing isotropic etching on the upper portion of the field plate electrode FP, the upper portion of the field plate electrode FP is further rounded. Therefore, the electric field is less likely to be concentrated between the gate electrode GE and the field plate electrode FP. That is, since the electric field between the gate electrode GE and the field plate electrode FP is more easily uniform, the insulation withstand voltage between them can be further ensured.

[0128] In Check Example 2, if Fig.29 As shown, during the formation of the conductive film CF2 around the lead-out portion FPa, the conductive film CF2 is also deposited in the space surrounded by the insulating film IF1, the insulating film IF2 and the gate insulating film GI. There is a problem that a portion of the conductive film CF2 existing in the space cannot be removed by anisotropic etching, leaving a residue RS.

[0129] In the first embodiment, the aspect ratio of the above-mentioned space is lower than that in the inspection example 2. Therefore, as Fig.16 As shown in the BB cross section of FIG. 1 , when anisotropic etching is performed on the conductive film CF2, the conductive film CF2 formed on the insulating film IF1 and the insulating film IF2 in contact with the lead-out portion FPa can be completely removed.

[0130] The reason why the aspect ratio of the above space is low is firstly due to Fig.10 The width of the upper portion of the lead-out portion FPa becomes narrower by performing a thermal oxidation process. Fig.10 Thermal oxidation process and Fig.12 The isotropic etching process of the lead-out portion FPa is rounded. These processes result in a wider opening of the above-mentioned space.

[0131] Next, during the isotropic etching process, since the starting point 10 of the first embodiment is at a high position, the depth of the above-mentioned space becomes shallower than that of the inspection example 2. Next, in the inspection example 2, as shown in FIG. Fig.29 As shown in FIG. 1 , since the upper surface of the insulating film IF1 in contact with the lead-out portion FPa is recessed downward, the shape of the lower end of the residue RS tends to protrude, thereby forming a deeper residue RS. Figure 13 to Figure 16 As shown in the BB cross section of FIG. 1 , the upper surface of the insulating film IF1 rises as it approaches the lead-out portion FPa. Therefore, since there is no conductive film CF2 that becomes protruding, it is easier to remove the conductive film CF2 by anisotropic etching.

[0132] Therefore, in the first embodiment, since the generation of the residue RS can be suppressed, the insulation withstand voltage between the lead portion FPa and the drift region NV (semiconductor substrate SUB) can be maintained, and the reliability of the semiconductor device 100 can be improved.

[0133] exist Fig.16 After the manufacturing process, Fig.17 As shown, for example, by a film formation process using a CVD method, an insulating film IF3 is formed on the gate insulating film GI, the gate electrode GE, the insulating film IF2, and the insulating film IF1 so as to cover the trench TR.

[0134] Next, if Fig.18As shown, anisotropic etching is performed on the insulating film IF3. Therefore, the insulating film IF3 and the gate insulating film GI on the upper surface TS of the semiconductor substrate SUB are removed. Fig.18 As shown in the AA cross section of FIG. 1 , the insulating film IF3 is left on the gate electrode GE so as to contact the gate insulating film GI. Fig.18 As shown in the BB cross section of FIG. 1 , the insulating film IF3 is left on the insulating films IF2 and IF1 so as to contact the gate insulating film GI.

[0135] Next, if Fig.19 As shown, a p-type body region PB is selectively formed in the semiconductor substrate SUB by introducing boron (B) using photolithography and ion implantation techniques, for example. Starting from the upper surface TS of the semiconductor substrate SUB, the body region PB is formed shallower than the depth of the trench TR.

[0136] Next, arsenic (As) is introduced, for example, by using photolithography and ion implantation techniques, such as Fig.19 As shown in the AA cross section of FIG. 1 , an n-type source region NS is selectively formed in the body region PB of the cell region CR. Note that Fig.19 As shown in the BB cross section of FIG. 1 , the source region NS is not formed in the body region PB adjacent to the lead-out portion FPa. Subsequently, by heat-treating the semiconductor substrate SUB, impurities included in the source region NS and the body region PB are activated.

[0137] Next, if Fig. 20 As shown, an interlayer insulating film IL is formed on the upper surface TS of the semiconductor substrate SUB by, for example, a CVD method so as to cover the trench TR.

[0138] Then, holes CH1, CH2, CH3 are formed in the interlayer insulating film IL. Specifically, first, a resist pattern having a pattern that opens the semiconductor substrate SUB forming the source region NS is formed on the interlayer insulating film IL. Next, anisotropic etching is performed by using the resist pattern as a mask to form a hole CH1 that extends through the interlayer insulating film IL and the source region NS and reaches the inside of the body region PB. Next, boron (B) is introduced into the body region PB at the bottom of the hole CH1 by using ion implantation, for example, to form a p-type high-concentration diffusion region PR. Thereafter, the resist pattern is removed by ashing.

[0139] Next, a resist pattern having an opening pattern is formed on the interlayer insulating film IL, the lead-out portion FPa, and the gate electrode GE. Next, anisotropic etching is performed by using the resist pattern as a mask to form a hole CH3 that extends through the interlayer insulating film IL, the insulating film IF3, and the insulating film IF2 and reaches the lead-out portion FPa. Although not shown here, a hole CH2 is also formed in the manufacturing process of forming the hole CH3. The hole CH2 extends through the interlayer insulating film IL and the insulating film IF3 and reaches the gate electrode GE. Thereafter, the resist pattern is removed by ashing.

[0140] Note that any one of the formation of the hole CH1 and the formation of the hole CH2 and the hole CH3 may be performed first.

[0141] Next, if Fig.21 As shown, a plug PG is formed inside each of the holes CH1 , CH2 , and CH3 , and a source electrode SE and a gate wiring GW are formed on the interlayer insulating film IL.

[0142] Specifically, first, a first barrier metal film is formed inside the holes CH1, CH2, CH3 and on the interlayer insulating film IL by a film forming process using sputtering or CVD. The first barrier metal film is composed of, for example, a laminated film of a titanium nitride film and a titanium film. Next, a first conductive film is formed on the first barrier metal film by a film forming process using CVD. The first conductive film is composed of, for example, a tungsten film. Next, the first barrier metal film and the first conductive film formed outside the holes CH1, CH2, CH3 are removed by CMP or anisotropic etching. Thus, a plug PG composed of the first barrier metal film and the first conductive film is formed to fill the inside of the holes CH1, CH2, CH3.

[0143] Next, a second barrier metal film is formed on the interlayer insulating film IL by sputtering. The second barrier metal film is composed of, for example, a titanium tungsten film. Next, a second conductive film is formed on the second barrier metal film by sputtering. The second conductive film is, for example, an aluminum alloy film to which copper or silicon is added. Next, a source electrode SE and a gate wiring GW are formed by patterning the second barrier metal film and the second conductive film.

[0144] Next, although not shown here, a protective film made of, for example, a polyimide film is formed on the source electrode SE and the gate wiring GW by, for example, a coating method. By forming an opening in a portion of the protective film, the region that becomes the source pad SP and the gate pad GP in the source electrode SE and the gate wiring GW is exposed.

[0145] Then, through the following manufacturing process, we obtained Figure 5The structure shown. First, if necessary, the lower surface BS of the semiconductor substrate SUB is polished. Next, arsenic (As), for example, is introduced by ion implantation to form an n-type drain region ND on the lower surface BS of the semiconductor substrate SUB. Note that if the semiconductor substrate SUB is composed of a stack of an n-type silicon substrate and an n-type semiconductor layer, since the high-concentration n-type silicon substrate constitutes the drain region ND, the above-mentioned formation of the drain region ND by ion implantation can be omitted. Next, a drain electrode DE is formed on the lower surface BS of the semiconductor substrate SUB by sputtering.

[0146] (Modified example)

[0147] The following uses Fig. 22 A semiconductor device 100 in a modified example of the first embodiment is described.

[0148] In the first embodiment, the plurality of trenches TR in the cell region CR extend in the Y direction to form a stripe shape. Fig. 22 As shown, there are a plurality of sections where the trenches TR extend in the X direction, and the plurality of trenches TR are interconnected to form a grid. The technology disclosed in the first embodiment can also be applied to the structure of the trenches TR in the modified example.

[0149] (Second embodiment) The following uses Fig.23 A semiconductor device 100 in the second embodiment is described. Note that in the following description, the differences from the first embodiment will be mainly described, and the description of overlapping points with the first embodiment will be omitted.

[0150] In the second embodiment, Fig. 9 Manufacturing process and Fig.10 An ion implantation process is added between the manufacturing processes. Fig. 9 After forming the field plate electrode FP including the lead-out portion FPa, as shown in FIG. Fig.23 As shown, n-type impurities such as arsenic (As) or phosphorus (P) are introduced into the field plate electrode FP including the lead-out portion FPa by ion implantation. Therefore, the impurity concentration of the n-type polysilicon film constituting the field plate electrode FP becomes higher than that of the configuration of the first embodiment.

[0151] Then, execute Fig.10 Since the impurity concentration of the field plate electrode FP in the second embodiment is higher than that in the first embodiment, the effect of enhancing oxidation becomes greater. Therefore, even when the thermal oxidation process is performed under the same conditions as in the first embodiment, the thickness of the silicon oxide film OX1 can be further increased.

[0152] Therefore, since the position of the starting point 10 can be made higher, the depth of the space surrounded by the insulating films IF1, IF2 and the gate insulating film GI around the lead-out portion FPa can be reduced. In addition, since the top of the field plate electrode FP can be further rounded and the width of the top of the field plate electrode FP can be narrower, the opening width of the above space can be further widened. In other words, according to the second embodiment, it becomes easier to further suppress the generation of the residue RS.

[0153] In the second embodiment, the wet etching process is used instead of the Fig.10 The thermal oxidation process can achieve higher results.

[0154] (Third Embodiment)

[0155] The following uses Fig.24 A semiconductor device 100 in the third embodiment is described. Note that in the following description, the differences from the first embodiment will be mainly described, and the description of overlapping points with the first embodiment will be omitted.

[0156] In the third embodiment, when executing Fig.10 After the thermal oxidation process, Fig.24 As shown, by a film forming process using CVD, for example, a further silicon oxide film OX2 is formed on the insulating film IF1 and the silicon oxide film OX1. Fig.24 As shown in the AA cross section, the silicon oxide film OX2 is formed so as not to completely fill the inside of the trench TR.

[0157] By forming the silicon oxide film OX2, the step between the insulating film IF1 and the silicon oxide film OX1 on the upper surface TS of the semiconductor substrate SUB is reduced. By performing isotropic etching in a state where the upper surfaces of these films are as flat as possible, Fig.13 After the manufacturing process, it is easier to shape the upper surface of the insulating film IF1 into a curved surface. Therefore, in the inspection example 1, it is easier to reduce the electric field concentration at the protruding point 20 (near the insulating film IF1) and further ensure the insulation withstand voltage between the gate electrode GE and the field plate electrode FP.

[0158] Furthermore, since the position of the starting point 10 can be further raised, the depth of the space surrounded by the insulating films IF1, IF2 and the gate insulating film GI around the lead-out portion FPa can be reduced. That is, according to the third embodiment, it becomes easier to suppress the generation of the residue RS.

[0159] exist Fig.11 During the isotropic etching process, the silicon oxide film OX2 is removed together with the silicon oxide film OX1. Fig.11 and 12 The manufacturing process is Fig.13 During the isotropic etching process of FIG. 1 , the silicon oxide film OX2 is removed together with the silicon oxide film OX1.

[0160] Note that the technology of the third embodiment can be applied in combination with the technology of the second embodiment.

[0161] (Fourth Embodiment) Fig.25 and 26 A semiconductor device 100 in a fourth embodiment is described. Note that in the following description, differences from the first embodiment will be mainly described, and description of overlapping points with the first embodiment will be omitted.

[0162] In the fourth embodiment, Fig.12 Before the chemical dry etching process, Fig.10 Thermal oxidation process and Fig.11 The isotropic etching process is repeated multiple times. Fig.11 After the isotropic etching process, Fig.25 As shown, in Fig.10 Under the same conditions, the silicon oxide film OX1 is formed again on the upper surface of the field plate electrode FP by a thermal oxidation process. In addition, the thermal oxidation process also increases the thickness of the thinned insulating film IF1.

[0163] Next, if Fig.26 As shown, by Fig.11 The isotropic etching process is performed under the same conditions, the silicon oxide film OX1 is removed, the thickness of the insulating film IF1 is reduced, and the upper portion of the field plate electrode FP is exposed from the insulating film IF1.

[0164] By forming the silicon oxide film OX1 again, the upper portion of the field plate electrode FP can be further rounded and the width of the upper portion of the field plate electrode FP can be narrowed. This allows the opening width of the space surrounded by the insulating films IF1, IF2 and the gate insulating film GI around the lead-out portion FPa to be further widened. That is, according to the fourth embodiment, it becomes easier to suppress the generation of the residue RS.

[0165] Note that if you omit Fig.11 and 12 manufacturing process, then Fig.10 Thermal oxidation process and Fig.13 The isotropic etching process is repeated multiple times.

[0166] Furthermore, the technology of the fourth embodiment may be applied in combination with the technologies of the second embodiment and the third embodiment.

[0167] Therefore, although the present invention has been specifically described based on the embodiments, the present invention is not limited to these embodiments, and various modifications can be made without departing from the gist thereof.

Claims

1. A method for manufacturing a semiconductor device, comprising: (a) providing a semiconductor substrate of a first conductivity type, the semiconductor substrate having an upper surface and a lower surface; (b) after (a), forming a trench in the semiconductor substrate to reach a predetermined depth from the upper surface of the semiconductor substrate toward the lower surface of the semiconductor substrate; (c) after (b), forming a first insulating film on the upper surface of the semiconductor substrate and inside the trench; (d) after (c), forming a first conductive film on the first insulating film to fill the inside of the trench; (e) after (d), removing the first conductive film outside the trench to form the first conductive film remaining inside the trench as a field plate electrode; (f) after (e), a portion of the field plate electrode is retained as a lead-out portion, and the other portion of the field plate electrode is selectively retracted toward the bottom of the trench; (g) after (f), forming a first silicon oxide film on the upper surface of the field plate electrode by thermal oxidation; (h) after (g), removing the first silicon oxide film and the first insulating film located on the upper surface of the semiconductor substrate, and retracting the first insulating film located inside the trench toward the bottom of the trench, so that in a cross-sectional view, the position of the upper surface of the first insulating film located inside the trench is lower than the position of the upper surface of the field plate electrode; (i) after (h), forming a gate insulating film inside the trench on the first insulating film, and forming a second insulating film to cover the field plate electrode exposed from the first insulating film; (j) after (i), forming a second conductive film on the gate insulating film, the second insulating film, and the first insulating film to fill the inside of the trench; as well as (k) after (j), removing the second conductive film outside the trench to form the second conductive film inside the trench remaining on the field plate electrode as a gate electrode, The second conductive film formed on the first insulating film and the second insulating film in contact with the lead portion by (j) is removed by (k).

2. The method for manufacturing a semiconductor device according to claim 1, wherein the thermal oxidation process in (g) is performed using water vapor under the condition of higher than 850 degrees Celsius and lower than 950 degrees Celsius.

3. The method for manufacturing a semiconductor device according to claim 2, wherein (h) comprises: (h1) after (g), removing the first silicon oxide film, reducing the thickness of the first insulating film, and exposing the upper portion of the field plate electrode from the first insulating film; (h2) after (h1), performing an isotropic etching process on the upper portion of the field plate electrode exposed from the first insulating film; as well as (h3) After (h2), the first insulating film located on the upper surface of the semiconductor substrate is removed, and the first insulating film located inside the trench is retracted toward the bottom of the trench, so that in a cross-sectional view, the position of the upper surface of the first insulating film located inside the trench is lower than the position of the upper surface of the field plate electrode. 4 . The method of manufacturing a semiconductor device according to claim 3 , wherein the first insulating film is a silicon oxide film, and (h1) and (h3) are performed by an isotropic etching process using a solution including hydrofluoric acid.

5. The method for manufacturing a semiconductor device according to claim 4, wherein the field plate electrode is made of a polysilicon film, and the isotropic etching process in (h2) is a chemical dry etching process using CF4 gas. 6 . The method of manufacturing a semiconductor device according to claim 5 , wherein the upper portion of the field plate electrode is rounded by the chemical dry etching process.

7. The method for manufacturing a semiconductor device according to claim 3, further comprising: (l) Between (f) and (g), introducing impurities of the first conductivity type into the field plate electrode by ion implantation.

8. The method for manufacturing a semiconductor device according to claim 3, further comprising: (m) between (g) and (h1), forming a second silicon oxide film on the first insulating film and the first silicon oxide film by a film forming process using CVD, In (h1), the second silicon oxide film is removed together with the first silicon oxide film.

9. The method for manufacturing a semiconductor device according to claim 3, wherein: After repeating (g) and (h1) multiple times, (h2) is performed.

10. The method for manufacturing a semiconductor device according to claim 2, further comprising: (n) Between (f) and (g), introducing impurities of the first conductivity type into the field plate electrode by ion implantation.

11. The method for manufacturing a semiconductor device according to claim 1, further comprising: (o) between (g) and (h), forming a second silicon oxide film on the first insulating film and the first silicon oxide film by film formation using a CVD method, In (h), the second silicon oxide film is removed together with the first silicon oxide film.

12. The method for manufacturing a semiconductor device according to claim 1, wherein: After repeating (g) and (h) multiple times, (i) is executed.

13. The method of manufacturing a semiconductor device according to claim 1, wherein the thermal oxidation of (g) is performed using oxygen gas under the condition of at least 1000 degrees Celsius and not more than 1200 degrees Celsius.

14. The method for manufacturing a semiconductor device according to claim 1, wherein (e) comprises: (e1) polishing the first conductive film located outside the groove; as well as (e2) After (e1), the position of the upper surface of the first conductive film inside the trench is retracted toward the bottom of the trench by anisotropic etching.

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