Manufacturing process of semiconductor electronic equipment integrated with different electronic components and semiconductor electronic equipment

Abstract

The invention relates to a manufacturing process of a semiconductor electronic device integrating different electronic components and the semiconductor electronic device. In order to manufacture a semiconductor electronic device, a wafer is provided having a substrate layer of a semiconductor material, the substrate layer having a first portion and a second portion different from the first portion. An epitaxial region of a single semiconductor material is grown on a first portion of a substrate layer. An epitaxial multilayer having a heterostructure is grown on the second portion of the substrate layer. From the epitaxial region, a first electronic component based on a single semiconductor material is formed, and from the heterostructure, a second electronic component based on the heterostructure is formed. Forming a growth mask on the substrate layer in order to grow the epitaxial multilayer; making an opening in the growth mask, thereby exposing a second portion of the substrate layer; and growing an epitaxial multilayer on the second portion of the substrate layer.

Description

Technical Field

[0001] The present disclosure relates to a manufacturing process of a semiconductor electronic device integrating different electronic components and to a semiconductor electronic device. Background Art

[0002] Semiconductor electronic devices are known which comprise active and / or passive electronic components based on silicon (eg CMOS transistors, DMOS transistors, BJTs, diodes, resistors etc.) which are integrated in the same silicon die and obtained, for example, via BCD (Bipolar-CMOS-DMOS) technology.

[0003] In practice, the operation of such electronic components is based on the electronic properties of a single semiconductor material: silicon.

[0004] The device monolithically integrates digital circuits, analog circuits, and power circuits on the same die, which operate at voltages that are very different from each other, such as from a few volts in the case of CMOS transistors for implementing logic functions to hundreds of volts in the case of DMOS transistors for power applications.

[0005] Silicon-based electronic components are integrated in <100> In the single crystal silicon region grown on a silicon wafer.

[0006] Semiconductor electronic devices including heterostructure-based electronic components such as HEMTs (High Electron Mobility Transistors) are also known.

[0007] In practice, the operation of such electronic components is based on the electronic properties of a heterojunction between two different semiconductor materials.

[0008] In detail, in HEMT, the conductive channel is based on the formation of a two-dimensional electron gas (2DEG) layer with high-mobility electrons formed at a heterojunction (i.e., at the interface between semiconductor materials with different band gaps). For example, HEMT is known to be based on a heterojunction between an aluminum gallium nitride (AlGaN) layer and a gallium nitride (GaN) layer.

[0009] HEMT devices, especially those based on AlGaN / GaN heterojunctions or heterostructures, have several advantages that make them particularly suitable and widely used in different applications. For example, the high breakdown threshold of HEMT devices is used for high-performance power switches; the high mobility of electrons in the conducting channel enables high-frequency amplifiers; in addition, the high concentration of electrons in the 2DEG allows for low on-state resistance (R ON ).

[0010] Additionally, HEMT devices used in radio frequency (RF) applications generally provide better RF performance than similar silicon LDMOS devices.

[0011] Heterostructure-based electronic components are integrated in <111> In a heterostructure grown epitaxially on a silicon wafer or on a substrate of sapphire (Al2O3) or silicon carbide (SiC).

[0012] In order to obtain a good crystal quality of the respective epitaxial regions and thus good electrical properties of the corresponding electronic components, starting from two different silicon wafers, the heterostructure-based electronic components and the silicon-based electronic components are integrated in mutually different dies.

[0013] However, this means that electronic devices combining both silicon-based and heterostructure-based components have a large footprint and therefore high manufacturing costs, high energy consumption and low electrical performance, for example due to parasitic capacitance introduced by electrical connections between the dies.

[0014] According to one method, a die in which a silicon-based component is formed and a die in which a heterostructure-based component is formed are bonded to each other via a die transfer technique.

[0015] However, the above method also has disadvantages in terms of manufacturing cost and reliability, as well as electrical performance in use. Summary of the invention

[0016] According to the present disclosure, a manufacturing process of a semiconductor electronic device and a semiconductor electronic device include forming an epitaxial region of a single semiconductor material on a first portion of a substrate layer, forming an epitaxial multilayer including a heterostructure on a second portion of the substrate layer different from the first portion, forming a first electronic component in the epitaxial region, and forming a second electronic component in the heterostructure. Forming the epitaxial multilayer includes forming a growth mask on the substrate layer, forming an opening in the growth mask to expose a second portion of the substrate layer, and forming the epitaxial multilayer on the second portion of the substrate layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] For a better understanding of the present disclosure, embodiments thereof will now be described by way of non-limiting examples only, with reference to the accompanying drawings, in which:

[0018] Figure 1 is a cross-sectional view of a semiconductor electronic device according to one embodiment;

[0019] Figure 2 Shows Figure 1 A top view of the device; and

[0020] Figure 3A-Figure 3N yes Figure 1 Cross-sectional views of the device in successive manufacturing steps. DETAILED DESCRIPTION

[0021] The following description refers to the arrangements shown in the accompanying drawings. Therefore, terms such as "above", "below", "top", "bottom", "right", "left", "high", "low", etc. are related to the accompanying drawings and should not be interpreted in a limiting manner.

[0022] Figure 1 and Figure 2 A semiconductor electronic device (hereinafter simply referred to as device) 1 is shown in a Cartesian reference system XYZ having a first X axis, a second Y axis and a third Z axis.

[0023] The device 1 is formed in a die 3 and includes one or more silicon-based electronic components 5, of which PMOS transistors 5A and NMOS transistors 5B are arranged in a Figure 1 As shown in FIG. 1 , and one or more heterostructure-based electronic components, wherein the HEMT7 is Figure 1 As shown in FIG, these are all integrated in die 3.

[0024] The die 3 comprises a substrate region 10 and a surface region 12 extending over the substrate region 10 , in particular in direct contact with the substrate region 10 .

[0025] The substrate region 10 includes a substrate 14 and one or more epitaxial layers disposed on the substrate 14 .

[0026] The substrate 14 is made of a semiconductor material (particularly a single-crystalline semiconductor material), and has a top surface 14A.

[0027] In detail, in this embodiment, the substrate 14 is made of single crystal silicon, and in particular, the top surface 14A is shaped according to the crystal direction. <111> Directional.

[0028] In this embodiment, the substrate region 10 includes: a first epitaxial layer, or a first deep layer 15, superimposed on the top surface 14A of the substrate 14; a second epitaxial layer, or a first intermediate layer 16, superimposed on the first deep layer 15; a third epitaxial layer, or a second deep layer 17, superimposed on the first intermediate layer 16; and a fourth epitaxial layer, or a second intermediate layer 18, superimposed on the second deep layer 17.

[0029] The epitaxial layers 15-18 are made of a semiconductor material, in particular the same material as the substrate 14 (here silicon), and are not shown in FIG. Figure 1 Marked with a dotted line.

[0030] During the design phase, the thickness along the third axis Z, the conductivity type (eg P or N) and the doping profile of the substrate 14 and the epitaxial layers 15 - 18 may be selected according to the specific application of the device 1 .

[0031] For example, epitaxial layers 15 - 18 may each have a thickness between 0.1 μm and 7 μm.

[0032] For example, in this embodiment, the substrate 14 is of P type, e.g., resistivity between 0.1 Ω·cm and 20 Ω·cm, and the epitaxial layers 15-18 are of N type. In this way, the first deep layer 15 can create a PN junction with the substrate 14a, which can be used to isolate the devices 5, 7 integrated in the die 3 from the substrate 14 in use.

[0033] The doping levels of the first deep layer 15 and the second deep layer 17 may be the same as or different from the doping levels of the first intermediate layer 16 and the second intermediate layer 18, and in particular, higher than the doping levels of the first intermediate layer 16 and the second intermediate layer 18. For example, the doping levels of the first deep layer 15 and the second deep layer 17 may be between 0.1 Ω·cm and 20 Ω·cm, and the doping levels of the first intermediate layer 16 and the second intermediate layer 18 may be between 0.1 Ω·cm and 20 Ω·cm.

[0034] The high doping level of the first deep layer 15 means that, in use, the depletion region between the first deep layer 15 and the substrate 14 extends mainly in the substrate 14 , thereby improving the electrical insulation of the components 5 , 7 from the substrate 14 .

[0035] Furthermore, the high doping level of the first deep layer 15 may allow, in use, to use the first deep layer 15 as a current conducting region of an electronic component integrated in the die 3 , for example if the silicon based component 5 comprises a BJT transistor.

[0036] In the case where the electronic components 5, 7 are designed to operate at high voltage relative to the substrate 14, for example, in order to operate normally with a voltage of 5 V applied at the corresponding terminals at a positive voltage starting from approximately 20 V relative to the substrate 14 (for example, 60 V, 100 V or 650 V), the presence of both the first deep layer 15 and the second deep layer 17 can be useful for simplifying the manufacture of the device 1 and for obtaining excellent electrical performance of the device 1 during use, depending on the specific application and the type of doping used.

[0037] The surface region 12 extends on the second intermediate layer 18 , in particular is in direct contact therewith, and comprises a first device part 20 in which the PMOS transistor 5A and the NMOS transistor 5B are integrated, and a second device part 21 in which the HEMT 7 is integrated.

[0038] The first device part 20 has a top surface 20A and comprises an epitaxial region 23 made of a semiconductor material, in particular, the same material as the second intermediate layer 18 , here single-crystalline silicon.

[0039] The epitaxial region 23 extends from the second intermediate layer 18 (in particular, here is in direct contact with the second intermediate layer 18 ) to the top surface 20A.

[0040] The thickness along the third axis Z, the conductivity type (eg, P or N) and the doping profile of the epitaxial region 23 may be selected at the design stage according to the specific application of the device 1 .

[0041] For example, in this embodiment, epitaxial region 23 is of N-type.

[0042] The first device part 20 comprises a plurality of doped regions which extend within the epitaxial region 23 and form functional regions of the silicon-based electronic component 5 .

[0043] In detail, Figure 1 In the embodiment of the present invention, P++ type doped regions 25A, 25B extend from the top surface 20A in the epitaxial region 23. The doped regions 25A, 25B respectively form the source region and the drain region of the PMOS transistor 5A and define the channel region 26 of the PMOS transistor 5A.

[0044] Furthermore, an N++-type doped region 27 extends from the top surface 20A into the epitaxial region 23 and forms a body contact region of the PMOS transistor 5A.

[0045] Still refer to Figure 1 In the embodiment, the P-type doped region 28 extends from the top surface 20A into the epitaxial region 23 and forms the body region of the NMOS transistor 5B.

[0046] N++ type doped regions 29A, 29B extend in the doped region 28 and respectively form a source region and a drain region of the NMOS transistor 5B and define a channel region 30 of the NMOS transistor 5B.

[0047] Furthermore, a P++ type doped region 31 extends within the doped region 28 and forms a body contact region of the NMOS transistor 5B.

[0048] In practice, the doped regions 25A, 25B, 27, 29A, 29B and 31 (ie, the doped source and drain regions and the body contact region) are highly doped regions, with a doping level of, for example, a peak concentration between 5·10 19 Atom / cm 3 and 5.10 20 Atom / cm 3 Alternatively, the doped region 28 (ie, the body region) is a low-doped region, the doping level of which is, for example, a peak concentration between 1·10 16 Atom / cm 3 and 2.10 18 Atom / cm3 between.

[0049] During the design phase, the number, arrangement, shape, size and doping profile of the doped regions may be selected depending on the specific silicon-based electronic components 5 integrated in the die 3 and the specific application of the device 1 .

[0050] Insulating portion 33 made of an insulating material (eg, oxide) may extend from top surface 20A into epitaxial region 23 , depending on the specific application.

[0051] In particular, Figure 1 In the embodiment, the insulating portion 33 extends parallel to the first axis X between the doping region 27 and the doping region 25A, between the doping region 25B and the doping region 31 , and between the doping region 31 and the doping region 29A.

[0052] A first insulating layer 35 (eg, an oxide or nitride layer) extends over the top surface 20A of the first device portion 20 .

[0053] The second insulating layer 36 (eg, an oxide layer) extends on the first insulating layer 35 .

[0054] The surface structure 38 of the silicon-based component 5 extends over the top surface 20A of the first device region 20, in direct contact therewith. The surface structure 38 forms other functional regions of the silicon-based device 5 and may include various conductive and / or insulating regions depending on the specific silicon-based electronic component 5 integrated in the die 3.

[0055] In this embodiment, the surface structure 38 includes insulated gate regions 40, 41 extending over the channel region 26 of the PMOS transistor 5A and the channel region 30 of the NMOS transistor 5B, respectively. Figure 1 In the figure, for simplicity, only the corresponding conductive regions (here, polysilicon regions) of the insulated gate regions 40 and 41 are illustrated and are still denoted by 40 and 41, and they each have a corresponding top surface 40A and 41A.

[0056] Although in Figure 1 Although not shown in the figure, the insulated gate regions 40, 41 may also each include a corresponding insulating region arranged between the corresponding polysilicon region and the top surface 20A, and a corresponding contact region made of a conductive material (e.g., metal) that contacts the corresponding surface 40A, 41A and forms the corresponding gate terminal G.

[0057] exist Figure 1In the embodiment, the surface structure 38 also includes source contact regions 42, 43 and drain contact regions 44, 45 made of conductive material, which extend through the first insulating layer 35 and the second insulating layer 36 and directly contact the top surface 20A, thereby forming corresponding source terminals S and drain terminals D.

[0058] Specifically, the source contact regions 42 and 43 extend in direct contact with the source region 25A of the PMOS transistor 5A and the source region 29A of the NMOS transistor 5B, respectively.

[0059] Furthermore, in the embodiment shown, the source contact regions 42 , 43 each also extend in direct contact with the respective body contact region 27 , 31 .

[0060] The drain contact regions 44 and 45 extend in direct contact with the drain region 25B of the PMOS transistor 5A and the drain region 29B of the NMOS transistor 5B, respectively.

[0061] The second device portion 21 of the surface region 12 has a top surface 21A and includes an epitaxial multilayer 49 extending over and grown from the second intermediate layer 18 .

[0062] The epitaxial multilayer 49 comprises a heterostructure 50 in which the HEMT transistor 7 is integrated.

[0063] exist Figure 1 In the embodiment of the present invention, the epitaxial multilayer 49 further comprises a transition region, which is formed here by a first buffer layer 52 and a second buffer layer 53 superposed on each other, which are arranged between the second intermediate layer 18 and the heterostructure 50. The transition region may be useful during the manufacture of the device 1 to facilitate the epitaxial growth of the heterostructure 50 on the second intermediate layer 18.

[0064] In detail, the first buffer layer 52 (eg, aluminum nitride (AlN)) extends on and directly contacts the second intermediate layer 18 , and the second buffer layer 53 (eg, aluminum gallium nitride (AlGaN)) extends on and directly contacts the first buffer layer 52 .

[0065] The heterostructure 50 includes a compound semiconductor material including elements of Group III and Group V of the periodic table, and forms the top surface 21A of the second device portion 21 .

[0066] Depending on the specific manufacturing steps used to manufacture the device 1 , the top surface 21A of the second device part 21 may extend at the same or different coordinates along the third axis Z than the coordinates at the top surface 20A of the first device part 20 .

[0067] In particular, in this embodiment, the top surface 21A of the second device part 21 is arranged at a lower height relative to the top surface 20A of the first device part 20 , measured along the third axis Z. This allows an improved manufacturing of the device 1 .

[0068] The heterostructure 50 includes a channel layer 55 and a barrier layer 56 stacked on each other.

[0069] The channel layer 55 is made of a first semiconductor material (eg, gallium nitride (GaN) or an alloy including gallium nitride, such as InGaN), here made of gallium nitride (GaN), extends over the transition region, in particular over the second buffer layer 53, and has a top surface 55A.

[0070] The barrier layer 56 is made of a second semiconductor material (e.g., a compound based on a ternary or quaternary alloy of gallium nitride, such as Al x Ga 1-x N, AlInGaN, In x Ga 1-x N、Al x In 1-x The second device portion 21 is made of Al, AlScN), here made of aluminum gallium nitride (AlGaN), and extends between the top surface 55A of the channel layer 55 and the top surface 21A of the second device portion 21.

[0071] The channel layer 55 and the barrier layer 56 may be of intrinsic type, P type, or N type according to specific applications; in particular, both the channel layer 55 and the barrier layer 56 may be of N type.

[0072] For example, when barrier layer 56 is AlGaN, the presence of aluminum atoms causes barrier layer 56 to be N-type.

[0073] The heterostructure 50 is configured to accommodate a two-dimensional gas (2DEG) of (mobile) charge carriers (particularly electrons here) arranged at the interface between the channel layer 55 and the barrier layer 56 , ie, at the top surface 55A of the channel layer 55 .

[0074] Insulating layer 58 has a top surface 58A, for example made of an oxide such as silicon oxide, extending above top surface 21 A. Insulating layer 58 may have a thickness, for example, between 20 nm and 1 μm.

[0075] The insulating layer 36 also extends over the second device part 21 , in particular over the insulating layer 58 .

[0076] The surface structure 60 of the heterostructure-based component 7 extends over the top surface 21A of the second device part 21 .

[0077] Depending on the specific heterostructure-based electronic component 7 integrated in the die 3 , the surface structure 60 may be various conductive and / or insulating areas, which form functional areas of the heterostructure-based component 7 .

[0078] In this embodiment, in which the heterostructure-based electronic component 7 is a HEMT, the surface structure 60 comprises a source region 61 and a drain region 62 extending at a distance from each other along a first axis X and made of an electrically conductive material.

[0079] The source region 61 and the drain region 62 are in electrical contact, in particular ohmic contact, with the heterostructure 50 , in particular with the two-dimensional gas formed at the interface between the channel layer 55 and the barrier layer 56 , and form a source terminal S and a drain terminal D of the HEMT 7 , respectively.

[0080] exist Figure 1 In the embodiment of FIG. 5 , the source region 61 and the drain region 62 extend parallel to the third axis Z through the insulating layers 36 , 58 to the top surface 21A.

[0081] However, depending on the specific application, the source region 61 and the drain region 62 may extend parallel to the third axis Z and also partially through the heterostructure 50 , for example through a portion of the barrier layer 56 or the entire thickness of the barrier layer 56 to the surface 55A.

[0082] The surface structure 60 also comprises a gate structure, here formed by a channel modulation region 64 and a gate contact region 65, which can be biased to electrically control the formation of a two-dimensional gas in the heterostructure 50 between the source region 61 and the drain region 62. The gate structure forms a gate terminal G of the HEMT 7.

[0083] In this embodiment, the HEMT 7 is of a normally-off type, ie, an enrichment type.

[0084] In detail, in this embodiment, the channel modulation region 64 is made of a semiconductor material and has a conductivity type different from that of the barrier layer 56, for example, a P-type. In particular, the channel modulation region 64 may be made of P-type gallium nitride (p-GaN).

[0085] However, the channel modulation region 64 may be formed of a collection of different materials including dielectric layers, metal layers, and / or semiconductor layers (serving as control electrodes with appropriate work functions).

[0086] The channel modulation region 64 extends along the first axis X between the source region 61 and the drain region 62 on the top surface 21A, and has a top surface 64A.

[0087] Depending on the specific manufacturing steps used to produce the device 1 , the top surface 64A of the channel modulation region 64 may extend at a coordinate along the third axis Z that is the same as or different from the coordinates at which the top surfaces 40A, 41A of the insulated gate regions 40 , 41 extend.

[0088] In particular, in this embodiment, the top surface 64A of the channel modulation region 64 is arranged at a distance from the second intermediate layer 18 measured along the third axis Z that is smaller than the distance of the top surfaces 40A, 41A of the insulating gate regions 40, 41 from the second intermediate layer 18 measured along the third axis Z. This may make it possible to improve the manufacturing reliability of the device 1.

[0089] A gate contact region 65 made of an electrically conductive material extends in electrical contact with the channel modulation region 64 , in particular here in contact with the top surface 64A.

[0090] The surface region 12 of the die 3 also includes a residual spacer portion 70 extending between the first device portion 20 and the second device portion 21 on the second intermediate layer 18 and in direct contact therewith.

[0091] like Figure 2 As can be seen in the schematic top view of FIG. 2 , the residual partition part 70 surrounds the second device part 21 .

[0092] Reference again Figure 1 , the residual partition portion 70 has a top surface which, in this embodiment, is continuous with, and in particular aligned with, the top surface 20A of the first device portion 20 and is therefore indicated by the same reference numeral.

[0093] The residual partition portion 70 is laterally contiguous with the second device portion 21 parallel to the first axis X.

[0094] In detail, the residual partition portion 70 has a first side wall 71 connected to the first device portion 20 and a second side wall 72 opposite to the first side wall 71 and connected to the second device portion 21 .

[0095] The residual separation portion 70 includes a defined region 75, for example including an oxide, in particular silicon oxide, which extends over and is in direct contact with the second intermediate layer 18; and a polycrystalline region 76, which is made of the same material (silicon) as the epitaxial region 23 of the first device portion 20, extending over and is in direct contact with the defined region 75.

[0096] The defined region 75 may be formed of a single layer, for example an oxide layer, in particular a silicon oxide layer, or of multiple layers, for example including one or more oxide layers and / or one or more nitride layers.

[0097] In detail, according to one embodiment, the definition region 75 may be made of silicon oxide.

[0098] According to various embodiments, the definition region 75 may include an oxide layer, in particular a silicon oxide layer, and a nitride layer.

[0099] According to one embodiment, the oxide layer may be in direct contact with the semiconductor layer 18 .

[0100] The thickness of the defined region 75 along the third axis Z may be, for example, between 7 nm and 300 nm, in particular and between.

[0101] In the present embodiment, the polycrystalline region 76 has a polycrystalline structure.

[0102] In this embodiment, the polycrystalline region 76 is monolithic with the epitaxial region 23 .

[0103] The inclination of the first sidewall 71 may depend on the crystal orientation of the epitaxial region 23 and on the thickness of the defined region 75 along the third axis Z. For example, in the epitaxial region 23, the crystal orientation of the epitaxial region 23 may be <111> In this orientation, the first side wall 71 may form an angle of approximately 54° with a direction parallel to the first axis X.

[0104] Polycrystalline region 76 extends at a distance from top surface 20A.

[0105] An insulating region 77 of insulating material (eg, oxide) extends in die 3 from top surface 20A between first device portion 20 and second device portion 21 .

[0106] In detail, the insulating region 77 extends parallel to the third axis Z in the first device portion 20 from the top surface 20A within the epitaxial region 23 and in the residual separation portion 70 between the top surface 20A and the polycrystalline region 76 .

[0107] exist Figure 1 In the embodiment of FIG. 4 , epitaxial multilayer 49 includes a portion that conformally extends on second sidewall 72 of residual spacer portion 70 , thereby forming a raised surface 78 .

[0108] The raised surface 78 is arranged at a higher coordinate along the third axis Z than the coordinate at which the top surface 21A extends and here also higher than the coordinate at which the top surface 58A of the insulating layer 58 extends.

[0109] The shape and structure of the residual partitioning portion 70 may vary depending on the specific manufacturing steps used to manufacture the device 1 .

[0110] The presence of a polycrystalline region (region 76) between the epitaxial multilayer (21) and the epitaxial region (23) can be useful for reducing stress caused by the lattice mismatch between the material forming the epitaxial multilayer (e.g., GaN) and the material forming the epitaxial region (e.g., silicon). Thus, the presence of the polycrystalline region can help reduce the risk of dislocation in the die 3 (and thereby reduce possible failure of the device 1).

[0111] The device 1 allows combining the functionality of the silicon-based component 5 and the heterostructure-based component 7 in a single die, thereby maintaining a small size relative to electronic devices in which the silicon-based component 5 and the heterostructure-based component 7 are integrated in different dies from each other.

[0112] Furthermore, the electrical connections between the silicon-based components 5 and the heterostructure-based components 7 can be obtained directly on the die 3. This can guarantee high electrical performance of the device 1 in use, for example in terms of the switching speed of the various components, minimal resistive losses in the electrical connections between them and minimal impact of overvoltages due to the presence of parasitic inductances.

[0113] Reference below FIG. 3A to FIG. 3N The steps for manufacturing the semiconductor electronic device 1 are described.

[0114] Figure 3A A cross section of a wafer 100 of a single crystalline semiconductor material, particularly silicon, having a top surface 100A is shown. Figure 1 The same components as those already described are denoted by the same reference numerals and will not be described in detail again.

[0115] Wafer 100 includes a substrate 14 on which epitaxial layers 15 , 16 , 17 , and 18 have been grown.

[0116] The fourth epitaxial layer or the second intermediate layer 18 forms the top surface 100A of the wafer 100 .

[0117] The second intermediate layer 18 includes a first portion 101A and a second portion 101B. The first portion 101A is intended to form a first device portion 20, that is, the PMOS transistor 5A and the NMOS transistor 5B are to be integrated; the second portion 101B is intended to form a second device portion 21, that is, the epitaxial multilayer 49 is to be grown on the second portion 101B and the HEMT 7 is to be integrated.

[0118] Next ( Figure 3B ), a definition layer 102 is formed on the top surface 100A, for example including oxide, especially silicon oxide.

[0119] The definition layer 102 may be formed of one or more layers of different materials, such as Figure 1The definition of area 75 is discussed above.

[0120] The definition layer 102 may have a small thickness along the third axis Z, for example between 7 nm and 300 nm, in particular from arrive

[0121] The definition layer 102 is intended to form the definition area 75 ( Figure 1 ).

[0122] The definition layer 102 may be formed by oxidizing a surface portion of the second intermediate layer 18 or by deposition on the top surface 100A. In the case of oxidation, after oxidation, the thickness of the second intermediate layer 18 may be about Figure 3A However, given that the thickness of the definition layer 102 is much smaller than the thickness of the second intermediate layer 18, for simplicity it can be assumed that the thickness of the second intermediate layer 18 will remain the same to a first approximation before and after oxidation.

[0123] Then( Figure 3C ), the definition layer 102 is removed at the first portion 101A of the second intermediate layer 18 (on which the first device portion 20 is intended to be formed), i.e., the portion of the second intermediate layer 18 on which the epitaxial region 23 is intended to be formed. Therefore, a portion of the definition layer 102, also referred to as the growth mask 103 in the following, remains.

[0124] In practice, the growth mask 103 exposes the first portion 101A of the second intermediate layer 18 and covers the second portion 101B of the second intermediate layer 18 .

[0125] exist Figure 3D In the process, a surface layer 105 of a semiconductor material is grown on the wafer 100, which semiconductor material is in particular the same material as the second intermediate layer 18 (here silicon).

[0126] The surface layer 105 has a top surface 105A.

[0127] The surface layer 105 comprises an epitaxial portion 106 grown parallel to the third axis Z from the second intermediate layer 18 , in particular from the respective first portion 101A, and a sacrificial portion 107 grown parallel to the third axis Z on the growth mask 103 .

[0128] The epitaxial portion 106 grown from the single crystalline substrate maintains the single crystalline structure of the second intermediate layer 18 and is intended to form the epitaxial region 23 of the first device portion 20 .

[0129] The sacrificial portion 107 grown from the amorphous substrate has a polycrystalline structure.

[0130] exist Figure 3EIn the embodiment, a doped region 28 corresponding to the body region of the NMOS transistor 5B and an optional insulating layer 108 are formed in the surface layer 105 .

[0131] In detail, the body region 28 is formed in the epitaxial portion 106 where the silicon-based component 5 is formed.

[0132] Body region 28 may be formed via implantation of dopant ions.

[0133] The insulating layer 108 (eg, silicon oxide) forms the insulating portion 33 ( Figure 1 ) and is intended to form an insulating region 77 ( Figure 1 ) section 109.

[0134] The insulating layer 108 may be obtained by forming an insulating trench (eg, shallow trench isolation (STI)) in the surface layer 105. In this case, the thickness of the epitaxial portion 106 and the sacrificial portion 107 may be reduced due to the formation of the insulating layer 108.

[0135] In addition, refer again Figure 3E Depending on the specific silicon-based electronic component 5 intended to be integrated in the die 3 of the device 1 , one or more surface layers 110 may be formed on the top surface 105A of the surface layer 105 .

[0136] In the illustrated embodiment, the surface layer 110 is intended to form the insulated gate regions 40, 41 ( Figure 1 ). In particular, in the surface layer 110, only a single gate layer (here of polysilicon) is illustrated here and is still indicated by 110. However, an oxide layer (not shown here) is formed between the top surface 105A and the polysilicon layer 110 in a manner known per se.

[0137] The polysilicon layer 110 has a top surface 110A.

[0138] On the surface 110A of the gate layer 110, a sacrificial mask layer 111 having a top surface 111A is also formed, for example, formed of an insulating material, such as a single insulating layer or insulating multilayers, for example including one or more of silicon oxide, silicon nitride, aluminum oxide and silicon carbide.

[0139] exist Figure 3F In the embodiment, an opening 113 is opened above the sacrificial portion 107 .

[0140] The opening 113 is formed by selectively removing portions of the layers 110 , 111 , thereby exposing the underlying sacrificial portion 107 .

[0141] The remaining portion of the sacrificial layer 111 may be used as an etching mask.

[0142] Then( Figure 3G ), the insulating layer 108 and the sacrificial portion 107 at the opening 113 are removed using an etching mask 111.

[0143] Therefore, in the sacrificial portion 107, a portion arranged under the etching mask is retained, which portion will form Figure 1 The polycrystalline region 76.

[0144] exist Figure 3G After the etching, the recess formed in the sacrificial portion 107 is continuous with the opening 113 and exposes a portion of the growth mask 103 .

[0145] exist Figure 3H In the growth mask 103, the exposed portion of the growth mask 103 is removed. Therefore, in the growth mask 103, the portion arranged below the polycrystalline region 76 is retained, that is, Figure 1 The definition area 75.

[0146] The etching of the exposed portions of the growth mask 103 may be performed using a selective chemistry that does not, to a first approximation, etch the underlying second intermediate layer 18 .

[0147] Therefore, in Figure 3H After etching, the opening 113 also exposes the second portion 101B of the second intermediate layer 18 .

[0148] Next ( Fig. 3I ), grown on the wafer 100 to form Figure 1 The working multilayer 114 of the epitaxial multilayer 49 is formed.

[0149] In detail, a first buffer layer is grown on the wafer 100. Figure 1 The first buffer layer 52 corresponds to the first buffer layer 52 of the top surface 100A and is therefore indicated by the same reference numerals. The first buffer layer 52 extends on the exposed portion of the top surface 100A, on the second sidewall 72 and on the etching mask 111.

[0150] A second buffer layer is grown on the first buffer layer 52. Figure 1 The buffer layer 53 corresponds to and is therefore indicated by the same reference numerals.

[0151] A channel layer is grown on the second buffer layer 53. Figure 1 The channel layer 55 corresponds to and is therefore denoted by the same reference numerals.

[0152] A barrier layer is grown on the channel layer 55. Figure 1 The barrier layer 56 corresponds to and is therefore denoted by the same reference numerals.

[0153] The working multilayer 114 includes a protruding portion 115 extending on the etching mask 111 and on the second sidewall 72 of the residual portion 70 , and a useful portion 116 extending directly on the top surface 100A of the second intermediate layer 18 .

[0154] The useful portion 116 has a substantially planar top surface 116A, in particular substantially parallel to the top surface 100A.

[0155] The useful portion 116 grown on the second intermediate layer 18 is of single-crystalline type and is used for integrating the heterostructure-based device 7 .

[0156] Then( Figure 3J ), a channel modulation region 64 is formed on the top surface 116A of the useful portion 116 in a manner known per se (eg via growing and defining specific layers).

[0157] In practice, in this embodiment, the useful portion 116 of the working multilayer 114 also includes the channel modulation region 64 .

[0158] Here, therefore, the surface 64A of the modulation zone 64 forms the most convex surface of the useful portion 116 , ie the surface of the useful portion 116 which, along the third axis Z, is at the greatest distance from the surface 100A.

[0159] The surface 110A on which the etching mask 111 extends can be arranged at a distance from the surface 100A along the third axis Z that is greater than the distance of the most convex surface of the useful portion 116 and less than the distance of the surface 110A. This can be useful in subsequent manufacturing steps to protect the channel modulation region 64 and thus improve the reliability of the process of manufacturing the device 1.

[0160] A protective layer 118 of insulating material is formed on the barrier layer 56 ( Figure 3K ), such as a single insulating layer or insulating multilayers, such as one or more of silicon oxide, silicon nitride, aluminum oxide and silicon carbide. The thickness of the protective layer 118 along the third axis Z is greater than the thickness of the channel modulation region 64 along the third axis Z, such as between 10 nm and 500 nm.

[0161] In other words, the protection layer 118 completely covers the channel modulation region 64 .

[0162] The protective layer 118 has a top surface 118A at the useful portion 116 , and the top surface 118A faces the top surface 116A of the useful portion 116 .

[0163] In this embodiment, the top surface 118A of the protective layer 118 extends at a height from the surface 100A along the third axis Z that is less than the height of the top surface 111A of the etch mask 111 from the surface 100A along the third axis Z. This may be useful in subsequent manufacturing steps to protect the channel modulation region 64 and thus improve the reliability of the process for manufacturing the device 1.

[0164] In addition, in this embodiment, the distance between the top surface 118A of the protective layer 118 and the top surface 64A of the channel modulation region 64 along the third axis Z is greater than the thickness of the etching mask 111 along the third axis Z, which can be useful in subsequent manufacturing steps to protect the channel modulation region 64 and thereby improve the reliability of the process for manufacturing the device 1.

[0165] exist Figure 3L In the embodiment, the raised portion 115 of the working multilayer 114 is at least partially removed until the top surface 111A of the etching mask 111 , thereby exposing the etching mask 111 .

[0166] Removal may be performed via planarization, such as chemical mechanical polishing (CMP) or other etching techniques.

[0167] In the illustrated embodiment, after removal, in the raised portion 115 of the working multilayer 114 , only the portion extending above the second sidewall 72 remains, which forms a raised surface 78 flush with the top surface 111A of the etching mask 111 .

[0168] In the protective layer 118 , a portion extending over the useful portion 116 of the working multilayer 114 remains, again indicated by 118 .

[0169] Then( Figure 3M ), the wafer 100 is etched to remove the etching mask 111 and thereby expose the gate layer 110.

[0170] In this embodiment, etching of the etching mask 111 also etches the protection layer 118, thereby reducing its thickness. However, since the thickness of the etching mask 111 is less than the distance between the top surface 64A of the channel modulation region 64 and the top surface 118A of the protection layer 118, the remaining protection layer 118 still completely covers the channel modulation region 64. Therefore, the channel modulation region 64 will not be damaged by the etching. Figure 3M The etching operation shown in FIG.

[0171] After etching, the protective layer 118 forms a reference Figure 1 The insulating layer 58 is described.

[0172] Depending on the materials forming the etching mask 111 and the protective layer 118 and depending on the specific etching used to remove the etching mask 111, Figure 3M The etching operation shown in FIG. 1 can selectively remove only the etching mask 111 without removing the protection layer 118 .

[0173] Next ( Figure 3N ), defining a gate layer 110, thereby forming insulated gate regions 40, 41. Furthermore, (heavily) doped regions 25A, 25B, 27, 29A, 29B, 31 are formed in the epitaxial portion 106 of the surface layer 105, which can be defined, for example, by subsequent steps of masking and ion implantation.

[0174] Next comes a manufacturing step (not shown here) for forming insulating and / or passivation layers (e.g., Figure 1 oxide layers 35, 36) and metal contact areas (e.g., Figure 1 areas 42-45 and 61, 62, 65).

[0175] This is followed by final manufacturing steps (not shown here), such as forming the top layer of metal interconnects and dicing of the wafer, to form the device 1 .

[0176] The present manufacturing process allows integrating both silicon-based electronic components 5 and heterostructure-based electronic components 7 in the same die, thereby obtaining a high crystallographic quality of the heterostructure 50 .

[0177] Indeed, the use of the growth mask 103 allows simultaneously growing the (single-crystalline) epitaxial portion 106 in which the silicon-based electronic component 5 is formed, while ensuring the surface quality of the top surface 100A beneath the growth mask 103 on which the working multilayer 114 is grown.

[0178] The fact that the growth mask 103 comprises an oxide, in particular silicon oxide, enables the growth mask 103 to be etched by a different chemistry than that which may be used to remove the second intermediate layer 18. Thus, an opening or recess 113 may be formed through the sacrificial portion 107, which exposes the underlying top surface 100A without affecting, at least to a first approximate extent, the growth of the epitaxial working multilayer 114 ( Figure 3G-Figure 3I In particular, the fact that the growth mask 103 comprises a layer comprising an oxide in direct contact with the semiconductor layer 18 can make it possible to further reduce the risk of damaging the surface 100A on which the epitaxial multilayer 49 is grown.

[0179] In particular, the fact that growth mask 103 is silicon oxide and layer 18 is silicon allows obtaining an etch rate of growth mask 103 that is highly selective with respect to the silicon of layer 18. Furthermore, before growing epitaxial working multilayer 114, surface 100A may also be cleaned using wet etching.

[0180] In practice, the growth mask 103 can be used as an etch stop layer during etching of the overlying sacrificial portion 107, thereby ensuring complete removal of the overlying sacrificial portion 107. In addition, the formation of the openings in the growth mask 103 does not adversely affect the quality of the underlying surface 100A, for example, in terms of terracing and pitting.

[0181] The epitaxial multilayer 49 and thus the heterostructure 50 may exhibit a high crystalline quality.

[0182] Therefore, the corresponding electronic component 7 that functions based on the formation of a two-dimensional gas in the heterostructure 50 can have high electrical performance in use.

[0183] At the same time, the electronic component 5 is also integrated in the single crystal silicon layer (epitaxial portion 106) which can have high crystal quality. Therefore, the electronic component 5 can have high electrical performance when used.

[0184] Furthermore, the growth mask 103 can be thick enough to serve as a mask for forming the epitaxial multilayer 49, and at the same time thin enough to minimize the non-planarity of the top surface 105A of the surface layer 105. In practice, the top surface 105A of the surface layer 105 can be considered to be substantially planar. This facilitates subsequent manufacturing steps that form both the silicon-based electronic component 5 and the heterostructure-based electronic component 7.

[0185] use <111> The possibility of using a silicon substrate 14 as a starting substrate for forming a semiconductor electronic device 1 can allow obtaining a high epitaxial quality of the heterostructure 50, in particular when the channel layer 55 is GaN. As a result, the electronic component 7 based on the heterostructure can have excellent electrical properties. The applicant has also found that using <111> The silicon substrate 14 also allows obtaining excellent electrical properties of the silicon-based electronic component 5 .

[0186] refer to Figure 3A-Figure 3N In an embodiment of the manufacturing process, the fact that some of the doped regions of the silicon-based device 5, in particular doped regions with a high doping level (such as the source region, the drain region and the body contact region of the PMOS transistor 5A and the NMOS transistor 5B) can be formed after growing the epitaxial multilayer 49 can further help to improve the reliability of the manufacturing of the device 1.

[0187] In fact, the epitaxial multilayer 49 can be grown using a larger thermal budget than the heavily highly doped regions can withstand. In this way, heavily doped regions of the silicon based device 5 can be formed with high reliability.

[0188] For example, the growth of the first buffer layer 52 of AlN can occur at a temperature of approximately 1100°C with a growth time interval between approximately 15 minutes and 30 minutes, while the growth of the GaN layer and the AlGaN layer forming the second buffer layer 53, the channel layer 55, the barrier layer 56 and the channel modulation region 64 can each occur at a temperature of approximately 1030°C-1080°C in successive growth steps with a growth interval of approximately 5 minutes-15 minutes.

[0189] However, it will be clear to those skilled in the art that the above manufacturing steps and the corresponding execution order may be different depending on the specific process and equipment used. Figure 3A-Figure 3N The differences have been shown in .

[0190] For example, epitaxial multilayer 49 may be grown before surface layer 105 .

[0191] For example, depending on the specific materials forming the epitaxial multilayer 49 and the epitaxial region 23 , the epitaxial multilayer 49 may be grown after forming the heavily doped region.

[0192] For example, the body regions of the NMOS transistor and the PMOS transistor may be formed before forming the insulating oxide (33, 108), or implanted after forming the field insulation (STI); in particular, they are formed before forming the oxide that forms the gate structure of the PMOS transistor and the NMOS transistor (i.e., for example, before the deposition of the polysilicon layer 110).

[0193] For example, multilayer 114 may be selectively grown starting from exposed portion 101B only. In this case, portion 115 would not exist; therefore, Figure 3L The removal indicated in may not be present.

[0194] Finally, it is clear that other modifications and variations may be made to the electronic device 1 and the corresponding manufacturing process described and illustrated herein, without departing from the scope of the present disclosure.

[0195] In addition to or as an alternative to the PMOS transistor 5A and the NMOS transistor 5B, the electronic device 1 may also include other silicon-based electronic components 5 (active and / or passive) integrated in the die 3 .

[0196] For example, Figure 2 As shown in , the silicon-based electronic component 5 may also include a bipolar transistor 5C and passive components 5D such as a diode and a resistor. Figure 2In FIG. 5 , the bipolar transistor 5C and the passive component 5D are integrated in respective device parts 120 , 121 that are different from each other and are schematically indicated by dashed lines.

[0197] For example, device portions 120 , 121 are formed in respective epitaxial regions of single-crystalline silicon grown on substrate region 10 , and in particular are formed monolithically with epitaxial region 23 .

[0198] Insulating regions, such as shallow or deep trenches, can be arranged in a manner known per se between the portions 120 , 121 and 20 , so that the respective electronic components are electrically insulated from one another in use.

[0199] Apart from Figure 2 In addition to or in place of the components shown in Figure 2 In addition to the components shown in , the device 1 may also include other silicon-based electronic components 5 integrated in the die 3. For example, the components 5 may include MOS transistors for medium voltage applications, such as from 15V to 20V; DMOS transistors and / or drift MOS transistors, such as for applications with operating voltages of 20V to 200V; thin film resistors; OTP or MTP memory; phase change memory; etc.

[0200] It will be clear to a person skilled in the art that the integration of different types of silicon-based electronic components 5 with each other can be obtained via manufacturing steps known per se and therefore not further illustrated herein, for example by using BCD technology.

[0201] For example, the conductivity type of the individual semiconductor regions, N or P, may be reversed compared to what has been described.

[0202] For example, the epitaxial multilayer 49 may include only the heterostructure 50. In other words, the heterostructure 50 may be grown directly on the substrate region 10.

[0203] For example, layers 14 - 18 may include one or more diffusion regions of dopant species (P or N), depending on the particular application.

[0204] For example, the heterostructure-based component 7 may include electronic components other than the HEMT 7 .

[0205] For example, the HEMT 7 may be of the normally off type, wherein the gate structure may be different from what has been described above; for example, the gate structure may be of the recessed type, and / or the fabrication of the gate structure may include the use of a fluorine plasma below the gate structure. Alternatively, the HEMT 7 may be of the normally on type, i.e., a depletion type.

[0206] For example, refer to Figure 1The insulating region 77 extending between the first device portion 20 and the second device portion 21 may have a different shape and structure than shown. For example, there may be one or more trenches in the die 3 extending along the third axis Z with a greater depth.

[0207] For example, the number of epitaxial layers forming substrate region 10 may vary depending on the specific application.

[0208] For example, depending on the desired thickness of the epitaxial multilayer 49 and the epitaxial region 23 along the third axis Z, the second intermediate layer 18 may not be present and the epitaxial multilayer 49 may be grown directly on the second deep layer 17 .

[0209] In the case of medium or low voltage applications (e.g., from 7V to 40V), the substrate region 10 may comprise only the substrate 14 and the first deep layer 15 (or also the first intermediate layer 16). In practice, in this case, the epitaxial multilayer 49 may be grown directly on the first deep layer 15 or, if present, on the first intermediate layer 16.

[0210] For example, the electronic component 5 may be an electronic component based on a single semiconductor other than silicon (eg, Ge, SiGe, etc.).

[0211] A manufacturing process of a semiconductor electronic device (1) is summarized as comprising: providing a wafer (100), the wafer comprising a substrate layer (18) of a semiconductor material, the substrate layer having a first portion (101A) and a second portion (101B) different from the first portion; growing an epitaxial region (23, 106) of a single semiconductor material on the first portion (101A) of the substrate layer; growing an epitaxial multilayer (49, 114) comprising a heterostructure (50) on the second portion (101B) of the substrate layer; starting from the epitaxial region (23, 106), forming a first electronic component (5A, 5B, 5C, 5D) based on the single semiconductor material; and starting from the heterostructure, forming a second electronic component (7) based on the heterostructure, wherein growing the epitaxial multilayer comprises: forming a growth mask (103) on the substrate layer (18); forming an opening in the growth mask (103) to expose the second portion of the substrate layer; and growing the epitaxial multilayer on the second portion of the substrate layer.

[0212] A growth mask (103) is formed before growing the epitaxial region, the growth mask exposing a first portion (101A) of the substrate layer (18).

[0213] Growing an epitaxial region includes growing a surface layer (105) of a single semiconductor material, the surface layer having a first portion (106) extending above a first portion (101A) of a substrate layer (18) and a second portion (107) extending above a growth mask (103); and wherein forming an opening in the growth mask (103) includes forming a recess in the second portion (107) of the surface layer extending to the growth mask.

[0214] The manufacturing process also includes forming an etching mask (111) extending on a first portion (106) of the surface layer (105) and having an opening (113) on a second portion (107) of the surface layer (105), wherein growing the epitaxial multilayer includes: growing a working multilayer (114) having a first portion (116) extending on a second portion (101B) of the substrate layer (18) and a second portion (115) extending on the etching mask; and removing the second portion (115) of the working multilayer, wherein the etching mask (111) extends in a direction (Z) from a surface (110A), the surface (110A) being arranged at a greater height from the substrate layer (18) in the direction (Z) than the first portion (116) of the working multilayer.

[0215] The growth mask (103) includes an oxide layer, such as silicon oxide.

[0216] The growth mask (103) has a thickness between 7 nm and 300 nm.

[0217] Forming the first electronic component (5A, 5B) includes forming one or more doped regions (25A, 25B, 29A, 29B, 27, 31) in the epitaxial region (23, 106) after the step of growing the epitaxial multilayer.

[0218] The first electronic component is a MOS transistor (5A, 5B) having an insulated gate region (40, 41), wherein forming the first electronic component includes forming an insulated gate region (110) above the epitaxial region (23, 106) prior to the step of growing the epitaxial multilayer.

[0219] The single semiconductor material is silicon, and the wafer (100) is <111> silicon.

[0220] The single semiconductor material is silicon, and the substrate layer (18) is a single crystal silicon layer.

[0221] A semiconductor electronic device (1) is summarized as comprising: a tube core (3); a first electronic component (5) based on a single semiconductor material; and a second electronic component (7) based on a heterostructure, wherein the tube core comprises: a substrate region (10) of semiconductor material; a first surface portion (20) comprising a single crystal region (23) of the single semiconductor material extending on the substrate region; and a second surface portion (21) different from the first surface portion and comprising an epitaxial multilayer (49) extending on the substrate region, the epitaxial multilayer comprising a heterostructure (50), the first electronic component (5) being integrated in the first surface portion of the tube core and the second electronic component (7) being integrated in the second surface portion of the tube core.

[0222] The die (3) further comprises a third surface portion (70) extending on the substrate region (10) between the first surface portion and the second surface portion, the third surface portion comprising a polycrystalline region (76) of a single semiconductor material, in particular monolithic with the single crystalline region (23).

[0223] The first component is one of the following: a CMOS transistor, a DMOS transistor, a bipolar transistor, or a passive electronic component based on a single semiconductor material.

[0224] The second component is a high mobility transistor (7) in which the heterostructure is based on materials from Group III and Group V of the periodic table, including, for example, GaN.

[0225] The substrate region (10) comprises a single-crystal substrate (14) having a first conductivity type (P) and at least one epitaxial layer (15, 18) having a second conductivity type (N) different from the first conductivity type and extending on the substrate.

[0226] The various embodiments described above can be combined to provide further embodiments. Aspects of the embodiments can be modified, if necessary, to employ concepts of the various patents, applications, and publications to provide further embodiments.

[0227] These and other changes can be made to the embodiments in light of the above detailed description. In general, in the appended claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full range of equivalents to which these claims are entitled. Therefore, the claims are not limited by the present disclosure.

Claims

1. A process for manufacturing a semiconductor electronic device, comprising: forming an epitaxial region of a single semiconductor material on a first portion of the substrate layer; forming an epitaxial multilayer including a heterostructure on a second portion of the substrate layer different from the first portion; forming a first electronic component in the epitaxial region; as well as forming a second electronic component in the heterostructure, The formation of epitaxial multilayers includes: forming a growth mask on the substrate layer; forming an opening in the growth mask to expose a second portion of the substrate layer; and An epitaxial multilayer is formed on the second portion of the substrate layer. 2 . The manufacturing process of claim 1 , wherein the growth mask is formed before growing the epitaxial region, the growth mask exposing a first portion of the substrate layer.

3. A manufacturing process according to claim 1, wherein forming the epitaxial region includes growing a surface layer of a single semiconductor material, the surface layer having a first portion extending above a first portion of the substrate layer and a second portion extending above a growth mask, and wherein forming an opening in the growth mask includes forming a recess in the second portion of the surface layer extending to the growth mask.

4. The manufacturing process of claim 3 further comprising forming an etching mask extending over a first portion of the surface layer and having an opening over a second portion of the surface layer, The formation of epitaxial multilayers includes: growing a working multilayer having a first portion extending over a second portion of the substrate layer and a second portion extending over the etch mask; as well as Remove the second part of the working multilayer, The etching mask extends from a surface which is arranged at a greater height from the substrate layer in one direction than the first part of the working multilayer in this direction.

5. The manufacturing process of claim 1, wherein the growth mask comprises an oxide layer, such as silicon oxide.

6. The manufacturing process of claim 1, wherein the thickness of the growth mask is in the range between 7 nm and 300 nm.

7. The manufacturing process of claim 1, wherein forming the first electronic component comprises forming a first doped region in the epitaxial region after forming the epitaxial multilayer.

8. The manufacturing process of claim 1, wherein the first electronic component is a MOS transistor having an insulated gate region, and forming the first electronic component includes forming the insulated gate region over the epitaxial region before forming the epitaxial multilayer.

9. The process of claim 1 wherein the single semiconductor material is silicon.

10. The manufacturing process of claim 1, wherein the single semiconductor material is silicon and the substrate layer is a single crystal silicon layer.

11. A device comprising: Die; A first electronic component on a single semiconductor material; as well as a second electronic component on the heterostructure, the second electronic component comprising a first conductive region coupled to the channel modulation region, The die includes: A substrate region of semiconductor material; a first surface portion comprising a single crystalline region of a single semiconductor material extending over a substrate region; and a second surface portion, different from the first surface portion and comprising an epitaxial multilayer extending over the substrate region, the epitaxial multilayer comprising a heterostructure, A first electronic component is integrated in a first surface portion of the die and a second electronic component is integrated in a second surface portion of the die, with the channel modulation region being located between the epitaxial multilayer and the first conductive region.

12. The apparatus of claim 11, wherein the die further comprises a third surface portion extending above the substrate region between the first surface portion and the second surface portion, the third surface portion comprising a polycrystalline region of a single semiconductor material monolithic with the single crystalline region.

13. The apparatus of claim 11, wherein the first component is one of: a CMOS transistor, a DMOS transistor, a bipolar transistor, or a passive electronic component on a single semiconductor material.

14. The apparatus of claim 11, wherein the second component is a high mobility transistor, wherein the heterostructure is based on materials from Group III and Group V of the periodic table.

15. The apparatus of claim 11, wherein the substrate region comprises a single crystalline substrate having a first conductivity type and at least one epitaxial layer having a second conductivity type different from the first conductivity type and extending on the substrate.

16. A device comprising: substrate; A first portion on the substrate, the first portion comprising: epitaxial region; and a first transistor extending into the epitaxial region along a first direction; a second portion on the substrate, separated from the first portion along a second direction transverse to the first direction; A third portion on the substrate is between the first portion and the second portion along the second direction, and the third portion includes: Define the layers; and Defines the polycrystalline region on the layer. The device of claim 16 , wherein the definition layer is a silicon oxide layer.

18. The device of claim 16, further comprising a second transistor in the second portion.

19. The apparatus of claim 16, wherein the second portion further comprises: a buffer layer on the substrate; a channel layer on the buffer layer; as well as A barrier layer on the channel layer.

20. The apparatus of claim 19, further comprising: a plurality of conductive regions on the barrier layer; as well as A channel modulation region between a first conductive region of the plurality of conductive regions and the barrier layer.

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