Semiconductor electronic device integrating heterostructure-based electronic components and having reduced mechanical stress

Abstract

The present disclosure relates to a semiconductor electronic device integrating a heterostructure-based electronic component and having reduced mechanical stress. A semiconductor electronic device has a substrate region of a semiconductor material; a heterostructure-based first electronic component having an epitaxial multilayer extending over the substrate region and including a heterostructure; and a separation region extending on the substrate region. The separation region includes a polycrystalline region of a polycrystalline-type semiconductor material arranged alongside the epitaxial multilayer along the first direction. The electronic device also has an epitaxial region of a single semiconductor material of a single crystal type extending over the substrate region. The polycrystalline region extends along a first direction between the epitaxial multilayer and the epitaxial region.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor electronic device integrating electronic components based on heterostructures and having reduced mechanical stress. The present disclosure also relates to a manufacturing process of the semiconductor electronic device. Background Art

[0002] Semiconductor electronic devices are known which include silicon-based active and / or passive electronic components (e.g. CMOS, DMOS, BJT transistors, diodes, resistors, etc.) which are integrated in the same silicon die and are manufactured, for example, using BCD (Bipolar-CMOS-DMOS) technology.

[0003] In practice, the operation of these electronic components is based on the electronic properties of a single semiconductor material: silicon.

[0004] These devices monolithically integrate digital circuits, analog circuits, and power circuits on the same die, operating at voltages that are very different from each other, e.g., from a few volts in the case of CMOS transistors for implementing logic functions up to hundreds of volts in the case of DMOS transistors for power applications.

[0005] Silicon-based electronic components are integrated into <100> A region of single crystal silicon grown on a silicon wafer.

[0006] Semiconductor electronic devices including heterostructure-based electronic components, such as HEMT transistors, are also known.

[0007] In practice, the operation of these electronic components is based on the electronic properties of a heterojunction between two different semiconductor materials.

[0008] In detail, in a HEMT transistor, a conductive channel is based on the formation of a two-dimensional electron gas (2DEG) layer with high mobility formed at a heterojunction (i.e., at an interface between semiconductor materials with different band gaps). For example, a HEMT device based on a heterojunction between an aluminum gallium nitride (AlGaN) layer and a gallium nitride (GaN) layer is known.

[0009] HEMT devices, especially those based on AlGaN / GaN heterostructures or heterojunctions, have several advantages that make them particularly suitable and widely used in different applications. For example, the high breakdown threshold of HEMT devices is used for high-performance power switches; the high mobility of electrons in the conduction channel allows the formation of high-frequency amplifiers; in addition, the high electron concentration in the 2DEG allows for low on-state resistance (R ON ).

[0010] Furthermore, HEMT devices used in radio frequency (RF) applications generally have better RF performance than similar silicon LDMOS devices.

[0011] Heterostructure-based electronic components are integrated into <111> In heterostructures grown epitaxially on silicon wafers or on sapphire (Al2O3) or silicon carbide (SiC) substrates.

[0012] Applicants have observed that growing heterostructures on silicon wafers can cause high mechanical stresses in the silicon wafer due to the different lattice pitches between the growth substrate (silicon) and the material forming the heterostructure (eg, GaN / AlGaN).

[0013] High mechanical stress can cause dislocations in the silicon wafer.

[0014] Dislocations can compromise the mechanical stability of the silicon wafer on which the heterostructure-based electronic components are formed. As a result, the heterostructure-based electronic components are susceptible to damage during manufacturing and in use.

[0015] Furthermore, due to the presence of electronic components based on silicon and integrated in silicon wafers, high mechanical stresses and dislocations can impair the mechanical stability and performance of silicon-based components.

[0016] Therefore, heterostructure-based electronic components and silicon-based electronic components are integrated into different dies from each other, starting from two different silicon wafers.

[0017] However, this means that electronic devices combining both silicon-based and heterostructure-based components have a high footprint and therefore high manufacturing cost, high power consumption and low electrical performance, for example due to parasitic capacitance or inductance introduced by electrical connections between the dies.

[0018] According to one method, a die in which a silicon-based component is formed and a die in which a heterostructure-based component is formed are bonded to each other by a die transfer technique.

[0019] However, even this approach has disadvantages in terms of cost and manufacturing as well as electrical performance reliability. Summary of the invention

[0020] Therefore, according to the present disclosure, a semiconductor electronic device and a manufacturing process of the semiconductor electronic device are provided. A system includes a semiconductor substrate, a first electronic device located on the semiconductor substrate. The first electronic device includes a heterostructure and an epitaxial multilayer. The separation region separates the first electronic device. The separation region includes a groove region, a polycrystalline portion, and an epitaxial region located on the semiconductor substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] For a better understanding of the present disclosure, embodiments thereof will now be described by way of non-limiting examples only, with reference to the accompanying drawings, in which:

[0022] Figure 1shows a cross section of a semiconductor electronic device according to an embodiment;

[0023] Figure 2 Shows Figure 1 A top plan view of the device;

[0024] FIG. 3A to FIG. 3O It shows that according to the embodiment Figure 1 steps in a manufacturing process of a device;

[0025] Figure 4 and Figure 5 According to other embodiments Figure 2 a top plan view of a portion of the device; and

[0026] Fig. 6A and Figure 6B Steps of a process for manufacturing a semiconductor electronic device according to various embodiments are shown. DETAILED DESCRIPTION

[0027] The following description refers to the arrangements shown in the accompanying drawings; therefore, expressions such as "upper", "lower", "lower", "upper", "right", "left", "high", "lower", etc. are related to the drawings and should not be interpreted in a limiting manner.

[0028] Figure 1 and Figure 2 A semiconductor electronic device (hereinafter simply referred to as device) 1 is shown in a Cartesian reference system XYZ having a first X axis, a second Y axis and a third Z axis.

[0029] The device 1 is formed in a die 3 and comprises: one or more silicon-based electronic components 5, with respect to the silicon-based electronic components 5 being Figure 1 A PMOS transistor 5A and an NMOS transistor 5B are shown; and one or more electronic components based on a heterostructure, about the electronic components based on the heterostructure in Figure 1 HEMT transistors 7 are shown, all of which are integrated in the die 3 .

[0030] The die 3 comprises a substrate region 10 and a surface region 12 extending on the substrate region 10 , in particular in direct contact with the substrate region 10 .

[0031] The substrate region 10 includes a substrate 14 and one or more epitaxial layers disposed on the substrate 14 .

[0032] The substrate 14 is made of a semiconductor material (particularly a single crystal), and has an upper surface 14A.

[0033] In detail, in this embodiment, the substrate 14 is made of single crystal silicon, and in particular, the upper surface 14A is formed according to <111> Crystal orientation.

[0034] In this embodiment, the substrate region 10 includes: a first epitaxial layer, or a first deep layer 15, overlying the upper surface 14A of the substrate 14; a second epitaxial layer, or a first intermediate layer 16, overlying the first deep layer 15; a third epitaxial layer, or a second deep layer 17, overlying the first intermediate layer 16; and a fourth epitaxial layer, or a second intermediate layer 18, overlying the second intermediate layer 17.

[0035] The epitaxial layers 15-18 are made of a semiconductor material, in particular the same semiconductor material as the substrate 14 (here silicon), and are not shown for the sake of clarity. Figure 1 Identified by dotted lines.

[0036] During the design phase, the thickness along the third axis Z, the conductivity type (eg, P or N), and the doping profile of the substrate 14 and the epitaxial layers 15 - 18 may be selected according to the specific application of the device 1 .

[0037] For example, epitaxial layers 15 - 18 may each have a thickness between 0.1 μm and 7 μm.

[0038] For example, in this embodiment, the substrate 14 is of P type, for example, with a resistivity between 0.1 Ω·cm and 20 Ω·cm, and the epitaxial layers 15-18 are of N type. In this way, the first deep layer 15 can form a PN junction with the substrate 14, which can be used to insulate the devices 5, 7 integrated into the die 3 from the substrate 14 in use.

[0039] The first and second deep layers 15, 17 may have a different (particularly higher) doping level relative to the first and second intermediate layers 16, 18. For example, the doping levels of the layers 15-18 may such as provide a resistivity between, for example, 0.1 Ω·cm and 20 Ω·cm.

[0040] The high doping level of the first deep layer 15 causes, in use, a depletion region between the first deep layer 15 and the substrate 14 to extend mainly into the substrate 14 , thereby improving the electrical insulation of the components 5 , 7 from the substrate 14 .

[0041] Furthermore, the high doping level of the first deep layer 15 may allow, in use, to use the first deep layer 15 as a current conducting region of an electronic component integrated into the die 3 , for example if the silicon based component 5 comprises a BJT transistor.

[0042] If the electronic components 5, 7 are designed to operate at high voltages relative to the substrate 14, for example starting from about 60V up to about 650V, or even higher, then the presence of both the first and second deep layers 15, 17 may be useful for simplifying the manufacture of the device 1 and obtaining excellent electrical performance of the device 1 during use.

[0043] The surface region 12 extends on the second intermediate layer 18 , in particular in direct contact therewith, and comprises a first device portion 20 in which the PMOS 5A and NMOS 5B transistors are integrated, and a second device portion 21 in which the HEMT transistor 7 is integrated.

[0044] The first device portion 20 has an upper surface 20A and comprises an epitaxial region 23 of a single-crystalline semiconductor material, in particular, the same material as the second intermediate layer 18 , here single-crystalline silicon.

[0045] The epitaxial region 23 extends from the second intermediate layer 18 , in particular here in direct contact with the second intermediate layer 18 , as far as the upper surface 20A.

[0046] The thickness along the third axis Z, the conductivity type (eg, P or N) and the doping profile of the epitaxial region 23 may be selected at the design stage according to the specific application of the device 1 .

[0047] For example, in this embodiment, the epitaxial region 23 is of N-type.

[0048] The first device portion 20 comprises a plurality of doped regions which extend within the epitaxial region 23 and form functional regions of the silicon-based electronic component 5 .

[0049] In practice, silicon-based electronic components 5 , here PMOS 5A and NMOS 5B transistors, are integrated in the epitaxial region 23 .

[0050] In detail, Figure 1 In the embodiment of FIG. 5 , P++ type doped regions 25A and 25B extend from the upper surface 20A in the epitaxial region 23 . The doped regions 25A and 25B respectively form the source region and the drain region of the PMOS transistor 5A and define the channel region 26 of the PMOS transistor 5A.

[0051] Furthermore, an N++-type doped region 27 extends from the upper surface 20A in the epitaxial region 23 and forms a body contact region of the PMOS transistor 5A.

[0052] Still refer to Figure 1 In the embodiment, the P-type doped region 28 extends from the upper surface 20A in the epitaxial region 23 and forms the body region of the NMOS transistor 5B.

[0053] N++ type doped regions 29A, 29B extend in the doped region 28 and respectively form a source region and a drain region of the NMOS transistor 5B and define a channel region 30 of the NMOS transistor 5B.

[0054] Furthermore, a P++ type doped region 31 extends within the doped region 28 and forms a body contact region of the NMOS transistor 5B.

[0055] In practice, the doped regions 25A, 25B, 27, 29A, 29B and 31 (ie, the source, drain doped regions and the body contact region) are highly doped regions, with a peak doping level of, for example, between 5·10 19 cm -3 and 5.10 20 cm -3 In contrast, the doped region 28 (ie, the body region) is a low-doped region, with a doping level of, for example, between 1·10 16 cm -3 and 2.10 18 cm -3 between.

[0056] The number, arrangement, shape, size and doping profile of the doped regions may be selected during the design phase according to the specific silicon-based electronic components 5 integrated in the die 3 and according to the specific application of the device 1 .

[0057] Depending on the specific application, insulating portion 33 of insulating material (eg, oxide) may extend from upper surface 20A within epitaxial region 23 .

[0058] In particular, Figure 1 In the embodiment, the insulating portion 33 extends parallel to the first axis X between the doped regions 27 and 25A, 25B and 31, 31 and 29A.

[0059] A first insulating layer 35 (eg, oxide or nitride) extends over the upper surface 20A of the first device portion 20 .

[0060] A second insulating layer 36 (eg, oxide) extends over the first insulating layer 35 .

[0061] The surface structure 38 of the silicon-based component 5 extends over the upper surface 20A of the first device region 20, in direct contact therewith. Depending on the specific silicon-based electronic component 5 integrated into the die 3, the surface structure 38 forms a further functional area of ​​the silicon-based device 5 and may include various conductive and / or insulating areas.

[0062] In this embodiment, the surface structure 38 includes gate insulating regions 40, 41, which extend over the channel region 26 of the PMOS transistor 5A and over the channel region 30 of the NMOS transistor 5B, respectively. For simplicity, regarding the gate insulating regions 40, 41, Figure 1 Only the respective conductive regions (here polysilicon, again indicated by 40 , 41 ) are shown, each having a respective upper surface 40A, 41A.

[0063] even though Figure 1 Not shown, the gate insulation regions 40, 41 may also each include a corresponding insulation region arranged between the corresponding polysilicon region and the upper surface 20A, and a corresponding contact region of a conductive material (e.g., metal) that contacts the corresponding surface 40A, 41A and forms the corresponding gate terminal G.

[0064] exist Figure 1 In the embodiment, the surface structure 38 also includes source contact regions 42, 43 and drain contact regions 44, 45 of conductive material, which extend through the first and second insulating layers 35, 36 and directly contact the upper surface 20A to form corresponding source S and drain D terminals.

[0065] Specifically, the source contact regions 42 and 43 extend in direct contact with the source region 25A of the PMOS transistor 5A and the source region 29A of the NMOS transistor 5B, respectively.

[0066] Furthermore, in the embodiment shown, the source contact regions 42 , 43 each also extend in direct contact with the respective body contact region 27 , 31 .

[0067] The drain contact regions 44 and 45 extend in direct contact with the drain region 25B of the PMOS transistor 5A and the drain region 29B of the NMOS transistor 5B, respectively.

[0068] The second device portion 21 of the surface region 12 has an upper surface 21A and includes an epitaxial multilayer 49 extending on and grown from the second intermediate layer 18 .

[0069] The epitaxial multilayer 49 comprises a heterostructure 50 in which the HEMT transistor 7 is integrated.

[0070] exist Figure 1 In the embodiment of the present invention, the epitaxial multilayer 49 further comprises a transition region, which is formed here by first and second buffer layers 52, 53 overlying each other, which are arranged between the second intermediate layer 18 and the heterostructure 50. The transition region may be useful during the manufacture of the device 1 to facilitate the epitaxial growth of the heterostructure 50 on the second intermediate layer 18.

[0071] In detail, the first buffer layer 52 (eg, aluminum nitride (AlN)) extends on and directly contacts the second intermediate layer 18 , and the second buffer layer 53 (eg, aluminum gallium nitride (AlGaN)) extends on and directly contacts the first buffer layer 52 .

[0072] The heterostructure 50 includes a compound semiconductor material including elements of Group III and Group V of the periodic table, and forms an upper surface 21A of the second device portion 21 .

[0073] Depending on the specific manufacturing steps used to manufacture the device 1 , the upper surface 21A of the second device portion 21 may extend to coordinates along the third axis Z that are equal to or different from the coordinates of the upper surface 20A of the first device portion 20 .

[0074] In particular, in this embodiment, the upper surface 21A of the second device part 21 is arranged at a lower height relative to the upper surface 20A of the first device part 20 , measured along the third axis Z. This may allow for improved manufacturing of the device 1 .

[0075] The heterostructure 50 includes a channel layer 55 and a barrier layer 56 overlying each other.

[0076] The channel layer 55 is made of a first semiconductor material (eg, gallium nitride (GaN) or an alloy including gallium nitride (such as InGaN)), here made of gallium nitride (GaN), extends over the transition region, in particular, over the second buffer layer 53, and has an upper surface 55A.

[0077] The barrier layer 56 is made of a second semiconductor material (e.g., a compound based on a ternary or quaternary gallium nitride alloy, such as Al x Ga 1-x N, AlInGaN, In x Ga 1-x N、Al x In 1-x The second device portion 21 is made of Al, AlScN (here, aluminum gallium nitride (AlGaN)), and extends between the upper surface 55A of the channel layer 55 and the upper surface 21A of the second device portion 21.

[0078] According to specific applications, the channel layer 55 and the barrier layer 56 may be of intrinsic type, P type or N type; in particular, both the channel layer 55 and the barrier layer 56 may be of N type.

[0079] For example, when the barrier layer 56 is AlGaN, the presence of aluminum atoms will make the barrier layer 56 N-type.

[0080] The heterostructure 50 is configured to accommodate a two-dimensional gas (2DEG) of (mobile) charge carriers, in particular electrons here, which is arranged at the interface between the channel layer 55 and the barrier layer 56 , ie at the upper surface 55A of the channel layer 55 .

[0081] An insulating layer 58 , for example made of an oxide such as silicon oxide, having an upper surface 58A, extends over upper surface 21A, for example with a thickness comprised between 20 nm and 1 μm.

[0082] The insulating layer 36 also extends over the second device portion 21 , in particular over the insulating layer 58 .

[0083] The surface structure 60 of the heterostructure-based component 7 extends over the upper surface 21A of the second device part 21 .

[0084] Depending on the specific heterostructure-based electronic component 7 integrated in the die 3 , the surface structure 60 may be various conductive and / or insulating areas, which form functional areas of the heterostructure-based component 7 .

[0085] In this embodiment, in which the heterostructure-based electronic component 7 is a HEMT transistor, the surface structure 60 comprises a source region 61 and a drain region 62 made of an electrically conductive material, which extend at a distance from each other along a first axis X.

[0086] The source region 61 and the drain region 62 are in electrical contact, in particular ohmic contact, with the heterostructure 50 , in particular with the two-dimensional gas formed at the interface between the channel layer 55 and the barrier layer 56 , and form a source terminal S and a drain terminal D of the HEMT transistor 7 , respectively.

[0087] exist Figure 1 In the embodiment of FIG. 5 , the source and drain regions 61 , 62 extend parallel to the third axis Z through the insulating layers 36 , 58 to the upper surface 21A.

[0088] However, depending on the specific application, the source and drain regions 61 , 62 may also extend partially through the heterostructure 50 parallel to the third axis Z, for example a portion of the barrier layer 56 or the entire thickness of the barrier layer 56 up to the surface 55A.

[0089] The surface structure 60 also comprises a gate structure, here formed by a channel modulation region 64 and a gate contact region 65, which can be biased to electrically control the formation of a two-dimensional gas in the heterostructure 50 between the source region 61 and the drain region 62. The gate structure forms the gate terminal G of the HEMT transistor 7.

[0090] In this embodiment, the HEMT transistor 7 is of a normally-off type, ie, an enhancement type.

[0091] In detail, in this embodiment, the channel modulation region 64 is made of a semiconductor material and has a different conductivity type, for example, P-type, relative to the barrier layer 56. In particular, the channel modulation region 64 may be made of P-type gallium nitride (p-GaN).

[0092] However, the channel modulation region 64 may also be made of a different material, such as a dielectric material, thereby obtaining an insulating gate structure.

[0093] The channel modulation region 64 extends along the first axis X between the source region 61 and the drain region 62 on the upper surface 21A, and has an upper surface 64A.

[0094] Depending on the specific manufacturing steps used to manufacture the device 1 , the upper surface 64A of the channel modulation region 64 may extend at coordinates along the third axis Z that are equal to or different from the coordinates of the upper surfaces 40A, 41A of the gate insulating regions 40 , 41 .

[0095] In particular, in this embodiment, the upper surface 64A of the channel modulation region 64 is arranged at a distance from the second intermediate layer 18 measured along the third axis Z that is smaller than the distance from the upper surfaces 40A, 41A of the gate insulating regions 40, 41 to the second intermediate layer 18 measured along the third axis Z. This may allow for improved manufacturing reliability of the device 1.

[0096] A gate contact region 65 made of an electrically conductive material extends in electrical contact with the channel modulation region 64 , in particular here in contact with the upper surface 64A.

[0097] The device 1 further comprises a separation region 70 in the surface region 12 of the die 3 , which extends over the substrate region 10 , in particular over the second intermediate layer 18 in direct contact therewith, beside the epitaxial multilayer 49 .

[0098] refer to Figure 1 and Figure 2 In the arrangement, the separation region 70 extends parallel to the first axis X between the epitaxial multilayer 49 and the epitaxial region 23.

[0099] In this embodiment, if Figure 2 As can be seen in FIG. 4 , the separation region 70 surrounds the epitaxial multilayer 49 .

[0100] In detail, the separation region 70 comprises a defined region 72 made of a material different from that of the second intermediate layer 18, and a polycrystalline region made of a polycrystalline semiconductor material, in particular polycrystalline silicon, which is here formed by two polycrystalline portions 73A, 73B.

[0101] The defined region 72 may be formed of a single layer, such as an oxide, in particular silicon oxide, or may be formed of multiple layers, such as including one or more layers of oxide and / or one or more layers of nitride.

[0102] In detail, according to one embodiment, the definition region 72 may be made of silicon oxide.

[0103] According to various embodiments, the defined region 72 may include an oxide layer, in particular silicon oxide, and a nitride layer. According to one embodiment, the oxide layer may be in direct contact with the second intermediate layer 18 .

[0104] The defined region 72 extends in direct contact with the second intermediate layer 18 .

[0105] The defined area 72 may have a diameter along the third axis Z of, for example, between 7 nm and 300 nm, in particular and The thickness between.

[0106] Polycrystalline portions 73A, 73B extend over defined region 72 and surround epitaxial multilayer 49 .

[0107] The separation region 70 also comprises a trench 75 which extends within the polycrystalline region, in particular here between the two polycrystalline portions 73A, 73B.

[0108] In detail, the groove 75 separates the two polycrystalline portions 73A, 73B from one another. In practice, in this embodiment, the two polycrystalline portions 73A, 73B are distinct from one another and extend at a distance from one another.

[0109] The trench 75 has a width W, measured between the two polycrystalline portions 73A, 73B, which may be between 0.2 μm and 3 μm (which may or may not include boundaries).

[0110] The polycrystalline portion 73A extends outside the trench 75 and, in this embodiment, is connected (monolithically) to the epitaxial region 23. In practice, the polycrystalline portion 73A forms the outer sidewall 76 of the separation region 70.

[0111] The inclination of the outer sidewall 76 may depend on the crystal orientation of the epitaxial region 23 and on the thickness of the defined region 75 along the third axis Z. For example, in the epitaxial region 23 according to <111> When the crystal direction is oriented, the outer sidewall 76 can form an angle of about 54° with a direction parallel to the first axis X.

[0112] The polycrystalline portion 73B extends inside the trench 75, where it contacts the epitaxial multilayer 49. In practice, the polycrystalline portion 73B forms the inner sidewalls 77 of the separation region 70.

[0113] The inclination of inner sidewall 77 may depend on the specific fabrication steps used to fabricate epitaxial multilayer 49 .

[0114] Depending on the specific manufacturing steps used to make the device 1, the trenches 75 may be partially or fully filled, or may be empty.

[0115] refer to Figure 1Trench 75 includes a peripheral portion 79 formed of one or more materials forming epitaxial multilayer 49 , and a central portion 80 , which may be empty or fully or partially filled with an insulating material, such as the same material forming insulating layer 36 .

[0116] In this embodiment, polycrystalline portions 73A, 73B extend at a distance from upper surface 20A. In detail, insulating region 82 of insulating material (eg oxide) extends in die 3 from upper surface 20A towards the inside of epitaxial region 23 and separation region 70 .

[0117] exist Figure 1 In the embodiment of FIG. 8 , epitaxial multilayer 49 includes a peripheral portion 84 that conformally extends over inner sidewalls 77 of separation region 70 and forms a raised surface 84A.

[0118] The raised surface 84A is arranged at a greater coordinate along the third axis Z with respect to the upper surface 21A and is here even larger than the upper surface 58A of the insulating layer 58 .

[0119] Furthermore, in this embodiment, trench 75 extends along third axis Z and also through insulating region 82 to a coordinate greater than upper surface 20A along third axis Z, specifically aligned with raised surface 84A. However, the shape and structure of trench 75 depends on the specific manufacturing steps used.

[0120] The polycrystalline region of the separation region 70 formed here by the polycrystalline portions 73A, 73B beside the epitaxial multilayer 49 serves as a spacing region between the epitaxial multilayer 49 and the epitaxial region 23 .

[0121] In fact, the presence of the polycrystalline region allows absorbing the mechanical stresses caused by the different lattice pitches between the material forming the epitaxial region 23 (here silicon) and the material forming the heterostructure 50 (here AlN, GaN and AlGaN).

[0122] Therefore, the heterostructure 50 is laterally subjected to low mechanical stress. As a result, the heterostructure 50 can have good crystal quality, so that the HEMT transistor 7 can have good electrical performance when used.

[0123] The presence of the separation region 70 also results in low mechanical stresses on the epitaxial region 23 and a low risk of dislocations. Thus, silicon-based electronic components 5 can be integrated into the epitaxial region 23 .

[0124] Furthermore, the Applicant has verified that the presence of the trench 75 helps to further reduce the mechanical stress next to the epitaxial multilayer 49 .

[0125] In practice, the device 1 may allow combining the functionality of silicon-based components 5 and heterostructure-based components 7 in a single die while maintaining a small size relative to electronic devices in which the silicon-based components 5 and heterostructure-based components 7 are integrated on different dies from each other.

[0126] Furthermore, electrical connections between the silicon-based component 5 and the heterostructure-based component 7 may be formed directly on the die 3. This may ensure high electrical performance of the device 1 in use.

[0127] Reference below FIG. 3A to FIG. 3O The manufacturing steps of the semiconductor electronic device 1 are described.

[0128] Figure 3A A cross section of a wafer 100 of a single crystal semiconductor material (particularly silicon) having an upper surface 100A is shown. Figure 1 Elements common to elements already described are denoted by the same reference numerals and are not described again in detail.

[0129] Wafer 100 includes a substrate 14 on which epitaxial layers 15 , 16 , 17 , and 18 have been grown.

[0130] The fourth epitaxial layer or the second intermediate layer 18 forms the upper surface 100A of the wafer 100 .

[0131] The second intermediate layer 18 comprises a first portion 101A on which the epitaxial region 23 is intended to be formed, a second portion 101B on which the epitaxial multilayer 49 is intended to be formed, and a third portion 101C on which the separation region 70 is intended to be formed.

[0132] Then, Figure 3B , a definition layer 102 including an oxide (eg, silicon oxide) is formed on the upper surface 100A.

[0133] The defining layer 102 may be a single layer or multiple layers, as discussed with respect to the defining regions 72 .

[0134] The definition layer 102 may have a thin thickness along the third axis Z, for example between 7 nm and 300 nm, in particular and between.

[0135] The limiting layer 102 is intended to form a limiting region 72 ( Figure 1 ).

[0136] The defining layer 102 may be formed by oxidizing a surface portion of the second intermediate layer 18 or by being deposited on the upper surface 100A. In the case of oxidation, the thickness of the second intermediate layer 18 after oxidation will be relatively Figure 3AHowever, given that the thickness of the defining layer 102 is much smaller than the thickness of the second intermediate layer 18, for simplicity it can be assumed that the thickness of the second intermediate layer 18 remains the same before and after oxidation (as a first approximation).

[0137] Then, Figure 3C The defining layer 102 is removed at the first portion 101A of the second intermediate layer 18 (ie, the portion of the second intermediate layer 18 on which the epitaxial region 23 is intended to be formed). Therefore, a portion of the defining layer 102 remains, also referred to as a growth mask 103 hereinafter.

[0138] In practice, the growth mask 103 exposes the first portion 101A of the second intermediate layer 18 and covers the second and third portions 101B, 101C of the second intermediate layer 18 .

[0139] exist Figure 3D In the process, a surface layer 105 of a semiconductor material is grown on the wafer 100, which semiconductor material is in particular the same material as the second intermediate layer 18 (here silicon).

[0140] The surface layer 105 has an upper surface 105A.

[0141] The surface layer 105 comprises an epitaxial portion 106 grown parallel to the third axis Z from the second intermediate layer 18 , in particular from the respective first portion 101A, and a sacrificial portion 107 grown parallel to the third axis Z on the growth mask 103 .

[0142] The epitaxial portion 106 grown from the single-crystal substrate maintains the single-crystal structure of the second intermediate layer 18 and is intended to form the epitaxial region 23 .

[0143] The sacrificial portion 107 grown from the amorphous substrate has a polycrystalline structure.

[0144] exist Figure 3E In the embodiment, a doped region 28 corresponding to the body region of the NMOS transistor 5B is formed in the surface layer 105 , and an insulating layer 108 is optionally formed.

[0145] In detail, the body region 28 is formed in the epitaxial portion 106 forming the silicon-based component 5 .

[0146] The body region 28 may be formed by implantation of dopant ions.

[0147] The insulating layer 108 (eg, silicon oxide) forms the insulating portion 33 ( Figure 1 ) and is intended to form an insulating region 82 ( Figure 1 ) section 109.

[0148] The insulating layer 108 may be formed by forming an insulating trench, such as a shallow trench isolation (STI), in the surface layer 105. In this case, the thickness of the epitaxial portion 106 and the sacrificial portion 107 may be reduced in response to the formation of the insulating layer 108. The portion 109 may be continuous or formed of a plurality of structures separated from each other, such as by alternating dielectric regions having different thicknesses from each other.

[0149] In addition, reference Figure 3E Depending on the specific silicon-based electronic components 5 that are desired to be integrated into the die 3 of the device 1 , one or more surface layers 110 may be formed on the upper surface 105A of the surface layer 105 .

[0150] In the embodiment shown, the surface layer 110 is intended to form the gate insulation regions 40, 41 ( Figure 1 ). In particular, only a single gate layer in the surface layer 110 is shown here, here polysilicon, still indicated by 110. However, an oxide layer (not shown here) is formed between the upper surface 105A and the polysilicon layer 110 in a manner known per se.

[0151] The polysilicon layer 110 has an upper surface 110A.

[0152] A mask sacrificial layer 111 having an upper surface 111A is formed on the surface 110A of the gate layer 110. The mask sacrificial layer 111 may be a single layer or multiple layers, for example, including silicon oxide, silicon nitride, aluminum oxide, silicon carbide, or a combination thereof.

[0153] exist Figure 3F In the embodiment, an opening 113 is opened above the sacrificial portion 107 .

[0154] The opening 113 is formed by selectively removing portions of the layers 110 , 111 , thereby exposing the underlying sacrificial portion 107 , in particular the portion facing the second portion 101B of the second intermediate layer 18 .

[0155] The remaining portion of the sacrificial layer 111 may be used as an etching mask.

[0156] Then, Figure 3G , the insulating layer 108 and the sacrificial portion 107 at the opening 113 are removed using the etching mask 111 .

[0157] Therefore, in the sacrificial portion 107, the third portion 101C arranged under the etching mask and facing the second intermediate layer 18 remains and will form Figure 1 The polycrystalline portions 73A, 73B of the embodiment of the present invention are shown in FIG. 1 (here indicated as the working polycrystalline region 114 ).

[0158] exist Figure 3G When etching, the recess formed in the sacrificial portion 107 is continuous with the opening 113 and exposes a portion of the growth mask 103 facing the second portion 101B of the second intermediate layer 18 .

[0159] exist Figure 3H In the growth mask 103, the exposed portion of the growth mask 103 is removed. Therefore, in the growth mask 103, the portion arranged below the working polycrystalline region 114 remains, that is, Figure 1 The limited area 72.

[0160] The etching of the exposed portions of the growth mask 103 may be performed using a selective chemical method that will not etch (as a first approximation) the underlying second intermediate layer 18 .

[0161] Therefore, in Figure 3H When etching, the opening 113 also exposes the second portion 101B of the second intermediate layer 18 .

[0162] exist Fig. 3I In the embodiment, the etching mask 111 is formed by opening corresponding windows and removing the exposed portion of the working polycrystalline region 114. Figure 1 Thus, in the working polycrystalline region 114, the polycrystalline portions 73A and 73B are retained.

[0163] In this embodiment, the formation of trench 75 also includes removing portions of insulating layer 109 .

[0164] Can be used to form Figure 3G The removal of the exposed portion of the working polycrystalline region 114 is performed using the same chemical method as the recess 113 .

[0165] Then, Figure 3J , grown on the wafer 100 to form Figure 1 The epitaxial multilayer 49 is a working multilayer 117.

[0166] In detail, a first buffer layer is grown on the wafer 100. Figure 1 The first buffer layer 52 corresponds to the first buffer layer 52 of the upper surface 100A and is therefore indicated by the same reference numerals. The first buffer layer 52 extends on the exposed portion of the upper surface 100A, on the inner sidewall 77 and on the etching mask 111.

[0167] A second buffer layer is grown on the first buffer layer 52. Figure 1 The buffer layer 53 corresponds to and is therefore denoted by the same reference numeral.

[0168] A channel layer is grown on the second buffer layer 53. Figure 1 The channel layer 55 corresponds to and is therefore denoted by the same reference numeral.

[0169] A barrier layer is grown on the channel layer 55. Figure 1 The barrier layer 56 corresponds to and is therefore indicated by the same reference numeral.

[0170] In the embodiment shown, a portion of the working epitaxial multilayer 117 is also grown within the trench 75 , in particular here conformally to the walls of the trench 75 , thereby forming a filling portion 118 and leaving a central portion 119 of the trench 75 empty.

[0171] Without loss of generality, the filling portion 118 can be formed by one or more of the materials forming the working multilayer 117 (e.g., AlN, AlGaN and / or GaN) or other materials (such as, for example, dielectrics or insulators, such as, for example, oxides or silicon nitrides, aluminum oxide, etc.), and depending on the specific growth conditions used to grow the working multilayer 117, the specific shape of the filling portion 118 can be different from that shown.

[0172] In practice, the working multilayer 117 includes, in addition to the filling portion 118 , a raised portion 120 extending on the etching mask 111 and on the inner sidewalls 77 of the separation region 70 , and a useful portion 121 extending directly on the upper surface 100A of the second intermediate layer 18 .

[0173] The useful portion 121 has a substantially planar upper surface 121A, in particular substantially parallel to the upper surface 100A.

[0174] The useful portion 121 grown on the second intermediate layer 18 is of single-crystalline type and is used for integrating the heterostructure-based device 7 .

[0175] Then, Figure 3K The channel modulation region 64 is formed on the upper surface 121A of the useful portion 121 in a manner known per se, for example by growing and defining specific layers.

[0176] In practice, in this embodiment, the useful portion 121 of the working multilayer 117 also includes the channel modulation region 64 .

[0177] Here, therefore, the surface 64A of the modulation zone 64 forms the most elevated surface of the useful portion 121 , ie the surface of the useful portion 121 which is at the greatest distance along the third axis Z from the surface 100A.

[0178] The surface 110A on which the etching mask 111 extends may be arranged at a distance from the surface 100A along the third axis Z which is greater than the highest surface of the useful portion 121. This may be useful in subsequent manufacturing steps to protect the channel modulation region 64 and thus improve the reliability of the manufacturing process of the device 1.

[0179] Figure 3L A protective layer 124 of insulating material, such as a single layer or multiple layers, is formed on the barrier layer 56. For example, the protective layer 124 includes silicon oxide, silicon nitride, aluminum oxide, silicon carbide or a combination thereof. The protective layer 124 has a thickness along the third axis Z that is greater than the thickness of the channel modulation region 64, for example, between 10 nm and 500 nm.

[0180] In other words, the protection layer 124 completely covers the channel modulation region 64 .

[0181] Protection layer 124 has an upper surface 124A facing upper surface 121A of useful portion 121 at useful portion 121 .

[0182] In this embodiment, the upper surface 124A of the protection layer 124 extends at a height from the surface 100A along the third axis Z that is lower than the height of the upper surface 111A of the etching mask 111 from the surface 100A along the third axis Z. This may be useful in subsequent manufacturing steps to protect the channel modulation region 64 and thus improve the reliability of the manufacturing process of the device 1.

[0183] In addition, in this embodiment, the distance between the upper surface 124A of the protective layer 124 and the upper surface 64A of the channel modulation region 64 along the third axis Z is greater than the thickness of the etching mask 111 along the third axis Z, which may be useful in subsequent process steps to protect the channel modulation region 64 and thereby improve the reliability of the manufacturing process of the device 1.

[0184] exist Figure 3M In the embodiment, the raised portion 120 of the working multilayer 117 is at least partially removed until the upper surface 111A of the etching mask 111 , thereby exposing the etching mask 111 .

[0185] Removal may be performed by planarization (eg, chemical mechanical polishing (CMP) or other etching techniques).

[0186] In the embodiment shown, after the raised portion 120 of the working multilayer 117 has been removed, only the portion extending on the inner side wall 77 remains, which forms the peripheral portion 84 ( Figure 1 ), whose surface 84A is flush with the upper surface 111A of the etching mask 111.

[0187] In the protective layer 124 , a portion still remains, which is indicated by 124 , and which extends over the useful portion 121 of the working multilayer 117 .

[0188] Then, Figure 3N , the wafer 100 is etched to remove the etching mask 111 , thereby exposing the gate layer 110 .

[0189] In this embodiment, the etching of the etching mask 111 also etches the protection layer 124, thereby reducing its thickness. However, since the thickness of the etching mask 111 is less than the distance between the upper surface 64A of the channel modulation region 64 and the upper surface 124A of the protection layer 124, the remaining protection layer 124 still completely covers the channel modulation region 64. Therefore, the channel modulation region 64 will not be damaged by the etching. Figure 3N damaged by etching.

[0190] After etching, the protective layer 124 forms a reference Figure 1 The insulating layer 58 is described.

[0191] Depending on the materials forming the etching mask 111 and the protective layer 118 and depending on the specific etching used to remove the etching mask 111, Figure 3N The etching may selectively remove only the etching mask 111 without removing the protection layer 124 .

[0192] Then, Fig.3O , defining a gate layer 110, thereby forming gate insulating regions 40, 41. Furthermore, (highly) doped regions 25A, 25B, 27, 29A, 29B, 31 are formed in the epitaxial portion 106 of the surface layer 105, for example by subsequent masking and ion implantation steps, depending on the specific application.

[0193] Subsequent manufacturing steps (not shown here) are used to form insulating and / or passivation layers (e.g., Figure 1 oxide layers 35, 36) and metal contact areas (e.g., Figure 1 areas 42-45 and 61, 62, 65).

[0194] Furthermore, final manufacturing steps (not shown here) follow, such as, for example, forming an upper layer of metal interconnects and dicing the wafer, which results in the formation of the device 1 .

[0195] In practice, the use of growth mask 103 allows the formation of Figure 1 The separation region 70. Therefore, the growth of the epitaxial multilayer 49 can generate low mechanical stress and thus reduce the probability of dislocation. Therefore, the manufacturing process has high reliability.

[0196] Furthermore, the use of growth mask 103 allows simultaneously growing single-crystalline epitaxial part 106 in which silicon-based electronic components 5 can be integrated, while ensuring the surface quality of upper surface 100A below growth mask 103 on which working multilayer 114 is grown.

[0197] This manufacturing process thus allows integrating both silicon-based electronic components 5 and heterostructure-based electronic components 7 in the same die, while obtaining a high crystalline quality of the heterostructure 50 .

[0198] The fact that the growth mask 103 can be made of a different material (here for example silicon oxide) than the second intermediate layer 18 (here for example silicon), and in particular can be etched by a different chemistry than the chemistry that can be used to remove the second intermediate layer 18, allows the formation of an opening or recess 113 through the sacrificial portion 107, which exposes the underlying upper surface 100A, without affecting (at least to a first approximation) the quality of the surface 100A on which the working epitaxial multilayer 117 is grown ( Figure 3G-3J ).

[0199] In practice, growth mask 103 can be used as a stop layer during etching of overlying sacrificial portion 107, thereby ensuring complete removal of overlying sacrificial portion 107. Furthermore, forming openings in growth mask 103 does not affect the quality of underlying surface 100A (e.g., in terms of steps and recesses).

[0200] The epitaxial multilayer 49 and thus the heterostructure 50 may be of high crystalline quality.

[0201] Therefore, the corresponding electronic component 7 that functions based on the formation of a two-dimensional gas in the heterostructure 50 can have high electrical performance in use.

[0202] At the same time, the electronic component 5 is also integrated in the single crystal silicon layer (epitaxial portion 106), which can have high crystal quality. Therefore, the electronic component 5 can have high electrical performance when used.

[0203] In addition, the thickness of the growth mask 103 can be thick enough to serve as a mask for forming the epitaxial multilayer 49, and at the same time thin enough to minimize the non-planarity of the upper surface 105A of the surface layer 105. In practice, the upper surface 105A of the surface layer 105 can be considered to be substantially planar. This allows to facilitate subsequent manufacturing steps that form both the silicon-based electronic component 5 and the heterostructure-based electronic component 7.

[0204] use <111> The possibility of a substrate 14 of oriented silicon as a starting substrate for forming the semiconductor electronic device 1 can allow obtaining a high epitaxial quality of the heterostructure 50, in particular when the channel layer 55 is GaN or comprises GaN. Thus, the electronic component 7 based on the heterostructure can have excellent electrical properties. The applicant has also verified that the use of <111> The silicon substrate 14 also allows obtaining excellent electrical properties of the silicon-based electronic component 5 .

[0205] refer to Figure 3A-Figure 3OIn an embodiment of the manufacturing process, the fact that some of the doped regions of the silicon-based device 5, in particular the highly doped regions (such as, for example, the source region, the drain region and the body contact region of the PMOS 5A and NMOS 5B transistors), can be formed after the growth of the epitaxial multilayer 49 can further help to improve the reliability of the manufacturing of the device 1.

[0206] In fact, the epitaxial multilayer 49 can be grown using a larger thermal budget than the highly doped regions can sustain. In this way, highly doped regions of the silicon-based device 5 can be formed with high reliability.

[0207] For example, the growth of the first buffer layer 52 of AlN can occur at a temperature of about 1100°C within a time interval between about 15 and 30 minutes, while the growth of the GaN layer and the AlGaN layer forming the second buffer layer 53, the channel layer 55, the barrier layer 56 and the channel modulation region 64 can occur in subsequent growth steps, each at a temperature of about 1030°C-1080°C within an interval of about 5-15 minutes.

[0208] However, it will be clear to those skilled in the art that the above manufacturing steps and corresponding execution order may be different depending on the specific process and machine used. Figure 3A-3O The difference shown in .

[0209] For example, depending on the specific materials forming the epitaxial multilayer 49 and the epitaxial region 23 , the epitaxial multilayer 49 may be grown after forming the highly doped region.

[0210] Surface 105A may be non-planar, for example, depending on the growth mode used to grow layer 105, the thickness of layer 102, and surface treatments performed after epitaxial growth (eg, chemical mechanical polishing).

[0211] Figure 4 A different embodiment of a separation region is shown, here indicated by 170. The separation region 170 comprises a polycrystalline region, here formed by three polycrystalline portions 173A, 173B, 173C, and two trenches 175A, 175B extending along a third axis Z through the polycrystalline region.

[0212] Furthermore, in this embodiment, the polycrystalline portions 173A, 173B, 173C are separated from one another by trenches 175A, 175B.

[0213] The trenches 175A, 175B are substantially concentric with each other and completely surround the epitaxial multilayer 49 in which the HEMT transistor 7 is integrated.

[0214] The trenches 175A, 175B may each have a width measured between two adjacent polycrystalline portions, for example, comprised between 0.2 μm and 3 μm. The trenches 175A, 175B may extend at a distance from each other, for example, comprised between 0.5 μm and 5 μm.

[0215] A higher number of trenches may further help reduce the mechanical stress between epitaxial multilayer 49 and epitaxial region 23 .

[0216] Figure 5 Another embodiment of a separation region is shown, indicated here by 190, comprising a polycrystalline region, here formed by a plurality of polycrystalline portions 195, and a trench, indicated here by 193, extending through the polycrystalline region and bounded internally by the epitaxial multilayer 49 and externally by the epitaxial region 23 (not shown here).

[0217] In detail, the polycrystalline portions 195 are arranged at a distance from one another within the groove 193. In practice, the polycrystalline portions 195 each form a polycrystalline column extending along the third axis Z starting from the delimited zone 72.

[0218] The pillars 195 may each have a width, for example, between 0.5 μm and 5 μm along the first axis X and / or the second axis Y. The pillars 195 may extend at a distance from each other, for example, between 0.2 μm and 3 μm.

[0219] The pillars 195 may have a constant or variable cross-section along the third axis Z, such as a polygonal or circular shape (regular or irregular).

[0220] Depending on the specific design layout, pillars 195 may be distributed around multiple layers 49 according to a regular or irregular distribution.

[0221] In practice, the pillars 195 form mutually distinct portions of a polycrystalline region extending alongside the epitaxial multilayer 49 , in particular around it.

[0222] Finally, it is clear that other modifications and variations may be made to the electronic device 1 and to the process for its manufacture described and illustrated herein, without thereby departing from the scope of the present disclosure.

[0223] The separation region 70 may have a Figure 1-2 A structure different from the structures shown and described in 4 and 5.

[0224] Trenches 75 , 175A, 175B, 190 may only partially surround epitaxial multilayer 49 .

[0225] The grooves 75, 175A, 175B, 190 may extend only partially through the polycrystalline region along the third axis Z, ie without contacting the defined region 72. In practice, in this case, Figure 1 The polycrystalline parts 73A, 73B, Figure 4 The polycrystalline portions 173A, 173B, 173C and Figure 5 The polycrystalline portions 195 are connected to each other and form a monolithic polycrystalline region.

[0226] In practice, the polycrystalline region separating the regions 70, 170, 190 may be formed by one or more polycrystalline portions that are continuous or separated from each other. In other words, the polycrystalline region may be a single monolithic region or a discontinuous region.

[0227] Grooves 175A, 175B, 190 may be empty or filled (partially or fully), similar to the Figure 1 Furthermore, the possible filling of trenches 175A, 175B, 190 around epitaxial multilayer 49 may be uniform or non-uniform, depending on the specific fabrication steps used.

[0228] The electronic device 1 may comprise only heterostructure based electronic components 7, but not silicon based electronic components 5. The presence of the separation regions, in particular the respective polycrystalline regions, helps to reduce the mechanical stresses caused by the growth of the epitaxial multilayer 49 and thus allows the heterostructure 50 to have good crystal quality.

[0229] In addition to or as an alternative to the PMOS 5A and NMOS 5B transistors, the electronic device 1 may also include other silicon-based electronic components 5 (active and / or passive) integrated in the die 3 .

[0230] For example, Figure 2 As shown in , the silicon-based electronic components 5 may also include bipolar transistors 5C and passive components 5D such as diodes and resistors. Figure 2 In FIG. 5 , the bipolar transistor 5C and the passive component 5D are integrated in respective device parts 120 , 121 that are different from each other and are schematically indicated by dashed lines.

[0231] For example, device portions 120 , 121 are formed in respective single crystal silicon epitaxial regions grown on substrate region 10 , which are particularly integral with epitaxial region 23 .

[0232] Insulating regions (eg shallow or deep trenches) may be arranged between the portions 120 , 121 and 20 in a manner known per se, such that the respective electronic components are electrically insulated from one another in use.

[0233] refer to Figure 1, the insulating region 82 extending between the first and second device portions 20, 21 may have a different shape and structure than shown. For example, it may include one or more trenches extending along the third axis Z in the epitaxial region 23 to a greater depth into the die 3, so as to electrically insulate the portion of the substrate region 10 arranged below the device portion 21 (in which the HEMT transistor 7 is integrated) from the portion of the substrate region 10 arranged below the device portion 20 (in which the PMOS 5A and NMOS 5B transistors are integrated) from each other.

[0234] This deep isolation trench formation can be integrated in the reference Figure 3A-3O Describe the manufacturing process. For example, Fig. 6A Shows Figure 3H 1 is a cross-section of a wafer 100 after the manufacturing steps.

[0235] exist Fig. 6A In the wafer 100 of FIG. 1 , deep insulation trenches 210 are formed in the wafer 100 , in particular in the epitaxial portion 106 of the surface layer 105 and partially in the substrate region 10 .

[0236] In this embodiment, deep isolation trench 210 is formed simultaneously with trench 75, thereby optimizing the number of photolithography and etching steps.

[0237] The deep insulating trench 210 and the trench 75 can be formed simultaneously even if they have different depths along the third axis Z in the wafer 100. In fact, the defined region 72 acts as a stop layer during the etching of the working polycrystalline region 114. Therefore, by modulating the etching time, the depth of the deep insulating trench 210 can be modulated without jeopardizing the formation of the trench 75.

[0238] However, the deep insulating trench 210 may be formed by dedicated photolithography and etching steps, ie, separate (either before or after) with respect to the steps used to form the trench 75 .

[0239] Then, Figure 6B , a working epitaxial multilayer is grown, here indicated by 212. In this embodiment, the working epitaxial multilayer 212 is conformally grown both within the trench 75 and within the deep insulating trench 210.

[0240] Apart from Figure 2 In addition to or in place of the components shown in Figure 2In addition to the components shown in , the device 1 may also include other silicon-based electronic components 5 integrated in the die 3. For example, the components 5 may include MOS transistors for medium voltage applications, such as 15V to 20V; DMOS transistors and / or drift MOS transistors, such as for applications with operating voltages of 20V to 200V; thin film resistors; OTP or MTP memory; phase change memory; etc.

[0241] It will be clear to the person skilled in the art that the integration of different types of silicon-based electronic components 5 with each other can be performed by manufacturing steps known per se and therefore not further illustrated here, for example by BCD technology.

[0242] For example, the conductivity type of the various semiconductor regions, n or p, may be reversed from that described.

[0243] Epitaxial multilayer 49 may include a different number of layers than has been shown and described.

[0244] For example, the epitaxial multilayer 49 may include only the heterostructure 50. In other words, the heterostructure 50 may be grown directly on the substrate region 10.

[0245] Depending on the specific application, the heterostructure 50 may include other semiconductor layers and / or insulating layers, for example, between the channel layer 55 and the barrier layer 56 .

[0246] For example, the heterostructure based component 7 may include electronic components other than the HEMT transistor 7 .

[0247] For example, the HEMT transistor 7 may be of the normally-off type, wherein the gate structure may be different from what has been described above; for example, the gate structure may be of the recessed type and / or the fabrication of the gate structure may include the use of a fluorine plasma below the gate structure. Alternatively, the HEMT transistor 7 may be of the normally-on type, i.e., of the depletion type.

[0248] For example, the number of epitaxial layers forming substrate region 10 may vary depending on the specific application.

[0249] For example, the growth of the working multilayer 114, 212 can be compared with the reference Figure 3J and 6B described differently, depending on the specific growth parameters used.

[0250] Therefore, the shape of the epitaxial multilayer 49 can be Figure 1 For example, the peripheral portion 84 may not conform to the inner side wall 77.

[0251] For example, the multilayer 114 may be selectively grown starting from only the exposed portion 101B of the second intermediate layer 18. In this case, reference numerals 114 may be omitted. Figure 3M Described removal steps.

[0252] For example, depending on the desired thickness of the epitaxial multilayer 49 and the epitaxial region 23 along the third axis Z, the second intermediate layer 18 may not be present and the epitaxial multilayer 49 may be grown directly on the second deep layer 17 .

[0253] In the case of medium or low voltage applications (e.g., from 7V to 40V), the substrate region 10 may comprise only the substrate 14 and the first deep layer 15 (or also the first intermediate layer 16). In practice, in this case, the epitaxial multilayer 49 may be grown directly on the first deep layer 15 or, if present, on the first intermediate layer 16.

[0254] In practice, as described above, in the present semiconductor electronic device, the substrate region 10 may include a single crystal substrate 14 having a first conductivity type (eg, P) and at least one epitaxial layer (15-18) extending on the substrate and having a conductivity type different from that of the substrate (eg, N).

[0255] For example, the electronic component 5 may be an electronic component based on a single semiconductor other than silicon, such as Ge, SiGe, or the like.

[0256] The above embodiments can be combined to provide further solutions.

[0257] A semiconductor electronic device (1) comprises: a substrate region (10) of semiconductor material; a first electronic component (7) based on a heterostructure, comprising an epitaxial multilayer (49) extending on the substrate region and comprising a heterostructure (50); a separation region (70; 170; 190) extending on the substrate region and comprising a polycrystalline region (73A, 73B; 173A, 173B, 173C; 195) of a polycrystalline semiconductor material arranged beside the epitaxial multilayer along a first direction (X, Y); and an epitaxial region (23) of a single semiconductor material of a single crystal type extending on the substrate region (10), the polycrystalline region (73A, 73B; 173A, 173B, 173C; 195) extending between the epitaxial multilayer (49) and the epitaxial region (23) along the first direction (X).

[0258] The semiconductor electronic device further comprises a second electronic component (5) based on a single semiconductor material and integrated into the epitaxial region (23), the second electronic component being, for example, one of the following: a CMOS transistor, a DMOS transistor, a bipolar transistor or a passive electronic component based on a single semiconductor material.

[0259] The separation region (70; 170; 190) includes at least one trench (75; 175A, 175B, 195) extending in the polycrystalline region.

[0260] The polycrystalline region includes a plurality of portions (73A, 73B; 173A, 173B, 173C; 195) that are distinct from one another and separated by at least one trench.

[0261] Two adjacent portions of the polycrystalline region (73A, 73B; 173A, 173B, 173C; 195) extend at a mutual distance of between 0.2 μm and 3 μm.

[0262] The portions (195) of the polycrystalline region are each pillars having a width between 0.5 μm and 5 μm.

[0263] The separation region also includes a defining region (72) comprising an oxide and extending between the substrate region (10) and the polycrystalline region.

[0264] The defined region (72) has a thickness between 7 nm and 300 nm.

[0265] The separation region (70; 170; 190) at least partially surrounds the epitaxial multilayer (49).

[0266] The epitaxial region (23) is made of a first semiconductor material (eg, silicon), and the heterostructure (50) includes a second semiconductor material (eg, GaN) different from the first semiconductor material.

[0267] A method for manufacturing a semiconductor electronic device (1), comprising providing a wafer (100), the wafer comprising a substrate layer (18) of semiconductor material, the substrate layer having a first growth portion (101B) and a second growth portion (101C) different from the first growth portion; growing an epitaxial multilayer (49) comprising a heterostructure (50) on the first growth portion; starting from the heterostructure, forming a first electronic component (7) based on the heterostructure; forming a separation region (70; 170; 190) on the second growth portion, the separation region comprising The invention comprises a polycrystalline region (73A, 73B; 173A, 173B, 173C; 195) of a polycrystalline type semiconductor material, which is arranged next to the epitaxial multilayer along a first direction (X, Y); and an epitaxial region (23) of a single semiconductor material of a single crystal type formed and extending on a substrate layer (18), wherein the polycrystalline region (73A, 73B; 173A, 173B, 173C; 195) extends between the epitaxial multilayer (49) and the epitaxial region (23) along a first direction (X).

[0268] The substrate layer includes a third growth portion (101A) different from the first and second growth portions, and also includes: forming a growth mask (103) on the substrate layer to cover the first growth portion (101B) and the second growth portion (101C) of the substrate layer; growing a surface layer (105) of a single semiconductor material, the surface layer (105) having a single crystal portion (106) extending on the third growth portion (101A) of the substrate layer and a polycrystalline portion (107) extending on the growth mask, the polycrystalline region of the separation region being formed starting from the polycrystalline portion of the surface layer, and the epitaxial region being formed starting from the single crystal portion of the surface layer; and before growing the epitaxial multilayer (117; 212), forming an opening (113) in the polycrystalline portion (107) of the surface layer (105) and in the growth mask (103) to expose the first growth portion (101B) of the substrate layer.

[0269] The manufacturing process also includes forming a second electronic component (5) based on a single semiconductor material, which is integrated into the single-crystalline portion (106) of the surface layer (105).

[0270] Forming the separation region (70; 170; 190) includes forming at least one trench (75; 175A, 175B, 195) through the polycrystalline portion (107) of the surface layer (105) above the third growth portion (101C) of the substrate layer (18).

[0271] The trench (75) is formed prior to growing the epitaxial multilayer.

[0272] The various embodiments described above can be combined to provide further embodiments. Aspects of the embodiments can be modified, if necessary, to employ concepts of the various patents, applications, and publications to provide further embodiments.

[0273] These and other changes can be made to the embodiments in light of the above detailed description. In general, in the following claims, the terms used should not be interpreted to limit the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full range of equivalents to which these claims are entitled. Therefore, the claims are not limited by this disclosure.

Claims

1. A semiconductor electronic device, comprising: A substrate region of semiconductor material; A first electronic component based on a heterostructure, comprising an epitaxial multilayer extending over a substrate region and comprising the heterostructure; a separation region extending on the substrate region and comprising a polycrystalline region of semiconductor material of a polycrystalline type arranged alongside the epitaxial multilayer along a first direction; an epitaxial region of a single semiconductor material of a single crystal type extending over a substrate region, The polycrystalline region extends along a first direction between the epitaxial multilayer and the epitaxial region; and The first trench in the separation region separates the polycrystalline region into a first portion and a second portion different from the first portion. 2 . The semiconductor electronic device according to claim 1 , further comprising a second electronic component based on a single semiconductor material and integrated into the epitaxial region, the second electronic component being one of the following: a CMOS transistor, a DMOS transistor, a bipolar transistor or a passive electronic component based on a single semiconductor material.

3. The semiconductor device according to claim 1, further comprising: A second trench in the separation region further separates the polycrystalline region into a third portion different from the first portion and the second portion. 4 . The semiconductor device according to claim 3 , wherein the first electronic component is surrounded by the first trench, and the first trench is surrounded by the second trench. 5 . The electronic device as claimed in claim 4 , wherein two adjacent portions of the polycrystalline region extend at a mutual distance of between 0.2 μm and 3 μm. 6 . The electronic device of claim 4 , wherein the portions of the polycrystalline region are each pillars having a width between 0.5 μm and 5 μm. 7 . The semiconductor electronic device of claim 1 , wherein the separation region further comprises a definition region comprising an oxide and extending between the substrate region and the polycrystalline region.

8. The semiconductor electronic device of claim 7, wherein the defined region has a thickness between 7 nm and 300 nm.

9. The semiconductor electronic device according to claim 1, wherein the separation region at least partially surrounds the epitaxial multilayer. 10 . The semiconductor electronic device of claim 1 , wherein the epitaxial region is made of a first semiconductor material, and the heterostructure comprises a second semiconductor material different from the first semiconductor material.

11. A process for manufacturing a semiconductor electronic device, comprising: providing a wafer including a substrate layer of semiconductor material, the substrate layer having a first growth portion and a second growth portion different from the first growth portion; growing an epitaxial multilayer including a heterostructure on the first growth portion; forming a first electronic component based on a heterostructure starting from the heterostructure; forming a separation region on the second growth portion, the separation region comprising a polycrystalline region of semiconductor material of a polycrystalline type arranged beside the epitaxial multilayer along the first direction; as well as forming an epitaxial region of a single semiconductor material of a single crystal type extending on the substrate layer, The polycrystalline region extends along a first direction between the epitaxial multilayer and the epitaxial region.

12. The manufacturing process of claim 11, wherein the substrate layer comprises a third growth portion different from the first growth portion and the second growth portion, further comprising: forming a growth mask on the substrate layer to cover the first growth portion and the second growth portion of the substrate layer; growing a surface layer of a single semiconductor material, the surface layer having a single crystal portion extending over the third growth portion of the substrate layer and a polycrystalline portion extending over the growth mask, the polycrystalline region of the separation region being formed starting from the polycrystalline portion of the surface layer, and the epitaxial region being formed starting from the single crystal portion of the surface layer; and Prior to growing the epitaxial multilayer, openings are formed in the polycrystalline portion of the surface layer and in the growth mask that expose a first growth portion of the substrate layer.

13. The manufacturing process of claim 12, further comprising forming a second electronic component based on a single semiconductor material, the second electronic component being integrated into the single crystalline portion of the surface layer.

14. The manufacturing process of claim 11, wherein forming the separation region comprises forming at least one trench through the polycrystalline portion of the surface layer over the third growth portion of the substrate layer.

15. The manufacturing process of claim 14, wherein the trenches are formed prior to growing the epitaxial multilayer.

16. The process of claim 11, wherein forming the separation region comprises: forming a trench through the polycrystalline region; as well as A plurality of polycrystalline portions are formed in the trenches.

17. The process of claim 16, wherein the plurality of polycrystalline portions is a plurality of polycrystalline columns.

18. A system comprising: Semiconductor substrates; A first electronic device on a semiconductor substrate, the first electronic device comprising: Heterogeneous structures; and Epitaxial multilayer; a trench region on the semiconductor substrate surrounding the first electronic device; a plurality of polycrystalline pillars in the trench; and The epitaxial region on the semiconductor substrate surrounding the trench.

19. The system of claim 18, wherein the epitaxial region is made of a first semiconductor material and the heterostructure comprises a second semiconductor material different from the first semiconductor material.

20. The system of claim 18, further comprising a second electronic device on the semiconductor substrate, the second electronic device being one of the following: a CMOS transistor, a DMOS transistor, a bipolar transistor, or a single semiconductor material passive electronic component.

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