Manufacturing process of semiconductor electronic device integrated with different electronic components and semiconductor electronic device

Abstract

The invention relates to a manufacturing process of a semiconductor electronic device integrating different electronic components and the semiconductor electronic device. In order to manufacture a semiconductor electronic device, a wafer is provided having a substrate layer of a semiconductor material, the substrate layer having a first portion and a second portion different from the first portion. An epitaxial region of a single semiconductor material is grown on a first portion of a substrate layer. An epitaxial multilayer having a heterostructure is grown on the second portion of the substrate layer. A first electronic component based on a single semiconductor material is formed from the epitaxial region, and a second electronic component based on a heterostructure is formed from the heterostructure. Forming the first electronic component includes forming a plurality of doped regions in the epitaxial region after the step of growing the epitaxial multilayer.

Description

Technical Field

[0001] The present disclosure relates to a manufacturing process of a semiconductor electronic device integrating different electronic components and to the semiconductor electronic device. Background Art

[0002] Semiconductor electronic devices are known which include silicon-based active and / or passive electronic components (e.g. CMOS, DMOS, BJT transistors, diodes, resistors, etc.) which are integrated in the same silicon die and are manufactured, for example, using BCD (Bipolar-CMOS-DMOS) technology.

[0003] In practice, the operation of these electronic components is based on the electronic properties of a single semiconductor material: silicon.

[0004] These devices monolithically integrate digital circuits, analog circuits, and power circuits on the same die, operating at voltages that are very different from each other, e.g., from a few volts in the case of CMOS transistors for implementing logic functions to hundreds of volts in the case of DMOS transistors for power applications.

[0005] Silicon-based electronic components are integrated into <100> A region of single crystal silicon grown on a silicon wafer.

[0006] Semiconductor electronic devices including heterostructure-based electronic components, such as HEMT transistors, are also known.

[0007] In practice, the operation of these electronic components is based on the electronic properties of a heterojunction between two different semiconductor materials.

[0008] In detail, in a HEMT transistor, a conductive channel is based on the formation of a two-dimensional electron gas (2DEG) layer with high mobility formed at a heterojunction (i.e., at an interface between semiconductor materials with different band gaps). For example, a HEMT device based on a heterojunction between an aluminum gallium nitride (AlGaN) layer and a gallium nitride (GaN) layer is known.

[0009] HEMT devices, especially those based on AlGaN / GaN heterostructures or heterojunctions, have several advantages that make them particularly suitable and widely used in different applications. For example, the high breakdown threshold of HEMT devices is used for high-performance power switches; the high mobility of electrons in the conduction channel allows the formation of high-frequency amplifiers; in addition, the high electron concentration in the 2DEG allows for low on-state resistance (R ON ).

[0010] Furthermore, HEMT devices used in radio frequency (RF) applications generally have better RF performance than similar silicon LDMOS devices.

[0011] Heterostructure-based electronic components are integrated into <111> On silicon wafers or on sapphire (Al 2 O 3 ) or in heterostructures grown epitaxially on silicon carbide (SiC) substrates.

[0012] In order to use a simple and low-cost manufacturing process, the heterostructure-based electronic components and the silicon-based electronic components are integrated in different dies from each other, starting from two different silicon wafers. In this way, the manufacturing processes of the silicon-based components and the heterostructure-based components do not affect each other.

[0013] For example, heterostructures can be grown using high thermal budgets without damaging silicon-based components.

[0014] However, this results in electronic devices combining both silicon-based components and heterostructure-based components having a large footprint and therefore high manufacturing cost, high power consumption, and low electrical performance, for example due to parasitic capacitance, resistance or inductance introduced by electrical connections between dies.

[0015] According to one method, a die in which a silicon-based component is formed and a die in which a heterostructure-based component is formed are bonded to each other by a die transfer technique.

[0016] However, even this approach has disadvantages in terms of cost, manufacturing and electrical performance reliability. Summary of the invention

[0017] According to the present disclosure, a process for manufacturing a semiconductor electronic device and a semiconductor electronic device are provided, including forming an epitaxial region of a single semiconductor material on a first portion of a substrate layer having a first portion and a second portion, the epitaxial region having a first surface opposite to the substrate layer. The process includes forming an epitaxial multilayer including a heterostructure on the second portion of the substrate layer; forming a separation portion having a second surface coplanar with the first surface between the epitaxial region and the epitaxial multilayer, and forming a first electronic component on the epitaxial region. The process includes forming a second electronic component on the heterostructure, and forming the first electronic component includes forming a plurality of doped regions in the epitaxial region after forming the epitaxial multilayer. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] For a better understanding of the present disclosure, embodiments thereof will now be described by way of non-limiting examples only, with reference to the accompanying drawings, in which:

[0019] Figure 1 shows a cross section of a semiconductor electronic device according to an embodiment;

[0020] Figure 2 Shows Figure 1 A top plan view of the device; and

[0021] Figures 3A-3N Shows Figure 1 Cross-section of the device during subsequent fabrication steps. DETAILED DESCRIPTION

[0022] The following description refers to the arrangements shown in the accompanying drawings; therefore, expressions such as "upper", "lower", "lower", "upper", "right", "left", "high", "lower", etc. are related to the drawings and should not be interpreted in a limiting manner.

[0023] Figure 1 and Figure 2 A semiconductor electronic device (hereinafter simply referred to as device) 1 is shown in a Cartesian reference system XYZ having a first X axis, a second Y axis and a third Z axis.

[0024] The device 1 is formed in a die 3 and comprises: one or more silicon-based electronic components 5, with respect to the silicon-based electronic components 5 being Figure 1 A PMOS transistor 5A and an NMOS transistor 5B are shown; and one or more electronic components based on a heterostructure, about the electronic components based on the heterostructure in Figure 1 HEMT transistors 7 are shown, all of which are integrated in the die 3 .

[0025] The die 3 comprises a substrate region 10 and a surface region 12 extending on the substrate region 10 , in particular in direct contact with the substrate region 10 .

[0026] The substrate region 10 includes a substrate 14 and one or more epitaxial layers disposed on the substrate 14 .

[0027] The substrate 14 is made of a semiconductor material (particularly a single crystal material), and has an upper surface 14A.

[0028] In detail, in this embodiment, the substrate 14 is made according to <111> The crystal direction of the single crystal silicon is oriented, and in particular, the upper surface 14A is made according to <111> Crystal orientation.

[0029] In this embodiment, the substrate region 10 includes: a first epitaxial layer, or a first deep layer 15, overlying the upper surface 14A of the substrate 14; a second epitaxial layer, or a first intermediate layer 16, overlying the first deep layer 15; a third epitaxial layer, or a second deep layer 17, overlying the first intermediate layer 16; and a fourth epitaxial layer, or a second intermediate layer 18, overlying the second intermediate layer 17.

[0030] The epitaxial layers 15-18 are made of a semiconductor material, in particular the same material as the substrate 14 (here silicon), and are not shown in FIG. Figure 1 Identified by dotted lines.

[0031] During the design phase, the thickness along the third axis Z, the conductivity type (eg, P or N), and the doping profile of the substrate 14 and the epitaxial layers 15 - 18 may be selected according to the specific application of the device 1 .

[0032] For example, epitaxial layers 15 - 18 may each have a thickness between 0.1 μm and 7 μm.

[0033] For example, in this embodiment, the substrate 14 is of P type, e.g., resistivity between 0.1 Ω·cm and 20 Ω·cm, and the epitaxial layers 15-18 are of N type. In this way, the first deep layer 15 can create a PN junction with the substrate 14, which can be used to insulate the devices 5, 7 integrated in the die 3 from the substrate 14 in use.

[0034] The first and second deep layers 15, 17 may have a doping level equal to or different from (particularly higher than) that of the first and second intermediate layers 16, 18. For example, the doping level of the first and second deep layers 15, 17 may be between 0.1 Ω·cm and 20 Ω·cm, while the doping level of the first and second intermediate layers 16, 18 may be between 0.1 Ω·cm and 20 Ω·cm.

[0035] The high doping level of the first deep layer 15 causes, in use, a depletion region between the first deep layer 15 and the substrate 14 to extend mainly into the substrate 14 , thereby improving the electrical insulation of the components 5 , 7 from the substrate 14 .

[0036] Furthermore, the high doping level of the first deep layer 15 may allow, in use, to use the first deep layer 15 as a current conducting region of an electronic component integrated into the die 3 , for example if the silicon based component 5 comprises a BJT transistor.

[0037] Depending on the specific application and the type of doping used, if the electronic components 5, 7 are designed to operate at a high voltage relative to the substrate 14, for example, to be able to operate normally when a 5V voltage (referred to as a positive voltage relative to the substrate 14, ranging from about 20V to, for example, 60V, 100V or 650V) is applied to the corresponding ends, then the presence of both the first and second deep layers 15, 17 can be useful for simplifying the manufacture of the device 1 and obtaining excellent electrical performance of the device 1 during use.

[0038] The surface region 12 extends on the second intermediate layer 18 , in particular is in direct contact therewith, and comprises a first device part 20 in which the PMOS transistor 5A and the NMOS transistor 5B are integrated, and a second device part 21 in which the HEMT transistor 7 is integrated.

[0039] The first device portion 20 has an upper surface 20A and comprises an epitaxial region 23 of semiconductor material, in particular, the same material as the second intermediate layer 18 , here single-crystalline silicon.

[0040] The epitaxial region 23 extends from the second intermediate layer 18 (in particular, here is in direct contact with the second intermediate layer 18 ) to the upper surface 20A.

[0041] The thickness along the third axis Z, the conductivity type (eg, P or N) and the doping profile of the epitaxial region 23 may be selected at the design stage according to the specific application of the device 1 .

[0042] For example, in this embodiment, epitaxial region 23 is of N-type.

[0043] The first device portion 20 comprises a plurality of doped regions which extend within the epitaxial region 23 and form functional regions of the silicon-based electronic component 5 .

[0044] In detail, Figure 1 In the embodiment of FIG. 5 , P++ type doped regions 25A and 25B extend from the upper surface 20A in the epitaxial region 23 . The doped regions 25A and 25B respectively form the source region and the drain region of the PMOS transistor 5A and define the channel region 26 of the PMOS transistor 5A.

[0045] Furthermore, an N++-type doped region 27 extends from the upper surface 20A in the epitaxial region 23 and forms a body contact region of the PMOS transistor 5A.

[0046] Still refer to Figure 1 In the embodiment, the P-type doped region 28 extends from the upper surface 20A in the epitaxial region 23 and forms the body region of the NMOS transistor 5B.

[0047] N++ type doped regions 29A, 29B extend in the doped region 28 and respectively form a source region and a drain region of the NMOS transistor 5B and define a channel region 30 of the NMOS transistor 5B.

[0048] Furthermore, a P++ type doped region 31 extends within the doped region 28 and forms a body contact region of the NMOS transistor 5B.

[0049] In practice, the doped regions 25A, 25B, 27, 29A, 29B and 31 (ie, the source and drain doped regions and the body contact region) are highly doped regions, with a peak concentration of, for example, between 5·10 19 Atom / cm -3 and 5.10 20 Atom / cm -3In contrast, the doped region 28 (ie, the body region) is a low-doped region, the peak concentration of which is, for example, between 1·10 16 Atom / cm -3 and 2.10 18 Atom / cm -3 between.

[0050] The number, arrangement, shape, size and doping profile of the doped regions may be selected during the design phase according to the specific silicon-based electronic components 5 integrated in the die 3 and according to the specific application of the device 1 .

[0051] Depending on the specific application, insulating portion 33 of insulating material (eg, oxide) may extend from upper surface 20A within epitaxial region 23 .

[0052] In particular, Figure 1 In FIG. 4 , the insulating portion 33 extends parallel to the first axis X between the doped regions 27 and 25A, 25B and 31 , 31 and 29A.

[0053] A first insulating layer 35 (eg, oxide or nitride) extends over the upper surface 20A of the first device portion 20 .

[0054] A second insulating layer 36 (eg, oxide) extends over the first insulating layer 35 .

[0055] The surface structure 38 of the silicon-based component 5 extends over the upper surface 20A of the first device region 20, in direct contact therewith. Depending on the specific silicon-based electronic component 5 integrated into the die 3, the surface structure 38 forms a further functional area of ​​the silicon-based device 5 and may include various conductive and / or insulating areas.

[0056] In this embodiment, the surface structure 38 includes gate insulating regions 40, 41, which extend over the channel region 26 of the PMOS transistor 5A and over the channel region 30 of the NMOS transistor 5B, respectively. For simplicity, regarding the gate insulating regions 40, 41, Figure 1 Only the respective conductive regions (here polysilicon, again indicated by 40 , 41 ) are shown, each having a respective upper surface 40A, 41A.

[0057] even though Figure 1 Not shown, the gate insulation regions 40, 41 may also each include a corresponding insulation region arranged between the corresponding polysilicon region and the upper surface 20A, and a corresponding contact region of a conductive material (e.g., metal) that contacts the corresponding surface 40A, 41A and forms the corresponding gate terminal G.

[0058] exist Figure 1In the embodiment, the surface structure 38 also includes source contact regions 42, 43 and drain contact regions 44, 45 of conductive material, which extend through the first and second insulating layers 35, 36 and directly contact the upper surface 20A to form corresponding source S and drain D terminals.

[0059] Specifically, the source contact regions 42 and 43 extend in direct contact with the source region 25A of the PMOS transistor 5A and the source region 29A of the NMOS transistor 5B, respectively.

[0060] Furthermore, in the embodiment shown, the source contact regions 42 , 43 each also extend in direct contact with the respective body contact region 27 , 31 .

[0061] The drain contact regions 44 and 45 extend in direct contact with the drain region 25B of the PMOS transistor 5A and the drain region 29B of the NMOS transistor 5B, respectively.

[0062] The second device portion 21 of the surface region 12 has an upper surface 21A and includes an epitaxial multilayer 49 extending on and grown from the second intermediate layer 18 .

[0063] The epitaxial multilayer 49 comprises a heterostructure 50 in which the HEMT transistor 7 is integrated.

[0064] exist Figure 1 In the embodiment of the present invention, the epitaxial multilayer 49 further comprises a transition region, which is formed here by a first and a second buffer layer 52, 53 superposed on each other, which are arranged between the second intermediate layer 18 and the heterostructure 50. The transition region may be useful during the manufacture of the device 1 to facilitate the epitaxial growth of the heterostructure 50 on the second intermediate layer 18.

[0065] In detail, the first buffer layer 52 (eg, aluminum nitride (AlN)) extends on and directly contacts the second intermediate layer 18 , and the second buffer layer 53 (eg, aluminum gallium nitride (AlGaN)) extends on and directly contacts the first buffer layer 52 .

[0066] The heterostructure 50 includes a compound semiconductor material including elements of Group III and Group V of the periodic table, and forms an upper surface 21A of the second device portion 21 .

[0067] Depending on the specific manufacturing steps used to manufacture the device 1 , the upper surface 21A of the second device portion 21 may extend to coordinates along the third axis Z that are equal to or different from the coordinates of the upper surface 20A of the first device portion 20 .

[0068] In particular, in this embodiment, the upper surface 21A of the second device part 21 is arranged at a lower height relative to the upper surface 20A of the first device part 20 , measured along the third axis Z. This may allow for improved manufacturing of the device 1 .

[0069] The heterostructure 50 includes a channel layer 55 and a barrier layer 56 overlying each other.

[0070] The channel layer 55 is made of a first semiconductor material (eg, gallium nitride (GaN) or an alloy including gallium nitride (such as InGaN)), here made of gallium nitride (GaN), extends over the transition region, in particular, over the second buffer layer 53, and has an upper surface 55A.

[0071] The barrier layer 56 is made of a second semiconductor material (e.g., a compound based on a ternary or quaternary gallium nitride alloy, such as AlxGa1-xN, AlInGaN, InxGa1-xN, AlxIn1-xAl, AlScN) (here aluminum gallium nitride (AlGaN)) and extends between the upper surface 55A of the channel layer 55 and the upper surface 21A of the second device portion 21.

[0072] According to specific applications, the channel layer 55 and the barrier layer 56 may be of intrinsic type, P type or N type; in particular, both the channel layer 55 and the barrier layer 56 may be of N type.

[0073] For example, when the barrier layer 56 is AlGaN, the presence of aluminum atoms will make the barrier layer 56 N-type.

[0074] The heterostructure 50 is configured to accommodate a two-dimensional gas (2DEG) of (mobile) charge carriers, in particular electrons here, which is arranged at the interface between the channel layer 55 and the barrier layer 56 , ie at the upper surface 55A of the channel layer 55 .

[0075] An insulating layer 58 (eg, made of an oxide such as silicon oxide) having an upper surface 58A extends over upper surface 21A.

[0076] The insulating layer 36 also extends over the second device portion 21, in particular over the insulating layer 58. The insulating layer 58 may have a thickness of, for example, between 20 nm and 1 μm.

[0077] The surface structure 60 of the heterostructure-based component 7 extends over the upper surface 21A of the second device part 21 .

[0078] Depending on the specific heterostructure-based electronic component 7 integrated in the die 3 , the surface structure 60 may be various conductive and / or insulating areas, which form functional areas of the heterostructure-based component 7 .

[0079] In this embodiment, in which the heterostructure-based electronic component 7 is a HEMT transistor, the surface structure 60 comprises a source region 61 and a drain region 62 made of an electrically conductive material, which extend at a distance from each other along a first axis X.

[0080] The source region 61 and the drain region 62 are in electrical contact, in particular ohmic contact, with the heterostructure 50 , in particular with the two-dimensional gas formed at the interface between the channel layer 55 and the barrier layer 56 , and form a source terminal S and a drain terminal D of the HEMT transistor 7 , respectively.

[0081] exist Figure 1 In the embodiment of FIG. 5 , the source and drain regions 61 , 62 extend parallel to the third axis Z through the insulating layers 36 , 58 to the upper surface 21A.

[0082] However, depending on the specific application, the source and drain regions 61 , 62 may also extend partially through the heterostructure 50 parallel to the third axis Z, for example a portion of the barrier layer 56 or the entire thickness of the barrier layer 56 up to the surface 55A.

[0083] The surface structure 60 also comprises a gate structure, here formed by a channel modulation region 64 and a gate contact region 65, which can be biased to electrically control the formation of a two-dimensional gas in the heterostructure 50 between the source region 61 and the drain region 62. The gate structure forms the gate terminal G of the HEMT transistor 7.

[0084] In this embodiment, the HEMT transistor 7 is of a normally-off type, ie, an enhancement type.

[0085] In detail, in this embodiment, the channel modulation region 64 is made of a semiconductor material and has a different conductivity type, for example, P-type, relative to the barrier layer 56. In particular, the channel modulation region 64 may be made of P-type gallium nitride (p-GaN).

[0086] However, the channel modulation region 64 may be formed of a collection of different materials, including a dielectric layer, a metal layer, and / or a semiconductor layer having a suitable work function to serve as a control electrode.

[0087] The channel modulation region 64 extends along the first axis X between the source region 61 and the drain region 62 on the upper surface 21A, and has an upper surface 64A.

[0088] Depending on the specific manufacturing steps used to manufacture the device 1 , the upper surface 64A of the channel modulation region 64 may extend at coordinates along the third axis Z that are equal to or different from the coordinates of the upper surfaces 40A, 41A of the gate insulating regions 40 , 41 .

[0089] In particular, in this embodiment, the upper surface 64A of the channel modulation region 64 is arranged at a distance from the second intermediate layer 18 measured along the third axis Z that is smaller than the distance from the upper surfaces 40A, 41A of the gate insulating regions 40, 41 to the second intermediate layer 18 measured along the third axis Z. This may allow for improved manufacturing reliability of the device 1.

[0090] A gate contact region 65 made of an electrically conductive material extends in electrical contact with the channel modulation region 64 , in particular here in contact with the upper surface 64A.

[0091] The surface region 12 of the die 3 also includes a residual spacer portion 70 extending over and in direct contact with the second intermediate layer 18 between the first and second device portions 20 , 21 .

[0092] like Figure 2 As can be seen in the schematic top view of , the remaining partition portion 70 surrounds the second device portion 21 .

[0093] Reference again Figure 1 , the residual partition portion 70 has an upper surface which, in this embodiment, is continuous with, in particular aligned with, the upper surface 20A of the first device portion 20 and is therefore indicated with the same reference numeral.

[0094] The residual partition part 70 is connected laterally to the second device part 21 parallel to the first axis X.

[0095] In detail, the residual partition portion 70 has a first side wall 71 connected to the first device portion 20 and a second side wall 72 opposite to the first side wall 71 and connected to the second device portion 21 .

[0096] The residual separation portion 70 includes a defined region 75, for example including an oxide, in particular silicon oxide, which extends over and is in direct contact with the second intermediate layer 18; and a polycrystalline region 76, which is made of the same material (silicon) as the epitaxial region 23 of the first device portion 20, extending over and is in direct contact with the defined region 75.

[0097] The defined region 75 may be formed of a single layer, such as an oxide, in particular silicon oxide, or may be formed of multiple layers, such as including one or more layers of oxide and / or one or more layers of nitride.

[0098] In detail, according to one embodiment, the definition region 75 may be made of silicon oxide.

[0099] According to various embodiments, the defined region 75 may include an oxide layer, in particular silicon oxide, and a nitride layer. According to one embodiment, the oxide layer may be in direct contact with the semiconductor layer 18 .

[0100] The defined region 75 may have a thickness along the third axis Z, for example, between 7 nm and 300 nm, in particular and The thickness between.

[0101] In this embodiment, polycrystalline region 76 has a polycrystalline structure.

[0102] In this embodiment, the polycrystalline region 76 is monolithic with the epitaxial region 23 .

[0103] The inclination of the first sidewall 71 may depend on the crystal orientation of the epitaxial region 23 and on the thickness of the defined region 75 along the third axis Z. For example, in the epitaxial region 23 according to <111> In the case of crystal orientation, the first side wall 71 may form an angle of about 54° with a direction parallel to the first axis X.

[0104] Polycrystalline region 76 extends at a distance from upper surface 20A.

[0105] An insulating region 77 of insulating material (eg, oxide) extends in the die 3 from the upper surface 20A between the first and second device portions 20 , 21 .

[0106] In detail, the insulating region 77 extends parallel to the third axis Z from the upper surface 20A within the epitaxial region 23 in the first device portion 20 and between the upper surface 20A and the polycrystalline region 76 in the residual separation portion 70 .

[0107] exist Figure 1 In the embodiment of FIG. 4 , epitaxial multilayer 49 includes a portion extending over second sidewall 72 of residual spacer portion 70 in a conformal manner, thereby forming a raised surface 78 .

[0108] The raised surface 78 is arranged at a greater coordinate along the third axis Z with respect to the upper surface 21A and is here even larger than the upper surface 58A of the insulating layer 58 .

[0109] The shape and structure of the residual partitioning portion 70 may vary depending on the specific manufacturing steps used to make the device 1 .

[0110] The presence of a polycrystalline region 76 between the epitaxial multilayer 21 and the epitaxial region 23 may be useful for reducing stress caused by the lattice mismatch between the material forming the epitaxial multilayer (e.g., GaN) and the material forming the epitaxial region (e.g., silicon). Thus, the presence of the polycrystalline region may help reduce the risk of dislocations in the die 3 (and therefore the risk that the device 1 may be damaged).

[0111] The device 1 allows combining the functionality of silicon-based components 5 and heterostructure-based components 7 in a single die while maintaining a small size relative to electronic devices in which the silicon-based components 5 and the heterostructure-based components 7 are integrated in different dies.

[0112] Furthermore, the electrical connections between the silicon-based components 5 and the heterostructure-based components 7 can be formed directly on the die 3. This can ensure high electrical performance of the device 1 in use; for example, in terms of the switching speed of the various components, minimal resistive losses associated with the electrical connections therebetween, and minimal overvoltage effects due to the presence of parasitic inductances.

[0113] Reference below FIG. 3A to FIG. 3N The manufacturing steps of the semiconductor electronic device 1 are described.

[0114] Figure 3A A cross section of a wafer 100 of a single crystal semiconductor material (particularly silicon) having an upper surface 100A is shown. Figure 1 Components common to components already described are denoted by the same reference numerals and are not described again in detail.

[0115] Wafer 100 includes a substrate 14 on which epitaxial layers 15 , 16 , 17 , and 18 have been grown.

[0116] The fourth epitaxial layer or the second intermediate layer 18 forms the upper surface 100A of the wafer 100 .

[0117] The second intermediate layer 18 comprises a first portion 101A on which the first device portion 20 is intended to be formed, i.e., in which the PMOS 5A and NMOS 5B transistors are intended to be integrated, and a second portion 101B on which the second device portion 21 is intended to be formed, i.e., on which the epitaxial multilayer 49 is intended to be grown and the HEMT transistor 7 is integrated.

[0118] Then, Figure 3B , a limiting layer 102 is formed on the upper surface 100A, for example including oxide, especially silicon oxide.

[0119] The defining layer 102 may be formed of one or more layers of different materials, such as Figure 1 The limited area 75 is discussed.

[0120] The definition layer 102 may have a thin thickness along the third axis Z, for example between 7 nm and 300 nm, in particular and between.

[0121] The defining layer 102 is intended to form a defining region 75 ( Figure 1 ).

[0122] The defining layer 102 may be formed by oxidizing a surface portion of the second intermediate layer 18 or by being deposited on the upper surface 100A. In the case of oxidation, the thickness of the second intermediate layer 18 may be increased relative to the thickness of the second intermediate layer 18 in response to oxidation. Figure 3A However, given that the thickness of the defining layer 102 is much smaller than the thickness of the second intermediate layer 18, for simplicity it can be assumed that the thickness of the second intermediate layer 18 remains the same before and after oxidation (as a first approximation).

[0123] Then, Figure 3C , the defining layer 102 is removed at the first portion 101A of the second intermediate layer 18 on which the first device portion 20 is intended to be formed, i.e., the portion of the second intermediate layer 18 on which the epitaxial region 23 is to be formed. Therefore, a portion of the defining layer 102 remains, also referred to as the growth mask 103 hereinafter.

[0124] In practice, the growth mask 103 exposes the first portion 101A of the second intermediate layer 18 and covers the second portion 101B of the second intermediate layer 18 .

[0125] exist Figure 3D In the process, a surface layer 105 of semiconductor material is grown on the wafer 100, in particular the same material as the second intermediate layer 18 (here silicon).

[0126] The surface layer 105 has an upper surface 105A.

[0127] The surface layer 105 comprises an epitaxial portion 106 grown parallel to the third axis Z from the second intermediate layer 18 (in particular from the respective first portion 101A), and a sacrificial portion 107 grown parallel to the third axis Z on the growth mask 103 .

[0128] The epitaxial portion 106 grown from the single crystalline substrate maintains the single crystalline structure of the second intermediate layer 18 and is intended to form the epitaxial region 23 of the first device portion 20 .

[0129] The sacrificial portion 107 grown from the amorphous substrate has a polycrystalline structure.

[0130] exist Figure 3E In the embodiment, a doped region 28 corresponding to the body region of the NMOS transistor 5B is formed in the surface layer 105 , and an insulating layer 108 is optionally formed.

[0131] In detail, the body region 28 is formed in the epitaxial portion 106 where the silicon-based component 5 is formed.

[0132] The body region 28 may be formed by dopant ion implantation.

[0133] The insulating layer 108 (eg, silicon oxide) forms the insulating portion 33 ( Figure 1 ) and is intended to form an insulating region 77 ( Figure 1 ) section 109.

[0134] The insulating layer 108 may be formed by forming an insulating trench, such as a shallow trench isolation (STI), in the surface layer 105. In this case, the thickness of the epitaxial portion 106 and the sacrificial portion 107 may be reduced in response to the formation of the insulating layer 108.

[0135] In addition, refer again Figure 3E Depending on the specific silicon-based electronic components 5 that are desired to be integrated into the die 3 of the device 1 , one or more surface layers 110 may be formed on the upper surface 105A of the surface layer 105 .

[0136] In the embodiment shown, the surface layer 110 is intended to form the gate insulation regions 40, 41 ( Figure 1 ). In particular, only a single gate layer of the surface layer 110 is shown here, here polysilicon, still indicated by 110. However, an oxide layer (not shown here) is formed between the upper surface 105A and the polysilicon layer 110 in a manner known per se.

[0137] The polysilicon layer 110 has an upper surface 110A.

[0138] A mask sacrificial layer 111 is also formed on the surface 110A of the gate layer 110 . The mask sacrificial layer 111 is, for example, an insulating material, such as a single layer or an insulating multilayer, including one or more of silicon oxide, silicon nitride, aluminum oxide and silicon carbide, and has an upper surface 111A.

[0139] exist Figure 3F In the embodiment, an opening 113 is opened above the sacrificial portion 107 .

[0140] The opening 113 is formed by selectively removing portions of the layers 110 , 111 , thereby exposing the sacrificial portion 107 underneath.

[0141] The remaining portion of the sacrificial layer 111 may be used as an etching mask.

[0142] Then, Figure 3G , the insulating layer 108 and the sacrificial portion 107 at the opening 113 are removed using the etching mask 111 .

[0143] Therefore, the portion of the sacrificial portion 107 disposed under the etching mask remains, which will form Figure 1 The polycrystalline region 76.

[0144] exist Figure 3GAfter the etching, the recess formed in the sacrificial portion 107 is continuous with the opening 113 and exposes a portion of the growth mask 103 .

[0145] exist Figure 3H In the embodiment of the present invention, the exposed portion of the growth mask 103 is removed. Therefore, the portion of the growth mask 103 arranged below the working polycrystalline region 76, i.e., Figure 1 The limited area 75 is retained.

[0146] The etching of the exposed portions of the growth mask 103 may be performed using a selective chemical method that does not etch (to a first approximate extent) the underlying second intermediate layer 18 .

[0147] Therefore, in Figure 3H After etching, the opening 113 also exposes the second portion 101B of the second intermediate layer 18 .

[0148] Then, Fig. 3I , grown on the wafer 100 to form Figure 1 The working multilayer 114 of the epitaxial multilayer 49 is formed.

[0149] In detail, a first buffer layer is grown on the wafer 100. Figure 1 The first buffer layer 52 corresponds to the first buffer layer 52 of the upper surface 100A and is therefore indicated by the same reference numerals. The first buffer layer 52 extends on the exposed portion of the upper surface 100A, on the second sidewall 72 and on the etching mask 111.

[0150] A second buffer layer is grown on the first buffer layer 52. Figure 1 The buffer layer 53 corresponds to and is therefore denoted by the same reference numeral.

[0151] A channel layer is grown on the second buffer layer 53. Figure 1 The channel layer 55 corresponds to and is therefore denoted by the same reference numeral.

[0152] A barrier layer is grown on the channel layer 55. Figure 1 The barrier layer 56 corresponds to and is therefore indicated by the same reference numeral.

[0153] The working multilayer 114 includes a raised portion 115 extending on the etching mask 111 and on the second sidewall 72 of the residual portion 70 , and a useful portion 116 extending directly on the upper surface 100A of the second intermediate layer 18 .

[0154] The useful portion 116 has a substantially planar upper surface 116A, in particular substantially parallel to the upper surface 100A.

[0155] The useful portion 116 grown on the second intermediate layer 18 is of single-crystalline type and is used for integrating the heterostructure-based device 7 .

[0156] Then, Figure 3J The channel modulation region 64 is formed on the upper surface 116A of the useful portion 116 in a manner known per se, for example by growing and defining specific layers.

[0157] In practice, in this embodiment, the useful portion 116 of the working multilayer 114 also includes the channel modulation region 64 .

[0158] Here, therefore, the surface 64A of the modulation zone 64 forms the most elevated surface of the useful portion 116 , ie the surface of the useful portion 116 which is at the greatest distance along the third axis Z from the surface 100A.

[0159] The surface 110A on which the etching mask 111 extends may be arranged at a distance from the surface 100A along the third axis Z, which distance is greater with respect to the highest surface of the useful portion 121 and smaller with respect to the surface 110A. This may be useful in subsequent manufacturing steps to protect the channel modulation region 64 and thus improve the reliability of the manufacturing process of the device 1.

[0160] Figure 3K A protective layer 118 of insulating material, such as a single layer or an insulating multilayer, is formed on the barrier layer 56, for example, one or more of silicon oxide, silicon nitride, aluminum oxide, and silicon carbide. The protective layer 118 has a thickness along the third axis Z that is greater than the thickness of the channel modulation region 64, for example, between 10 nm and 500 nm.

[0161] In other words, the protection layer 118 completely covers the channel modulation region 64 .

[0162] The protective layer 118 has an upper surface 118A at the useful portion 116 that faces the upper surface 116A of the useful portion 116 .

[0163] In this embodiment, the upper surface 118A of the protection layer 118 extends to a height from the surface 100A along the third axis Z that is lower than the height of the upper surface 111A of the etching mask 111 from the surface 100A along the third axis Z. This may be useful in subsequent manufacturing steps to protect the channel modulation region 64 and thus improve the reliability of the manufacturing process of the device 1.

[0164] In addition, in this embodiment, the distance between the upper surface 118A of the protective layer 118 and the upper surface 64A of the channel modulation region 64 along the third axis Z is greater than the thickness of the etching mask 111 along the third axis Z, which may be useful in subsequent process steps to protect the channel modulation region 64 and thereby improve the reliability of the manufacturing process of the device 1.

[0165] exist Figure 3L In the embodiment, the raised portion 115 of the working multilayer 114 is at least partially removed until the upper surface 111A of the etching mask 111 , thereby exposing the etching mask 111 .

[0166] Removal may be performed by planarization (eg, chemical mechanical polishing (CMP)) or other etching techniques.

[0167] In the illustrated embodiment, after removal, only the portion of the raised portion 115 of the working multilayer 114 extending over the second sidewall 72 remains, which portion forms a raised portion 78 flush with the upper surface 111A of the etching mask 111 .

[0168] The portion of the protective layer 118 extending over the useful portion 116 of the working multilayer 114 (still indicated by 118) remains.

[0169] Then, Figure 3M , the wafer 100 is etched to remove the etching mask 111 , thereby exposing the gate layer 110 .

[0170] In this embodiment, the etching of the etching mask 111 also etches the protection layer 118, thereby reducing its thickness. However, since the thickness of the etching mask 111 is less than the distance between the upper surface 64A of the channel modulation region 64 and the upper surface 118A of the protection layer 118, the remaining protection layer 118 still completely covers the channel modulation region 64. Therefore, the channel modulation region 64 will not be damaged by the etching. Figure 3M damaged by etching.

[0171] After etching, the protective layer 118 forms a reference Figure 1 The insulating layer 58 is described.

[0172] Depending on the materials forming the etching mask 111 and the protective layer 118 and depending on the specific etching used to remove the etching mask 111, Figure 3M The etching may selectively remove only the etching mask 111 without removing the protection layer 118 .

[0173] Then, Figure 3N , defining a gate layer 110, thereby forming gate insulating regions 40, 41. Furthermore, (highly) doped regions 25A, 25B, 27, 29A, 29B, 31 are formed in the epitaxial portion 106 of the surface layer 105; for example, they may be defined by subsequent operations of masking and ion implantation.

[0174] Subsequent manufacturing steps (not shown here) are used to form insulating and / or passivation layers (e.g., Figure 1 oxide layers 35, 36) and metal contact areas (e.g., Figure 1areas 42-45 and 61, 62, 65).

[0175] Furthermore, final manufacturing steps (not shown here) follow, such as, for example, forming an upper layer of metal interconnects and dicing the wafer, which results in the formation of the device 1 .

[0176] In practice, in the present manufacturing process, at least parts of the doped regions 25A, 25B, 27 , 28 , 29A, 29B, 31 of the silicon based components 5 (here PMOS 5A, NMOS 5B transistors) are formed after growing the epitaxial multilayer 49 .

[0177] In particular, highly doped doped regions of the silicon-based component 5 , ie here the source 25A, 29A and drain 25B, 29B regions, and the body contact regions 27 , 31 of the transistors 5A, 5B, are formed after growing the epitaxial multilayer 49 .

[0178] This allows the epitaxial multilayer 49 , 114 to be grown using a high thermal budget, which allows obtaining a good growth quality of the epitaxial multilayer 49 while not negatively affecting the manufacture of the silicon-based component 5 .

[0179] For example, in practice, the growth of the first buffer layer 52 of AlN may occur at a temperature of about 1100° C. within a time interval between about 15 and 30 minutes, and the growth of the GaN and AlGaN layers forming the second buffer layer 53, the channel layer 55, the barrier layer 56 and the channel modulation region 64 may occur in subsequent growth steps, each at a temperature of about 1030° C.-1080° C. within a time interval of about 5-15 minutes. Such a thermal budget will cause the doping atoms of the highly doped regions of the transistors 5A, 5B to diffuse and thus cause low reliability of the manufacturing process.

[0180] In contrast, the present manufacturing process allows both the silicon-based electronic component 5 and the heterostructure-based electronic component 7 to be integrated in the same die, while obtaining high crystal quality of the heterostructure 50 and high manufacturing reliability of the silicon-based component 5. Therefore, the silicon-based component 5 and the heterostructure-based component 7 can have high electrical performance in use.

[0181] Furthermore, in the embodiment shown, in which the silicon-based component 5 comprises MOS transistors 5A, 5B, the fact that the working multilayer 114 can be grown after forming the gate insulating layer 110 and before defining the gate insulating layer 110 allows simplifying the manufacturing steps associated with the formation of the epitaxial multilayer 49.

[0182] In fact, for example, the gate insulating layer 110 may be used as a support for the formation of the etching mask 111 .

[0183] In addition, reference Figure 3A-Figure 3N In an embodiment of the manufacturing process, using the growth mask 103 can allow the simultaneous growth of the single crystal epitaxial portion 106 in which the silicon-based electronic component 5 is formed, and ensure the surface quality of the upper surface 100A below the growth mask 103 on which the working multilayer 114 is grown.

[0184] The fact that the growth mask 103 may comprise an oxide, in particular silicon oxide, allows the growth mask 103 to be etched by a different chemistry than that which may be used to remove the second intermediate layer 18. Thus, an opening or recess 113 may be formed through the sacrificial portion 107, which exposes the underlying upper surface 100A without affecting (at least to a first approximation) the quality of the surface 100A on which the working epitaxial multilayer 114 is to be grown ( Figure 3G-3I ).

[0185] In particular, the fact that the growth mask 103 comprises a layer comprising an oxide in direct contact with the semiconductor layer 18 may allow further reducing the risk of damaging the surface 100A on which the epitaxial multilayer 49 is to be grown.

[0186] In particular, the fact that growth mask 103 is made of silicon oxide and layer 18 is made of silicon allows obtaining a highly selective etch rate of growth mask 103 relative to the silicon of layer 18. Furthermore, before growing working epitaxial multilayer 114, wet etching may also be used to clean surface 100A.

[0187] In practice, growth mask 103 can be used as a stop layer during etching of overlying sacrificial portion 107, thereby ensuring complete removal of overlying sacrificial portion 107. Furthermore, forming openings in growth mask 103 does not affect the quality of underlying surface 100A (e.g., in terms of steps and recesses).

[0188] The epitaxial multilayer 49 and thus the heterostructure 50 may have a high crystal quality. Thus, the corresponding electronic component 7 functioning based on the formation of a two-dimensional gas in the heterostructure 50 may have high electrical performance in use.

[0189] At the same time, the electronic component 5 is also integrated in the single crystal silicon layer (epitaxial portion 106), which can have high crystal quality. Therefore, the electronic component 5 can have high electrical performance when used.

[0190] In addition, the thickness of the growth mask 103 can be thick enough to serve as a mask for forming the epitaxial multilayer 49, and at the same time thin enough to minimize the non-planarity of the upper surface 105A of the surface layer 105. In practice, the upper surface 105A of the surface layer 105 can be considered to be substantially planar. This allows to facilitate subsequent manufacturing steps that form both the silicon-based electronic component 5 and the heterostructure-based electronic component 7.

[0191] use <111> The possibility of using a silicon substrate 14 as a starting substrate for forming the semiconductor electronic device 1 can allow obtaining a high epitaxial quality of the heterostructure 50, in particular when the channel layer 55 is GaN. As a result, the electronic component 7 based on the heterostructure can have excellent electrical properties. The applicant has also verified that the use of <111> The silicon substrate 14 also allows obtaining excellent electrical properties of the silicon-based electronic component 5 .

[0192] However, it will be clear to those skilled in the art that the above manufacturing steps and corresponding execution order may be different depending on the specific process and machine used. Figures 3A-3N The difference shown in .

[0193] For example, epitaxial multilayer 49 may be grown before surface layer 105 .

[0194] For example, the body regions of the NMOS and PMOS transistors can be formed before forming the insulating oxide (33, 108) or implanted after forming the field insulation (STI); in particular, they are formed before forming the oxide constituting the gate structure of the PMOS and NMOS transistors (i.e., for example, before depositing the polysilicon layer 110).

[0195] For example, multilayer 114 may be selectively grown only from exposed portion 101B. In this case, portion 115 would not exist; therefore, Figure 3L The removal may not exist.

[0196] Finally, it is clear that other modifications and variations may be made to the electronic device 1 and to the process for its manufacture described and illustrated herein, without thereby departing from the scope of the present disclosure as defined in the appended claims.

[0197] In addition to or as an alternative to the PMOS 5A and NMOS 5B transistors, the electronic device 1 may also include other silicon-based electronic components 5 (active and / or passive) integrated in the die 3 .

[0198] For example, Figure 2 As shown in , the silicon-based electronic components 5 may also include bipolar transistors 5C and passive components 5D such as diodes and resistors. Figure 2 In FIG. 5 , the bipolar transistor 5C and the passive component 5D are integrated in respective device parts 120 , 121 that are different from each other and are schematically indicated by dashed lines.

[0199] For example, device portions 120 , 121 are formed in respective single crystal silicon epitaxial regions grown on substrate region 10 , which are particularly monolithic with epitaxial region 23 .

[0200] Insulating regions (eg shallow or deep trenches) may be arranged between the portions 120 , 121 and 20 in a manner known per se, such that the respective electronic components are electrically insulated from one another in use.

[0201] Apart from Figure 2 In addition to or in place of the components shown in Figure 2 In addition to the components shown in , the device 1 may also include other silicon-based electronic components 5 integrated in the die 3. For example, the components 5 may include MOS transistors for medium voltage applications, such as 15V to 20V; DMOS transistors and / or drift MOS transistors, such as for applications with operating voltages of 20V to 200V; thin film resistors; OTP or MTP memory; phase change memory; etc.

[0202] It will be clear to the person skilled in the art that the integration of different types of silicon-based electronic components 5 with each other can be performed by manufacturing steps known per se and therefore not further illustrated here, for example by BCD technology.

[0203] For example, the conductivity type of the various semiconductor regions, n or p, may be reversed from that described.

[0204] For example, the epitaxial multilayer 49 may include only the heterostructure 50. In other words, the heterostructure 50 may be grown directly on the substrate region 10.

[0205] For example, layers 14 - 18 may include one or more diffusion regions of a dopant substance (P or N), depending on the particular application.

[0206] For example, the heterostructure based component 7 may include electronic components other than the HEMT transistor 7 .

[0207] For example, the HEMT transistor 7 may be of the normally-off type, wherein the gate structure may be different from what has been described above; for example, the gate structure may be of the recessed type and / or the fabrication of the gate structure may include the use of a fluorine plasma below the gate structure. Alternatively, the HEMT transistor 7 may be of the normally-on type, i.e., of the depletion type.

[0208] For example, refer to Figure 1 The insulating region 77 extending between the first and second device portions 20, 21 may have a different shape and structure than shown. For example, it may be one or more trenches extending along the third axis Z to a greater depth in the die 3.

[0209] For example, the number of epitaxial layers forming substrate region 10 may vary depending on the specific application.

[0210] For example, depending on the desired thickness of the epitaxial multilayer 49 and the epitaxial region 23 along the third axis Z, the second intermediate layer 18 may not be present and the epitaxial multilayer 49 may be grown directly on the second deep layer 17 .

[0211] In the case of medium or low voltage applications (e.g., from 7V to 40V), the substrate region 10 may comprise only the substrate 14 and the first deep layer 15 (or also the first intermediate layer 16). In practice, in this case, the epitaxial multilayer 49 may be grown directly on the first deep layer 15 or, if present, on the first intermediate layer 16.

[0212] For example, the electronic component 5 may be an electronic component based on a single semiconductor other than silicon, such as Ge, SiGe, or the like.

[0213] A process for manufacturing a semiconductor electronic device is summarized as comprising: providing a wafer (100) comprising a substrate layer (18) of semiconductor material, the substrate layer having a first portion (101A) and a second portion (101B) different from the first portion; growing an epitaxial region (23, 106) of a single semiconductor material on the first portion (101A) of the substrate layer; growing an epitaxial multilayer (49, 114) comprising a heterostructure (50) on the second portion (101B) of the substrate layer; forming a first electronic component (5A, 5B, 5C, 5D) based on the single semiconductor material from the epitaxial region (23, 106); and forming a second electronic component (7) based on the heterostructure from the heterostructure, wherein forming the first electronic component comprises forming a plurality of doped regions (25A, 25B, 27, 29A, 29B, 31) in the epitaxial region (23) after the step of growing the epitaxial multilayer.

[0214] The first electronic component is a MOS transistor (5A, 5B), and forming the plurality of doped regions includes forming one or more of: a source region (25A, 29A), a drain region (25B, 29B), and a body contact region (27, 31) of the MOS transistor in the epitaxial region.

[0215] The first electronic component is a MOS transistor (5A, 5B) having a gate insulating region (40, 41), and forming the first electronic component further includes: forming a gate insulating layer (110), such as polysilicon, on the epitaxial region (106) before growing the epitaxial multilayer (114, 49); and defining the gate insulating layer after the step of growing the epitaxial multilayer to form the gate insulating region.

[0216] The doping region is between 1·10 16 Atom / cm 3 and 4.10 21 Atom / cm 3between the doping levels.

[0217] Growing the epitaxial multilayer includes: forming a growth mask (103) on the substrate layer (18); and forming an opening in the growth mask (103) to expose a second portion of the substrate layer.

[0218] A growth mask (103) is formed before growing the epitaxial region, the growth mask exposing a first portion (101A) of the substrate layer (18).

[0219] Growing an epitaxial region includes growing a surface layer (105) of a single semiconductor material, the surface layer having a first portion (106) extending on a first portion (101A) of a substrate layer (18) and a second portion (107) extending on a growth mask (103); and forming an opening in the growth mask (103) includes forming a recess in the second portion (107) of the surface layer extending to the growth mask.

[0220] The manufacturing process also includes forming an etching mask (111) extending on a first portion (106) of the surface layer (105) and having an opening (113) above a second portion (107) of the surface layer (105), wherein growing an epitaxial multilayer includes: growing a working multilayer (114) having a first portion (116) extending on a second portion (101B) of the substrate layer (18) and a second portion (115) extending on the etching mask; and removing the second portion (115) of the working multilayer, wherein the etching mask (111) extends from a surface (110A) along a direction (Z), and the surface (110A) is arranged at a certain height along the direction (Z) from the substrate layer (18), and the height is higher relative to the first portion (116) of the working multilayer.

[0221] The growth mask (103) includes an oxide layer, such as silicon oxide.

[0222] The growth mask (103) has a thickness between 7 nm and 300 nm.

[0223] The second electronic component is a HEMT transistor (7), wherein the heterostructure is based on materials of Group III and Group V of the Periodic Table of Elements, including, for example, GaN.

[0224] The HEMT transistor includes a channel modulation region (64) of semiconductor material having an upper surface (64A), and forming the second electronic component includes growing the channel modulation region on the heterostructure (50) so that the upper surface (64A) of the channel modulation region (64) is arranged at a distance from the substrate layer (18) along a direction (Z), and the distance is less than the distance between the upper surface (110A) of the gate insulating layer (110) and the substrate layer along the direction (Z).

[0225] The wafer comprises a substrate (14) having a first conductivity type (P), a substrate layer (15, 16, 17, 18) having a second conductivity type (N) different from the first conductivity type and extending on the substrate.

[0226] The single semiconductor material is silicon, and the wafer (100) is single crystal silicon, in particular <111> silicon.

[0227] A semiconductor electronic device (1) is summarized as comprising: a tube core (3); a first electronic component (5) based on a single semiconductor material; and a second electronic component (7) based on a heterostructure, wherein the tube core comprises: a substrate region (10) of semiconductor material; a first surface portion (20) comprising a single crystal region (23) of the single semiconductor material extending on the substrate region; and a second surface portion (21) which is different from the first surface portion and comprises an epitaxial multilayer (49) extending on the substrate region, the epitaxial multilayer comprising a heterostructure (50), the first electronic component (5) being integrated into the first surface portion of the tube core and the second electronic component (7) being integrated into the second surface portion of the tube core.

[0228] The various embodiments described above can be combined to provide further embodiments. Aspects of the embodiments can be modified, if necessary, to employ concepts of the various patents, applications, and publications to provide further embodiments.

[0229] These and other changes can be made to the embodiments in light of the above detailed description. In general, in the following claims, the terms used should not be interpreted to limit the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full range of equivalents to which these claims are entitled. Therefore, the claims are not limited by this disclosure.

Claims

1. A process for manufacturing a semiconductor electronic device, comprising: forming an epitaxial region of a single semiconductor material on a first portion of a substrate layer having a first portion and a second portion, the epitaxial region having a first surface opposite the substrate layer; forming an epitaxial multilayer including a heterostructure on a second portion of the substrate layer; forming a separation portion having a second surface coplanar with the first surface between the epitaxial region and the epitaxial multilayer; forming a first electronic component on the epitaxial region; as well as forming a second electronic component on the heterostructure, The forming of the first electronic component includes forming a plurality of doped regions in the epitaxial region after forming the epitaxial multilayer. 2 . The manufacturing process of claim 1 , wherein the first electronic component is a MOS transistor, and forming the plurality of doped regions comprises forming a source region, a drain region, and a body contact region of the MOS transistor in the epitaxial region.

3. The manufacturing process of claim 1, wherein the first electronic component is a MOS transistor having a gate insulating region, and forming the first electronic component further comprises: forming a gate insulating layer on the epitaxial region before forming the epitaxial multilayer; as well as A gate insulating layer is defined after forming the epitaxial multilayer, thereby forming a gate insulating region.

4. The process of claim 1, wherein the doped region has a 16 Atom / cm 3 and 4.10 21 Atom / cm 3 within the range of doping levels.

5. The process of claim 1 , wherein growing the epitaxial multilayer comprises: forming a growth mask on the substrate layer; as well as An opening is formed in the growth mask to expose a second portion of the substrate layer.

6. The manufacturing process of claim 5, wherein a growth mask is formed before forming the epitaxial region, the growth mask exposing the first portion of the substrate layer.

7. A manufacturing process according to claim 5, wherein forming an epitaxial region includes growing a surface layer of a single semiconductor material, the surface layer having a first portion extending on a first portion of a substrate layer and a second portion extending on a growth mask; and wherein forming an opening in the growth mask includes forming a recess in the second portion of the surface layer extending to the growth mask.

8. The manufacturing process of claim 7, further comprising forming an etch mask extending over the first portion of the surface layer and having an opening over the second portion of the surface layer, The formation of epitaxial multilayers includes: growing a working multilayer having a first portion extending over a second portion of the substrate layer and a second portion extending over the etch mask; as well as Remove the second part of the working multilayer, The etching mask is separated from the substrate layer by a first distance along a first direction, and the first distance is greater than a second distance between the first portion of the working multilayer and the substrate layer along the first direction.

9. The process of claim 5, wherein the growth mask comprises an oxide layer.

10. The manufacturing process of claim 5, wherein the growth mask has a thickness in the range of 7 nm and 300 nm.

11. The manufacturing process of claim 3, wherein the second electronic component is a HEMT transistor and the heterostructure is based on materials from Group III and Group V of the Periodic Table of Elements.

12. The manufacturing process of claim 11 , wherein the HEMT transistor comprises a channel modulation region of semiconductor material having an upper surface, and forming the second electronic component comprises growing the channel modulation region on the heterostructure so that the upper surface of the channel modulation region is arranged at a first distance from the substrate layer along the first direction, the first distance being less than a second distance between the upper surface of the gate insulating layer and the substrate layer along the first direction.

13. The manufacturing process of claim 12, further comprising a substrate coupled to the substrate layer and having a first conductivity type, the substrate layer having a second conductivity type different from the first conductivity type and extending over the substrate.

14. The process of claim 13 wherein the single semiconductor material is silicon.

15. An electronic device comprising: Die; a first electronic component; as well as a second electronic component coupled to the first electronic component, The die includes: A substrate region of semiconductor material; a first surface portion comprising a single crystalline region of a single semiconductor material extending over a substrate region; and a second surface portion, different from the first surface portion and comprising an epitaxial multilayer extending over the substrate region, the epitaxial multilayer comprising a heterostructure, A first electronic component is integrated into a first surface portion of the die and a second electronic component is integrated into a second surface portion of the die.

16. The electronic device according to claim 15, wherein the second electronic component comprises: Gate contact region; as well as Channel modulation region between the heterostructure and the gate contact region.

17. The electronic device of claim 15, further comprising a buffer layer between the substrate region and the epitaxial multilayer.

18. A method comprising: forming a definition layer on the wafer, the definition layer having a first portion on the first portion of the wafer and a second portion on the second portion of the wafer; exposing a first portion of the wafer by removing a first portion of the defining layer; forming a surface layer having a first portion on the first portion of the wafer and a second portion on the defining layer; forming a mask on a first portion of the surface layer; exposing the defining layer by removing a second portion of the surface layer; as well as A working multilayer is formed having a first portion over the mask and a second portion over the second portion of the wafer. 19 . The method of claim 18 , further comprising, after forming the surface layer, forming a doped region and a plurality of insulating portions in the first portion of the surface layer.

20. The method of claim 18, wherein working multiple layers comprises: Buffer layer; a channel layer on the buffer layer; and A barrier layer on the channel layer.

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