Semiconductor device and preparation method thereof

Abstract

The invention relates to a semiconductor device and a preparation method thereof. The preparation method of the semiconductor device comprises the following steps: providing a substrate, and forming a plurality of side walls on one side of the substrate; a gap is formed between every two adjacent side walls, and the sizes of at least two gaps are different; patterning the substrate based on the side wall, and forming a groove below the interval; removing the side wall; forming a trench isolation structure in the trench; the trench isolation structure is used for defining a pixel region; removing the part, located in the pixel region, of the substrate to form a plurality of pixel accommodating grooves; pixel units are formed in the pixel accommodating grooves; according to the embodiment of the invention, the semiconductor device with a plurality of pixel units of different sizes can be prepared according to requirements, the application of the semiconductor device on a CMOS (Complementary Metal Oxide Semiconductor) backside illuminated image sensor is facilitated, and the backside illuminated image sensor meets different market requirements.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for preparing the same. Background Art

[0002] A complementary metal-oxide-semiconductor (CMOS) back-illuminated image sensor includes a plurality of pixel units and a deep trench isolation structure between the pixel units.

[0003] However, in the current manufacturing process of CMOS back-illuminated image sensors, the sizes of deep trench isolation structures between multiple pixel units are the same, and the sizes of multiple pixel units are also the same, resulting in limitations in their application in CMOS back-illuminated image sensors.

[0004] Therefore, how to prepare a CMOS back-illuminated image sensor with multiple pixel units of different sizes according to demand is an urgent problem to be solved. Summary of the invention

[0005] Based on this, the embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same, which can be used to manufacture a CMOS back-illuminated image sensor having a plurality of pixel units of different sizes according to requirements.

[0006] Some embodiments of the present disclosure provide a method for preparing a semiconductor device, comprising the following steps:

[0007] A substrate is provided, and a plurality of sidewalls are formed on one side of the substrate; there are intervals between adjacent sidewalls, and at least two intervals have different sizes;

[0008] Based on the sidewall patterning substrate, a groove is formed below the spacer;

[0009] Remove side walls;

[0010] forming a trench isolation structure in the trench; the trench isolation structure is used to define a pixel area;

[0011] Removing the portion of the substrate located in the pixel area to form a plurality of pixel accommodating grooves;

[0012] A pixel unit is formed in the pixel receiving groove.

[0013] In some embodiments, forming a trench isolation structure in a trench includes: stacking and depositing a first dielectric layer and a second dielectric layer in the trench.

[0014] In which, in different regions of the trench isolation structure corresponding to different size intervals, the surface of the first dielectric layer close to the second dielectric layer is located in different planes.

[0015] In some embodiments, forming a pixel unit in a pixel receiving groove includes: stacking a conductive layer and a receiving layer in the pixel receiving groove.

[0016] The surfaces of the conductive layers in different pixel receiving grooves facing away from the substrate are located in the same plane.

[0017] In some embodiments, the method for preparing a semiconductor device further includes:

[0018] forming a light shielding layer covering the trench isolation structure; the light shielding layer has an opening exposing the pixel area;

[0019] A color filter film is formed in the opening; the color filter film covers the top surface of the corresponding pixel unit away from the substrate.

[0020] In some embodiments, a plurality of spacers are formed on one side of the substrate, including:

[0021] A plurality of initial spacers are formed on one side of the substrate and are spaced apart from each other; the distance between any two adjacent initial spacers is the same;

[0022] A portion of the initial side walls is selectively removed to form a plurality of side walls.

[0023] In some embodiments, a plurality of initial spacers distributed at intervals are formed on one side of a substrate, including:

[0024] forming a plurality of sacrificial structures distributed at intervals on one side of the substrate;

[0025] Forming a sidewall material layer on one side surface of the substrate, wherein the sidewall material layer covers the sidewalls and top surfaces of the plurality of sacrificial structures;

[0026] Removing the sidewall material layer on the top surface of the sacrificial structure, so that the sidewall material layer remaining on the sidewall of the sacrificial structure serves as the initial sidewall;

[0027] Removal of sacrificial structures.

[0028] Based on the same inventive concept, the embodiments of the present disclosure also provide a semiconductor device, which is obtained by the preparation method in some of the above embodiments. The semiconductor device includes a substrate and a plurality of pixel units. A trench isolation structure and a plurality of pixel accommodating grooves are provided in the substrate. The trench isolation structure is used to define the setting position of the pixel accommodating groove, and the size of the interval between at least two pixel accommodating grooves is different. The plurality of pixel units are respectively located in the corresponding pixel accommodating grooves.

[0029] In the embodiments of the present disclosure, the semiconductor device adopts the above structure. The technical effect that can be achieved by the semiconductor device is the same as the technical effect that can be achieved by the method for preparing the semiconductor device in the aforementioned embodiments, and will not be described in detail here.

[0030] In some embodiments, the trench isolation structure includes a first dielectric layer and a second dielectric layer that are stacked; wherein in different regions of the trench isolation structure corresponding to different size intervals, the surface of the first dielectric layer close to the second dielectric layer is located in different planes.

[0031] In some embodiments, the pixel unit includes a conductive layer and a receiving layer that are stacked.

[0032] The surfaces of the conductive layers in different pixel receiving grooves facing away from the substrate are located in the same plane.

[0033] In some embodiments, the semiconductor device further comprises: a light shielding layer and a plurality of color filter films. The light shielding layer covers the trench isolation structure. The light shielding layer has an opening for exposing the pixel unit. The plurality of color filter films are respectively formed in the corresponding openings and cover the top surface of the corresponding pixel unit away from the substrate.

[0034] As described above, in the embodiment of the present disclosure, a plurality of spaced sidewalls are first formed on one side of the substrate, and at least two of the spacers are of different sizes; then, based on the sidewall patterning substrate, a groove is formed below the spacer, so that a plurality of grooves of different sizes can be formed in the substrate, and then a groove isolation structure of different sizes that meets the requirements can be formed; finally, a pixel area is defined based on the groove isolation structure, and a pixel unit is formed in the pixel area. The unexpected technical effect is that the embodiment of the present disclosure can form pixel units of different sizes that meet the requirements based on the groove isolation structure of different sizes, so as to prepare a semiconductor device with a plurality of pixel units of different sizes according to the requirements, which is beneficial to the use of semiconductor devices on CMOS back-illuminated image sensors, so that back-illuminated image sensors meet different market requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0036] Figure 1 is a flow chart of a method for preparing a semiconductor device provided in an embodiment;

[0037] Figure 2 A flow chart of forming a sidewall spacer in a method for preparing a semiconductor device provided in an embodiment;

[0038] Figure 3 A flow chart of forming an initial sidewall spacer in a method for preparing a semiconductor device provided in an embodiment;

[0039] Figure 4A flow chart of forming a light shielding layer and a light filter film in a method for preparing a semiconductor device provided in an embodiment;

[0040] Figure 5 A schematic cross-sectional view of a structure obtained after providing a substrate in a method for preparing a semiconductor device according to an embodiment;

[0041] Figure 6 A schematic cross-sectional view of a structure obtained after forming a first mask in a method for preparing a semiconductor device provided by an embodiment;

[0042] Figure 7 A schematic cross-sectional view of a structure obtained after removing a first mask in a method for preparing a semiconductor device provided by an embodiment;

[0043] Figure 8 A schematic cross-sectional view of a structure obtained in step S112 in a method for preparing a semiconductor device provided in an embodiment;

[0044] Fig. 9 A schematic cross-sectional view of a structure obtained in step S113 in a method for preparing a semiconductor device provided in an embodiment;

[0045] Fig.10 A schematic cross-sectional view of a structure obtained in step S114 in a method for preparing a semiconductor device provided in an embodiment;

[0046] Fig.11 A cross-sectional schematic diagram of another structure obtained in step S120 in a method for preparing a semiconductor device provided in an embodiment;

[0047] Fig.12 A cross-sectional schematic diagram of another structure obtained in step S200 in a method for preparing a semiconductor device provided in an embodiment;

[0048] Fig.13 A cross-sectional schematic diagram of another structure obtained in step S400 in a method for preparing a semiconductor device provided in an embodiment;

[0049] Fig.14 A schematic cross-sectional view of another structure obtained in step S500 in a method for preparing a semiconductor device provided in an embodiment;

[0050] Fig.15 A cross-sectional schematic diagram of another structure obtained in step S600 in a method for preparing a semiconductor device provided in an embodiment;

[0051] Fig.16 A cross-sectional schematic diagram of another structure obtained in step S800 in a method for preparing a semiconductor device provided in an embodiment; and Fig.16The present invention is also a cross-sectional schematic diagram of a semiconductor device provided by an embodiment.

[0052] Description of reference numerals:

[0053] 1-substrate; 10-metal interconnect structure; 11-oxide layer; 20-sacrificial material layer; 2-sacrificial structure; 300-sidewall material layer; 30-initial sidewall; 3-sidewall; 4-trench isolation structure; 41-first dielectric layer; 42-second dielectric layer; 5-pixel unit; 51-conductive layer; 52-receiving layer; 6-light shielding layer; 7-color filter film; Y-first mask; G1-trench; G2-pixel accommodating groove. DETAILED DESCRIPTION

[0054] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. Embodiments of the present disclosure are given in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0055] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0056] It should be understood that spatial relationship terms such as "under", "below", "below", "under", "above", "above", etc., can be used here to describe the relationship between an element or feature shown in the figures and other elements or features. It should be understood that in addition to the orientations shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0057] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0058] As used herein, a "deposition" process includes, but is not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD).

[0059] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic diagrams of ideal embodiments (and intermediate structures) of the invention, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the invention.

[0060] The back-illuminated image sensor places the components of the photosensitive layer (such as microlenses and pixel units) on the back side of the substrate and allows light to enter directly from the back of the substrate, avoiding the light in the front-illuminated image sensor structure being affected by the circuits and transistors between the microlenses and pixel units, thereby significantly improving the efficiency of light and greatly improving the photosensitivity of the image sensor under low light conditions.

[0061] A complementary metal-oxide-semiconductor (CMOS) back-illuminated image sensor includes a plurality of pixel units and a deep trench isolation structure between the pixel units.

[0062] However, in the current manufacturing process of CMOS back-illuminated image sensors, the sizes of deep trench isolation structures between multiple pixel units are the same, and the sizes of multiple pixel units are also the same, resulting in limitations in their application in CMOS back-illuminated image sensors.

[0063] Therefore, how to prepare a CMOS back-illuminated image sensor with multiple pixel units of different sizes according to demand is an urgent problem to be solved.

[0064] In view of the above-mentioned deficiencies in the related art, an object of the embodiments of the present disclosure is to provide a semiconductor device and a method for manufacturing the same, so as to effectively improve the voltage resistance of the gate oxide layer.

[0065] See also Figure 1 In some embodiments, the present disclosure provides a method for preparing a semiconductor device, the method comprising steps S100 to S600.

[0066] S100, providing a substrate, and forming a plurality of sidewalls on one side of the substrate; there are intervals between adjacent sidewalls, and at least two intervals have different sizes.

[0067] S200 , forming a groove below the spacer based on the sidewall patterning substrate.

[0068] S300, remove the side walls.

[0069] S400, forming a trench isolation structure in the trench; the trench isolation structure is used to define a pixel area.

[0070] S500, removing the portion of the substrate located in the pixel area to form a plurality of pixel accommodating grooves.

[0071] S600, forming a pixel unit in the pixel receiving groove.

[0072] In the disclosed embodiment, a plurality of spaced sidewalls are first formed on one side of the substrate, and at least two of the spacers are of different sizes; then, based on the sidewall patterning substrate, a groove is formed below the spacer, so that a plurality of grooves of different sizes can be formed in the substrate, and then a groove isolation structure of different sizes that meets the requirements can be formed; finally, a pixel region is defined based on the groove isolation structure, and a pixel unit is formed in the pixel region. In this way, based on the groove isolation structure of different sizes, pixel units of different sizes that meet the requirements can be formed, so that a semiconductor device with a plurality of pixel units of different sizes can be prepared according to the requirements, which is beneficial to the application of semiconductor devices on CMOS back-illuminated image sensors, so that back-illuminated image sensors can meet different market requirements.

[0073] In some embodiments, step S400 forms a trench isolation structure in the trench, including: stacking and depositing a first dielectric layer and a second dielectric layer in the trench.

[0074] In which, in different regions of the trench isolation structure corresponding to different size intervals, the surface of the first dielectric layer close to the second dielectric layer is located in different planes.

[0075] In some embodiments, step S600 forms a pixel unit in the pixel receiving groove, including: stacking a conductive layer and a receiving layer in the pixel receiving groove.

[0076] The surfaces of the conductive layers in different pixel receiving grooves facing away from the substrate are located in the same plane.

[0077] It should be noted that, in the above-mentioned embodiments, the execution of each step in the method is not strictly limited in order, and these steps may not necessarily be executed in the order described, but may be executed in other ways. Moreover, at least a part of any step may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but may be executed at different times, and the execution order of these sub-steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least a part of the sub-steps or stages of other steps. The method is limited to being able to realize the preparation of the corresponding semiconductor device.

[0078] Based on this, with respect to the methods for preparing semiconductor devices provided in some of the above embodiments, the present disclosure provides some methods in the following embodiments as some possible implementations of the above preparation methods.

[0079] In some embodiments, see Figure 2 , step S100 forms a plurality of sidewall spacers on one side of the substrate, including steps S110 to S120.

[0080] S110, forming a plurality of initial spacers distributed at intervals on one side of the substrate; the distance between any two adjacent initial spacers is the same.

[0081] S120, selectively removing a portion of the initial sidewalls to form a plurality of sidewalls.

[0082] In some embodiments, see Figure 3 Step S110 forms a plurality of initial spacers distributed at intervals on one side of the substrate, including steps S111 to S114.

[0083] S111, forming a plurality of sacrificial structures distributed at intervals on one side of the substrate.

[0084] S112, forming a spacer material layer on one side surface of the substrate, wherein the spacer material layer covers the sidewalls and top surfaces of the plurality of sacrificial structures.

[0085] S113, removing the spacer material layer on the top surface of the sacrificial structure, so that the spacer material layer remaining on the side wall of the sacrificial structure serves as an initial spacer.

[0086] S114, removing the sacrificial structure.

[0087] In some embodiments, see Figure 4 The method for preparing the semiconductor device also includes steps S700 to S800.

[0088] S700, forming a light shielding layer covering the trench isolation structure; the light shielding layer has an opening exposing the pixel area.

[0089] S800, forming a color filter film in the opening; the color filter film covers the top surface of the corresponding pixel unit facing away from the substrate.

[0090] In order to more clearly illustrate the method for preparing the semiconductor device provided in the above embodiment, Figure 1 to Figure 16 The preparation method is described in detail.

[0091] In step S111, refer to Figure 3 S111 and Figure 5~Figure 7 , a plurality of sacrificial structures 2 are formed on one side of the substrate 1 and are distributed at intervals.

[0092] For some examples, see Figure 5 , providing a substrate 1.

[0093] In some examples, the material of the substrate 1 may be any suitable substrate material known in the art, for example, it may be at least one of the following materials: silicon (Si), germanium (Ge), red phosphorus, silicon germanium (SiGe), carbon silicon (SiC), carbon germanium silicon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), or it may also be double-sided polished silicon wafers (Double Side Polished Wafers, referred to as DSP), or it may be a ceramic substrate such as alumina, a quartz or glass substrate, etc., and this embodiment is not limited here.

[0094] For example, the thickness of the substrate 1 ranges from 2µm to 4µm. For example, the thickness of the substrate 1 may be 2µm, 2.5µm, 3µm, 3.5µm or 4µm, etc.

[0095] In some embodiments, a metal interconnection structure 10 is formed on the other side of the substrate 1 , and the metal interconnection structure 10 is used to realize interconnection and conduction of devices in the substrate 1 .

[0096] In some embodiments, an oxide layer 11 is formed on one surface of the substrate 1 .

[0097] By way of example, the material of the oxide layer 11 may include, but is not limited to, silicon oxide.

[0098] By way of example, the oxide layer 11 may be formed by a thermal oxidation process or a chemical vapor deposition process, but is not limited thereto.

[0099] In some embodiments, forming a plurality of sacrificial structures 2 spaced apart on one side of the substrate 1 includes:

[0100] See also Figure 6 , forming a sacrificial material layer 20 on a side of the oxide layer 11 facing away from the substrate 1;

[0101] Please continue reading Figure 6 , forming a first mask Y on a side of the sacrificial material layer 20 facing away from the substrate 1;

[0102] See also Figure 7 , etching the sacrificial material layer 20 based on the first mask Y to form a plurality of sacrificial structures 2 distributed at intervals;

[0103] Please continue reading Figure 7 , remove the first mask Y.

[0104] In the embodiment of the present disclosure, the spacings between the multiple sacrificial structures 2 may be the same, which helps to improve the uniformity of the widths of the multiple spacers formed subsequently, but the present invention is not limited thereto.

[0105] By way of example, the material of the sacrificial material layer 20 may include, but is not limited to, silicon.

[0106] For example, the sacrificial material layer 20 may be formed by epitaxial process, spin coating, spray coating or other processes, but is not limited thereto.

[0107] For example, the material of the first mask Y may include but is not limited to photoresist. An anti-reflection layer (not shown in the figure) may also be formed between the first mask Y and the sacrificial material layer 20, so as to reduce the reflection of light when exposing the photoresist and improve the pattern accuracy of the formed first mask Y.

[0108] In step S112, refer to Figure 3 S112 and Figure 8 A spacer material layer 300 is formed on one side surface of the substrate 1 , and the spacer material layer 300 covers the sidewalls and top surfaces of the plurality of sacrificial structures 2 .

[0109] For example, the material of the spacer material layer 300 may include but is not limited to silicon nitride or silicon oxynitride.

[0110] By way of example, the spacer material layer 300 may be formed by a deposition process, but is not limited thereto.

[0111] In step S113, refer to Figure 3 S113 and Fig. 9 , remove the spacer material layer 300 on the top surface of the sacrificial structure 2 , and use the spacer material layer 300 remaining on the sidewall of the sacrificial structure 2 as the initial spacer 30 .

[0112] In some examples, an etching process may be used to remove a portion of the spacer material layer 300 , and the spacer material layer 300 on the sidewalls of the plurality of sacrificial structures 2 is retained as the initial spacer 30 .

[0113] For example, a second mask (not shown) may be formed on the side of the spacer material layer 300 away from the oxide layer 11 , and the spacer material layer 300 is etched based on the second mask to retain the spacer material layer 300 of the sidewalls of the multiple sacrificial structures 2 as the initial spacer 30 .

[0114] By way of example, the material of the second mask may include, but is not limited to, silicon nitride.

[0115] For example, a deposition process may be used to form a second mask on a side of the spacer material layer 300 away from the oxide layer 11 , but the present invention is not limited thereto.

[0116] In step S114, refer to Figure 3 S114 and Fig.10 , removing the sacrificial structure 2.

[0117] For example, the sacrificial structure 2 may be removed by dry etching, but the invention is not limited thereto.

[0118] In step S120, refer to Figure 2 S120 and Fig.11 , a portion of the initial sidewalls 30 are selectively removed to form a plurality of sidewalls 3. There are intervals between adjacent sidewalls 3, and at least two intervals have different sizes.

[0119] In some examples, a photolithography process and an etching process may be used to etch out locations where trench isolation structures of different sizes are desired according to a preset target.

[0120] In step S200, refer to Figure 1 S200 and Fig.12 , the substrate 1 is patterned based on the sidewall 3 to form a groove G1 below the spacer.

[0121] In some examples, patterning the substrate 1 based on the spacer 3 to form the trench G1 below the spacer includes: etching the oxide layer 11 and the substrate 1 based on the spacer 3 to form a plurality of trenches G1 of different sizes in the substrate 1 .

[0122] In some examples, a plurality of trenches G1 with different sizes may be formed in the substrate 1 by a dry etching process.

[0123] By way of example, the trench G1 may be a deep trench.

[0124] In step S300, refer to Figure 1 S300 and Fig.13 , remove side wall 3.

[0125] In some examples, an etching process may be used to remove the sidewall spacer 3 .

[0126] In step S400, refer to Figure 1 S400 and Fig.13 , a trench isolation structure 4 is formed in the trench G1; the trench isolation structure 4 is used to define a pixel area.

[0127] In some embodiments, forming the trench isolation structure 4 in the trench G1 includes: stacking and depositing a first dielectric layer 41 and a second dielectric layer 42 in the trench G1. In different regions of the trench isolation structure 4 corresponding to different size intervals, the surface of the first dielectric layer 41 close to the second dielectric layer 42 is located in different planes.

[0128] For example, the material of the first dielectric layer 41 may include, but is not limited to, silicon boride. The material of the second dielectric layer 42 may include, but is not limited to, silicon gallium or silicon indium.

[0129] For example, a deposition process may be used to sequentially form the first dielectric layer 41 and the second dielectric layer 42 in the trench G1 , and a planarization process may be used to remove the second dielectric layer 42 on the surface of the substrate 1 . However, the present invention is not limited thereto.

[0130] In step S500, refer to Figure 1 S500 and Fig.14 , the portion of the substrate 1 located in the pixel area is removed to form a plurality of pixel accommodating grooves G2.

[0131] In some examples, a dry etching process may be used to remove the portion of the substrate 1 located in the pixel area to form a plurality of pixel receiving grooves G2 to define the areas where pixel units are required.

[0132] In step S600, refer to Figure 1 S600 and Fig.15 , a pixel unit 5 is formed in the pixel receiving groove G2.

[0133] In some embodiments, forming the pixel unit 5 in the pixel receiving groove G2 includes: stacking a conductive layer 51 and a receiving layer 52 in the pixel receiving groove G2. The surfaces of the conductive layers 51 in different pixel receiving grooves G2 facing away from the substrate 1 are located in the same plane.

[0134] For example, the material of the conductive layer 51 includes silicon phosphide, silicon arsenide or silicon antimonide. The material of the receiving layer 52 includes silicon arsenide.

[0135] By way of example, the pixel unit 5 includes a light emitting device, such as a light emitting diode.

[0136] In step S800, refer to Figure 1 S700 and Fig.16 , forming a light shielding layer 6 covering the trench isolation structure 4; the light shielding layer 6 has an opening exposing the pixel area.

[0137] In some examples, the material of the light shielding layer 6 includes but is not limited to metal, for example, the material of the light shielding layer 6 may be aluminum.

[0138] In step S800, please continue to refer to Figure 1 S800 and Fig.16 , a color filter film 7 is formed in the opening; the color filter film 7 covers the top surface of the corresponding pixel unit 5 facing away from the substrate 1.

[0139] In some embodiments, forming a color filter film 7 in the opening includes forming a blue filter layer, a green filter layer and a red filter layer in the opening. According to the arrangement rule of pixel RGB, the color filter films 7 on the top surfaces of adjacent pixel units 5 have different colors.

[0140] Based on the same inventive concept, the present disclosure also provides a semiconductor device, which is obtained by using the preparation methods in some of the above embodiments. Fig.15 The semiconductor device includes a substrate 1 and a plurality of pixel units 5. A trench isolation structure 4 and a plurality of pixel accommodating grooves G2 are provided in the substrate 1. The trench isolation structure 4 is used to define the setting position of the pixel accommodating grooves G2, and the size of the interval between at least two pixel accommodating grooves G2 is different. The plurality of pixel units 5 are respectively located in the corresponding pixel accommodating grooves G2.

[0141] In the embodiments of the present disclosure, the semiconductor device adopts the above structure. The technical effect that can be achieved by the semiconductor device is the same as the technical effect that can be achieved by the method for preparing the semiconductor device in the aforementioned embodiments, and will not be described in detail here.

[0142] In some embodiments, the trench isolation structure 4 includes a first dielectric layer 41 and a second dielectric layer 42 which are stacked; wherein in different regions of the trench isolation structure 4 corresponding to different size intervals, the surface of the first dielectric layer 41 close to the second dielectric layer 42 is located in different planes.

[0143] For example, the material of the first dielectric layer 41 includes silicon boride. The material of the second dielectric layer 42 includes silicon gallium.

[0144] In some embodiments, the pixel unit 5 includes a stacked conductive layer 51 and a receiving layer 52. The surfaces of the conductive layers 51 in different pixel receiving grooves G2 facing away from the substrate 1 are located in the same plane.

[0145] By way of example, the material of the conductive layer 51 includes silicon phosphide, and the material of the receiving layer 52 includes silicon arsenide.

[0146] In some embodiments, the semiconductor device further includes: a light shielding layer 6 and a plurality of color filter films 7. The light shielding layer 6 covers the trench isolation structure 4. The light shielding layer 6 has an opening exposing the pixel unit 5. The plurality of color filter films 7 are respectively formed in the corresponding openings and cover the top surface of the corresponding pixel unit 5 away from the substrate 1.

[0147] In some examples, the material of the light shielding layer 6 includes but is not limited to metal, for example, the material of the light shielding layer 6 may be aluminum.

[0148] In some embodiments, the color filter film 7 includes: a blue filter layer, a green filter layer and a red filter layer. According to the arrangement rule of pixel RGB, the color filter films 7 on the top surfaces of adjacent pixel units 5 have different colors.

[0149] As described above, in the embodiment of the present disclosure, a plurality of spaced sidewalls are first formed on one side of the substrate, and at least two of the spacers are of different sizes; then, based on the sidewall patterning substrate, a groove is formed below the spacer, so that a plurality of grooves of different sizes can be formed in the substrate, and then a groove isolation structure of different sizes that meets the requirements can be formed; finally, a pixel area is defined based on the groove isolation structure, and a pixel unit is formed in the pixel area. The unexpected technical effect is that the embodiment of the present disclosure can form pixel units of different sizes that meet the requirements based on the groove isolation structure of different sizes, so as to prepare a semiconductor device with a plurality of pixel units of different sizes according to the requirements, which is beneficial to the use of semiconductor devices on CMOS back-illuminated image sensors, so that back-illuminated image sensors meet different market requirements.

[0150] In the description of this specification, the technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0151] The above-described embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure shall be subject to the attached claims.

Claims

1. A method for preparing a semiconductor device, characterized in that: include: Providing a substrate, and forming a plurality of sidewalls on one side of the substrate; There is a gap between adjacent side walls, and at least two of the gaps have different sizes; Patterning the substrate based on the sidewalls to form a groove below the spacer; removing the side wall; forming a trench isolation structure in the trench; the trench isolation structure is used to define a pixel area; Removing the portion of the substrate located in the pixel area to form a plurality of pixel accommodating grooves; A pixel unit is formed in the pixel receiving groove.

2. The method for preparing a semiconductor device according to claim 1, wherein: The forming of the trench isolation structure in the trench comprises: stacking and depositing a first dielectric layer and a second dielectric layer in the trench; Wherein, in different regions of the trench isolation structure corresponding to the intervals of different sizes, the surface of the first dielectric layer close to the second dielectric layer is located in different planes.

3. The method for preparing a semiconductor device according to claim 1, wherein: The forming of the pixel unit in the pixel accommodating groove comprises: forming a conductive layer and a receiving layer in the pixel accommodating groove by stacking; Wherein, surfaces of the conductive layers in different pixel receiving grooves facing away from the substrate are located in the same plane.

4. The method for preparing a semiconductor device according to claim 1, wherein: Also includes: forming a light shielding layer covering the trench isolation structure; The light shielding layer has an opening exposing the pixel area; forming a color filter film in the opening; The color filter film covers the top surface of the corresponding pixel unit facing away from the substrate.

5. The method for preparing a semiconductor device according to any one of claims 1 to 4, characterized in that: The step of forming a plurality of sidewalls on one side of the substrate comprises: A plurality of initial spacers are formed on one side of the substrate and are spaced apart from each other; the distance between any two adjacent initial spacers is the same; A portion of the initial sidewall spacers is selectively removed to form the plurality of sidewall spacers.

6. The method for preparing a semiconductor device according to claim 5, characterized in that: The method of forming a plurality of initial spacers distributed at intervals on one side of the substrate comprises: forming a plurality of sacrificial structures distributed at intervals on one side of the substrate; Forming a spacer material layer on one side surface of the substrate, wherein the spacer material layer covers the sidewalls and top surfaces of the plurality of sacrificial structures; removing the spacer material layer on the top surface of the sacrificial structure, so that the spacer material layer remaining on the sidewall of the sacrificial structure serves as the initial spacer; The sacrificial structure is removed.

7. A semiconductor device, characterized in that: include: A substrate, wherein a trench isolation structure and a plurality of pixel accommodating grooves are provided in the substrate; wherein the trench isolation structure is used to define the location of the pixel accommodating grooves, and the spacing between at least two of the pixel accommodating grooves is different in size; A plurality of pixel units are respectively located in the corresponding pixel accommodating grooves.

8. The semiconductor device according to claim 7, wherein: The trench isolation structure comprises a first dielectric layer and a second dielectric layer which are stacked; wherein, in different regions of the trench isolation structure corresponding to the intervals of different sizes, the surface of the first dielectric layer close to the second dielectric layer is located in different planes.

9. The semiconductor device according to claim 7, wherein: The pixel unit includes a conductive layer and a receiving layer which are stacked; Wherein, surfaces of the conductive layers in different pixel receiving grooves facing away from the substrate are located in the same plane.

10. The semiconductor device according to any one of claims 7 to 9, wherein: Also includes: a light shielding layer, covering the trench isolation structure; The light shielding layer has an opening exposing the pixel unit; A plurality of color filter films are respectively formed in the corresponding openings and cover the top surface of the corresponding pixel unit away from the substrate.

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