Preparation method of TOPCON battery
By preparing a doped layer on the back of the silicon wafer substrate of the TOPCON battery and depositing a passivation layer made of intrinsic hydrogenated amorphous silicon material on the back of the first tunneling layer, the tunneling layer diffusion during the high-temperature annealing process is solved. The problem of this has achieved the improvement of battery performance stability and conversion efficiency.
Patent Information
- Application Number
- CN202411454728.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-17
- Publication Date
- 2025-02-07
AI Technical Summary
During the high-temperature annealing process, the first tunnel layer of the TOPCON battery is prone to diffusion, affecting its stability and conversion efficiency.
A doped layer is prepared on the back of the silicon wafer substrate, and a passivation layer made of intrinsic hydrogenated amorphous silicon material is deposited on the back of the first tunneling layer to prevent the tunneling layer material from diffusing.
It effectively prevents the diffusion of the first tunnel layer during the high-temperature annealing process, ensures the overall performance of the battery, and improves the conversion efficiency.
Smart Images
Figure CN119403263A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the technical field of solar cells, and in particular to a method for preparing a TOPCON cell. Background Art
[0002] With the development of photovoltaic technology, TOPCON cells, as a highly efficient solar cell technology, have gradually attracted the attention of the industry. TOPCON cells are a solar cell technology with a first tunneling layer passivation contact based on the principle of selective carriers. They are tunneling oxide passivation contact solar cells with N-type silicon as the substrate. In the manufacturing process of TOPCON cells, the formation of the first tunneling layer usually requires high-temperature annealing to enhance its dielectric properties. However, under high temperature conditions, the first tunneling layer is prone to diffusion, that is, the tunneling layer material may penetrate into the silicon substrate, resulting in changes in the thickness and uniformity of the tunneling layer. This diffusion not only affects the function of the tunneling layer, but may also increase the contact resistance, thereby reducing the overall performance of the battery.
[0003] Therefore, how to improve the stability of the first tunneling layer during high-temperature annealing and thereby improve the conversion efficiency of the TOPCON cell has become one of the key technical problems that need to be urgently solved in this field. Summary of the invention
[0004] The present invention provides a TOPCON battery preparation method, which can prevent the first tunneling layer from expanding during annealing treatment, thereby ensuring the overall stable performance of the battery.
[0005] The embodiments of the present invention can be implemented as follows:
[0006] An embodiment of the present invention provides a method for preparing a TOPCON battery, which comprises:
[0007] preparing a doping layer on the back side of a silicon wafer substrate;
[0008] depositing a first tunneling layer on the back side of the doped layer;
[0009] Depositing a passivation layer on the back side of the first tunneling layer;
[0010] Wherein, in the step of depositing a passivation layer on the back side of the first tunneling layer, the passivation layer is made of intrinsic hydrogenated amorphous silicon material.
[0011] Optionally, the step of depositing a passivation layer on the back side of the first tunneling layer comprises:
[0012] Hydrogen and silane are ionized by an electric field, thereby preparing intrinsic hydrogenated amorphous silicon on the back side of the first tunneling layer.
[0013] Optionally, the step of depositing a passivation layer on the back side of the first tunneling layer further comprises:
[0014] A passivation layer with a thickness of 2nm-10nm is deposited on the back side of the first tunneling layer.
[0015] Optionally, the step of depositing a passivation layer on the back side of the first tunneling layer further comprises:
[0016] A passivation layer is deposited on the back side of the first tunneling layer by using low temperature plasma enhanced chemical vapor deposition technology.
[0017] Optionally, the step of depositing a passivation layer on the back side of the first tunneling layer further comprises:
[0018] The temperature for preparing the passivation layer is 400°C-450°C.
[0019] Optionally, the step of depositing a first tunneling layer on the back side of the doped layer comprises:
[0020] A first tunneling layer is deposited on the back side of the doping layer by using low-temperature plasma enhanced chemical vapor deposition technology or atomic layer deposition technology.
[0021] Optionally, the step of depositing a first tunneling layer on the back side of the doped layer further comprises:
[0022] The thickness of the first tunneling layer is 1 nm-2 nm, and the temperature for preparing the first tunneling layer is 200° C.-400° C.
[0023] Optionally, the step of preparing a doping layer on the back side of the silicon wafer substrate includes:
[0024] A doping layer is formed on the back side of the silicon wafer substrate by phosphorus diffusion or ion implantation, and the thickness of the doping layer is 1.5 nm to 3 nm.
[0025] Optionally, the TOPCON battery preparation method further includes:
[0026] The silicon wafer substrate is cleaned.
[0027] Optionally, the TOPCON battery preparation method further includes:
[0028] The silicon wafer substrate is annealed at a temperature of 900° C.-1100° C. and an oxidation annealing time of 4200s-4600s.
[0029] The beneficial effects of the TOPCON battery preparation method of the embodiment of the present invention include, for example:
[0030] The TOPCON cell preparation method includes preparing a doping layer on the back of a silicon wafer substrate; depositing a first tunneling layer on the back of the doping layer; and depositing a passivation layer on the back of the first tunneling layer; wherein, in the step of depositing the passivation layer on the back of the first tunneling layer, the passivation layer is made of intrinsic hydrogenated amorphous silicon material. In the preparation process, the passivation layer is made of intrinsic hydrogenated amorphous silicon material on the back of the first tunneling layer. The intrinsic hydrogenated amorphous silicon can provide a good surface passivation effect, which can effectively reduce the defect state density on the surface of crystalline silicon, thereby reducing the carrier recombination rate. Moreover, the passivation layer can form a contact layer on the first tunneling layer, and the passivation layer and the first tunneling layer can form a passivation contact structure together, thereby effectively reducing the carrier surface recombination and metal contact recombination. In addition, the intrinsic hydrogenated amorphous silicon is relatively insensitive to temperature changes, and can maintain a good passivation effect at high temperatures, preventing the phenomenon of expansion and penetration of the first tunneling layer due to excessively high temperature during the annealing process, thereby ensuring the overall stability of the battery cell performance. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.
[0032] Figure 1 Flow chart of the TOPCON battery preparation method provided in this embodiment. DETAILED DESCRIPTION
[0033] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.
[0034] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0035] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.
[0036] In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. appear to indicate an orientation or position relationship, they are based on the orientation or position relationship shown in the accompanying drawings, or are the orientation or position relationship in which the product of the invention is usually placed when used. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.
[0037] In addition, the terms “first”, “second”, etc., if used, are merely used to distinguish between the descriptions and should not be understood as indicating or implying relative importance.
[0038] It should be noted that, in the absence of conflict, the features in the embodiments of the present invention may be combined with each other.
[0039] Example
[0040] With the development of photovoltaic technology, TOPCON cells have gradually attracted the attention of the industry as a high-efficiency solar cell technology. TOPCON cells achieve high-efficiency energy conversion by forming an ultra-thin first tunneling oxide layer on the surface of the silicon wafer and depositing a doped polysilicon layer on it. However, in the actual production process, this technology faces many challenges, among which the stability and conversion efficiency of the tunneling layer during the annealing process are particularly prominent. In the manufacturing process of TOPCON cells, the formation of the first tunneling layer usually requires high-temperature annealing to enhance its dielectric properties. However, under high temperature conditions, the first tunneling layer is prone to diffusion, that is, the tunneling layer material may penetrate into the silicon substrate, resulting in changes in the thickness and uniformity of the tunneling layer. This diffusion not only affects the function of the tunneling layer, but may also increase the contact resistance, thereby reducing the overall performance of the battery.
[0041] Due to the expansion problem of the tunneling layer, the actual conversion efficiency of the TOPCON cell may be lower than expected. Conversion efficiency refers to the ratio of solar cells to electrical energy, and is one of the key indicators for measuring the performance of solar cells. The instability and unevenness of the tunneling layer will directly or indirectly affect the transmission efficiency of carriers, and thus affect the photoelectric conversion efficiency of the TOPCON cell. Although a variety of methods have been tried to improve this problem, there are still certain limitations in practical applications, resulting in the average conversion efficiency of TOPCON cells failing to reach the ideal level.
[0042] Therefore, how to improve the stability of the first tunneling layer during high-temperature annealing and thereby improve the conversion efficiency of the TOPCON cell has become one of the key technical problems that need to be urgently solved in this field.
[0043] Please refer to Figure 1 This embodiment provides a TOPCON battery preparation method, which can effectively improve the above-mentioned technical problems, prevent the first tunneling layer from expanding during annealing, and ensure the overall stability of the battery performance.
[0044] The TOPCON battery preparation method comprises:
[0045] S1: Prepare silicon wafer substrate.
[0046] Specifically, a silicon wafer is provided as a substrate, and the substrate includes a front side and a back side.
[0047] S2: Perform texturing and cleaning on the silicon wafer substrate.
[0048] Specifically, the silicon wafer is cleaned to remove surface pollutants and organic matter to ensure the cleanliness of subsequent processes, and then the silicon wafer is textured to form a pyramid texture surface on the surface of the substrate to reduce the reflectivity of the substrate surface to sunlight and increase the substrate's absorption of sunlight, thereby improving the photoelectric conversion efficiency of the battery.
[0049] In this embodiment, the texturing time of the silicon wafer is 425s-450s, and the texturing temperature is 85°C.
[0050] S3: sequentially preparing a second tunneling layer, a polysilicon layer and a second anti-reflection layer on the front side of the silicon wafer substrate.
[0051] Specifically, the laughing gas is ionized into plasma by an electric field and then reacts with silicon, thereby depositing a layer of SiO2 with a thickness of 1.2nm-3nm on the front side of the silicon wafer substrate. 2 The preparation time of the second tunneling layer is 130 s, and the laughing gas flow rate is 9000 sccm.
[0052] In this embodiment, SiO 2 The thickness of the film is 1.8 nm. In other embodiments, SiO 2 The thickness of the film may also be 1.2 nm, 2 nm, 2.3 nm or 3 nm, which is not specifically limited here.
[0053] In this embodiment, the thickness of the polysilicon layer is 90nm-120nm. Specifically, the thickness of the polysilicon layer is 120nm. In other embodiments, the thickness of the polysilicon layer may also be 90nm, 100nm or 110nm, which is not specifically limited here.
[0054] In this embodiment, the second anti-reflection layer is made of silicon nitride, which can reduce the reflectivity of the battery surface to incident light, thereby increasing the open circuit voltage and short circuit current of the battery, thereby increasing the photoelectric conversion efficiency of the battery.
[0055] In this embodiment, the thickness of the second anti-reflection layer is 80nm-82nm. Specifically, the thickness of the second anti-reflection layer is 80nm. In other embodiments, the thickness of the second anti-reflection layer can also be 81nm or 82nm, which is not specifically limited here.
[0056] S4: Prepare an electrode on the front side of the second anti-reflection layer.
[0057] Specifically, a positive electrode is prepared on the front side of the second anti-reflection layer, and the positive electrode is used to obtain electrons for reduction reaction.
[0058] S5: preparing a doping layer on the back side of the silicon wafer substrate.
[0059] Specifically, a doping layer is formed on the back side of the silicon wafer substrate by phosphorus diffusion or ion implantation, and the thickness of the formed doping layer is 1.5 nm-3 nm. In this embodiment, the thickness of the doping layer is 1.5 nm.
[0060] In other embodiments, the thickness of the doping layer may be 1.8 nm, 2 nm, 2.3 nm or 3 nm, which is not specifically limited herein.
[0061] S6: depositing a first tunneling layer on the back side of the doped layer.
[0062] Specifically, a first tunneling layer is deposited on the back of the doped layer using a low-temperature plasma enhanced chemical vapor deposition technique or an atomic layer deposition technique. The laughing gas is ionized into plasma by an electric field and then reacts with silicon, thereby depositing the first tunneling layer on the back of the silicon wafer substrate. The first tunneling layer is prepared as SiO 2 The first tunneling layer is deposited on the back of the substrate silicon wafer, which allows the tunneling of carriers and provides a good surface passivation effect.
[0063] In this embodiment, the thickness of the first tunneling layer is 1nm-2nm, the temperature for preparing the first tunneling layer is 200℃-400℃, and the flow rate of nitrous oxide is 9000sccm. Specifically, the thickness of the first tunneling layer is 2nm, and the preparation temperature is 200℃. In other embodiments, the thickness of the first tunneling layer can also be 1nm, 1.2nm, etc.; the preparation temperature can also be 230℃, 300℃ or 400℃, which are not specifically limited here.
[0064] S7: Depositing a passivation layer on the back side of the first tunneling layer.
[0065] Among them, the passivation layer uses intrinsic hydrogenated amorphous silicon material. In the process of generating the passivation layer, the reaction between silane and hydrogen is the main process. The introduction of hydrogen bonds can well passivate the dangling bonds of the interface and provide sufficient hydrogen (H) to saturate the interface defects, so as to achieve the best chemical passivation effect. In addition, phosphorus will diffuse into the silicon substrate under high temperature environment. The appropriate amount of phosphorus entering the silicon substrate can improve the contact effect of the silicon substrate surface. In the process of phosphorus internal expansion, intrinsic hydrogenated amorphous silicon can act as a buffer layer to prevent the first tunneling layer from expanding due to excessively high annealing temperature.
[0066] Specifically, hydrogen and silane are ionized by an electric field, thereby preparing intrinsic hydrogenated amorphous silicon on the back side of the first tunneling layer.
[0067] In this embodiment, the thickness of the passivation layer is 2nm-10nm. Specifically, the thickness of the passivation layer is 2nm. In other embodiments, the thickness of the passivation layer can also be 3nm, 5nm, 7nm or 10nm, which is not specifically limited here.
[0068] In this embodiment, a passivation layer is deposited on the back of the first tunneling layer by low-temperature plasma enhanced chemical vapor deposition technology; wherein the temperature for preparing the passivation layer is 400°C-450°C. Specifically, the temperature for preparing the passivation layer is 400°C; in other embodiments, the temperature for preparing the passivation layer may also be 420°C, 430°C or 450°C, which is not specifically limited here.
[0069] S8: performing annealing treatment on the silicon wafer substrate after the treatment in step S8, wherein the annealing temperature is 900° C.-1100° C., and the oxidation annealing time is 4200s-4600s.
[0070] Specifically, the silicon wafer substrate is subjected to high temperature annealing treatment to improve the quality of the film and increase the conversion efficiency of the battery.
[0071] S9: preparing a first anti-reflection layer and an electrode on the back side of the passivation layer.
[0072] Specifically, the structure of the first anti-reflection layer is the same as that of the second anti-reflection layer. Screen printing is performed on the first anti-reflection layer to form a negative electrode. The negative electrode is in ohmic contact with the silicon wafer substrate.
[0073] In summary, the embodiment of the present invention provides a TOPCON battery preparation method, which includes preparing a doped layer on the back of a silicon wafer substrate; depositing a first tunneling layer on the back of the doped layer; and depositing a passivation layer on the back of the first tunneling layer; wherein, in the step of depositing the passivation layer on the back of the first tunneling layer, the passivation layer uses an intrinsic hydrogenated amorphous silicon material. During the preparation process, the passivation layer is made of an intrinsic hydrogenated amorphous silicon material on the back of the first tunneling layer. The intrinsic hydrogenated amorphous silicon can provide a good surface passivation effect, which can effectively reduce the defect state density on the surface of crystalline silicon, thereby reducing the carrier recombination rate, and the passivation layer can form a contact layer on the first tunneling layer, and the passivation layer and the first tunneling layer can form a passivation contact structure together, thereby effectively reducing the carrier surface recombination and metal contact recombination. In addition, the intrinsic hydrogenated amorphous silicon is relatively insensitive to temperature changes, and can maintain a good passivation effect at high temperatures, preventing the phenomenon of expansion and penetration of the first tunneling layer due to excessively high temperature during the annealing process, thereby ensuring the overall stability of the battery cell performance.
[0074] Example 1
[0075] This embodiment provides a TOPCON battery, which is prepared by using the TOPCON battery preparation method provided in the above embodiment.
[0076] The TOPCON cell includes a silicon wafer substrate, on the front side of which a second tunneling layer, a polysilicon layer, a second anti-reflection layer and a positive electrode are sequentially stacked, and on the back side of which a doping layer, a first tunneling layer, a passivation layer, a first anti-reflection layer and a negative electrode are sequentially stacked.
[0077] Comparative Example
[0078] The comparative example provides a TOPCON battery. Compared with Example 1, in the structure of the TOPCON battery provided in the comparative example, no passivation layer is provided on the back side of the first tunneling layer.
[0079] Test Case
[0080] The relevant data of the power and photoelectric conversion efficiency of the TOPCON cells obtained in Example 1 and the comparative example were collected respectively, and the results are shown in Table 1.
[0081] Table 1
[0082]
[0083]
[0084] It can be seen from the above results that, relative to the comparative example, the embodiment scheme of the present invention is adopted, and the passivation layer is made of intrinsic hydrogenated amorphous silicon material on the back side of the first tunneling layer. The intrinsic hydrogenated amorphous silicon can provide a good surface passivation effect, and can effectively reduce the defect state density on the surface of crystalline silicon, thereby reducing the carrier recombination rate, and the passivation layer can form a contact layer on the first tunneling layer, and the passivation layer and the first tunneling layer can jointly form a passivation contact structure, thereby effectively reducing the carrier surface recombination and metal contact recombination. In addition, the intrinsic hydrogenated amorphous silicon is relatively insensitive to temperature changes, and can maintain a good passivation effect at high temperatures, thereby preventing the first tunneling layer from expanding due to excessively high temperatures during the annealing process, thereby ensuring the overall stable performance of the battery cell.
[0085] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.
Claims
1. A method for preparing a TOPCON battery, characterized in that: include: preparing a doping layer on the back side of a silicon wafer substrate; depositing a first tunneling layer on the back side of the doped layer; Depositing a passivation layer on the back side of the first tunneling layer; Wherein, in the step of depositing a passivation layer on the back side of the first tunneling layer, the passivation layer is made of intrinsic hydrogenated amorphous silicon material.
2. The method for preparing a TOPCON battery according to claim 1, characterized in that: The step of depositing a passivation layer on the back side of the first tunneling layer comprises: Hydrogen and silane are ionized by an electric field, thereby preparing intrinsic hydrogenated amorphous silicon on the back side of the first tunneling layer.
3. The method for preparing a TOPCON battery according to claim 2, characterized in that: The step of depositing a passivation layer on the back side of the first tunneling layer further comprises: A passivation layer with a thickness of 2nm-10nm is deposited on the back side of the first tunneling layer.
4. The method for preparing a TOPCON battery according to claim 2, characterized in that: The step of depositing a passivation layer on the back side of the first tunneling layer further comprises: A passivation layer is deposited on the back side of the first tunneling layer by using low temperature plasma enhanced chemical vapor deposition technology.
5. The method for preparing a TOPCON battery according to claim 1, characterized in that: The step of depositing a passivation layer on the back side of the first tunneling layer further comprises: The temperature for preparing the passivation layer is 400°C-450°C.
6. The method for preparing a TOPCON battery according to claim 1, characterized in that: The step of depositing a first tunneling layer on the back side of the doped layer comprises: A first tunneling layer is deposited on the back side of the doping layer by using low-temperature plasma enhanced chemical vapor deposition technology or atomic layer deposition technology.
7. The method for preparing a TOPCON battery according to claim 6, characterized in that: The step of depositing a first tunneling layer on the back side of the doped layer further comprises: The thickness of the first tunneling layer is 1 nm-2 nm, and the temperature for preparing the first tunneling layer is 200° C.-400° C.
8. The method for preparing a TOPCON battery according to claim 1, characterized in that: The step of preparing a doping layer on the back side of the silicon wafer substrate comprises: A doping layer is formed on the back side of the silicon wafer substrate by phosphorus diffusion or ion implantation, and the thickness of the doping layer is 1.5 nm to 3 nm.
9. The method for preparing a TOPCON battery according to claim 1, characterized in that: The TOPCON battery preparation method also includes: The silicon wafer substrate is cleaned.
10. The method for preparing a TOPCON battery according to claim 9, characterized in that: The TOPCON battery preparation method also includes: The silicon wafer substrate is annealed at a temperature of 900° C.-1100° C. and an oxidation annealing time of 4200s-4600s.