TOPCon solar cell, preparation method thereof and photovoltaic module
By simplifying the combination of LPCVD and laser transfer technology, the cumbersome problem of TOPCon solar cell preparation process is solved, efficient doping and annealing process is achieved, parasitic absorption of the polysilicon layer is reduced, and the conversion efficiency of the solar cell is improved.
Patent Information
- Application Number
- CN202411550477.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-01
- Publication Date
- 2025-02-07
AI Technical Summary
The preparation process of existing TOPCon solar cells is complicated, especially during double-sided tunneling and thinning of the back polysilicon layer, which leads to an impact on the conversion efficiency.
The tunneling oxide layer and intrinsic amorphous silicon layer were prepared by primary LPCVD, combined with laser transfer technology, and the doped polysilicon layer was formed by primary annealing, and the non-metal was finally removed by laser etching. polysilicon layer in the region.
The preparation process is simplified, the production efficiency is improved, the parasitic absorption of the polysilicon layer is reduced, the conversion efficiency of solar cells is improved, and the high-performance TOPCon solar cells are realized.
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Figure CN119403274A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of solar cells, and in particular to a TOPCon solar cell and a preparation method thereof, and a photovoltaic module. Background Art
[0002] With the rapid development of society, people have put forward higher and higher requirements on the conversion efficiency of solar cells. Tunneling oxide passivated contact cells (TOPCon) have attracted widespread attention due to their many advantages such as high efficiency, low attenuation, and high compatibility with passivated emitter and rear area contact cell (PERC) production lines.
[0003] Currently, improving the efficiency of TOPCon cells has always been one of the research focuses of the industry. One of the approaches is to add a tunneling passivation layer on the front side to achieve double-sided passivation, as well as thinning the polysilicon layer (poly layer) on the back side.
[0004] However, double-sided tunneling usually requires two low-pressure chemical vapor deposition (LPCVD) techniques, and the poly region is achieved through a customized mask or ion implantation technology, resulting in a cumbersome preparation process. Secondly, the thinning of the poly on the back side will bring great challenges to the slurry, because the wet etching process is unstable, and usually there will be inconsistent local poly etching thickness, which affects the battery conversion efficiency.
[0005] It should be noted that the above content is not necessarily prior art, nor is it intended to limit the scope of patent protection of this application. Summary of the invention
[0006] The embodiments of the present application provide a TOPCon solar cell and a method for preparing the same, and a photovoltaic module, aiming to solve the above-mentioned technical problems.
[0007] In a first aspect, an embodiment of the present application provides a method for preparing a TOPCon solar cell, comprising: Providing a silicon wafer, wherein the silicon wafer is an N-type silicon wafer, the front side of the silicon wafer has a front metal region and a front non-metal region, and the back side of the silicon wafer has a back metal region and a back non-metal region; forming a P-type diffusion layer on the front side of the silicon wafer; Using LPCVD, a tunneling oxide layer and an intrinsic amorphous silicon layer are sequentially formed on the P-type diffusion layer and the back side of the silicon wafer; Performing a P-type doping treatment on the intrinsic amorphous silicon layer located in the front metal region, and performing an N-type doping treatment on the intrinsic amorphous silicon layer located in the back metal region; Annealing the silicon wafer that has undergone the P-type doping treatment and the N-type doping treatment, so that the intrinsic amorphous silicon layer located in the front metal region is converted into a P-type doped polysilicon layer, the intrinsic amorphous silicon layer located in the back metal region is converted into an N-type doped polysilicon layer, and the intrinsic amorphous silicon layer located in the front non-metallic region and the back non-metallic region is converted into an intrinsic polysilicon layer; The intrinsic polysilicon layer is removed.
[0008] Optionally, performing a P-type doping process on the intrinsic amorphous silicon layer located in the front metal region includes: Using a first laser transfer technology, printing a slurry containing a P-type doping element on the surface of the intrinsic amorphous silicon layer located in the front metal area, and drying the slurry; The N-type doping treatment of the intrinsic amorphous silicon layer located in the back metal region includes: The second laser transfer technology is used to print a slurry containing an N-type doping element on the surface of the intrinsic amorphous silicon layer located in the back metal region, and then the slurry is dried.
[0009] Optionally, in the first laser transfer technology, the laser power is 20-100 W, the drying temperature is 280-320° C., and the drying time is 2-3 min; and / or In the second laser transfer technology, the laser power is 20-100 W, the drying temperature is 280-320° C., and the drying time is 2-3 min.
[0010] Optionally, the P-type doping element includes one or more of boron, aluminum, and gallium, and the N-type doping element includes one or more of phosphorus, arsenic, and antimony.
[0011] Optionally, in the annealing treatment, the annealing temperature is 700-850° C., and the annealing time is 30-120 min.
[0012] Optionally, removing the intrinsic polysilicon layer includes: Using laser etching to remove the intrinsic polysilicon layer located in the front non-metallic area and the back non-metallic area; In the laser etching, the laser wavelength is 490-575nm, and the laser power is 10-50W.
[0013] Optionally, after removing the intrinsic polysilicon layer, the method further comprises: Depositing a passivation layer and an anti-reflection layer on the front side and the back side of the silicon wafer in sequence; forming a first electrode, wherein the first electrode penetrates the anti-reflection layer and the passivation layer on the front side of the silicon wafer and contacts the P-type doped polysilicon layer; A second electrode is formed, wherein the second electrode penetrates the anti-reflection layer and the passivation layer on the back side of the silicon wafer and contacts the N-type doped polysilicon layer.
[0014] In a second aspect, an embodiment of the present application provides a TOPCon solar cell, which is formed by the preparation method of a TOPCon solar cell described in any one of the above embodiments, and the TOPCon solar cell includes: A silicon wafer, wherein the silicon wafer is an N-type silicon wafer, the front side of the silicon wafer has a front metal region and a front non-metal region, and the back side of the silicon wafer has a back metal region and a back non-metal region; A P-type diffusion layer, a tunneling oxide layer and a P-type doped polysilicon layer are located on the front side of the silicon wafer and are stacked in sequence in a direction away from the silicon wafer; wherein the P-type doped polysilicon layer is only located in the front metal region; A tunneling oxide layer and an N-type doped polysilicon layer are located on the back side of the silicon wafer and are stacked in sequence in a direction away from the silicon wafer; wherein the N-type doped polysilicon layer is only located in the back metal region.
[0015] Optionally, the TOPCon solar cell also includes: A passivation layer and an anti-reflection layer located on the front side and the back side of the silicon wafer and stacked in sequence in a direction away from the silicon wafer; A first electrode located on the front side of the silicon wafer, the first electrode penetrates the anti-reflection layer and the passivation layer and contacts the P-type doped polysilicon layer; A second electrode is located on the back side of the silicon wafer, wherein the second electrode penetrates the anti-reflection layer and the passivation layer and contacts the N-type doped polysilicon layer.
[0016] In a third aspect, an embodiment of the present application provides a photovoltaic module, comprising the TOPCon solar cell described in any one of the above embodiments.
[0017] The preparation method of the TOPCon solar cell provided in the embodiment of the present application only requires one LPCVD to prepare the tunnel oxide layer and the intrinsic amorphous silicon layer, avoiding the two depositions required by the traditional technology and the two de-plating problems caused by the wet method, thereby simplifying the preparation process and effectively improving the production efficiency; subsequently, when forming the P-type doped polysilicon layer and the N-type doped polysilicon layer, only one annealing treatment is required, which is beneficial to saving production costs; finally, the polysilicon in the front non-metallic area and the back non-metallic area is removed, thereby effectively reducing the parasitic absorption of the polysilicon layer, increasing the current, and realizing high-performance solar cells. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in the present application and should not be regarded as limiting the scope of the present application.
[0019] Figure 1 is a flow chart of a method for preparing a TOPCon solar cell provided in an embodiment of the present application; Figure 2 is a schematic diagram of a product after a tunnel oxide layer and an intrinsic amorphous silicon layer are formed in an embodiment of the present application; Figure 3 This is a schematic diagram of the product after printing the slurry in the embodiment of the present application; Figure 4 This is a schematic diagram of a product after doping treatment in an embodiment of the present application; Figure 5 This is a schematic diagram of a product after silicon wafer texturing in an embodiment of the present application; Figure 6 is a schematic diagram of a product after a P-type diffusion layer is formed in an embodiment of the present application; Figure 7 is a schematic diagram of a product after the borosilicate glass layer on the surface of the silicon wafer is removed in an embodiment of the present application; Figure 8 is a schematic diagram of a product after a passivation layer and an anti-reflection layer are formed in an embodiment of the present application; Fig. 9 It is a schematic diagram of the structure of the TOPCon solar cell provided in the embodiment of the present application.
[0020] Description of reference numerals: 10. Silicon wafer; 20. Borosilicate glass layer; 30. P-type diffusion layer; 40. Tunneling oxide layer; 50. Intrinsic amorphous silicon layer; 60. Slurry containing P-type doping elements; 70. P-type doped polysilicon layer; 80. Slurry containing N-type doping elements; 90. N-type doped polysilicon layer; 100. Passivation layer; 110. Anti-reflection layer; 120. First electrode; 130. Second electrode. DETAILED DESCRIPTION
[0021] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings. In the accompanying drawings, for clarity, the sizes of layers, regions, elements and their relative sizes may be exaggerated. Wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limitations on the present application. It should be noted that, in the absence of conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.
[0022] It should be understood that when an element or layer is referred to as "on", "under", "adjacent to", "connected to" or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "under", "directly adjacent to", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part. When a second element, component, region, layer or section is discussed, it does not necessarily mean that the first element, component, region, layer or section must be present in the present disclosure.
[0023] In this application, unless otherwise clearly specified and limited, the terms "set", "install", "connect", "connect", "fix" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral one; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0024] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein, for example. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.
[0025] The technical solution of the present application provides a TOPCon solar cell and a preparation method thereof, and a photovoltaic module. The preparation method of the TOPCon solar cell only requires one LPCVD to prepare the tunnel oxide layer and the intrinsic amorphous silicon layer, avoiding the problem of two de-plating caused by two depositions, thereby simplifying the preparation process, thereby effectively improving production efficiency; subsequently, when forming the P-type doped polysilicon layer and the N-type doped polysilicon layer, only one annealing treatment is required, which is conducive to saving production costs; finally, the polysilicon in the front non-metallic area and the back non-metallic area is removed, thereby effectively reducing the parasitic absorption of the polysilicon layer, increasing the current, and realizing a high-performance solar cell.
[0026] Hereinafter, exemplary embodiments according to the present application will be described in more detail with reference to the accompanying drawings. It should be noted that these exemplary embodiments can be implemented in many different forms and should not be construed as being limited to the embodiments described herein.
[0027] like Figures 1 to 9 As shown, the embodiment of the present application provides a method for preparing a TOPCon solar cell, comprising: S01: providing a silicon wafer 10, wherein the silicon wafer 10 is an N-type silicon wafer, the front side of the silicon wafer 10 has a front side metal region and a front side non-metal region, and the back side of the silicon wafer 10 has a back side metal region and a back side non-metal region; S02: forming a P-type diffusion layer 30 on the front side of the silicon wafer 10; S03: using LPCVD to sequentially form a tunnel oxide layer 40 and an intrinsic amorphous silicon layer 50 on the P-type diffusion layer 30 and the back side of the silicon wafer 10; S04: performing a P-type doping treatment on the intrinsic amorphous silicon layer 50 located in the front metal region, and performing an N-type doping treatment on the intrinsic amorphous silicon layer 50 located in the back metal region; S05: performing annealing on the silicon wafer 10 that has undergone the P-type doping treatment and the N-type doping treatment, so that the intrinsic amorphous silicon layer 50 located in the front metal region is converted into a P-type doped polysilicon layer 70, the intrinsic amorphous silicon layer 50 located in the back metal region is converted into an N-type doped polysilicon layer 90, and the intrinsic amorphous silicon layer 50 located in the front non-metal region and the back non-metal region is converted into an intrinsic polysilicon layer; S06: removing the intrinsic polysilicon layer.
[0028] In some embodiments, the thickness of the tunneling oxide layer 40 is 1-2 nm. If the thickness of the tunneling oxide layer 40 is too thick, it will greatly affect the contact resistance of the battery and affect the efficiency. By setting a thinner tunneling oxide layer 40, a low contact effect can be achieved while ensuring an excellent passivation effect. Exemplarily, the thickness of the tunneling oxide layer 40 can be 1 nm, 1.5 nm, 2 nm, etc.
[0029] In some embodiments, when the tunnel oxide layer 40 is deposited, the deposition temperature is 600-630°C. If the deposition temperature is too high, the tunnel oxide layer will be thicker, which will greatly affect the contact resistance of the battery. If the deposition temperature is too low, the tunnel oxide layer will be thinner and cannot achieve a good passivation effect. For example, the deposition temperature when depositing the tunnel oxide layer 40 can be 600°C, 610°C, 620°C, 630°C, etc. In some embodiments, when the tunnel oxide layer 40 is deposited, the deposition time is 5-25 minutes. For example, the deposition time can be 5 minutes, 15 minutes, and 25 minutes to prepare a tunnel oxide layer 40 with a suitable thickness. In some embodiments, when depositing the tunnel oxide layer 40, the oxygen flow rate is 10000-40000sccm. Too large an oxygen flow rate will result in a thicker tunnel oxide layer, which will greatly affect the contact resistance of the battery. Too small an oxygen flow rate will result in a thinner tunnel oxide layer, and a good passivation effect cannot be achieved. By way of example, the oxygen flow rate can be 10000sccm, 20000sccm, 30000sccm, 40000sccm, and so on.
[0030] In some embodiments, the thickness of the intrinsic amorphous silicon layer 50 is 30-120nm. If the thickness of the intrinsic amorphous silicon layer 50 is too thick, the deposition time of the intrinsic amorphous silicon will be wasted, the process time will be increased, and the cost investment will be increased; if the thickness of the intrinsic amorphous silicon layer 50 is too thin, the passivation effect of the doped polysilicon formed subsequently cannot be achieved, and the corrosion of the electrode slurry (the slurry containing the P-type doping element or the slurry containing the N-type doping element) cannot be blocked. By setting the thickness of the intrinsic amorphous silicon layer 50 in a suitable range, a better passivation effect can be achieved, and the cost investment can be reduced, and the corrosion of the electrode slurry can be well blocked. Exemplarily, the thickness of the intrinsic amorphous silicon layer 50 can be 30nm, 75nm, 120nm, etc.
[0031] In some embodiments, when the intrinsic amorphous silicon layer 50 is deposited, the deposition temperature is 550-600°C. For example, the deposition temperature when the intrinsic amorphous silicon layer 50 is deposited can be 550°C, 560°C, 570°C, 580°C, 590°C, and 600°C. In some embodiments, when the intrinsic amorphous silicon layer 50 is deposited, the deposition time is 10-40 minutes. For example, the deposition time can be 10 minutes, 20 minutes, 30 minutes, 40 minutes, etc., so as to prepare the intrinsic amorphous silicon layer 50 with a suitable thickness. In some embodiments, when the intrinsic amorphous silicon layer 50 is deposited, the silane flow rate is 500-1000 sccm. If the silane flow rate is too large, the deposited amorphous silicon will be thicker. If the silane flow rate is too small, the deposited amorphous silicon will be thinner. By controlling the silane flow rate in a suitable range, amorphous silicon with a moderate thickness can be deposited. For example, the silane flow rate can be 500 sccm, 750 sccm, 1000 sccm, etc.
[0032] In some embodiments, the P-type doping treatment of the intrinsic amorphous silicon layer located in the front metal area includes: using a first laser transfer technology to print a slurry containing P-type doping elements on the surface of the intrinsic amorphous silicon layer located in the front metal area, and drying it.
[0033] In some embodiments, the N-type doping treatment of the intrinsic amorphous silicon layer located in the back metal area includes: using a second laser transfer technology to print a slurry containing N-type doping elements on the surface of the intrinsic amorphous silicon layer located in the back metal area, and drying it.
[0034] In some embodiments, the P-type doping element includes one or more of boron, aluminum, and gallium, and the N-type doping element includes one or more of phosphorus, arsenic, and antimony.
[0035] In some embodiments, whether it is printing of a slurry containing a P-type doping element or printing of a slurry containing an N-type doping element, laser transfer technology is used to realize the printing of the slurry. Laser transfer uses a hard transparent carrier, and the carrier groove pattern is a hollow equidistantly distributed grid line shape. The doping slurry is filled into the groove by a scraper or a scraper, and then the laser is used to scan and process it upside down. The back of the silicon wafer 10 sample is facing up, and the organic components in the slurry in the carrier groove are heated and volatilized due to the high-energy laser, resulting in a large recoil pressure in the carrier groove, which impacts the slurry, so that the slurry containing the P-type doping element is desorbed from the groove and deposited on the front metal area, and the slurry containing the N-type doping element is desorbed from the groove and deposited on the back metal area. The use of laser for doping treatment is not only efficient, but also has high printing accuracy.
[0036] In some embodiments, the light sources used in the first laser transfer technology and the second laser transfer technology are both green light sources, and the laser powers are respectively and independently 20-100W. For example, the laser powers can be respectively and independently 20W, 60W, 100W, etc.; the printing widths of the slurry 60 containing P-type doping elements and the slurry 80 containing N-type doping elements are respectively and independently 200-500μm. If the printing width of the slurry is too large, the doped polysilicon area formed subsequently will become larger, the shading phenomenon will be aggravated, and the parasitic absorption of the polysilicon will also become larger. , affecting the battery efficiency; if the printing width of the paste is too small, the passivation contact effect of the metal area cannot be achieved; by controlling the printing width of the paste 60 containing P-type doping elements and the paste 80 containing N-type doping elements within a suitable range, the polysilicon shading phenomenon and parasitic absorption phenomenon can be minimized, and the passivation contact effect of the metal area can be achieved. By way of example, the printing width of the paste 60 containing P-type doping elements or the paste 80 containing N-type doping elements can be respectively and independently 200μm, 300μm, 400μm, 500μm, etc.
[0037] In some embodiments, after printing the slurry, the slurry needs to be dried. For the slurry 60 containing P-type doping elements and the slurry 80 containing N-type doping elements, the drying temperatures are respectively and independently 280-320°C, and the drying times are respectively and independently 2-3 minutes. Exemplarily, the drying temperatures of the slurry 60 containing P-type doping elements or the slurry 80 containing N-type doping elements are respectively and independently 280°C, 300°C, 320°C, etc., and the drying times of the slurry 60 containing P-type doping elements or the slurry 80 containing N-type doping elements are respectively and independently 2 minutes, 2.5 minutes, 3 minutes, etc.
[0038] In some embodiments, after the slurry is dried, it is necessary to put it into a high-temperature furnace for annealing to convert amorphous silicon into polysilicon, so as to realize a P-type doped polysilicon layer located in the front metal region and an N-type doped polysilicon layer located in the back metal region. The annealing temperature is 700-850°C. If the annealing temperature is too high, the doping elements will pass through the polysilicon layer and the tunneling oxide layer to reach the substrate, and the Auger recombination will be aggravated; if the annealing temperature is too low, the passivation contact effect of the doped polysilicon will not be maximized. For example, the annealing temperature can be 700°C, 750°C, 800°C, 850°C, etc.; the annealing time is 30-120min. If the annealing time is too short, the passivation contact effect of the doped polysilicon will not be maximized. If the annealing time is too long, the doped atoms will pass through the polysilicon layer and the tunneling oxide layer to reach the substrate, and the Auger recombination will be aggravated. For example, the annealing time can be 30min, 75min, 120min, etc.
[0039] It should be noted that during the annealing process, the intrinsic amorphous silicon layer 50 located in the front non-metallic region and the back non-metallic region is transformed into an intrinsic polycrystalline silicon layer.
[0040] In some embodiments, laser etching is used to remove the intrinsic polysilicon layer located in the front non-metallic region and the back non-metallic region, and laser damage and the source slurry layer can also be removed by wet method.
[0041] Specifically, the laser wavelength used for laser etching is 490-575nm. Exemplarily, the laser wavelength can be 490nm, 532nm, and 575nm; the laser shape is a square spot with an overlap rate of 50%, and the laser power is 10-50W. Exemplarily, the laser power can be 10W, 30W, 50W, and so on.
[0042] In some embodiments, after removing the intrinsic polysilicon layer located in the front non-metallic region and the back non-metallic region, the tunnel oxide layer located in the front non-metallic region and the back non-metallic region may also be removed, thereby further reducing the parasitic absorption phenomenon and improving the battery efficiency.
[0043] In some embodiments, when obtaining the silicon wafer 10, the silicon wafer 10 needs to be textured. The silicon wafer 10 is used to receive incident light and generate carriers. By way of example, in some embodiments, the material of the silicon wafer 10 can be a doped single crystal silicon material. Further, the doping elements of the silicon wafer 10 can be an N-type silicon wafer, wherein the doping elements can include any one or more of phosphorus (P), arsenic (As), bismuth (Bi) and antimony (Sb) in group V elements.
[0044] Exemplarily, an N-type silicon wafer is placed in a cleaning machine for alkaline polishing and texturing, so as to remove metal ions, oil stains and other impurities on the surface and give the surface of the silicon wafer 10 a suede effect.
[0045] It should also be noted that, in some embodiments, the P-type diffusion layer 30 forms a PN junction with the silicon wafer 10. Specifically, the diffusion temperature is 900-1100°C. If the diffusion temperature is too high, the composite of the front non-metallic area will be aggravated and the opening voltage will be reduced. If the diffusion temperature is too low, the PN junction depth will be shallow, affecting the sintering of the electrode slurry. Exemplarily, the diffusion temperature can be 900°C, 1000°C, 1100°C, etc. Among them, the P-type diffusion layer 30 can be a boron diffusion layer.
[0046] In some embodiments, when the P-type diffusion layer 30 is a boron diffusion layer, the back side of the silicon wafer 10 needs to be alkali polished, and the borosilicate glass layer 20 on the front side of the silicon wafer 10 needs to be removed. Specifically, the borosilicate glass layer 20 (BSG) on the back side of the edge is removed by using a chain cleaning machine (the front side has BSG as a mask layer, and the back side is alkali polished, that is, the velvet surface on the back side is polished off), and finally the BSG layer on the front side is removed by using a chain cleaning machine.
[0047] In some embodiments, after removing the intrinsic amorphous silicon layer 50 located in the front non-metallic region and the back non-metallic region, the method for preparing a TOPCon solar cell further includes: S07: depositing a passivation layer 100 and an anti-reflection layer 110 in sequence on the front side of the silicon wafer 10 and the back side of the silicon wafer 10 .
[0048] In step S07, the thickness of the passivation layer is 3-5 nm, and the thickness of the anti-reflection layer 110 is 70-90 nm. Exemplarily, the thickness of the passivation layer can be 3 nm, 4 nm, 5 nm, etc., and the thickness of the anti-reflection layer 110 can be 70 nm, 80 nm, 90 nm, etc.
[0049] The material of the passivation layer may include aluminum oxide. The material of the anti-reflection layer may include silicon nitride. Providing the passivation layer and the anti-reflection layer may further increase the passivation effect.
[0050] S08: forming a first electrode 120, wherein the first electrode 120 penetrates the anti-reflection layer 110 and the passivation layer 100 on the front side of the silicon wafer 10 and contacts the P-type doped polysilicon layer 70; A second electrode 130 is formed. The second electrode 130 penetrates the anti-reflection layer 110 and the passivation layer 100 on the back side of the silicon wafer 10 and contacts the N-type doped polysilicon layer 90 .
[0051] The preparation method of the TOPCon solar cell provided in the embodiment of the present application only requires one LPCVD to prepare the tunnel oxide layer and the intrinsic amorphous silicon layer, avoiding the two depositions required by the traditional technology and the two de-plating problems caused by the wet method, thereby simplifying the preparation process and effectively improving the production efficiency; then, laser transfer is used to achieve boron and phosphorus doping of the polysilicon layer in the front and back metal regions, and only one annealing is required, which is beneficial to saving production costs; finally, laser etching is used to remove the polysilicon in the undoped areas of the front and back non-metallic regions, thereby effectively reducing the parasitic absorption of the polysilicon layer, increasing the current, and realizing high-performance solar cells.
[0052] The present application also provides a TOPCon solar cell, including: A silicon wafer 10, wherein the silicon wafer 10 is an N-type silicon wafer 10, wherein the front side of the silicon wafer 10 has a front metal region and a front non-metal region, and the back side of the silicon wafer 10 has a back metal region and a back non-metal region; A P-type diffusion layer 30, a tunneling oxide layer 40 and a P-type doped polysilicon layer 70 are located on the front side of the silicon wafer 10 and are stacked in sequence in a direction away from the silicon wafer 10; wherein the P-type doped polysilicon layer 70 is located in the front metal region; A tunneling oxide layer 40 and an N-type doped polysilicon layer 90 are located on the back side of the silicon wafer 10 and are sequentially stacked in a direction away from the silicon wafer 10; wherein the N-type doped polysilicon layer 90 is located in the back metal region.
[0053] In some embodiments, the TOPCon solar cell is characterized in that it further comprises: A passivation layer 100 and an anti-reflection layer 110 located on the front side of the silicon wafer 10 and on the back side of the silicon wafer 10 and stacked in sequence in a direction away from the silicon wafer 10; A first electrode 120 located on the front side of the silicon wafer 10 , wherein the first electrode 120 penetrates the anti-reflection layer 110 and the passivation layer 100 and contacts the P-type doped polysilicon layer 70 ; The second electrode 130 is located on the back side of the silicon wafer 10 . The second electrode 130 penetrates the anti-reflection layer 110 and the passivation layer 100 and contacts the N-type doped polysilicon layer 90 .
[0054] In some embodiments, the P-type diffusion layer 30 is a boron diffusion layer, wherein the boron doping concentration of the boron diffusion layer is 3-7E18 cm -3 If the boron doping concentration is too high, the recombination of the front non-metallic area will be aggravated, affecting the efficiency; if the boron doping concentration is too low, the reverse saturation current will increase, the leakage will increase, and the efficiency will be affected. For example, the boron doping concentration can be 3E18cm -3 、5E18cm -3 、7E18cm -3 etc.
[0055] In some embodiments, the P-type doped polysilicon layer 70 is a boron-doped polysilicon layer, and the boron doping concentration of the boron-doped polysilicon layer is 3-7E19 cm -3 If the boron doping concentration is too high, the passivation effect of P-type doped polysilicon will be poor (surface recombination will be aggravated); if the boron doping concentration is too low, the passivation effect will not be optimal, and the contact resistance of the battery will be increased, affecting the efficiency. For example, the boron doping concentration can be 3E19cm -3 、5E19cm -3 、7E19cm -3 etc.
[0056] In some embodiments, the N-type doped polysilicon layer 90 is a phosphorus-doped polysilicon layer, and the phosphorus doping concentration of the phosphorus-doped polysilicon layer is 1-5E20cm -3 If the phosphorus doping concentration is too high, the passivation effect of N-type doped polysilicon will be poor (surface recombination will be aggravated); if the phosphorus doping concentration is too low, the passivation effect will not be optimal, and the contact resistance of the battery will be increased, affecting the efficiency. For example, the doping concentration can be 1E20cm -3 、3E20cm -3 、5E20cm -3 etc.
[0057] The following specific examples further illustrate the present application, but should not be construed as limiting the present application. Without departing from the spirit and substance of the present application, modifications or replacements made to the methods, steps or conditions of the present application are within the scope of the present application.
[0058] [Example 1] Step 1: N-type silicon wafers are alkaline polished and texturized in a cleaning machine.
[0059] Step 2: Place the silicon wafer into a diffusion furnace for boron diffusion on the front side to form a PN junction. The diffusion temperature is 900°C. The boron doping concentration of the obtained boron doped layer is 3E18cm -3 .
[0060] The third step: Use a chain cleaning machine to remove the BSG on the back of the edge, use BSG on the front as a mask layer to perform alkali polishing on the back, and finally use a chain to remove the BSG on the front.
[0061] Step 4: Use LPCVD to deposit a SiO2 tunneling oxide layer and an intrinsic amorphous silicon layer on both sides of the silicon wafer; the deposition temperature of the tunneling oxide layer is 600°C, the deposition time of the tunneling oxide layer is 5 minutes, and the required oxygen flow rate is 10000 sccm; the deposition temperature of the intrinsic amorphous silicon layer is 550°C, the deposition time of the intrinsic amorphous silicon layer is 10 minutes, and the required silane flow rate is 500 sccm.
[0062] Step 5: Use laser transfer technology to print boron source slurry on the front metal area, with a drying time of 2 minutes and a drying temperature of 300°C; print phosphorus source slurry on the back metal area, with a drying time of 2 minutes and a drying temperature of 300°C. The laser power is 20W, and the printing width of both the boron source slurry and the phosphorus source slurry is 200μm; then put it into a high-temperature furnace for annealing, with an annealing time of 30 minutes and an annealing temperature of 700 minutes. The atmosphere is a mixed gas of oxygen and nitrogen. The intrinsic amorphous silicon layer in the front metal area is converted into a boron-doped polycrystalline silicon layer, and the intrinsic amorphous silicon layer in the back metal area is converted into a phosphorus-doped polycrystalline silicon layer. At the same time, the intrinsic amorphous silicon layers in the front non-metallic area and the back non-metallic area are converted into intrinsic polycrystalline silicon layers. The boron doping concentration of the boron-doped polycrystalline silicon layer is 3E19cm -3 The phosphorus doping concentration of the phosphorus-doped polysilicon layer is 1E20cm -3 .
[0063] Step 6: Use laser etching technology to remove the intrinsic polysilicon layer and tunnel oxide layer in the front non-metallic area and the back non-metallic area, and then wet remove the laser damage and the source slurry layer. The laser wavelength is 490nm and the laser power is 10W.
[0064] Step 7: Use ALD (atomic layer deposition) to deposit aluminum oxide on the front and back sides to form a passivation layer; then use PECVD (plasma enhanced chemical vapor deposition) to form an anti-reflection layer on the front and back sides.
[0065] Step 8: Form a first electrode and a second electrode on the front and back sides respectively.
[0066] [Example 2] Step 1: N-type silicon wafers are alkaline polished and texturized in a cleaning machine.
[0067] Step 2: Place the silicon wafer into a diffusion furnace for boron diffusion on the front side to form a PN junction. The diffusion temperature is 1000°C, and the boron doping concentration of the obtained boron doped layer is 5E18cm -3 .
[0068] The third step: Use a chain cleaning machine to remove the BSG on the back of the edge, use BSG on the front as a mask layer to perform alkali polishing on the back, and finally use a chain to remove the BSG on the front.
[0069] Step 4: Use LPCVD to deposit a SiO2 tunneling oxide layer and an intrinsic amorphous silicon layer on both sides of the silicon wafer; the deposition temperature of the tunneling oxide layer is 615°C, the deposition time of the tunneling oxide layer is 15 minutes, and the required oxygen flow rate is 25000sccm; the deposition temperature of the intrinsic amorphous silicon layer is 575°C, the deposition time of the intrinsic amorphous silicon layer is 25 minutes, and the required silane flow rate is 750sccm.
[0070] Step 5: Use laser transfer technology to print boron source paste on the front metal area, with a drying time of 2.5 minutes and a drying temperature of 300°C; print phosphorus source paste on the back metal area, with a drying time of 2.5 minutes and a drying temperature of 300°C. The laser power is 60W, and the printing width of both the boron source paste and the phosphorus source paste is 350μm; then put it into a high-temperature furnace for annealing, with an annealing time of 75 minutes and an annealing temperature of 775 minutes. The atmosphere is a mixed gas of oxygen and nitrogen. The intrinsic amorphous silicon layer in the front metal area is converted into a boron-doped polycrystalline silicon layer, and the intrinsic amorphous silicon layer in the back metal area is converted into a phosphorus-doped polycrystalline silicon layer. At the same time, the intrinsic amorphous silicon layers in the front non-metallic area and the back non-metallic area are converted into intrinsic polycrystalline silicon layers. The boron doping concentration of the boron-doped polycrystalline silicon layer is 5E19cm -3 The phosphorus doping concentration of the phosphorus-doped polysilicon layer is 3E20cm -3 .
[0071] Step 6: Use laser etching technology to remove the intrinsic polysilicon layer and tunnel oxide layer in the front non-metallic area and the back non-metallic area, and then wet remove the laser damage and the source slurry layer. The laser wavelength is 532nm and the laser power is 30W.
[0072] Step 7: Use ALD to deposit aluminum oxide on the front and back sides to form a passivation layer; then use PECVD to form an anti-reflection layer on the front and back sides.
[0073] Step 8: Form a first electrode and a second electrode on the front and back sides respectively.
[0074] [Example 3] Step 1: N-type silicon wafers are alkaline polished and texturized in a cleaning machine.
[0075] Step 2: Place the silicon wafer into a diffusion furnace for boron diffusion on the front side to form a PN junction. The diffusion temperature is 1100°C, and the boron doping concentration of the obtained boron doped layer is E18cm -3 .
[0076] The third step: Use a chain cleaning machine to remove the BSG on the back of the edge, use BSG on the front as a mask layer to perform alkali polishing on the back, and finally use a chain to remove the BSG on the front.
[0077] Step 4: Use LPCVD to deposit a SiO2 tunneling oxide layer and an intrinsic amorphous silicon layer on both sides of the silicon wafer; the deposition temperature of the tunneling oxide layer is 630°C, the deposition time of the tunneling oxide layer is 25 minutes, and the required oxygen flow rate is 40,000 sccm; the deposition temperature of the intrinsic amorphous silicon layer is 600°C, the deposition time of the intrinsic amorphous silicon layer is 40 minutes, and the required silane flow rate is 1000 sccm.
[0078] Step 5: Use laser transfer technology to print boron source slurry on the front metal area, with a drying time of 3 minutes and a drying temperature of 300°C; print phosphorus source slurry on the back metal area, with a drying time of 3 minutes and a drying temperature of 300°C. The laser power is 100W, and the printing width of both the boron source slurry and the phosphorus source slurry is 500μm; then put it into a high-temperature furnace for annealing, with an annealing time of 120 minutes and an annealing temperature of 850 minutes. The atmosphere is a mixed gas of oxygen and nitrogen. The intrinsic amorphous silicon layer in the front metal area is converted into a boron-doped polycrystalline silicon layer, and the intrinsic amorphous silicon layer in the back metal area is converted into a phosphorus-doped polycrystalline silicon layer. At the same time, the intrinsic amorphous silicon layers in the front non-metallic area and the back non-metallic area are converted into intrinsic polycrystalline silicon layers. The boron doping concentration of the boron-doped polycrystalline silicon layer is 7E19cm -3 The phosphorus doping concentration of the phosphorus-doped polysilicon layer is 5E20cm -3 .
[0079] Step 6: Use laser etching technology to remove the intrinsic polysilicon layer and tunnel oxide layer in the front non-metallic area and the back non-metallic area, and then wet remove the laser damage and the source slurry layer. The laser wavelength is 575nm and the laser power is 50W.
[0080] Step 7: Use ALD to deposit aluminum oxide on the front and back sides to form a passivation layer; then use PECVD to form an anti-reflection layer on the front and back sides.
[0081] Step 8: Form a first electrode and a second electrode on the front and back sides respectively.
[0082] In order to more clearly illustrate the technical effects of the embodiments of the present application, the present application also points out the structure and preparation method of the TOPCon solar cell of [Comparative Example 1].
[0083] [Comparative Example 1] The TOPCon solar cell of Comparative Example 1 was prepared by referring to the preparation method of Example 1, except that, in Comparative Example 1, The fourth step is to deposit a SiO2 tunneling oxide layer and an intrinsic amorphous silicon layer on the front of the silicon wafer by LPCVD; the deposition temperature of the tunneling oxide layer is 600°C, the deposition time of the tunneling oxide layer is 5 minutes, and the required oxygen flow rate is 10000 sccm; the deposition temperature of the intrinsic amorphous silicon layer is 550°C, the deposition time of the intrinsic amorphous silicon layer is 10 minutes, and the required silane flow rate is 500 sccm; The intrinsic amorphous silicon layer on the front side of the silicon wafer is doped with boron to form a P-type doped polysilicon layer; The fifth step is to deposit a SiO2 tunneling oxide layer and an intrinsic amorphous silicon layer on the back of the silicon wafer by LPCVD; the deposition temperature of the tunneling oxide layer is 600°C, the deposition time of the tunneling oxide layer is 5 minutes, and the required oxygen flow rate is 10000 sccm; the deposition temperature of the intrinsic amorphous silicon layer is 550°C, the deposition time of the intrinsic amorphous silicon layer is 10 minutes, and the required silane flow rate is 500 sccm; The intrinsic amorphous silicon layer on the back of the silicon wafer is doped with phosphorus to form an N-type doped polysilicon layer; And Comparative Example 1 does not have the sixth step.
[0084] The following is a performance test of the TOPCon solar cells provided in Examples 1-3 of the present application and Comparative Example 1, thereby obtaining the open circuit voltage Voc, short circuit current density Jsc, fill factor FF, and photoelectric conversion efficiency PCE of the corresponding TOPCon solar cells. The test results are shown in Table 1 below: Table 1
[0085] Data result analysis: According to Table 1, compared with Comparative Example 1, the open circuit voltage, fill factor and photoelectric conversion efficiency of the TOPCon solar cells obtained by the preparation method of Examples 1-3 of the present application are significantly improved, which shows that the preparation process of the TOPCon solar cells of Examples 1-3 of the present application can simplify the process and improve production efficiency while also effectively reducing the parasitic absorption of the polysilicon layer and improving device performance, thereby realizing high-performance solar cells.
[0086] To summarize, the embodiment of the present application adopts the above-mentioned technical solution, and only one LPCVD is required to prepare the tunnel oxide layer and the intrinsic amorphous silicon layer, avoiding the two depositions required by traditional technology, and the two de-plating problems caused by the wet method, thereby simplifying the preparation process, thereby effectively improving production efficiency; then, laser transfer is used to achieve boron and phosphorus doping of the polysilicon layer in the front and back metal regions, and only one annealing is required, which is beneficial to saving production costs; finally, laser etching is used to remove the polysilicon in the undoped areas of the front and back non-metallic regions, thereby effectively reducing the parasitic absorption of the polysilicon layer, increasing the current, and realizing high-performance solar cells.
[0087] The embodiment of the present application further provides a photovoltaic module (not shown), comprising the above-mentioned TOPCon solar cell.
[0088] The embodiment of the present application also provides a photovoltaic system, including the photovoltaic components in any of the above embodiments. The advantages of the above photovoltaic components are also possessed by the photovoltaic system, which will not be repeated here. The above photovoltaic system has a wide range of applications, not only limited to photovoltaic power stations, such as ground power stations, rooftop power stations and water power stations, but also includes various equipment and devices that use solar energy to generate electricity, such as user solar power supplies, solar street lights, solar cars and solar buildings. Of course, it can be understood that the application scenarios of the photovoltaic system are not limited to this, that is to say, the photovoltaic system can be used in all fields where solar energy is required for power generation. Taking the photovoltaic power generation system network as an example, the photovoltaic system may include a photovoltaic array, a junction box and an inverter. The photovoltaic array may be an array combination of multiple photovoltaic components. For example, multiple photovoltaic components may form multiple photovoltaic arrays. The photovoltaic array is connected to a junction box. The junction box can converge the current generated by the photovoltaic array. The converged current flows through the inverter and is converted into the alternating current required by the mains power grid, and then connected to the mains network to realize solar power supply.
[0089] It should be noted that the terms "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc. are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. The orientation words "inside" and "outside" refer to the inside and outside relative to the outline of each component itself. For example, if the device in the accompanying drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be positioned as "below other devices or structures" or "below other devices or structures". Therefore, the exemplary term "above..." can include both "above..." and "below..." orientations. The device can also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatial relative descriptions used here are interpreted accordingly.
[0090] It should also be noted that "one embodiment", "another embodiment", "embodiment", etc. mentioned in this application refer to the specific features, structures or characteristics described in conjunction with the embodiment included in at least one embodiment generally described in this application. The same expression appearing in multiple places in the specification does not necessarily refer to the same embodiment. Further, when describing a specific feature, structure or characteristic in conjunction with any embodiment, it is claimed that the realization of such feature, structure or characteristic in conjunction with other embodiments also falls within the scope of this application.
[0091] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.
[0092] It should also be noted that the above are only preferred embodiments of the present application, and the patent protection scope of the present application is not limited thereto. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.
Claims
1. A method for preparing a TOPCon solar cell, characterized in that: include: Providing a silicon wafer, wherein the silicon wafer is an N-type silicon wafer, the front side of the silicon wafer has a front metal region and a front non-metal region, and the back side of the silicon wafer has a back metal region and a back non-metal region; forming a P-type diffusion layer on the front side of the silicon wafer; Using LPCVD, a tunneling oxide layer and an intrinsic amorphous silicon layer are sequentially formed on the P-type diffusion layer and the back side of the silicon wafer; Performing a P-type doping treatment on the intrinsic amorphous silicon layer located in the front metal region, and performing an N-type doping treatment on the intrinsic amorphous silicon layer located in the back metal region; Annealing the silicon wafer that has undergone the P-type doping treatment and the N-type doping treatment, so that the intrinsic amorphous silicon layer located in the front metal region is converted into a P-type doped polysilicon layer, the intrinsic amorphous silicon layer located in the back metal region is converted into an N-type doped polysilicon layer, and the intrinsic amorphous silicon layer located in the front non-metallic region and the back non-metallic region is converted into an intrinsic polysilicon layer; The intrinsic polysilicon layer is removed.
2. The method for preparing a TOPCon solar cell according to claim 1, characterized in that: The step of performing a P-type doping process on the intrinsic amorphous silicon layer located in the front metal region comprises: Using a first laser transfer technology, printing a slurry containing a P-type doping element on the surface of the intrinsic amorphous silicon layer located in the front metal area, and drying the slurry; The N-type doping treatment of the intrinsic amorphous silicon layer located in the back metal region includes: The second laser transfer technology is used to print a slurry containing an N-type doping element on the surface of the intrinsic amorphous silicon layer located in the back metal region, and then the slurry is dried.
3. The method for preparing a TOPCon solar cell according to claim 2, characterized in that: In the first laser transfer technology, the laser power is 20-100W, the drying temperature is 280-320°C, and the drying time is 2-3min; and / or In the second laser transfer technology, the laser power is 20-100W, the drying temperature is 280-320°C, and the drying time is 2-3min.
4. The method for preparing a TOPCon solar cell according to claim 2, characterized in that: The P-type doping element includes one or more of boron, aluminum, and gallium, and the N-type doping element includes one or more of phosphorus, arsenic, and antimony.
5. The method for preparing a TOPCon solar cell according to any one of claims 1 to 4, characterized in that: In the annealing treatment, the annealing temperature is 700-850° C. and the annealing time is 30-120 min.
6. The method for preparing a TOPCon solar cell according to any one of claims 1 to 4, characterized in that: The removing of the intrinsic polysilicon layer comprises: Using laser etching to remove the intrinsic polysilicon layer located in the front non-metallic area and the back non-metallic area; In the laser etching, the laser wavelength is 490-575nm, and the laser power is 10-50W.
7. The method for preparing a TOPCon solar cell according to any one of claims 1 to 4, characterized in that: After removing the intrinsic polysilicon layer, the method further comprises: Depositing a passivation layer and an anti-reflection layer on the front side and the back side of the silicon wafer in sequence; forming a first electrode, wherein the first electrode penetrates the anti-reflection layer and the passivation layer on the front side of the silicon wafer and contacts the P-type doped polysilicon layer; A second electrode is formed, wherein the second electrode penetrates the anti-reflection layer and the passivation layer on the back side of the silicon wafer and contacts the N-type doped polysilicon layer.
8. A TOPCon solar cell, characterized in that: A TOPCon solar cell is formed by the preparation method of any one of claims 1 to 7, wherein the TOPCon solar cell comprises: A silicon wafer, wherein the silicon wafer is an N-type silicon wafer, the front side of the silicon wafer has a front metal region and a front non-metal region, and the back side of the silicon wafer has a back metal region and a back non-metal region; A P-type diffusion layer, a tunneling oxide layer and a P-type doped polysilicon layer are located on the front side of the silicon wafer and are stacked in sequence in a direction away from the silicon wafer; wherein the P-type doped polysilicon layer is only located in the front metal region; A tunneling oxide layer and an N-type doped polysilicon layer are located on the back side of the silicon wafer and are stacked in sequence in a direction away from the silicon wafer; wherein the N-type doped polysilicon layer is only located in the back metal region.
9. The TOPCon solar cell according to claim 8, characterized in that: Also includes: A passivation layer and an anti-reflection layer located on the front side and the back side of the silicon wafer and stacked in sequence in a direction away from the silicon wafer; A first electrode located on the front side of the silicon wafer, the first electrode penetrates the anti-reflection layer and the passivation layer and contacts the P-type doped polysilicon layer; A second electrode is located on the back side of the silicon wafer, wherein the second electrode penetrates the anti-reflection layer and the passivation layer and contacts the N-type doped polysilicon layer.
10. A photovoltaic module, characterized in that: Comprising the TOPCon solar cell according to any one of claims 8-9.