Light emitting diode and method of manufacturing light emitting diode

Abstract

This disclosure provides a light-emitting diode (LED) and a method for fabricating an LED. The LED includes: an epitaxial structure, an insulating structure, a first electrode pad, and a second electrode pad; the insulating structure covers the epitaxial structure, and a first through-hole and a second through-hole are formed in the insulating structure; the first electrode pad includes a first electrode pad filling layer and a first electrode pad soldering layer, the second electrode pad includes a second electrode pad filling layer and a second electrode pad soldering layer, the first electrode pad filling layer is located in the first through-hole, the second electrode pad filling layer is located in the second through-hole, the first electrode pad soldering layer covers the surface of the insulating structure surrounding the first electrode pad filling layer and the first through-hole, and the second electrode pad soldering layer covers the surface of the insulating structure surrounding the second electrode pad filling layer and the second through-hole.

Description

Technical Field

[0001] This disclosure relates to the field of light-emitting devices, and in particular to a light-emitting diode and a method for fabricating a light-emitting diode. Background Technology

[0002] Light-emitting diodes (LEDs) are semiconductor devices that emit light. They have advantages such as energy saving, high brightness, high durability, long lifespan, and lightweight, and have been widely used in both backlight displays and direct-view displays.

[0003] The related technology provides a light-emitting diode, which includes an epitaxial structure, an insulating structure, an electrode structure, etc.

[0004] In the aforementioned light-emitting diodes, the small contact area of ​​the electrode structure leads to relatively poor heat dissipation, resulting in decreased stability. Summary of the Invention

[0005] This disclosure provides a light-emitting diode (LED) and a method for fabricating an LED, which can significantly improve the heat dissipation performance and reliability of the chip. The technical solution is as follows:

[0006] On one hand, a light-emitting diode (LED) is provided, the LED comprising:

[0007] Epitaxial structure, insulating structure, first electrode pad, and second electrode pad;

[0008] The insulating structure covers the epitaxial structure, and a first through hole and a second through hole are formed on the insulating structure;

[0009] The first electrode pad includes a first electrode pad fill layer and a first electrode pad solder layer, and the second electrode pad includes a second electrode pad fill layer and a second electrode pad solder layer. The first electrode pad fill layer is located in the first via, and the second electrode pad fill layer is located in the second via. The first electrode pad solder layer covers the insulating structure surface around the first electrode pad fill layer and the first via, and the second electrode pad solder layer covers the insulating structure surface around the second electrode pad fill layer and the second via.

[0010] Optionally, the first electrode pad filling layer and the second electrode pad filling layer are stacks composed of multiple metals selected from Cr, Ti, Al, Ni, Pt, and Au.

[0011] Optionally, the first electrode pad filling layer and the second electrode pad filling layer are Ti, Al, Ti, Al, Ti, Al, Ti, Al, Ti stacked structures, or the first electrode pad filling layer and the second electrode pad filling layer are Cr, Al, Ti, Al, Ti, Al, Ti, Pt, Ti stacked structures. Optionally, the first electrode pad soldering layer and the second electrode pad soldering layer are stacked structures composed of multiple metals selected from Cr, Al, AlCu, Ti, Ni, Pt, Au, and AuSn.

[0012] Optionally, the first electrode pad welding layer and the second electrode pad welding layer are Ti, Ni, Ti, Ni, Ti, Ni, AuSn stacked structures.

[0013] Optionally, the insulating structure includes a first insulating layer and a second insulating layer stacked together, and the first through hole and the second through hole are formed in the second insulating layer;

[0014] The thickness of the first electrode pad fill layer and the second electrode pad fill layer is equal to the thickness of the second insulating layer.

[0015] Optionally, the cross-sections of the first through hole and the second through hole are inverted trapezoids, the cross-sections of the first electrode pad filling layer and the second electrode pad filling layer are regular trapezoids, the first electrode pad soldering layer covers the sidewall gap between the first through hole and the first electrode pad filling layer, and the second electrode pad soldering layer covers the sidewall gap between the second through hole and the second electrode pad filling layer.

[0016] On the other hand, a method for fabricating a light-emitting diode includes:

[0017] Fabrication of epitaxial structures;

[0018] An insulating structure is fabricated, the insulating structure covering the epitaxial structure, and a first through hole and a second through hole are formed on the insulating structure;

[0019] A first electrode pad and a second electrode pad are fabricated. The first electrode pad includes a first electrode pad filler layer and a first electrode pad solder layer. The second electrode pad includes a second electrode pad filler layer and a second electrode pad solder layer. The first electrode pad filler layer is located in the first via, and the second electrode pad filler layer is located in the second via. The first electrode pad solder layer covers the insulating structure surface surrounding the first electrode pad filler layer and the first via. The second electrode pad solder layer covers the insulating structure surface surrounding the second electrode pad filler layer and the second via.

[0020] Optionally, the fabrication of the first electrode pad and the second electrode pad includes:

[0021] A first mask pattern is fabricated on the insulating structure, the first mask pattern exposing the first through hole and the second through hole;

[0022] Under the cover of the first mask pattern, the first electrode pad filling layer and the second electrode pad filling layer are respectively fabricated in the first through hole and the second through hole by metal evaporation process;

[0023] A second mask pattern is created, which exposes the first through hole and the surrounding defined area, as well as the second through hole and the surrounding defined area.

[0024] Under the cover of the second mask pattern, the first electrode pad welding layer and the second electrode pad welding layer are respectively fabricated on the first electrode pad filling layer and the second electrode pad filling layer by metal evaporation process.

[0025] Optionally, the first electrode pad filling layer and the second electrode pad filling layer are stacks composed of multiple metals selected from Cr, Ti, Al, Ni, Pt, and Au.

[0026] The beneficial effects of the technical solutions provided in this disclosure are:

[0027] In this embodiment, an electrode pad filling layer is first provided in the through hole of the insulating structure to fill the through hole, and then an electrode pad welding layer is provided. The electrode pad welding layer covers the electrode pad filling layer and the insulating layer within a certain range around the through hole, thereby making the flat surface area of ​​the electrode pad for welding larger, improving the chip heat dissipation capacity, reducing thermal resistance, and strengthening the bonding between the chip and the substrate, thus improving the stability of the light-emitting diode. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a schematic diagram of the structure of a light-emitting diode provided in an embodiment of the present disclosure;

[0030] Figure 2 A top view of the structure of a light-emitting diode provided in an embodiment of this disclosure;

[0031] Figure 3 This is a flowchart of a method for fabricating a light-emitting diode (LED) according to an embodiment of the present disclosure.

[0032] Figure 4 A flowchart illustrating another method for fabricating a light-emitting diode (LED) according to an embodiment of this disclosure.

[0033] The attached figures are labeled as follows:

[0034] 10: Epitaxial structure; 20: Insulating structure;

[0035] 101: Substrate; 102: First semiconductor layer; 103: Active layer; 104: Second semiconductor layer; 105: Transparent conductive layer; 106: Dielectric reflective layer; 107: Silver mirror layer; 108: First insulating layer; 109: Second insulating layer; 110: First electrode; 111: Second electrode; 112: First electrode pad filling layer; 113: First electrode pad soldering layer; 114: Second electrode pad filling layer; 115: Second electrode pad soldering layer; 116: Isolation trench; 117: Stepped structure; 118: First through-hole; 119: Second through-hole; 120: Third through-hole; 121: Fourth through-hole;

[0036] 201: First electrode pad; 202: Second electrode pad. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0038] The automotive lighting market typically uses high-power flip-chip LEDs. Because these chips need to operate under high current for extended periods, their heat dissipation capabilities are crucial. Prolonged use under high current exacerbates the thermal effects, leading to several consequences: first, increased junction temperature, which can damage the chip; second, accelerated aging; and third, decreased luminous efficiency and reduced lifespan. The heat dissipation capacity of an LED chip directly impacts its high-temperature resistance and lifespan. Therefore, improving the chip's heat dissipation and reducing thermal resistance effectively lowers the junction temperature during operation, prevents excessive heat buildup, and extends the LED's lifespan.

[0039] The common approach to improving chip heat dissipation is to increase the effective bonding area between the chip electrodes and the substrate. The chip electrode area needs to be relatively flat to be effectively bonded to the substrate after reflow soldering. However, due to the three-dimensional structure of the chip surface, the flat area is relatively small, resulting in a small effective bonding area between the chip electrodes and the substrate, ultimately leading to relatively poor heat dissipation.

[0040] Figure 1 This is a schematic diagram of the structure of a light-emitting diode provided in an embodiment of this disclosure. See also... Figure 1The light-emitting diode includes: an epitaxial structure 10, an insulating structure 20, a first electrode pad 201, and a second electrode pad 202.

[0041] The insulating structure 20 covers the epitaxial structure 10, and a first through hole 118 and a second through hole 119 are formed on the insulating structure 20. The first electrode pad 201 includes a first electrode pad filling layer 112 and a first electrode pad soldering layer 113, and the second electrode pad 202 includes a second electrode pad filling layer 114 and a second electrode pad soldering layer 115. The first electrode pad filling layer 112 is located in the first through hole 118, and the second electrode pad filling layer 114 is located in the second through hole 119. The first electrode pad soldering layer 113 covers the surface of the insulating structure 20 around the first electrode pad filling layer 112 and the first through hole 118, and the second electrode pad soldering layer 115 covers the surface of the insulating structure 20 around the second electrode pad filling layer 114 and the second through hole 119.

[0042] In this embodiment, an electrode pad filling layer is first provided in the through hole of the insulating structure to fill the through hole, and then an electrode pad welding layer is provided. The electrode pad welding layer covers the electrode pad filling layer and the insulating layer within a certain range around the through hole, thereby making the flat surface area of ​​the electrode pad for welding larger, improving the chip heat dissipation capacity, reducing thermal resistance, and strengthening the bonding between the chip and the substrate, thus improving the stability of the light-emitting diode.

[0043] In this embodiment of the disclosure, the first electrode pad filling layer 112 and the second electrode pad filling layer 114 can be a stack of multiple metals selected from Cr, Ti, Al, Ni, Pt, and Au.

[0044] Among them, Cr has good electrical conductivity and can be used for ohmic contacts between electrodes and epitaxial structures. Ti has good adhesion and can enhance adhesion. Al has good reflectivity and can improve the reflectivity of light. Ni has a high melting point and is inert, so it can be used as a protective layer. Pt is a very corrosion-resistant metal and can protect the underlying material from corrosive environments. Au has good electrical conductivity.

[0045] In one possible implementation of this disclosure, the first electrode pad filling layer 112 and the second electrode pad filling layer 114 can be a Ti, Al, Ti, Al, Ti, Al, Ti, Al, Ti metal stack structure.

[0046] In this implementation, Ti serves as the adhesion layer and Al serves as the reflective layer, ensuring the reflective and conductive effects of the electrode pad filling layer.

[0047] In another possible implementation of this disclosure, the first electrode pad filling layer 112 and the second electrode pad filling layer 114 can be Cr, Al, Ti, Al, Ti, Al, Ti, Pt, Ti metal stack structure.

[0048] In this implementation, Cr serves as the ohmic contact, Al as the reflective layer, Ti as the adhesive layer, and Pt as the protective layer, ensuring the reflective and conductive effects of the electrode pad filling layer.

[0049] In this embodiment of the disclosure, the first electrode pad welding layer 113 and the second electrode pad welding layer 115 can be a stack of multiple metals selected from Cr, Al, AlCu, Ti, Ni, Pt, Au, and AuSn.

[0050] The roles of Cr, Al, Ti, Ni, Pt, and Au will not be repeated here as previously described. AlCu can be an AlCu alloy with 10% Al content, making the evaporation process more stable, preventing the formation of metal particles, and avoiding the rupture of the upper film layer. AuSn can be used as a welding layer, exhibiting good stability at high temperatures.

[0051] In this embodiment of the disclosure, the first electrode pad welding layer 113 and the second electrode pad welding layer 115 can be a Ti, Ni, Ti, Ni, Ti, Ni, AuSn stacked structure.

[0052] In this implementation, Ti serves as the adhesion layer, Ni as the protective layer, and AuSn as the welding layer, ensuring the stability of the electrode pad welding layer and the welding effect.

[0053] In this embodiment of the present disclosure, the insulating structure 20 includes a first insulating layer 108 and a second insulating layer 109; a first through hole 118 and a second through hole 119 are formed in the second insulating layer 109.

[0054] In this embodiment of the disclosure, the thickness of the first electrode pad filling layer 112 and the second electrode pad filling layer 114 is equal to the thickness of the second insulating layer 109.

[0055] In this implementation, the thickness of the first electrode pad filling layer 112 and the second electrode pad filling layer 114 is equal to the thickness of the second insulating layer 109. The first electrode pad filling layer 112 and the second electrode pad filling layer 114 can fill the through holes of the insulating layer, making the first electrode pad welding layer 113 and the second electrode pad welding layer 115 formed by the thickness more flat, and can simultaneously cover the through holes and the insulating layer, forming a larger welding surface.

[0056] In this embodiment, the cross-sections of the first through hole 118 and the second through hole 119 are inverted trapezoids, the cross-sections of the first electrode pad filling layer 112 and the second electrode pad filling layer 114 are trapezoids, the first electrode pad soldering layer 113 covers the sidewall gap between the first through hole 118 and the first electrode pad filling layer 112, and the second electrode pad soldering layer 115 covers the sidewall gap between the second through hole 119 and the second electrode pad filling layer 114.

[0057] In this implementation, the through hole is designed as an inverted trapezoid and the fill layer is set as a trapezoid, which facilitates manufacturing. At this time, the gap between the through hole and the fill layer is covered by a welding layer, which will only form a very small depression and will not affect the overall flatness of the welding layer surface.

[0058] For example, the epitaxial structure 10 includes a first semiconductor layer 102, an active layer 103, and a second semiconductor layer 104.

[0059] like Figure 1 As shown in the embodiments of this disclosure, the light-emitting diode may further include a substrate 101, a transparent conductive layer 105, a dielectric film reflective layer 106, a silver mirror layer 107, a first electrode 110, and a second electrode 111.

[0060] The first semiconductor layer 102, the active layer 103, and the second semiconductor layer 104 are sequentially stacked on the substrate 101. The first semiconductor layer 102, the active layer 103, and the second semiconductor layer 104 have stepped structures 117 extending to the first semiconductor layer 102, meaning the bottom surface of the stepped structure 117 is located on the first semiconductor layer 102. The first semiconductor layer 102, the active layer 103, and the second semiconductor layer 104 also have isolation trenches 116 extending to the substrate 101, meaning the bottom of the isolation trenches 116 is located on the substrate 101.

[0061] A transparent conductive layer 105, a dielectric reflective layer 106, and a silver mirror layer 107 are sequentially stacked on the second semiconductor layer 104. The dielectric reflective layer 106 encapsulates the transparent conductive layer 105 and has multiple through holes. The silver mirror layer 107 is connected to the transparent conductive layer 105 through the through holes. The first insulating layer 108 covers the silver mirror layer 107, the isolation groove 116, and the stepped structure 117. The first insulating layer 108 has a third through hole 120 and a fourth through hole 121 at the top surface of the silver mirror layer 107 and the stepped structure 117, respectively. The first electrode 110 is connected to the silver mirror layer 107 through the third through hole 120 at the silver mirror layer 107. The second electrode 111 is connected to the first semiconductor layer 102 through the fourth through hole 121 at the bottom surface of the stepped structure 117. The first electrode pad 201 is connected to the first electrode 110 through the first through hole 118. The second electrode pad 202 is connected to the second electrode 111 through the second through hole 119.

[0062] In this embodiment of the disclosure, the substrate 101 can be any one of a sapphire substrate, a Si substrate, or a SiC substrate, and the material of the substrate 101 is not limited in this embodiment of the disclosure.

[0063] For example, substrate 101 is a sapphire substrate.

[0064] In this embodiment of the disclosure, the first semiconductor layer 102 can be an N-type semiconductor layer, and the second semiconductor layer 104 can be a P-type semiconductor layer.

[0065] For example, the first semiconductor layer 102 can be an N-type GaN material, and the second semiconductor layer 104 can be a P-type GaN material.

[0066] In other embodiments, the first semiconductor layer 102 may be a P-type semiconductor layer, and the second semiconductor layer 104 may be an N-type semiconductor layer.

[0067] In this embodiment of the disclosure, the active layer 103 can be a multi-quantum well layer, such as an InGaN / GaN multi-quantum well layer.

[0068] In this embodiment of the disclosure, the transparent conductive layer 105 can be an indium tin oxide (ITO) layer. ITO has excellent transparency and conductivity, allowing light to pass through while also conducting current to form an electrical connection.

[0069] In this embodiment, the thickness of the transparent conductive layer 105 can be 170 to 250 angstroms. If the transparent conductive layer is too thick, it will absorb light and reduce the light emission rate. If the film layer is too thin, it will lead to poor current spreadability.

[0070] In this embodiment of the disclosure, the dielectric film reflective layer 106 may be a SiO2 layer or a stack formed of SiO2 and Ti3O5 or other combinations thereof.

[0071] For example, when the dielectric film reflective layer 106 is a single-layer SiO2 layer, a plasma-enhanced chemical vapor deposition (PECVD) device is used to deposit the dielectric film reflective layer.

[0072] For example, when the dielectric film reflective layer 106 is a stack or other combination of SiO2 and Ti3O5, it is prepared by an optical coating machine.

[0073] In this embodiment, the silver mirror layer 107 can be a combination of one or more metal or alloy layers such as Ag, Ni, Ti, TiW, Al, AlCu, Ti, Ni, Pt, and Au, wherein the metal Ag is the main structure and plays the role of light reflection and current spread, while Ni and TiW can prevent the migration and diffusion of the metal silver.

[0074] For example, the silver mirror layer 107 is a stack of Ag, Ni, Ti, TiW, Al, AlCu, Ti, Ni, Pt, and Au.

[0075] In this embodiment of the disclosure, the first insulating layer 108 may be a distributed Bragg reflector (DBR) layer or a SiO2 layer, wherein the DBR layer is a stack formed of SiO2 and Ti3O5.

[0076] In this embodiment, the second insulating layer 109 can be a DBR layer or a SiO2 layer, wherein the DBR layer is a stack of SiO2 and Ti3O5.

[0077] In this embodiment of the disclosure, the first electrode 110 and the second electrode 111 can be a combination of one or more metal or alloy layers such as Cr, Al, AlCu, Ti, Ni, Pt and Au.

[0078] For example, the first electrode 110 and the second electrode 111 are Cr, Al, AlCu, Ti, Ni, Pt and Au stacks.

[0079] It is worth noting that, in the embodiments of this disclosure, the structure can be selectively added or reduced based on the structure of the light-emitting diode described above, and this disclosure does not limit this.

[0080] Figure 2 This is a top view of a light-emitting diode (LED) according to an embodiment of this disclosure. See also... Figure 2 The first electrode pad filling layer 112 is located inside the first through hole 118, the second electrode pad filling layer 114 is located inside the second through hole 119, the first electrode pad welding layer 113 covers the first electrode pad filling layer 112 and its surroundings, and the second electrode pad welding layer 115 covers the second electrode pad filling layer 114 and its surroundings, which effectively increases the welding area and can significantly improve the high temperature resistance and reliability of the chip.

[0081] Figure 3 This is a flowchart illustrating a method for fabricating a light-emitting diode (LED) according to an embodiment of this disclosure. See also... Figure 3 The method includes the following steps:

[0082] S11. Fabricate the extensional structure.

[0083] S12. Fabricate an insulating structure that covers the epitaxial structure, and the insulating structure has a first through hole and a second through hole.

[0084] S13. Fabricate a first electrode pad and a second electrode pad. The first electrode pad includes a first electrode pad filler layer and a first electrode pad solder layer. The second electrode pad includes a second electrode pad filler layer and a second electrode pad solder layer. The first electrode pad filler layer is located in the first via. The second electrode pad filler layer is located in the second via. The first electrode pad solder layer covers the insulating structure surface around the first electrode pad filler layer and the first via. The second electrode pad solder layer covers the insulating structure surface around the second electrode pad filler layer and the second via.

[0085] In this embodiment, an electrode pad filling layer is first provided in the through hole of the insulating structure to fill the through hole, and then an electrode pad welding layer is provided. The electrode pad welding layer covers the electrode pad filling layer and the insulating layer within a certain range around the through hole, thereby making the flat surface area of ​​the electrode pad for welding larger, improving the chip heat dissipation capacity, reducing thermal resistance, and strengthening the bonding between the chip and the substrate, thus improving the stability of the light-emitting diode.

[0086] Figure 4 A flowchart illustrating another method for fabricating a light-emitting diode (LED) according to an embodiment of this disclosure. See also... Figure 4 The method includes the following steps:

[0087] S21. A first semiconductor layer, an active layer, and a second semiconductor layer are sequentially formed on a substrate, and the second semiconductor layer, the active layer, and the first semiconductor layer constitute an epitaxial structure.

[0088] The substrate can be any one of sapphire substrate, Si substrate, and SiC substrate.

[0089] In one example, step S21 includes:

[0090] The first step is to fabricate the first semiconductor layer.

[0091] In this embodiment of the disclosure, the first semiconductor layer is N-type GaN.

[0092] The second step is to create the active layer.

[0093] In this embodiment of the disclosure, the active layer is a multi-quantum well layer, such as an InGaN / GaN multi-quantum well layer.

[0094] The third step is to fabricate the second semiconductor layer.

[0095] In this embodiment of the disclosure, the second semiconductor layer is a P-type GaN.

[0096] In this embodiment of the present disclosure, a first semiconductor layer, an active layer, and a second semiconductor layer are sequentially stacked on a substrate.

[0097] S22. The extension structure is graphically processed to form a stepped structure and an isolation groove. The stepped structure includes the bottom surface of the step and the top surface of the step.

[0098] In this embodiment, the top surface of the stepped structure is located in the second semiconductor layer, and the bottom surface of the stepped structure is located in the first semiconductor layer. The bottom of the isolation trench is located on the substrate surface.

[0099] In this embodiment of the disclosure, the step structure is etched by ICP.

[0100] S23. Fabricate a transparent conductive layer on the surface of the epitaxial structure.

[0101] In this embodiment, the transparent conductive layer can be an ITO layer. ITO has excellent transparency and conductivity, allowing light to pass through while also conducting current to form an electrical connection.

[0102] In this embodiment, the thickness of the transparent conductive layer can be 170 to 250 angstroms. If the transparent conductive layer is too thick, it will absorb light and reduce the light emission rate. If the film layer is too thin, it will lead to poor current spreadability.

[0103] S24. A dielectric reflective layer is fabricated on the surface of the epitaxial structure. The dielectric reflective layer encapsulates a transparent conductive layer, and multiple through holes are formed on the dielectric reflective layer.

[0104] In the embodiments of this disclosure, the dielectric film reflective layer may be a SiO2 layer or a stack formed of SiO2 and Ti3O5 or other combinations thereof.

[0105] For example, when the dielectric film reflective layer is a single-layer SiO2 layer, a plasma-enhanced chemical vapor deposition (PECVD) device is used to deposit the dielectric film reflective layer.

[0106] For example, when the dielectric film reflective layer is a stack or other combination of SiO2 and Ti3O5, it is prepared by an optical coating machine.

[0107] In this embodiment of the disclosure, vias in the dielectric film reflective layer are fabricated by means of buffered oxide etching (BOE), inductively coupled plasma etching (ICP), or a combination of ICP etching and BOE etching.

[0108] S25. A silver mirror layer is fabricated on the surface of the dielectric film reflective layer, and the silver mirror layer is connected to the transparent conductive layer through a through hole.

[0109] In this embodiment, the silver mirror layer can be a combination of one or more metal or alloy layers such as Ag, Ni, Ti, TiW, Al, AlCu, Ti, Ni, Pt, and Au, wherein the metal Ag is the main structure and plays the role of light reflection and current spread, while Ni and TiW can prevent the migration and diffusion of the metal silver.

[0110] For example, the silver mirror layer is a stack of Ag, Ni, Ti, TiW, Al, AlCu, Ti, Ni, Pt, and Au.

[0111] S26. Make a first insulating layer and open a third and fourth through hole. The first insulating layer covers the silver mirror layer, the isolation groove and the top and bottom surfaces of the stepped structure.

[0112] In this embodiment of the disclosure, the first insulating layer may be a distributed Bragg reflector (DBR) layer or a SiO2 layer, wherein the DBR layer is a stack of SiO2 and Ti3O5.

[0113] In this embodiment of the present disclosure, the first insulating layer has third through holes at the silver mirror layer and at the top surface of the stepped structure, respectively.

[0114] In this embodiment of the disclosure, the third and fourth through holes are fabricated by etching or corrosion.

[0115] S27. Fabricate the first and second electrodes.

[0116] In the embodiments disclosed herein, the first electrode and the second electrode may be a combination of one or more metal or alloy layers such as Cr, Al, AlCu, Ti, Ni, Pt and Au.

[0117] For example, the first electrode and the second electrode are a stack of Cr, Al, AlCu, Ti, Ni, Pt and Au.

[0118] S28. A second insulating layer is fabricated and a first through hole and a second through hole are opened. The second insulating layer covers the first electrode, the second electrode and the first insulating layer.

[0119] In this embodiment, the second insulating layer may be a distributed Bragg reflector, a DBR layer, or a SiO2 layer, wherein the DBR layer is a stack of SiO2 and Ti3O5.

[0120] In this embodiment, the second insulating layer has a first through hole and a second through hole at the first electrode and the second electrode, respectively. The first electrode pad is connected to the first electrode through the first through hole at the first electrode, and the second electrode pad is connected to the second electrode through the second through hole at the second electrode.

[0121] In this embodiment of the disclosure, the first through hole and the second through hole are made by etching or corrosion.

[0122] S29. Fabricate the first electrode pad and the second electrode pad.

[0123] In this embodiment of the disclosure, step S29 includes:

[0124] The first step is to fabricate a first mask pattern on the insulating structure, which exposes the first through hole and the second through hole.

[0125] The second step involves fabricating a first electrode pad filling layer and a second electrode pad filling layer in the first and second vias respectively using a metal evaporation process, while the first mask pattern is in place.

[0126] In this embodiment of the present disclosure, the first electrode pad filling layer is located in the first through hole, and the second electrode pad filling layer is located in the second through hole.

[0127] In this embodiment of the disclosure, the first electrode pad filling layer and the second electrode pad filling layer can be a stack of multiple metals selected from Cr, Ti, Al, Ni, Pt, and Au.

[0128] Among them, Cr has good electrical conductivity and can be used for ohmic contacts between electrodes and epitaxial structures. Ti has good adhesion and can enhance adhesion. Al has good reflectivity and can improve the reflectivity of light. Ni has a high melting point and is inert, so it can be used as a protective layer. Pt is a very corrosion-resistant metal and can protect the underlying material from corrosive environments. Au has good electrical conductivity.

[0129] In one possible implementation of this disclosure, the first electrode pad filling layer and the second electrode pad filling layer can be a Ti, Al, Ti, Al, Ti, Al, Ti, Al, Ti metal stack structure.

[0130] In this implementation, Ti serves as the adhesion layer and Al serves as the reflective layer, ensuring the reflective and conductive effects of the electrode pad filling layer.

[0131] In another possible implementation of this disclosure, the first electrode pad filling layer and the second electrode pad filling layer can be Cr, Al, Ti, Al, Ti, Al, Ti, Pt, Ti metal stack structure.

[0132] In this implementation, Cr serves as the ohmic contact, Al as the reflective layer, Ti as the adhesive layer, and Pt as the protective layer, ensuring the reflective and conductive effects of the electrode pad filling layer.

[0133] After the metal evaporation process is completed, the first mask pattern and the metal layer on the first mask pattern are removed by a stripping process, and the remaining metal layer in the through hole is used as the pad filling layer.

[0134] The third step is to create a second mask pattern, which exposes the first through hole and the surrounding defined area, as well as the second through hole and the surrounding defined area.

[0135] In this embodiment of the disclosure, the thickness of the first electrode pad filling layer and the second electrode pad filling layer is equal to the thickness of the second insulating layer.

[0136] In this implementation, the thickness of the first electrode pad filling layer and the second electrode pad filling layer is equal to the thickness of the second insulating layer. The first electrode pad filling layer and the second electrode pad filling layer can fill the through-hole of the insulating layer, making the first electrode pad welding layer and the second electrode pad welding layer formed by the thickness more flat, and can simultaneously cover the through-hole and the insulating layer, forming a larger welding surface.

[0137] The fourth step involves fabricating the first electrode pad welding layer and the second electrode pad welding layer on the first electrode pad filling layer and the second electrode pad filling layer respectively using a metal evaporation process, under the cover of the second mask pattern.

[0138] In this embodiment of the disclosure, the first electrode pad welding layer and the second electrode pad welding layer can be a stack of multiple metals selected from Cr, Al, AlCu, Ti, Ni, Pt, Au, and AuSn.

[0139] The roles of Cr, Al, Ti, Ni, Pt, and Au will not be repeated here as previously described. AlCu can be an AlCu alloy with 10% Al content, making the evaporation process more stable, preventing the formation of metal particles, and avoiding the rupture of the upper film layer. AuSn can be used as a welding layer, exhibiting good stability at high temperatures.

[0140] In this embodiment of the disclosure, the first electrode pad welding layer and the second electrode pad welding layer can be a Ti, Ni, Ti, Ni, Ti, Ni, AuSn stacked structure.

[0141] In this implementation, Ti serves as the adhesion layer, Ni as the protective layer, and AuSn as the welding layer, ensuring the stability of the electrode pad welding layer and the welding effect.

[0142] After the metal evaporation process is completed, the second mask pattern and the metal layer on the second mask pattern are removed by a stripping process, and the remaining metal layer is used as the solder pad layer.

[0143] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A light-emitting diode, characterized in that, The light-emitting diode includes: an epitaxial structure (10), an insulating structure (20), a first electrode pad (201), and a second electrode pad (202); The insulating structure (20) covers the epitaxial structure (10), and the insulating structure (20) has a first through hole (118) and a second through hole (119). The first electrode pad (201) includes a first electrode pad filling layer (112) and a first electrode pad soldering layer (113), and the second electrode pad (202) includes a second electrode pad filling layer (114) and a second electrode pad soldering layer (115). The first electrode pad filling layer (112) is located in the first via (118), and the second electrode pad filling layer (114) is located in the second via (119). The first electrode pad soldering layer (113) covers the surface of the insulating structure (20) around the first electrode pad filling layer (112) and the first via (118), and the second electrode pad soldering layer (115) covers the surface of the insulating structure (20) around the second electrode pad filling layer (114) and the second via (119).

2. The light-emitting diode according to claim 1, characterized in that, The first electrode pad filling layer (112) and the second electrode pad filling layer (114) are stacks composed of multiple metals among Cr, Ti, Al, Ni, Pt and Au.

3. The light-emitting diode according to claim 2, characterized in that, The first electrode pad filling layer (112) and the second electrode pad filling layer (114) are Ti, Al, Ti, Al, Ti, Al, Ti, Al, Ti stacked structures, or the first electrode pad filling layer (112) and the second electrode pad filling layer (114) are Cr, Al, Ti, Al, Ti, Al, Ti, Pt, Ti stacked structures.

4. The light-emitting diode according to any one of claims 1 to 3, characterized in that, The first electrode pad welding layer (113) and the second electrode pad welding layer (115) are stacks composed of multiple metals among Cr, Al, AlCu, Ti, Ni, Pt, Au and AuSn.

5. The light-emitting diode according to claim 4, characterized in that, The first electrode pad welding layer (113) and the second electrode pad welding layer (115) are Ti, Ni, Ti, Ni, Ti, Ni, AuSn stacked structures.

6. The light-emitting diode according to any one of claims 1 to 3, characterized in that, The insulating structure (20) includes a first insulating layer (108) and a second insulating layer (109) stacked together, and the first through hole (118) and the second through hole (119) are formed in the second insulating layer (109); The thickness of the first electrode pad filling layer (112) and the second electrode pad filling layer (114) is equal to the thickness of the second insulating layer (109).

7. The light-emitting diode according to any one of claims 1 to 3, characterized in that, The cross-sections of the first through hole (118) and the second through hole (119) are inverted trapezoids, the cross-sections of the first electrode pad filling layer (112) and the second electrode pad filling layer (114) are regular trapezoids, the first electrode pad solder layer (113) covers the side wall gap between the first through hole (118) and the first electrode pad filling layer (112), and the second electrode pad solder layer (115) covers the side wall gap between the second through hole (119) and the second electrode pad filling layer (114).

8. A method for fabricating a light-emitting diode, characterized in that, The method includes: Fabrication of epitaxial structures; An insulating structure is fabricated, the insulating structure covering the epitaxial structure, and a first through hole and a second through hole are formed on the insulating structure; A first electrode pad and a second electrode pad are fabricated. The first electrode pad includes a first electrode pad filler layer and a first electrode pad solder layer. The second electrode pad includes a second electrode pad filler layer and a second electrode pad solder layer. The first electrode pad filler layer is located in the first via, and the second electrode pad filler layer is located in the second via. The first electrode pad solder layer covers the insulating structure surface surrounding the first electrode pad filler layer and the first via. The second electrode pad solder layer covers the insulating structure surface surrounding the second electrode pad filler layer and the second via.

9. The method for fabricating a light-emitting diode according to claim 8, characterized in that, The fabrication of the first electrode pad and the second electrode pad includes: A first mask pattern is fabricated on the insulating structure, the first mask pattern exposing the first through hole and the second through hole; Under the cover of the first mask pattern, the first electrode pad filling layer and the second electrode pad filling layer are respectively fabricated in the first through hole and the second through hole by metal evaporation process; A second mask pattern is created, which exposes the first through hole and the surrounding defined area, as well as the second through hole and the surrounding defined area. Under the cover of the second mask pattern, the first electrode pad welding layer and the second electrode pad welding layer are respectively fabricated on the first electrode pad filling layer and the second electrode pad filling layer by metal evaporation process.

10. The method for fabricating a light-emitting diode according to claim 9, characterized in that, The first electrode pad filling layer and the second electrode pad filling layer are stacked layers composed of multiple metals among Cr, Ti, Al, Ni, Pt and Au.

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