Laminated ceramic electronic component

Abstract

Provided is a laminated ceramic electronic component capable of reducing ESR. A multilayer ceramic capacitor (1) has a first external electrode (40A) and a second external electrode (40B), the first external electrode (40A) having a first base electrode layer (50A), a first conductive resin layer (60A) disposed on the first base electrode layer (50A) and containing a thermosetting resin and a metal component, and a first Ni plating layer (71A) disposed on the first conductive resin layer (60A); the second external electrode (40B) has a second base electrode layer (50B), a second conductive resin layer (60B) that is disposed on the second base electrode layer (50B) and contains a thermosetting resin and a metal component, and a second Ni plating layer (71B) that is disposed on the second conductive resin layer (60B). Tensile stress remains inside the first Ni plating layer (71A) and the second Ni plating layer (71B) as internal stress.

Description

Technical Field

[0001] The present invention relates to a laminated ceramic electronic component. Background Art

[0002] In recent years, laminated ceramic electronic components represented by laminated ceramic capacitors are required to have durability under harsh environments such as flexural stress caused by thermal expansion. As a response to this, a technology of using a thermosetting conductive resin paste on the external electrodes of laminated ceramic electronic components is known. As a document showing such a technology, Patent Document 1 can be cited. Patent Document 1 describes a laminated ceramic capacitor having an external electrode having a layer structure in which an electrode layer, a conductive epoxy-based thermosetting resin layer, a nickel-plated layer, and a tin-based layer are sequentially laminated.

[0003] Prior Art Literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 11-162771 Summary of the invention

[0006] Problem that the invention aims to solve

[0007] In addition, in order to ensure durability in severe environments and meet the required performance, various measures such as reduction of ESR are being taken for laminated ceramic electronic components, and further improvement of performance is required.

[0008] An object of the present invention is to provide a multilayer ceramic electronic component capable of reducing ESR.

[0009] Technical solutions to solve problems

[0010] The laminated ceramic electronic component of the present invention comprises: a laminated body including a plurality of laminated ceramic layers, and having a first main surface and a second main surface opposite to each other in a height direction, a first side surface and a second side surface opposite to each other in a width direction perpendicular to the height direction, and a first end surface and a second end surface opposite to each other in a length direction perpendicular to the height direction and the width direction; a first internal conductor layer arranged on the plurality of ceramic layers and exposed at the first end surface; a second internal conductor layer arranged on the plurality of ceramic layers and exposed at the second end surface; a first external electrode arranged on the first end surface; and a second external electrode arranged on the second end surface, wherein the first external The electrode comprises: a first base electrode layer including a metal component, a first conductive resin layer including a thermosetting resin and a metal component and arranged on the first base electrode layer, and a first Ni plating layer arranged on the first conductive resin layer; the second external electrode comprises: a second base electrode layer including a metal component, a second conductive resin layer including a thermosetting resin and a metal component and arranged on the second base electrode layer, and a second Ni plating layer arranged on the second conductive resin layer; tensile stress remains as internal stress in the first Ni plating layer, and tensile stress remains as internal stress in the second Ni plating layer.

[0011] Effects of the Invention

[0012] According to the present invention, a multilayer ceramic electronic component capable of reducing ESR can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a perspective view of the appearance of the multilayer ceramic capacitor according to the present embodiment.

[0014] Figure 2 It is along Figure 1 FIG. 1 is a cross-sectional view of the multilayer ceramic capacitor taken along line II-II shown in FIG.

[0015] Figure 3 It is along Figure 2 FIG. 1 is a cross-sectional view of the multilayer ceramic capacitor taken along line III-III.

[0016] Figure 4 It is along Figure 2 FIG. 1 is a cross-sectional view of the multilayer ceramic capacitor taken along line IV-IV shown in FIG.

[0017] Figure 5 yes Figure 2 The enlarged view of the V portion of the multilayer ceramic capacitor shown is a schematic diagram for explaining the state of the force generated on the end surface side of the multilayer ceramic capacitor.

[0018] Figure 6FIG. 1 is a schematic diagram showing an example of the structure of a dual-structured multilayer ceramic capacitor.

[0019] Figure 7 FIG. 1 is a schematic diagram showing an example of the structure of a triple-structured multilayer ceramic capacitor.

[0020] Figure 8 FIG. 1 is a schematic diagram showing an example of the structure of a quadruple-structured multilayer ceramic capacitor. DETAILED DESCRIPTION

[0021] <Implementation Method>

[0022] Below, use Figure 1 to Figure 4 A multilayer ceramic capacitor 1 as a multilayer ceramic electronic component according to a first embodiment of the present disclosure will be described. Figure 1 It is a perspective view of the appearance of the multilayer ceramic capacitor 1 according to the present embodiment. Figure 2 It is along Figure 1 A cross-sectional view of the multilayer ceramic capacitor 1 taken along line II-II. Figure 3 It is along Figure 2 FIG. 1 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line III-III. Figure 4 It is along Figure 2 1 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line IV-IV.

[0023] The multilayer ceramic capacitor 1 includes a multilayer body 10 and external electrodes 40 .

[0024] exist Figure 1 to Figure 4 , an XYZ orthogonal coordinate system is shown. The length direction L of the laminated ceramic capacitor 1 and the laminated body 10 corresponds to the X direction. The width direction W of the laminated ceramic capacitor 1 and the laminated body 10 corresponds to the Y direction. The stacking direction T as the height direction of the laminated ceramic capacitor 1 and the laminated body 10 corresponds to the Z direction. Here, Figure 2 The section shown is also referred to as the LT section. Figure 3 The section shown is also referred to as the WT section. Figure 4 The section shown is also referred to as the LW section.

[0025] like Figure 1 to Figure 4 As shown, the stack 10 includes a first main surface TS1 and a second main surface TS2 opposite to each other in the stacking direction T, a first side surface WS1 and a second side surface WS2 opposite to each other in the width direction W perpendicular to the stacking direction T, and a first end surface LS1 and a second end surface LS2 opposite to each other in the length direction L perpendicular to the stacking direction T and the width direction W.

[0026] like Figure 1As shown, the laminate 10 has a substantially rectangular parallelepiped shape. In addition, the dimension of the length direction L of the laminate 10 is not necessarily longer than the dimension of the width direction W. It is preferred that the corners and ridges of the laminate 10 are rounded. The corner is the portion where three faces of the laminate intersect, and the ridge is the portion where two faces of the laminate intersect. In addition, a part or all of the surface constituting the laminate 10 may be formed with concave and convex portions.

[0027] The size of the laminate 10 is not particularly limited, but if the dimension in the longitudinal direction L of the laminate 10 is set as the L dimension, the L dimension is preferably 0.2 mm or more and 10 mm or less. In addition, if the dimension in the stacking direction T of the laminate 10 is set as the T dimension, the T dimension is preferably 0.1 mm or more and 10 mm or less. In addition, if the dimension in the width direction W of the laminate 10 is set as the W dimension, the W dimension is preferably 0.1 mm or more and 10 mm or less.

[0028] like Figure 2 as well as Figure 3 As shown, the laminate 10 includes an inner layer portion 11 , and a first main surface side outer layer portion 12A as a first outer layer portion and a second main surface side outer layer portion 12B as a second outer layer portion arranged in the lamination direction T to sandwich the inner layer portion 11 .

[0029] The inner layer portion 11 includes a plurality of dielectric layers 20 as a plurality of ceramic layers, and a plurality of internal electrode layers 30 as a plurality of internal conductor layers. The inner layer portion 11 includes the internal electrode layer 30 located closest to the first main surface TS1 side to the internal electrode layer 30 located closest to the second main surface TS2 side in the stacking direction T. In the inner layer portion 11, the plurality of internal electrode layers 30 are arranged opposite to each other with the dielectric layer 20 interposed therebetween. The inner layer portion 11 is a portion that generates electrostatic capacitance and substantially functions as a capacitor.

[0030] The plurality of dielectric layers 20 are made of dielectric material. The dielectric material may be, for example, dielectric ceramics containing BaTiO3, CaTiO3, SrTiO3, or CaZrO3. In addition, the dielectric material may be a material in which auxiliary components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds are added to these main components.

[0031] The thickness of the dielectric layer 20 is preferably not less than 0.5 μm and not more than 15 μm. The number of laminated dielectric layers 20 is preferably not less than 10 and not more than 700. The number of dielectric layers 20 is the sum of the number of dielectric layers of the inner layer portion 11 and the number of dielectric layers of the first main surface side outer layer portion 12A and the second main surface side outer layer portion 12B.

[0032] The plurality of internal electrode layers 30 include a plurality of first internal electrode layers 31 as first internal conductor layers and a plurality of second internal electrode layers 32 as second internal conductor layers. The plurality of first internal electrode layers 31 are arranged on the plurality of dielectric layers 20. The plurality of second internal electrode layers 32 are arranged on the plurality of dielectric layers 20. The plurality of first internal electrode layers 31 and the plurality of second internal electrode layers 32 are alternately arranged in the stacking direction T of the stacked body 10 with the dielectric layers 20 interposed therebetween. The first internal electrode layers 31 and the second internal electrode layers 32 are arranged with the dielectric layers 20 interposed therebetween.

[0033] The first internal electrode layer 31 includes a first opposing portion 31A opposing the second internal electrode layer 32 and a first lead portion 31B led out from the first opposing portion 31A to the first end surface LS1. The first lead portion 31B is exposed at the first end surface LS1.

[0034] The second internal electrode layer 32 includes a second opposing portion 32A opposing the first internal electrode layer 31 and a second lead portion 32B led out from the second opposing portion 32A to the second end surface LS2. The second lead portion 32B is exposed at the second end surface LS2.

[0035] In the present embodiment, the first opposing portion 31A and the second opposing portion 32A are opposed to each other via the dielectric layer 20 , thereby forming capacitance and exhibiting capacitor characteristics.

[0036] The shapes of the first opposing portion 31A and the second opposing portion 32A are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded, or the corners of the rectangular shape may be formed obliquely. The shapes of the first lead-out portion 31B and the second lead-out portion 32B are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded, or the corners of the rectangular shape may be formed obliquely.

[0037] The dimension in the width direction W of the first opposing portion 31A and the dimension in the width direction W of the first lead portion 31B may be formed to be the same dimension, or one of the dimensions may be smaller. The dimension in the width direction W of the second opposing portion 32A and the dimension in the width direction W of the second lead portion 32B may be formed to be the same dimension, or one of the dimensions may be smaller.

[0038] The first internal electrode layer 31 and the second internal electrode layer 32 are made of a suitable conductive material such as a metal such as Ni, Cu, Ag, Pd, Au, or an alloy containing at least one of these metals. When an alloy is used, the first internal electrode layer 31 and the second internal electrode layer 32 may be made of, for example, an Ag-Pd alloy.

[0039] The thickness of each of the first internal electrode layer 31 and the second internal electrode layer 32 is preferably about 0.2 μm or more and 2.0 μm or less, for example. The total number of the first internal electrode layers 31 and the second internal electrode layers 32 is preferably 10 or more and 700 or less.

[0040] The first main surface side outer layer portion 12A is located on the first main surface TS1 side of the stacked body 10. The first main surface side outer layer portion 12A is an aggregate of a plurality of dielectric layers 20 located between the first main surface TS1 and the internal electrode layer 30 closest to the first main surface TS1. The dielectric layer 20 used in the first main surface side outer layer portion 12A may be the same as the dielectric layer 20 used in the internal layer portion 11, or may be a dielectric layer composed of a different material.

[0041] The second main surface side outer layer portion 12B is located on the second main surface TS2 side of the stacked body 10. The second main surface side outer layer portion 12B is an aggregate of a plurality of dielectric layers 20 located between the second main surface TS2 and the internal electrode layer 30 closest to the second main surface TS2. The dielectric layer 20 used in the second main surface side outer layer portion 12B may be the same as the dielectric layer 20 used in the internal layer portion 11, or may be a dielectric layer composed of a different material.

[0042] The laminate 10 also includes an opposing electrode portion 11E. The opposing electrode portion 11E is a portion where the first opposing portion 31A of the first internal electrode layer 31 and the second opposing portion 32A of the second internal electrode layer 32 face each other. The opposing electrode portion 11E is configured as a part of the inner layer portion 11. Figure 4 2 shows the range of the opposing electrode portion 11E in the width direction W and the length direction L. In addition, the opposing electrode portion 11E is also referred to as a capacitor effective portion.

[0043] In addition, the stacked body 10 has a side outer layer portion. The side outer layer portion has a first side outer layer portion WG1 and a second side outer layer portion WG2. The first side outer layer portion WG1 is a portion including the dielectric layer 20 located between the opposing electrode portion 11E and the first side WS1. The second side outer layer portion WG2 is a portion including the dielectric layer 20 located between the opposing electrode portion 11E and the second side WS2. Figure 3 as well as Figure 4 , the range of the first side outer layer portion WG1 and the second side outer layer portion WG2 in the width direction W is shown. In addition, the side outer layer portion is also called a W gap or a side gap.

[0044] In addition, the stacked body 10 has an end face side outer layer portion. The end face side outer layer portion has a first end face side outer layer portion LG1 and a second end face side outer layer portion LG2. The first end face side outer layer portion LG1 is a portion including the dielectric layer 20 located between the opposing electrode portion 11E and the first end face LS1. The second end face side outer layer portion LG2 is a portion including the dielectric layer 20 located between the opposing electrode portion 11E and the second end face LS2. Figure 2 as well as Figure 4 , the range of the first end surface side outer layer portion LG1 and the second end surface side outer layer portion LG2 in the length direction L is shown. In addition, the end surface side outer layer portion is also called an L gap or an end gap.

[0045] The external electrode 40 includes a first external electrode 40A disposed on the first end surface LS1 side and a second external electrode 40B disposed on the second end surface LS2 side.

[0046] The first external electrode 40A is arranged on the first end surface LS1. The first external electrode 40A is connected to the first internal electrode layer 31. The first external electrode 40A may also be arranged on a portion of the first main surface TS1 and a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2. In the present embodiment, the first external electrode 40A is formed by extending from the first end surface LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0047] The second external electrode 40B is arranged on the second end surface LS2. The second external electrode 40B is connected to the second internal electrode layer 32. The second external electrode 40B may also be arranged on a portion of the first main surface TS1 and a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2. In the present embodiment, the second external electrode 40B is formed by extending from the second end surface LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0048] As described above, in the laminate 10, the first opposing portion 31A of the first internal electrode layer 31 and the second opposing portion 32A of the second internal electrode layer 32 are opposed to each other via the dielectric layer 20, thereby forming a capacitor. Therefore, the first external electrode 40A connected to the first internal electrode layer 31 and the second external electrode 40B connected to the second internal electrode layer 32 exhibit capacitor characteristics.

[0049] The first external electrode 40A includes a first base electrode layer 50A including a metal component, a first conductive resin layer 60A disposed on the first base electrode layer 50A, and a first plated layer 70A disposed on the first conductive resin layer 60A. The first plated layer 70A includes a first Ni plated layer 71A as a lower plated layer and a first Sn plated layer 72A as an upper plated layer.

[0050] The second external electrode 40B includes a second base electrode layer 50B including a metal component, a second conductive resin layer 60B disposed on the second base electrode layer 50B, and a second plated layer 70B disposed on the second conductive resin layer 60B. The second plated layer 70B includes a second Ni plated layer 71B as a lower plated layer and a second Sn plated layer 72B as an upper plated layer.

[0051] like Figure 2 , Figure 4 As shown, the first Ni plating layer 71A includes a first end surface side Ni plating layer 71A1 and a first side surface side Ni plating layer 71A2. The first end portion of the first Ni plating layer 71A indicates a portion of the first Ni plating layer 71A located closer to the second end surface LS2 than the first conductive resin layer 60A in the longitudinal direction L.

[0052] like Figure 2 , Figure 4 As shown, the second Ni plating layer 71B includes a second end surface side Ni plating layer 71B1 and a second side surface side Ni plating layer 71B2. The second end portion of the second Ni plating layer 71B indicates a portion of the second Ni plating layer 71B located closer to the first end surface LS1 than the second conductive resin layer 60B in the longitudinal direction L.

[0053] Here, the basic structure of each layer constituting the first external electrode 40A and the second external electrode 40B is the same. In addition, the first external electrode 40A and the second external electrode 40B are substantially plane-symmetrical with respect to the LW cross section at the center of the longitudinal direction L of the multilayer ceramic capacitor 1. Therefore, when there is no need to distinguish between the first external electrode 40A and the second external electrode 40B, the first external electrode 40A and the second external electrode 40B are sometimes collectively referred to as the external electrode 40. In addition, when there is no need to distinguish between the first base electrode layer 50A and the second base electrode layer 50B, the first base electrode layer 50A and the second base electrode layer 50B are sometimes collectively referred to as the base electrode layer 50. In addition, when there is no need to distinguish between the first conductive resin layer 60A and the second conductive resin layer 60B, the first conductive resin layer 60A and the second conductive resin layer 60B are sometimes collectively referred to as the conductive resin layer 60. In addition, when there is no need to distinguish between the first plating layer 70A and the second plating layer 70B, the first plating layer 70A and the second plating layer 70B are sometimes collectively referred to as the plating layer 70. In addition, when there is no need to distinguish between the first Ni plating layer 71A and the second Ni plating layer 71B, the first Ni plating layer 71A and the second Ni plating layer 71B are sometimes collectively referred to as the Ni plating layer 71. In addition, when there is no need to distinguish between the first Sn plating layer 72A and the second Sn plating layer 72B, the first Sn plating layer 72A and the second Sn plating layer 72B are sometimes collectively referred to as the Sn plating layer 72. When there is no need to distinguish the first end surface side Ni plating layer 71A1 and the second end surface side Ni plating layer 71B1, the first end surface side Ni plating layer 71A1 and the second end surface side Ni plating layer 71B1 are sometimes collectively referred to as the end surface side Ni plating layer 711. When there is no need to distinguish the first side surface side Ni plating layer 71A2 and the second side surface side Ni plating layer 71B2, the first side surface side Ni plating layer 71A2 and the second side surface side Ni plating layer 71B2 are sometimes collectively referred to as the side surface side Ni plating layer 712. In addition, when there is no need to distinguish the first end surface LS1 and the second end surface LS2, the first end surface LS1 and the second end surface LS2 are sometimes collectively referred to as the end surface LS.

[0054] The foundation electrode layer 50 includes a first foundation electrode layer 50A and a second foundation electrode layer 50B.

[0055] The first base electrode layer 50A is arranged on the first end surface LS1. The first base electrode layer 50A is connected to the first internal electrode layer 31. In addition, the first base electrode layer 50A may also be arranged on a portion of the first main surface TS1 and a portion of the second main surface TS2, a portion of the first side surface WS1, and a portion of the second side surface WS2. In the present embodiment, the first base electrode layer 50A is formed by extending from the first end surface LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2, a portion of the first side surface WS1, and a portion of the second side surface WS2.

[0056] The second base electrode layer 50B is arranged on the second end surface LS2. The second base electrode layer 50B is connected to the second internal electrode layer 32. In addition, the second base electrode layer 50B may also be arranged on a portion of the first main surface TS1 and a portion of the second main surface TS2, a portion of the first side surface WS1, and a portion of the second side surface WS2. In the present embodiment, the second base electrode layer 50B is formed by extending from the second end surface LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, a portion of the first side surface WS1, and a portion of the second side surface WS2.

[0057] The first base electrode layer 50A and the second base electrode layer 50B of the present embodiment are sintered layers. The sintered layer preferably contains a metal component, and any one of a glass component or a ceramic component, or contains both of them. Thereby, the adhesion between the stack 10 and the base electrode layer can be improved. The metal component, for example, contains at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. The glass component, for example, contains at least one selected from B, Si, Ba, Mg, Al, Li, etc. In the presence of a glass component, it helps the sintering of the metal component in the base electrode layer and can promote sintering. The ceramic component can use the same type of ceramic material as the dielectric layer 20, or a different type of ceramic material. The ceramic component, for example, contains at least one selected from BaTiO3, CaTiO3, (Ba, Ca)TiO3, SrTiO3, CaZrO3, etc.

[0058] The sintered layer is obtained by, for example, applying a conductive paste containing glass and metal to a stacked body and sintering it. The sintered layer can be obtained by simultaneously sintering a stacked chip having an internal electrode and a dielectric layer and a conductive paste applied to the stacked chip, or can be obtained by sintering a stacked body after obtaining a stacked body by sintering the stacked chip having an internal electrode and a dielectric layer, and then applying a conductive paste to the stacked body and sintering it. In addition, when the stacked chip having an internal electrode and a dielectric layer and the conductive paste applied to the stacked chip are sintered at the same time, it is preferred to sinter a conductive paste to which a ceramic material is added instead of a glass component to form a sintered layer. In this case, as the added ceramic material, it is particularly preferred to use a ceramic material of the same type as the dielectric layer 20. The sintered layer can also be a plurality of layers.

[0059] The thickness in the longitudinal direction of the first foundation electrode layer 50A located at the first end surface LS1 is preferably about 2 μm or more and 220 μm or less in the central portion in the stacking direction T and the width direction W of the first foundation electrode layer 50A, for example.

[0060] The thickness of the second foundation electrode layer 50B in the longitudinal direction located at the second end surface LS2 is preferably about 2 μm or more and 220 μm or less in the central portion in the stacking direction T and the width direction W of the second foundation electrode layer 50B, for example.

[0061] When the first base electrode layer 50A is also provided on a portion of at least one of the first main surface TS1 or the second main surface TS2, the thickness in the stacking direction of the first base electrode layer 50A provided on the portion is preferably greater than 4 μm and less than 40 μm in the central portion in the length direction L and the width direction W of the first base electrode layer 50A provided on the portion.

[0062] When the first base electrode layer 50A is also provided on a portion of at least one surface of the first side surface WS1 or the second side surface WS2, the thickness in the width direction of the first base electrode layer 50A provided on the portion is preferably greater than 4 μm and less than 40 μm in the central portion in the length direction L and the stacking direction T of the first base electrode layer 50A provided on the portion.

[0063] When the second base electrode layer 50B is also provided on a portion of at least one of the first main surface TS1 or the second main surface TS2, the thickness in the stacking direction of the second base electrode layer 50B provided on the portion is preferably greater than 4 μm and less than 40 μm in the central portion in the length direction L and the width direction W of the second base electrode layer 50B provided on the portion.

[0064] When the second base electrode layer 50B is also provided on a portion of at least one surface of the first side surface WS1 or the second side surface WS2, the thickness in the width direction of the second base electrode layer 50B provided on the portion is preferably greater than 4 μm and less than 40 μm in the central portion in the length direction L and the stacking direction T of the second base electrode layer 50B provided on the portion.

[0065] The external electrode 40 includes a conductive resin layer 60 including a resin component and a metal component and disposed on the base electrode layer 50. The conductive resin layer 60 includes a first conductive resin layer 60A and a second conductive resin layer 60B.

[0066] The first conductive resin layer 60A is arranged to cover the first base electrode layer 50A. In addition, the end of the first conductive resin layer 60A is preferably in contact with the laminate 10. The end of the first conductive resin layer 60A refers to a portion of the first conductive resin layer 60A that is closer to the second end surface LS2 than the first base electrode layer 50A in the length direction L. The second conductive resin layer 60B is arranged to cover the second base electrode layer 50B. In addition, the end of the second conductive resin layer 60B is preferably in contact with the laminate 10. The end of the second conductive resin layer 60B refers to a portion of the second conductive resin layer 60B that is closer to the first end surface LS1 than the second base electrode layer 50B in the length direction L.

[0067] The thickness in the longitudinal direction of the first conductive resin layer 60A located on the first end surface LS1 side is preferably about 10 μm or more and 200 μm or less in the center portion in the stacking direction T and the width direction W of the first conductive resin layer 60A, for example.

[0068] The thickness in the longitudinal direction of the second conductive resin layer 60B located on the second end surface LS2 side is preferably about 10 μm or more and 200 μm or less in the center portion in the stacking direction T and the width direction W of the second conductive resin layer 60B, for example.

[0069] When the first conductive resin layer 60A is also provided on a portion of the first main surface TS1 side and a portion of the second main surface TS2 side, the thickness of the first conductive resin layer 60A provided on the portion in the stacking direction T is, for example, greater than 10 μm and less than 200 μm in the central portion of the length direction L and the width direction W of the first conductive resin layer 60A provided on the portion.

[0070] When the first conductive resin layer 60A is also provided on a portion of the first side surface WS1 and a portion of the second side surface WS2, the thickness of the first conductive resin layer 60A provided on the portion in the width direction W is preferably greater than 10 μm and less than 200 μm in the central portion in the length direction L and the stacking direction T of the first conductive resin layer 60A provided on the portion.

[0071] When the second conductive resin layer 60B is also provided on a portion of the first main surface TS1 side and a portion of the second main surface TS2 side, the thickness of the second conductive resin layer 60B provided on the portion in the stacking direction T is preferably greater than 10 μm and less than 200 μm in the central portion of the length direction L and the width direction W of the second conductive resin layer 60B provided on the portion.

[0072] When the second conductive resin layer 60B is also provided on a portion of the first side WS1 side and a portion of the second side WS2 side, the thickness of the second conductive resin layer 60B provided on the portion in the width direction W is preferably greater than 10 μm and less than 200 μm in the central portion of the length direction L and the stacking direction T of the second conductive resin layer 60B provided on the portion.

[0073] The conductive resin layer 60 is disposed on the base electrode layer 50. Furthermore, the plating layer 70 is disposed so as to cover the conductive resin layer 60. The plating layer 70 includes a Ni plating layer 71 and a Sn plating layer 72.

[0074] The conductive resin layer 60 includes a resin portion and a conductive filler dispersed in the resin portion.

[0075] The resin portion of the conductive resin layer 60 may also include at least one selected from various known thermosetting resins such as epoxy resin, phenoxy resin, phenolic resin, polyurethane resin, silicone resin, polyimide resin, etc. Among them, epoxy resin with excellent heat resistance, moisture resistance, adhesion, etc. is one of the most suitable resins. In addition, the resin portion of the conductive resin layer 60 preferably includes a curing agent together with the thermosetting resin. When epoxy resin is used as the base resin, the curing agent of the epoxy resin may also be various known compounds such as phenol, amine, anhydride, imidazole, active ester, and amide-imide.

[0076] Since the conductive resin layer 60 includes such a resin portion, it is more flexible than the base electrode layer 50 which is a plated film or a fired product including a metal component and a glass component. Therefore, even when a physical impact or an impact caused by a thermal cycle is applied to the multilayer ceramic capacitor 1, the conductive resin layer 60 functions as a buffer layer. Therefore, the conductive resin layer 60 suppresses the occurrence of cracks in the multilayer ceramic capacitor 1.

[0077] The conductive filler is dispersed in the resin portion with a substantially uniform distribution. The conductive filler is mainly responsible for the electrical conductivity of the conductive resin layer 60. Specifically, a plurality of conductive fillers are in contact with each other, thereby forming an electrical path inside the conductive resin layer 60, and the base electrode layer 50 and the plated layer 70 are electrically connected.

[0078] The metal constituting the conductive filler may be Ag alone, or an alloy containing Ag, or a metal powder coated with Ag on the surface of the metal powder. Ag has the lowest resistivity among metals, so it is suitable for electrode materials. In addition, since Ag is a noble metal, it is not easily oxidized and has high weather resistance. Therefore, Ag metal powder is suitable as a conductive filler. In addition, when using a conductive filler coated with Ag on the surface of the metal powder, it is preferred to use Cu, Ni, Sn, Bi or alloy powders containing them as the metal powder.

[0079] Furthermore, the conductive filler may be a conductive filler in which Cu or Ni has been subjected to an oxidation resistance treatment. In addition, the conductive filler may be a metal powder in which Sn, Ni or Cu is coated on the surface of the metal powder. When a conductive filler in which Sn, Ni or Cu is coated on the surface of the metal powder is used, the metal powder is preferably Ag, Cu, Ni, Sn, Bi or an alloy powder thereof.

[0080] The shape of the conductive filler is not particularly limited. The conductive filler may be a spherical or flat conductive filler, but it is preferred to use a mixture of spherical metal powder and flat metal powder.

[0081] The average particle diameter of the conductive filler may be, for example, 0.3 μm or more and 10 μm or less.

[0082] The average particle size of the conductive filler included in the conductive resin layer 60 is measured by calculation using a laser diffraction particle size measurement method based on ISO 13320, regardless of the shape of the conductive filler.

[0083] The plating layer 70 includes a first plating layer 70A and a second plating layer 70B.

[0084] The first plating layer 70A is configured to cover the first conductive resin layer 60A. In the present embodiment, the first plating layer 70A is configured to extend from the first end surface LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2. More specifically, with respect to the first plating layer 70A, the first end surface side Ni plating layer 71A1 is configured on the first end surface LS1, and the first side surface side Ni plating layer 71A2 is configured to extend from the first end surface LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0085] The second plating layer 70B is configured to cover the second conductive resin layer 60B. In the present embodiment, the second plating layer 70B is configured to extend from the first end surface LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2. More specifically, with respect to the second plating layer 70B, the second end surface side Ni plating layer 71B1 is configured on the second end surface LS2, and the second side surface side Ni plating layer 71B2 is configured to extend from the second end surface LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0086] The plating layer 70 is preferably a two-layer structure of a Ni plating layer 71 and a Sn plating layer 72. Preferably, a first Sn plating layer 72A is arranged on the first Ni plating layer 71A, and preferably, a second Sn plating layer 72B is arranged on the second Ni plating layer 71B. The Ni plating layer 71 prevents the base electrode layer 50 and the conductive resin layer 60 from being corroded by the solder when the multilayer ceramic capacitor 1 is mounted. The Sn plating layer 72 improves the wettability of the solder when the multilayer ceramic capacitor 1 is mounted. As a result, the mounting of the multilayer ceramic capacitor 1 becomes easy.

[0087] The thickness of each of the first Ni plating layer 71A and the first Sn plating layer 72A is preferably 1 μm or more and 15 μm or less.

[0088] The thickness of each of the second Ni plating layer 71B and the second Sn plating layer 72B is preferably 1 μm or more and 15 μm or less.

[0089] Figure 5 yes Figure 2 The enlarged view of the V portion of the multilayer ceramic capacitor 1 shown in FIG. 1 is a schematic diagram for explaining the state of the force generated on the end surface LS side of the multilayer ceramic capacitor 1. As described above, since the basic structure of the first Ni plating 71A and the second Ni plating 71B is the same, Figure 5, they are collectively described as Ni plating 71. In addition, the same applies to other layers constituting the first external electrode 40A and the second external electrode 40B. Figure 5 As shown, the conductive resin layer 60 is disposed on the base electrode layer 50. Furthermore, a plating layer 70 described later is disposed so as to cover the conductive resin layer 60. The plating layer 70 includes a Ni plating layer 71 and a Sn plating layer 72. The Ni plating layer 71 includes an end surface side Ni plating layer 711 and a side surface side Ni plating layer 712.

[0090] The Ni plating layer 71 is formed so as to generate tensile stress uniformly in the direction intersecting with the thickness direction of the plating layer 70. In other words, tensile stress remains as internal stress inside the Ni plating layer 71. The end surface side Ni plating layer 711 generates tensile stress in the direction intersecting with the thickness direction of the plating layer 70, and the end surface side Ni plating layer 711 will shrink in the direction intersecting with the thickness direction of the plating layer 70. Figure 5 As shown in the figure, the side Ni plating layers 712 formed on both ends of the end surface Ni plating layer 711 are stretched toward the center of the end surface Ni plating layer 711. That is, the side Ni plating layers 712 formed on both sides of the end surface Ni plating layer 711 are subjected to forces in the direction of pressing the conductive resin layer 60 toward the base electrode layer 50. As a result, the conductivity of the conductive resin layer 60 is improved, and the effect of reducing ESR (Equivalent Series Resistance) is produced.

[0091] In addition, the side Ni plating layer 712 generates tensile stress in the direction intersecting with the thickness direction of the plating layer 70, so that the side Ni plating layer 712 contracts in the direction intersecting with the thickness direction of the plating layer 70. Therefore, the side Ni plating layer 712 is tightly fixed to the conductive resin layer 60 in the circumferential direction of the side Ni plating layer 712, and the end surface Ni plating layer 711 is stretched in the longitudinal direction L to press the conductive resin layer 60 against the base electrode layer 50. As a result, the conductivity of the conductive resin layer 60 is improved, and the ESR is reduced.

[0092] Furthermore, the tensile stress is preferably 50 MPa or more, thereby further improving the ESR reduction effect.

[0093] If the stress of the Ni plating layer 71 exceeds 206 MPa, it becomes difficult to manufacture the multilayer ceramic capacitor 1, so the tensile stress is preferably 206 MPa or less. This makes it easier to manufacture the multilayer ceramic capacitor 1 while further improving the ESR reduction effect.

[0094] In addition, if the dimension in the length direction of the multilayer ceramic capacitor 1 including the stacked body 10 and the external electrode 40 is set to L dimension, the L dimension is preferably 0.2 mm or more and 10 mm or less. In addition, if the dimension in the stacking direction of the multilayer ceramic capacitor 1 is set to T dimension, the T dimension is preferably 0.1 mm or more and 10 mm or less. In addition, the dimension in the width direction of the multilayer ceramic capacitor 1 is set to W dimension. The W dimension is preferably 0.1 mm or more and 10 mm or less.

[0095] Next, a method for manufacturing the multilayer ceramic capacitor 1 according to the present embodiment will be described.

[0096] A dielectric sheet for the dielectric layer 20 and a conductive paste for the internal electrode layer 30 are prepared. The dielectric sheet and the conductive paste for the internal electrode contain a binder and a solvent. The binder and the solvent may be known binders and solvents.

[0097] On the dielectric sheet, a conductive paste for the internal electrode layer 30 is printed in a predetermined pattern by, for example, screen printing or gravure printing. Thus, a dielectric sheet having a pattern of the first internal electrode layer 31 and a dielectric sheet having a pattern of the second internal electrode layer 32 are prepared.

[0098] By stacking a predetermined number of dielectric sheets without printing the pattern of the internal electrode layer, a portion of the first main surface side outer layer portion 12A on the first main surface TS1 side is formed. By stacking a dielectric sheet with a pattern of the first internal electrode layer 31 printed thereon and a dielectric sheet with a pattern of the second internal electrode layer 32 printed thereon in sequence, a portion of the inner layer portion 11 is formed. By stacking a predetermined number of dielectric sheets without printing the pattern of the internal electrode layer on the portion that becomes the inner layer portion 11, a portion of the second main surface side outer layer portion 12B on the second main surface TS2 side is formed. In this way, a laminated sheet is produced.

[0099] The laminated sheets are pressed in the laminating direction by isostatic pressing or the like, thereby producing a laminated block.

[0100] The stacked blocks are cut into predetermined sizes to produce stacked small pieces. At this time, the corners and ridges of the stacked small pieces may be rounded by barrel grinding or the like.

[0101] The stacked small pieces are fired to produce the stacked body 10. The firing temperature depends on the materials of the dielectric layer 20 and the internal electrode layer 30, but is preferably 900°C or higher and 1400°C or lower.

[0102] A conductive paste that becomes the base electrode layer 50 is applied to both end surfaces of the laminate 10. In the present embodiment, the base electrode layer 50 is a sintered layer. For example, a conductive paste containing a glass component and a metal is applied to the laminate 10 by a method such as dipping. Then, a sintering treatment is performed to form the base electrode layer 50. The temperature of the sintering treatment at this time is preferably 700° C. or higher and 950° C. or lower.

[0103] Next, the conductive resin layer 60 is formed. The conductive resin layer 60 may be formed on the surface of the foundation electrode layer 50 or may be directly formed on the laminated body 10. In the present embodiment, the conductive resin layer 60 is formed on the surface of the foundation electrode layer 50.

[0104] First, a conductive resin paste is prepared in which a conductive filler is dispersed in a thermosetting resin as a base resin that becomes a resin portion. The conductive resin paste is produced by stirring and mixing the thermosetting resin and the conductive filler. Therefore, the conductive filler is dispersed in the conductive resin paste in a uniform distribution. Here, the thermosetting resin is, for example, epoxy resin. The conductive filler is, for example, Ag metal powder.

[0105] Then, the conductive resin paste is applied to the base electrode layer 50 by the dipping method, and a heat treatment is performed at a temperature of 200° C. to 550° C. As a result, the resin portion is thermally cured to form the conductive resin layer 60. The atmosphere during the heat treatment is preferably an N2 atmosphere. In addition, in order to prevent the scattering of the resin and the oxidation of various metal components, the oxygen concentration is preferably suppressed to 100 ppm or less.

[0106] Then, a plating layer 70 is formed on the surface of the conductive resin layer 60. In this embodiment, a Ni plating layer 71 and a Sn plating layer 72 are formed on the conductive resin layer 60. The Ni plating layer 71 and the Sn plating layer 72 are formed sequentially by electroplating. As a plating method, for example, barrel plating is preferably used.

[0107] In addition, the stress generated in the entire first Ni plating layer 71A and the second Ni plating layer 71B of the present invention can be controlled by the following method.

[0108] In addition, it is known that the stress generated by plating varies according to the current density applied during film formation. The current density applied to the multilayer ceramic capacitor 1 is random. At the front end of the Ni-plated layer located on the first main surface TS1 or the second main surface TS2 or the first side WS1 or the second side WS2, the average current density applied to each front end from the initial film formation of the Ni plating to a thickness of, for example, 3 μm is the same on any surface of the front end of the Ni-plated layer located on the first main surface TS1 or the second main surface TS2 or the first side WS1 or the second side WS2. Therefore, the same stress is applied to any surface of the Ni-plated layer 70 on the first main surface TS1, the second main surface TS2, the first side WS1, and the second side WS2.

[0109] The first Ni layer 71A and the second Ni plating layer 71B can be formed by, for example, using a plating bath of a plating solution prepared by adjusting the input amounts of Ni sulfate and Ni sulfamate. By adjusting the ratio of Ni sulfate and Ni sulfamate in the plating solution, the residual stress value inside the formed Ni plating layer 71 can be adjusted.

[0110] In the present embodiment, a Sn plating layer 72 is further formed on the Ni plating layer 71, a first Sn plating layer 72A is formed on the first Ni plating layer 71A, and a second Sn plating layer 72B is formed on the second Ni plating layer 71B. As a method for forming the Sn plating layer 72, an electrolytic plating method is used. As a plating method, roller plating is preferably used. Thus, when the multilayer ceramic capacitor 1 is installed, the wettability of the solder used for installation can be improved, and installation can be easily performed. The multilayer ceramic capacitor 1 is manufactured by the above manufacturing method.

[0111] According to the multilayer ceramic capacitor 1 of the present embodiment, the following effects are achieved.

[0112] In recent years, ceramic electronic components, such as multilayer ceramic capacitors, have been used in harsher environments than before. For example, electronic components used in mobile devices such as mobile phones and portable music players are required to withstand the impact of being dropped. Specifically, it is necessary that even if the electronic components are subjected to the impact of being dropped, the electronic components do not fall off the mounting substrate, or cracks do not occur in the electronic components.

[0113] Furthermore, electronic components used in vehicle-mounted devices such as ECUs (Electronic Control Units) are required to withstand the impact of thermal cycles. Specifically, they must not crack even when subjected to flexural stress caused by thermal expansion and contraction of the mounting substrates during thermal cycles.

[0114] Therefore, as a countermeasure to prevent cracks from occurring in the ceramic electronic component body even in a severe environment, it has been proposed to use a thermosetting conductive resin paste for the external electrodes of the ceramic electronic component. For example, an epoxy-based thermosetting resin layer is formed between a conventional electrode layer and a Ni plating layer.

[0115] In such a structure, when stress is caused by the impact when it is dropped or flexural stress is generated due to thermal expansion and contraction of the mounting substrate caused by thermal cycles, the epoxy-based thermosetting resin layer releases the stress transmitted to the mounting substrate due to the deformation of the mounting substrate, thereby suppressing the generation of cracks in the ceramic electronic component body.

[0116] However, in the multilayer ceramic electronic component as disclosed in Patent Document 1, there is no definition of stress in the Ni plating layer disposed on the conductive resin layer.

[0117] In the present invention, by leaving a tensile stress inside the Ni plating layer, the Ni plating layer presses the conductive resin layer toward the base electrode layer, the conductive resin layer is compressed, and the contact amount between the conductive fillers in the conductive resin layer increases, so that the conductivity of the conductive resin layer can be improved. Therefore, a laminated ceramic electronic component with reduced ESR and improved initial characteristics can be provided.

[0118] (1) A laminated ceramic capacitor 1 (laminated ceramic electronic component 1) according to the present embodiment comprises: a laminate 10 including a plurality of laminated dielectric layers 20 (ceramic layers 20), and having a first main surface TS1 and a second main surface TS2 opposite to each other in a lamination direction T, a first side surface WS1 and a second side surface WS2 opposite to each other in a width direction W perpendicular to the lamination direction T, and a first end surface LS1 and a second end surface LS2 opposite to each other in a length direction L perpendicular to the lamination direction T and the width direction W; a first internal electrode layer 31 (first internal conductor layer 31) arranged on the plurality of dielectric layers 20 and exposed on the first end surface LS1; a second internal electrode layer 32 (second internal conductor layer 32) arranged on the plurality of dielectric layers 20 and exposed on the second end surface LS2; and a first external electrode 40A arranged on the first end surface LS1. On; and a second external electrode 40B, arranged on the second end face LS2, wherein the first external electrode 40A has a first base electrode layer 50A including a metal component, a first conductive resin layer 60A including a thermosetting resin and a metal component arranged on the first base electrode layer 50A, and a first Ni plating layer 71A arranged on the first conductive resin layer 60A, the second external electrode 40B has a second base electrode layer 50B including a metal component, a second conductive resin layer 60B including a thermosetting resin and a metal component arranged on the second base electrode layer 50B, and a second Ni plating layer 71B arranged on the second conductive resin layer 60B, tensile stress remains in the first Ni plating layer 71A as internal stress, and tensile stress remains in the second Ni plating layer 71B as internal stress.

[0119] Thus, a multilayer ceramic electronic component capable of reducing ESR can be provided.

[0120] (2) In the multilayer ceramic capacitor 1 of the present embodiment, the tensile stress generated in the first Ni plating layer 71A and the second Ni plating layer 71B is 50 MPa or more.

[0121] This can further reduce the ESR.

[0122] (3) The multilayer ceramic capacitor 1 of the present embodiment includes the first Sn plating layer 72A disposed on the first Ni plating layer 71A, and the second Sn plating layer 72B disposed on the second Ni plating layer 71B.

[0123] This can improve solder wettability and reduce ESR.

[0124] (4) In the multilayer ceramic capacitor 1 of the present embodiment, the first foundation electrode layer 50A includes a glass component or a ceramic component, and the second foundation electrode layer 50B includes a glass component or a ceramic component.

[0125] This can improve the adhesion between the laminate and the base electrode layer and reduce the ESR.

[0126] <Example>

[0127] Using the manufacturing method involved in the above embodiment, a Figure 1 to Figure 4 As samples of the embodiments and comparative examples, multilayer ceramic capacitors with structures of are used. In addition, regarding the samples, the stress of the Ni plating layer is controlled by the method described in the above-mentioned manufacturing method so as to become the stress described in Table 1 to produce the samples, and 22 samples are produced under each stress condition. The specifications of the multilayer ceramic capacitors are as follows.

[0128] · Dimensions of multilayer ceramic capacitors: 3.2 mm (length direction L) × 2.5 mm (width direction W) × 2.5 mm (stacking direction T)

[0129] Ceramic material: BaTiO3

[0130] Electrostatic capacitance: 0.01μF

[0131] Rated voltage: 50V

[0132] ·External electrode structure

[0133] (1) Base electrode layer: an electrode containing conductive metal (Cu) and glass components

[0134] Thickness of the base electrode layer at the center of the base electrode layer in the height direction located at the first end surface and the second end surface: 15 μm

[0135] Thickness of the underlying electrode layer at the center of the underlying electrode layer in the longitudinal direction on the first and second principal surfaces, the first and second side surfaces: 4 μm

[0136] (2) Conductive resin layer

[0137] Conductive resin layer: Conductive filler: Ag

[0138] Resin: Epoxy

[0139] Thermal curing temperature: 200°C

[0140] Thickness of the first conductive resin layer located at the first end face and the second end face at the center in the height direction: 20 μm

[0141] Thickness of the underlying electrode layer at the center of the length direction of the underlying electrode layer on the first and second principal surfaces, the first and second side surfaces: 20 μm

[0142] (3) Ni plating layer

[0143] Thickness of Ni plating layer: The thickness of the Ni plating layer at the central part in the height direction of the Ni plating layer on the first end face and the second end face: 2 μm

[0144] Thickness of Ni plating layer: The thickness of the Ni plating layer at the central part in the longitudinal direction of the Ni plating layer on the first main surface, the second main surface, the first side surface and the second side surface: 2.0 μm

[0145] (4)Sn plating layer

[0146] Thickness of Sn plating layer: The thickness of the Sn plating layer at the central part in the height direction of the Sn plating layer on the first end face and the second end face: 1.5 μm

[0147] Thickness of Sn plating layer: The thickness of the Sn plating layer at the central part in the longitudinal direction of the Sn plating layer on the first main surface, the second main surface, the first side surface and the second side surface: 1.0 μm

[0148] Next, for the samples of the examples and comparative examples, stress measurement and ESR measurement of Ni plating were carried out. Different multilayer ceramic capacitors among the multilayer ceramic capacitors manufactured in the same batch were used for stress measurement and ESR measurement of Ni plating. For the stress measurement of the Ni plating layer, the average value of the data with n = 2 was used as the measurement result. For the ESR of each of the examples and comparative examples, the average value of the data with n = 20 at a measurement frequency of 1 MHz was used as the measurement result. Moreover, as a judgment criterion, a value with an ESR of 8 mΩ or less was judged as "〇", a value with an ESR of 10 mΩ or less was judged as "△", and a value with an ESR greater than 10 mΩ was judged as "×".

[0149] [Table 1]

[0150]

[0151] <Stress measurement of Ni plating>

[0152] Hereinafter, the stress measurement of Ni plating in this example will be described. The stress of the Ni plating layer was measured by the following method.

[0153] First, the multilayer ceramic capacitor 1 was immersed in a metal stripper (Melstrip (registered trademark) HN980M manufactured by Meltex Co., Ltd.) liquid for 5 minutes, and then washed with water to remove the Sn plating layer. The Ni plating layers on the first end surface LS1 side and the second end surface LS2 side of the multilayer ceramic capacitor 1 were measured using X-ray diffraction (μ-XRD (X-ray Diffraction)) in the range of φ100μm at approximately the middle of the surface of the Ni plating layers on the first main surface TS1 and the second main surface TS2 and on the first side surface WS1 and the second side surface WS2.

[0154] In more detail, the stress of the Ni plating layer on the first main surface TS1 was measured by taking the positions of the center of the length direction L and the center of the width direction W of the first Ni plating layer 71A and the second Ni plating layer 71B on the first main surface TS1 as the object. In addition, the stress of the Ni plating layer on the second main surface TS2 was measured by taking the positions of the center of the length direction L and the center of the width direction W of the first Ni plating layer 71A and the second Ni plating layer 71B on the second main surface TS2 as the object. In addition, the stress of the Ni plating layer on the first side surface WS1 was measured by taking the positions of the center of the length direction L and the center of the stacking direction T of the first Ni plating layer 71A and the second Ni plating layer 71B on the first side surface WS1 as the object. In addition, the stress of the Ni plating layer on the second side surface WS2 was measured by taking the positions of the center of the length direction L and the center of the stacking direction T of the first Ni plating layer 71A and the second Ni plating layer 71B on the second side surface WS2 as the object. The two prepared samples were measured, and the average value of the measured values ​​at the above eight locations was taken as the measured value of stress.

[0155] <Measurement of ESR of Multilayer Ceramic Capacitors>

[0156] The following is an explanation of the measurement of ESR in this embodiment. For the measurement of ESR of the multilayer ceramic capacitor 1, the multilayer ceramic capacitor 1 was heat treated at 150°C for 1 hour in an air atmosphere before the measurement, and then mounted on a measurement substrate. 24±2 hours after the completion of the heat treatment, the measurement frequency was set to 1 MHz and the measurement was performed using a network analyzer. The 20 samples prepared were measured, and the average value was used as the value in Table 1 above.

[0157] Based on the above results, it is shown that in the present invention, by setting the stress of the Ni plating layer arranged on the conductive resin layer to a tensile stress, the Ni plating presses the conductive resin layer toward the base electrode layer side, the conductive resin layer is compressed, and the contact amount between the conductive fillers in the conductive resin layer is increased, which has the effect of improving the conductivity of the conductive resin layer.

[0158] Furthermore, by setting the stress of the Ni plating layer to 50 MPa or more, the effects of the present invention can be made more significant, and a multilayer ceramic capacitor having improved initial characteristics can be provided.

[0159] The structure of the multilayer ceramic capacitor 1 is not limited to Figures 1 to 4 For example, the multilayer ceramic capacitor 1 may also be Figure 6 , Figure 7 , Figure 8 As shown, there are multilayer ceramic capacitors with a 2-cell structure, a 3-cell structure, and a 4-cell structure.

[0160] Figure 6 The illustrated multilayer ceramic capacitor 1 is a dual-structure multilayer ceramic capacitor 1 and includes, as the internal electrode layer 30 , a floating internal electrode layer 35 that is not led out to either the first end surface LS1 or the second end surface LS2 in addition to the first internal electrode layer 33 and the second internal electrode layer 34 . Figure 7 The illustrated multilayer ceramic capacitor 1 is a multilayer ceramic capacitor 1 of a triple structure including a first floating internal electrode layer 35A and a second floating internal electrode layer 35B as floating internal electrode layers 35 . Figure 8 The multilayer ceramic capacitor 1 shown is a multilayer ceramic capacitor 1 having a four-connection structure including a first floating internal electrode layer 35A, a second floating internal electrode layer 35B, and a third floating internal electrode layer 35C as floating internal electrode layers 35. In this way, by providing a floating internal electrode layer 35 as an internal electrode layer 30, the multilayer ceramic capacitor 1 has a structure in which the opposing electrode portion is divided into a plurality of parts. Thus, a plurality of capacitor components are formed between the opposing internal electrode layers 30, and these capacitor components are connected in series. Therefore, the voltage applied to each capacitor component becomes lower, and a high withstand voltage of the multilayer ceramic capacitor 1 can be sought. In addition, it is self-evident that the multilayer ceramic capacitor 1 of this embodiment can also be a multi-connection structure of four or more.

[0161] Furthermore, the multilayer ceramic capacitor 1 may be a two-terminal multilayer ceramic capacitor having two external electrodes, or may be a multi-terminal multilayer ceramic capacitor having a large number of external electrodes.

[0162] In addition, in the above-mentioned embodiment, as a laminated ceramic electronic component, a laminated ceramic capacitor in which the dielectric layer 20 composed of dielectric ceramics is used as a ceramic layer is exemplified. However, the laminated ceramic electronic component disclosed in the present invention is not limited to this. For example, the ceramic electronic component disclosed in the present invention can also be applied to various laminated ceramic electronic components such as piezoelectric components using piezoelectric ceramics as ceramic layers, thermistors using semiconductor ceramics as ceramic layers, and inductors using magnetic ceramics as ceramic layers. Piezoelectric ceramics include PZT (lead zirconate titanate) ceramics, semiconductor ceramics include spinel ceramics, and magnetic ceramics include ferrite ceramics.

[0163] The present invention is not limited to the configuration of the above-described embodiment, and can be applied with appropriate changes within the scope of the present invention. In addition, a configuration obtained by combining two or more of the desired configurations described in the above-described embodiment also constitutes the present invention.

[0164] <1>

[0165] A laminated ceramic electronic component comprising:

[0166] A laminated body comprising a plurality of laminated ceramic layers, and having a first main surface and a second main surface opposite to each other in a height direction, a first side surface and a second side surface opposite to each other in a width direction perpendicular to the height direction, and a first end surface and a second end surface opposite to each other in a length direction perpendicular to the height direction and the width direction;

[0167] a first internal conductor layer, disposed on the plurality of ceramic layers and exposed at the first end surface;

[0168] a second internal conductor layer, disposed on the plurality of ceramic layers and exposed at the second end surface;

[0169] a first external electrode disposed on the first end surface; and

[0170] a second external electrode disposed on the second end surface,

[0171] in,

[0172] The first external electrode comprises: a first base electrode layer including a metal component, a first conductive resin layer including a thermosetting resin and a metal component disposed on the first base electrode layer, and a first Ni plating layer disposed on the first conductive resin layer.

[0173] The second external electrode comprises: a second base electrode layer including a metal component, a second conductive resin layer including a thermosetting resin and a metal component disposed on the second base electrode layer, and a second Ni plating layer disposed on the second conductive resin layer.

[0174] In the first Ni plating layer, tensile stress remains as internal stress.

[0175] In the second Ni plating layer, tensile stress remains as internal stress.

[0176] <2>

[0177] exist <1> In the described multilayer ceramic electronic component,

[0178] The tensile stress is greater than 50 MPa.

[0179] <3>

[0180] exist <1> or <2> In the described multilayer ceramic electronic component,

[0181] A first Sn plating layer is arranged on the first Ni plating layer,

[0182] A second Sn plating layer is disposed on the second Ni plating layer.

[0183] <4>

[0184] exist <1> to <3> In the multilayer ceramic electronic component described in any one of

[0185] The first base electrode layer includes a glass component or a ceramic component.

[0186] The second base electrode layer includes a glass component or a ceramic component.

[0187] Description of Reference Numerals

[0188] 1: Multilayer ceramic capacitors (multilayer ceramic electronic components);

[0189] 10: laminate;

[0190] 20: dielectric layer (ceramic layer);

[0191] 31: first internal electrode layer (first internal conductor layer);

[0192] 32: second internal electrode layer (second internal conductor layer);

[0193] 40A: 1st external electrode;

[0194] 40B: second external electrode;

[0195] 50A: 1st base electrode layer;

[0196] 50B: second base electrode layer;

[0197] 60A: first conductive resin layer;

[0198] 60B: second conductive resin layer;

[0199] 71A: 1st Ni plating layer;

[0200] 71B: second Ni plating layer;

[0201] T: height direction;

[0202] TS1: 1st main surface;

[0203] TS2: 2nd main surface;

[0204] W: width direction;

[0205] WS1: side 1;

[0206] WS2: side 2;

[0207] L: length direction;

[0208] LS1: 1st end face;

[0209] LS2: Second end face.

Claims

1. A laminated ceramic electronic component comprising: A laminated body comprising a plurality of laminated ceramic layers, and having a first main surface and a second main surface opposite to each other in a height direction, a first side surface and a second side surface opposite to each other in a width direction perpendicular to the height direction, and a first end surface and a second end surface opposite to each other in a length direction perpendicular to the height direction and the width direction; a first internal conductor layer, disposed on the plurality of ceramic layers and exposed at the first end surface; a second internal conductor layer, disposed on the plurality of ceramic layers and exposed at the second end surface; a first external electrode disposed on the first end surface; and a second external electrode disposed on the second end surface, in, The first external electrode comprises: a first base electrode layer including a metal component, a first conductive resin layer including a thermosetting resin and a metal component disposed on the first base electrode layer, and a first Ni plating layer disposed on the first conductive resin layer. The second external electrode comprises: a second base electrode layer including a metal component, a second conductive resin layer including a thermosetting resin and a metal component disposed on the second base electrode layer, and a second Ni plating layer disposed on the second conductive resin layer. In the first Ni plating layer, tensile stress remains as internal stress. In the second Ni plating layer, tensile stress remains as internal stress.

2. The multilayer ceramic electronic component according to claim 1, wherein The tensile stress is greater than 50 MPa.

3. The multilayer ceramic electronic component according to claim 1 or 2, wherein: A first Sn plating layer is arranged on the first Ni plating layer, A second Sn plating layer is disposed on the second Ni plating layer.

4. The multilayer ceramic electronic component according to any one of claims 1 to 3, wherein The first base electrode layer includes a glass component or a ceramic component. The second base electrode layer includes a glass component or a ceramic component.

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