Semiconductor power module

Abstract

In a general aspect, a power module package (400) includes a substrate (105) having a ceramic layer (105a) having a first major surface and a second major surface opposite the first major surface. The substrate also includes a patterned metal layer (110) disposed on the first major surface. The package further includes a first plurality of semiconductor dies (120) disposed on a first portion (110a) of the patterned metal layer. The first plurality of semiconductor dies is linearly arranged along a first axis (120a). The package also includes a second plurality of semiconductor dies (125) disposed on a second portion (110b) of the patterned metal layer. The second plurality of semiconductor dies is linearly arranged along a second axis (125a) parallel to the first axis.

Description

Technical Field

[0001] The present invention relates to semiconductor device assemblies and more particularly to packaged power semiconductor device circuits. Background Art

[0002] Semiconductor devices (e.g., semiconductor dies) may be included in a package assembly or module package, where such an assembly may include one or more semiconductor dies. For example, a power semiconductor device package may implement multiple circuits, such as a half-bridge circuit including multiple semiconductor dies. Some considerations in the design and production of such power semiconductor device packages include factors such as material costs for different numbers of semiconductor dies and the ease of package scaling. In addition, with respect to the performance of such power semiconductor device packages, the reduction of parasitic impedances such as stray inductance is an important consideration. Summary of the invention

[0003] In general terms, a power module package includes: a substrate having a ceramic layer, the ceramic layer having a first main surface and a second main surface opposite to the first main surface. The substrate also includes a patterned metal layer disposed on the first main surface. The power module package also includes: a first plurality of semiconductor dies, the first plurality of semiconductor dies are disposed on a first portion of the patterned metal layer. The first plurality of semiconductor dies are linearly arranged along a first axis. The power module package also includes: a second plurality of semiconductor dies, the second plurality of semiconductor dies are disposed on a second portion of the patterned metal layer. The second plurality of semiconductor dies are linearly arranged along a second axis parallel to the first axis. The power module package also includes: a plurality of power terminals, the plurality of power terminals are arranged on a first edge of the power module package. The first edge is parallel to the first axis and the second axis. The power module package also includes: a switch node terminal, the switch node terminal is arranged on a second edge of the package. The second edge is opposite and parallel to the first edge. The power module package includes: a first plurality of signal pins, the first plurality of signal pins are located on a third edge of the package. The third edge is orthogonal to the first edge and the second edge. The power module package also includes: a second plurality of signal pins, the second plurality of signal pins are located on a fourth edge of the package. The fourth edge is opposite to and parallel to the third edge.

[0004] In another general aspect, a power module package includes: a substrate including a patterned metal layer disposed thereon; and a first plurality of semiconductor dies disposed on a first portion of the patterned metal layer. The first plurality of semiconductor dies includes a first plurality of power transistors arranged linearly along a first axis. The power module package also includes: a second plurality of semiconductor dies disposed on a second portion of the patterned metal layer. The second plurality of semiconductor dies includes a second plurality of transistors arranged linearly along a second axis parallel to the first axis. The power module package also includes: a first plurality of conductive clips, the first plurality of conductive clips coupling the first plurality of power transistors to a third portion of the patterned metal layer disposed between the first portion of the patterned metal layer and the second portion of the patterned metal layer, respectively. The third portion of the patterned metal layer is arranged along a third axis parallel to the first axis and the second axis. The power module package also includes: a second plurality of conductive clips, the second plurality of conductive clips coupling the second plurality of power transistors to a fourth portion of the patterned metal layer disposed between the second portion of the patterned metal layer and the third portion of the patterned metal layer, respectively. A fourth portion of the patterned metal layer is arranged along a fourth axis that is parallel to the first axis, the second axis, and the third axis.

[0005] In another general aspect, a method for producing a power module package includes: coupling a first plurality of semiconductor die to a first portion of a patterned metal layer and a second portion of the patterned metal layer in a substrate, wherein the first plurality of high-side semiconductor die are linearly arranged on the substrate along a first axis. The method also includes: coupling a second plurality of semiconductor die to a third portion of the patterned metal layer and a fourth portion of the patterned metal layer, wherein the second plurality of semiconductor die are linearly arranged on the substrate along a second axis parallel to the first axis. The method also includes: coupling a plurality of power terminals to the substrate, wherein the plurality of power terminals are arranged on a first edge of the power module package, the first edge being parallel to the first axis and the second axis. The method also includes: coupling a switch node terminal to the substrate, wherein the switch node terminal is arranged on a second edge of the power module package, the second edge being opposite and parallel to the first edge. The method also includes: coupling a lead frame to the substrate; and forming corresponding wire bonds coupling the lead frame to the plurality of high-side semiconductor switches and the plurality of low-side semiconductor switches. The method further includes: coupling a first plurality of signal pins to corresponding portions of the lead frame, wherein the first plurality of signal pins are located on a third edge of the power module package, the third edge being orthogonal to the first edge and the second edge. The method further includes: coupling a second plurality of signal pins to corresponding portions of the lead frame, wherein the second plurality of signal pins are located on a fourth edge of the power module package, the fourth edge being opposite and parallel to the third edge. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a schematic diagram illustrating an example substrate assembly of a semiconductor device module package.

[0007] Figure 2 is a schematic diagram illustrating an example substrate assembly of another semiconductor device module package.

[0008] Figure 3 is a schematic diagram illustrating an example substrate assembly of yet another semiconductor device module package.

[0009] FIG. 4A to FIG. 4E are schematic diagrams illustrating various views of an example semiconductor device module package.

[0010] Figure 5 is a schematic diagram illustrating another example semiconductor device module package.

[0011] Fig. 6A and Figure 6B For example 4A to 4D Schematic diagram of current flow in a semiconductor device module package.

[0012] Figure 7is a flow chart illustrating an example method for producing a power module package.

[0013] The same reference numerals in the various drawings indicate the same elements. Reference numerals for some similar elements may not be repeated for all such elements. In some cases, different reference numerals may be used for the same or similar elements. Some reference numerals for some elements of a given implementation may not be repeated in each of the drawings corresponding to that implementation. Some reference numerals for some elements of a given implementation may be repeated in other drawings corresponding to that implementation, but may not be specifically discussed with reference to each corresponding drawing. The drawings are for the purpose of illustrating example implementations and may not necessarily be drawn to scale. DETAILED DESCRIPTION

[0014] The present disclosure relates to packaged semiconductor device devices, which may be referred to as packaged modules, semiconductor device module packages, power semiconductor device module packages, and / or packages. Such semiconductor device module packages may include, for example, half-bridge circuits, full-bridge circuits, or other circuits. For purposes of illustration and by way of example, the specific implementations described herein are for half-bridge circuits. Such half-bridge circuits may include a plurality of high-side semiconductor switches (e.g., power transistors) connected in parallel to each other and a plurality of low-side semiconductor switches (e.g., power transistors) connected in parallel to each other. In some specific implementations, the methods illustrated and described herein may be used to implement semiconductor device modules including circuits other than half-bridge circuits.

[0015] Compared with existing methods, the methods described and illustrated herein can reduce material costs, achieve direct package scaling, and reduce parasitic impedances such as stray inductance. For example, the example half-bridge circuit package implementation described herein includes a plurality of high-side transistors arranged in a single row, and a plurality of low-side transistors arranged in a single row in parallel with the row of high-side transistors. In addition, in the example implementation described herein, the power terminal is arranged on or along the first edge of the package body. For example, the first edge is an edge close to the row of high-side transistors. At the same time, in the example implementation described herein, the switch node terminal is arranged on or along the second edge of the package body opposite to the first edge. For example, the second edge is an edge close to the row of low-side transistors. Furthermore, in the disclosed example implementation, the signal pin is arranged along the third edge and / or the fourth edge of the package body, wherein the third edge and the fourth edge are orthogonal to the first edge and the second edge.

[0016] The example implementations described herein achieve efficient use of substrate space, thereby helping to reduce material costs compared to existing comparable circuit implementations. For example, such module packages may include a direct bonded metal (DBM) substrate, such as a direct bonded copper (DBC) substrate, which may be a major component of the material cost of such packages. Therefore, compared to the aforementioned comparable module packages, a reduction in material cost can be achieved by reducing the size of the substrate. By way of example, such substrates may include a ceramic base or a ceramic layer on which a patterned or non-patterned metal layer may be formed. In some implementations, the DBM substrate may be configured as a printed circuit board having circuit traces, conductive vias, and the like.

[0017] In addition, such an arrangement also facilitates direct scaling of the associated package for different numbers of high-side switches and low-side switches. For example, the methods described herein facilitate scaling in a single axis or direction. That is, the substrate and the overall size of the package can be increased or decreased along a single axis to accommodate a desired number of low-side and high-side semiconductor switch (e.g., power transistor) dies, respectively. The illustrated and described example arrangements also allow for the implementation of current paths (e.g., path length and direction), which can also facilitate the implementation of low parasitic impedances such as low stray inductance.

[0018] Figure 1 1 is a schematic diagram of an exemplary substrate assembly 100 illustrating a semiconductor device module package. The substrate assembly 100 includes a DBM substrate 105, which may be a DBC substrate. Figure 1 As shown, the DBM substrate 105 has a dimension X1 and a dimension Y. For purposes of illustration and discussion, these dimensions are described as being along the x-axis and the y-axis, respectively. Figure 2 and Figure 3 As further discussed in , without changing the dimension on the y-axis (eg, dimension Y), the DBM substrate 105 can be scaled along the x-axis (eg, by changing dimension X1) to accommodate fewer or more semiconductor dies. Figure 1 As shown, the DBM substrate 105 includes a ceramic layer 105a, wherein a patterned metal layer 110 is disposed on the main surface of the ceramic layer 105a. In this example, the patterned metal layer 110 includes a metal layer portion 110a, a metal layer portion 110b, a metal layer portion 110c, and a metal layer portion 110d. The patterned metal layer 110 also includes Figure 1 Additional parts not specifically mentioned in the .

[0019] The substrate assembly 100 includes a high-side transistor 120, for example, four high-side transistors 120. The high-side transistors 120 are arranged in a single row on the metal layer portion 110a. That is, the high-side transistors 120 are arranged linearly along the axis 120a. In this example, the high-side transistors 120 can be implemented using corresponding semiconductor dies including power transistors such as power metal oxide semiconductor field effect transistors (MOSFETs). In this example, the corresponding drain terminals of the high-side transistors 120 are coupled to the metal layer portion 110a. At the same time, in this example, the source terminals of the high-side transistors 120 are respectively coupled to the metal layer portions 110c through conductive clips 122. As shown in FIG. Figure 1 As shown, metal layer portion 110c is arranged along axis 121a, which is disposed between metal layer portion 110a and metal layer portion 110b and is parallel to axis 120a.

[0020] The substrate assembly 100 also includes low-side transistors 125, for example, four low-side transistors 125. The low-side transistors 125 are arranged in a single row on the metal layer portion 110b. That is, the low-side transistors 125 are arranged linearly along an axis 125a, wherein the axis 125a is parallel to the axis 120a. In this example, as with the high-side transistor 120, the low-side transistor 125 can be implemented using a corresponding semiconductor die including a power transistor such as a power MOSFET. In this example, the corresponding drain terminal of the high-side transistor 120 is coupled to the metal layer portion 110a. At the same time, in this example, the source terminals of the low-side transistors 125 are respectively coupled to the metal layer portion 110d through the conductive clips 127. Figure 1 As shown, metal layer portion 110d is arranged along axis 126a, which is disposed between metal layer portion 110c and metal layer portion 110b and is parallel to axis 120a, axis 121a, and axis 125a.

[0021] like Figure 1 As shown, substrate assembly 100 includes conductive pillars 130a, 130b, 135a, 135b, 140a, and 140b. In this example, the first positive power terminal may be coupled to metal layer portion 110a via conductive pillar 130a, and the second positive power terminal may be coupled to metal layer portion 110a via conductive pillar 130b. That is, the positive power terminal may be coupled to the corresponding drain terminal of high-side transistor 120 via conductive pillar 130a, conductive pillar 130b, and / or metal layer portion 110a. At the same time, in this example, the negative power terminal may be coupled to metal layer portion 110d via conductive pillar 135a and conductive pillar 135b. That is, the negative power terminal may be coupled to the corresponding source terminal of low-side transistor 125 via conductive pillar 135a, conductive pillar 135b, metal layer portion 110a, and conductive clip 127. For example, as 4A to 4DAs shown, such power terminals may be arranged or positioned along edge 107a of DBM substrate 105, where edge 107a is parallel to axis 120a, axis 121a, axis 125a, and axis 126a.

[0022] Furthermore, in this example, the switch node terminal or output terminal of the half-bridge circuit can be coupled to the metal layer portion 110b via the conductive pillar 140a, and coupled to the metal layer portion 110d via the conductive pillar 140b. That is, the output terminal can be coupled to the corresponding drain terminal of the low-side transistor 125 via the conductive pillar 140a and the metal layer portion 110b. Furthermore, the output terminal can be coupled to the corresponding source terminal of the high-side transistor 120 via the conductive pillar 140b, the metal layer portion 110c, and the conductive clip 122. For example, as 4A to 4D As shown, such power terminals may be arranged or positioned along edge 107b of DBM substrate 105, where edge 107b is opposite and parallel to edge 107a.

[0023] The substrate assembly 100 also includes a lead frame 145, which may include a plurality of signal leads. Figure 1 In the example of the lead frame 145, the lead frame 145 includes signal leads 145a, signal leads 145b, signal leads 145c, signal leads 145d, signal leads 145e, signal leads 145f, and signal leads 145g. The specific arrangement of the signal leads of the substrate assembly will depend on the specific implementation. The example implementation of the signal leads and / or signal pins is at least Figure 4D and Figure 5 This is shown in and will be discussed further below.

[0024] exist Figure 1 In the example substrate assembly 100, the signal lead 145a is a high-side transistor gate signal lead. For example, the signal lead 145a is coupled to the corresponding gate terminal of the high-side transistor 120 via the bonding wire 150. That is, a single bonding wire (bonding wire 150) couples the signal lead 145a to the corresponding gate terminal of each high-side transistor 120. The signal lead 145b of the substrate assembly 100 is a high-side transistor source sense signal lead. Figure 1 As shown, the signal lead 145b is coupled to the corresponding source terminal of the high-side transistor 120 via the conductive clip 122 through the bonding wire 155. That is, in this example, each bonding wire 155 couples the signal lead 145b to each conductive clip 122 and its corresponding high-side transistor source terminal. In this example, the signal lead 145b is also directly coupled to the metal layer portion 110c.

[0025] In addition, Figure 1In the example substrate assembly 100, the signal lead 145c is a low-side transistor gate signal lead. For example, the signal lead 145c is coupled to the corresponding gate terminal of the low-side transistor 125 via the bonding wire 160. That is, a single bonding wire (bonding wire 160) couples the signal lead 145c to the corresponding gate terminal of each low-side transistor 125. The signal lead 145d of the substrate assembly 100 is a low-side transistor source sense signal lead. Figure 1 As shown, the signal lead 145d is coupled to the corresponding source terminal of the low-side transistor 125 via the conductive clip 127 through the bonding wire 165. That is, in this example, each bonding wire 165 couples the signal lead 145d to each conductive clip 127 and its corresponding low-side transistor source terminal. In addition, in this example, the signal lead 145d is also directly coupled to the metal layer portion 110d, such as via direct wire attachment using welding, sintering or other wire attachment processes.

[0026] like Figure 1 As shown, in substrate assembly 100, signal lead 145e is coupled to metal layer portion 110a. Therefore, in this example, signal lead 145e is a positive power sensing signal lead because it is coupled to the corresponding drain terminal of high-side transistor 120 via metal layer portion 110a.

[0027] The substrate assembly 100 also includes a thermistor 147, which can be used for temperature sensing during operation of the half-bridge circuit of the substrate assembly 100. For example, the signal lead 145f and the signal lead 145g are coupled to the thermistor 147. Therefore, the signal lead 145f and the signal lead 145g can be referred to as thermal sensing signal leads.

[0028] For example, Figure 4D and Figure 5 As shown, the signal pins associated with the signal leads 145a to 145g can be arranged along the edges of the package body corresponding to the edge 107c and the edge 107d of the DBM substrate 105, respectively. In this example, the edge 107c and the edge 107d are opposite and parallel to each other and are orthogonal to the edge 107a and the edge 107b. For example, the first plurality of signal pins or signal leads can be arranged along the edge of the package body corresponding to the edge 107c, and the second plurality of signal pins can be arranged along the edge of the package body corresponding to the edge 107d.

[0029] Figure 2 is a schematic diagram illustrating an example substrate assembly 200 of another semiconductor device module package. Figure 2 The substrate assembly 200 includes aspects similar to the substrate assembly 100. Therefore, for the sake of brevity, the substrate assembly 200 will not be described herein with respect to the substrate assembly 100. Figure 2 The details of the above aspects are described.

[0030] Comparing substrate assembly 200 to substrate assembly 100, substrate assembly 200 does not have four high-side transistors 120 and four low-side transistors 125, but substrate assembly 200 includes six high-side transistors 120 and six low-side transistors 125. Therefore, in this example, DBM substrate 205 of substrate assembly 200 is scaled on the x-axis based on DBM substrate 105 of substrate assembly 100. That is, in substrate assembly 200, for the same size of high-side transistors 120 and low-side transistors 125, dimension X2 of DBM substrate 205 is larger than dimension X1 in substrate assembly 100, thereby providing additional substrate surface area for two additional high-side transistors 120 and two additional low-side transistors 125. As described above, in this example, this dimension of DBM substrate 205 can be equal to dimension Y of DBM substrate 105.

[0031] Figure 3 is a schematic diagram illustrating an example substrate assembly 300 of another semiconductor device module package. As with the substrate assembly 200, Figure 3 The substrate assembly 300 includes aspects similar to those of the substrate assembly 100. Therefore, for the sake of brevity, the substrate assembly 300 will not be described herein with respect to Figure 3 The details of the above aspects are described.

[0032] Comparing substrate assembly 300 to substrate assembly 100 and substrate assembly 200, substrate assembly 300 does not have four or six high-side transistors 120 and four or six low-side transistors 125, but includes eight high-side transistors 120 and eight low-side transistors 125. Therefore, in this example, DBM substrate 305 of substrate assembly 200 is scaled on the x-axis based on DBM substrate 105 of substrate assembly 100 and DBM substrate 205 of substrate assembly 200. That is, in substrate assembly 300, for the same size of high-side transistor 120 and low-side transistor 125, dimension X3 of DBM substrate 305 is larger than dimension X1 in substrate assembly 100, and larger than dimension X2 in substrate assembly 200, thereby providing additional substrate surface area for additional high-side transistor 120 and additional low-side transistor 125. As described above, in this example, this dimension of DBM substrate 205 may be equal to dimension Y of DBM substrate 105 and greater than dimension Y of DBM substrate 205.

[0033] As illustrated by substrate assembly 100, substrate assembly 200, and substrate assembly 300, the related substrates are easy to design and produce by scaling along a single axis or a single direction. In some implementations, substrate assemblies with less than four high-side transistors 120 and less than four low-side transistors 125 can also be produced, and corresponding substrates like DBM substrate 105, DBM substrate 205, and DBM substrate 305 can be produced by scaling on the x-axis, where the resulting dimension on the x-axis will be smaller than dimension X1 of substrate assembly 100.

[0034] FIG. 4A to FIG. 4E 4 is a schematic diagram illustrating various views of an example semiconductor device module package 400 and its components. For purposes of illustration, FIG. 4A to FIG. 4E Examples include Figure 3 In some implementations, other substrate assemblies such as substrate assembly 100 or substrate assembly 200 may be used.

[0035] Figure 4A FIG. 4 is an exploded view of a portion of a semiconductor device module package 400. The package includes a substrate assembly 300 and associated power terminals and conductive pillars, wherein the conductive pillars are denoted by 400 series reference numerals, which correspond to Figure 1 The conductive posts of the substrate assembly 100 are referenced by a series of 100 reference numerals. For example, Figure 4A In the example of FIG. 4 , the positive power terminal 431a (DC+ terminal) can be coupled to the DBM substrate 305 of the substrate assembly 300 via the conductive pillar 430a, and the positive power terminal 431b (DC+ terminal) can be coupled to the DBM substrate 305 of the substrate assembly 300 via the conductive pillar 430b. The negative power terminal 436 (DC– terminal) can be coupled to the DBM substrate 305 via the conductive pillar 435a and the conductive pillar 435b. In addition, the switch node terminal 441 (A / C output terminal) can be coupled to the DBM substrate 305 via the conductive pillar 440a and the conductive pillar 440b. Figure 4B is an example Figure 4A A schematic diagram of an unexploded view of an example of Figure 4B In the view of Figure 4A The power terminals and switch node terminals in are shown as being coupled to the DBM substrate 305 of the substrate assembly 300 via their respective conductive pillars.

[0036] Figure 4C 4 illustrates the process of encapsulating the components in the molding compound 470 after performing a molding operation such as a transfer molding operation. Figure 4B Components in. Figure 4CAs shown, the corresponding surfaces of the positive power supply terminal 431a, the positive power supply terminal 431b, the negative power supply terminal 436, and the switch node terminal 441 are exposed through the main surface 470a of the molding material 470. That is, the positive power supply terminal 431a, the positive power supply terminal 431b, the negative power supply terminal 436, and the switch node terminal 441 are partially encapsulated in the molding material 470. Figure 4C As shown, portions of the lead frame of the substrate assembly 300 are also exposed through the major surface 470 a of the molding compound 470 .

[0037] Figure 4D 4. The semiconductor device module package 400 is illustrated after the first plurality of signal pins 475 are attached along the edge 407c of the semiconductor device module package 400 and the second plurality of signal pins 475 are attached along the edge 407d of the semiconductor device module package 400. Figure 4C The semiconductor device module package 400 is shown in FIG. Figure 4D As further illustrated, the positive power terminal 431 a , the positive power terminal 431 b , and the negative power terminal 436 are arranged along or located on an edge 407 a of the semiconductor device module package 400 . Figure 4D The switch node terminal 441 in the semiconductor device module package 400 is arranged along or on the edge 407b. In this example, the signal pin 475 is a signal pin configured for press-fit coupling or friction coupling in the corresponding circuit board. In some specific implementations, the signal pin 475 can be welded and / or sintered to the portion of the corresponding lead frame exposed through the molding compound 470.

[0038] Further references Figure 1 In some implementations, edge 407a of semiconductor device module package 400 may correspond to edge 107a of DBM substrate 105. Edge 407b of semiconductor device module package 400 may correspond to edge 107b of DBM substrate 105. Edge 407c of semiconductor element module package 400 may correspond to edge 107c of DBM substrate 105. Edge 407d of semiconductor element module package 400 may correspond to edge 107d of DBM substrate 105. That is, edge 407b is opposite and parallel to edge 407a of semiconductor device module package 400. Edge 407d is opposite and parallel to edge 407d of semiconductor device module package 400. Edge 407c and edge 407d are orthogonal to edge 407a and edge 407b.

[0039] Figure 4E is an example based on Figure 4D Schematic diagram of the semiconductor device module package 400 obtained by reversing and rotating the perspective of the semiconductor device module package 400 in FIG. Figure 4EAs shown, the metal layer 415 of the corresponding DBM substrate, such as DBM substrate 305, is exposed through the main surface 470b of the molding compound 470, wherein the main surface 470b is opposite to the main surface 470a of the molding compound 470. In this example, the metal layer 415 may be disposed on, included in, and / or defined on the main surface of the DBM substrate 305, which is opposite to the main surface of the DBM substrate 305 on which the patterned metal layer and the semiconductor switch are disposed.

[0040] Figure 5 is a schematic diagram illustrating another example semiconductor device module package 500. The semiconductor device module package 500 is different from the semiconductor device module package 400 in that the signal pins 575 of the semiconductor device module package 500 are formed from the signal leads of the lead frame of the semiconductor device module package 500, such as using a metal processing process. That is, in the semiconductor device module package 500, the signal leads of the lead frame and the corresponding signal pins can be monolithic, and the signal pins are not independent components coupled to (sintered or soldered to) the exposed portions of the signal leads of the corresponding lead frame.

[0041] Fig. 6A and Figure 6B is an example FIG. 4A to FIG. 4E Schematic diagram of current flow in a semiconductor device module package. Fig. 6A The current 623 through the high-side transistor 120 is illustrated using a dashed arrow. Fig. 6A As shown, current 623 flows from positive power supply terminal 431a and positive power supply terminal 431b to switch node terminal 441. That is, current 623 flows from positive power supply terminal 431a and positive power supply terminal 431b through high-side transistor 120 and corresponding conductive pillars, conductive clips and metal layer portions to 441a / / and 441b / / . Fig. 6A The current 623 shown in can be referred to as the high-side current.

[0042] and Fig. 6A compared to, Figure 6B The current 628 through the low-side transistor 125 is illustrated using a dashed arrow. Figure 6B As shown, current 628 flows from switch node terminal 441 to negative power supply terminal 436. That is, current 628 flows from switch node terminal 441 through low-side transistor 125 and corresponding conductive pillars, conductive clips, and metal layer portions to negative power supply terminal 436. Figure 6B The current 628 shown in can be referred to as the low-side current.

[0043] exist Fig. 6A and Figure 6BIn the example of , current 623 and current 628 are counter-currents, or currents that are parallel but in opposite directions. This arrangement and the resulting counter-currents can reduce the stray inductance of the power module described herein because such counter-currents will cause the corresponding magnetic fields associated with current 623 (high-side current) and current 628 (low-side current) to cancel each other, wherein such uncancelled magnetic fields increase the stray inductance.

[0044] Figure 7 is a flow chart illustrating an example method 700 for producing a power module package such as the packages described herein. The method 700 includes, in block 705, coupling a plurality of high-side semiconductor switches such as high-side transistors 120 to a first portion of a patterned metal layer of a substrate such as metal layer portion 110a of DBM substrate 105. In this example, the plurality of high-side semiconductor switches may be linearly arranged on the substrate along a first axis such as axis 120a.

[0045] In block 710, method 700 includes coupling a plurality of low-side semiconductor switches, such as low-side transistor 125, to a second portion of the patterned metal layer, such as metal layer portion 110b. In this example, the plurality of low-side semiconductor switches may be linearly arranged on the substrate along a second axis, such as axis 125a, parallel to the first axis. In some implementations, the operations in blocks 705 and 710 may be performed together, for example, by a welding operation and / or a sintering operation.

[0046] At block 715, method 700 includes coupling or attaching a conductive clip, such as conductive clip 122 and conductive clip 127, to the semiconductor switch and the substrate. For example, in some implementations, such as Figure 1 In the substrate assembly 100 of FIG. 1 , the conductive clip may connect the source terminal of the high-side transistor 120 to the metal layer portion 110 c and the source terminal of the low-side transistor 125 to the metal layer portion 110 d. In some implementations, the operations in block 715 may include a welding operation and / or a sintering operation.

[0047] At block 720, method 700 includes coupling or attaching a leadframe, such as at least one signal lead of a leadframe, to the substrate. The leadframe may be a single leadframe (eg, a signal lead within a support frame) that is subsequently trimmed to separate the individual signal leads. For example, referring to Figure 1 The operation in block 720 may include coupling the signal leads 145 b to 145 g of the lead frame 145 to the DBM substrate 105. In block 725, the method includes forming wire bonds, such as the wire bonds 150, 155, 160, and 165 of the substrate assembly 100, between the signal leads of the lead frame, the semiconductor switch, and / or the conductive clip.

[0048] In block 730, method 700 includes coupling power terminals such as positive power terminals 431a, positive power terminals 431b, and negative power terminals 436 to the substrate via conductive pillars such as conductive pillars 430a, 430b, 435a, and 435b. In this example, the power terminals are connected along a first edge of the package such as Figure 4D In block 730, method 700 further includes coupling a switch node terminal such as switch node terminal 441 to the substrate via a conductive pillar such as conductive pillar 440a and conductive pillar 440b. In this example, the switch node terminal is disposed along a second edge of the package such as Figure 4D The second edge (edge ​​407b) is arranged or positioned with respect to the edge 407b in the embodiment. In this example, the second edge (edge ​​407b) is opposite and parallel to the first edge (edge ​​407a). The operation in frame 730 may include: welding, sintering or soldering the conductive post and the associated terminal.

[0049] In block 735, the method 700 includes performing a molding process such as a transfer molding process to encapsulate a portion of the semiconductor device package in a molding compound such as Figure 4C , Figure 4D and Figure 4E In some implementations, such as those described herein, the power terminals and output terminals in the frame 730 can be exposed through the main surface of the molding material, such as the positive power terminal 431a, the positive power terminal 431b, the negative power terminal 436, and the switch node terminal 441 are exposed through the main surface 470a of the molding material 470. Further, in this example, the portions of the lead frame can also be exposed through the main surface 470a of the molding material 470, such as Figure 4C The examples in the exposure.

[0050] In block 740, method 700 includes coupling or attaching a signal pin, such as signal pin 475, to an exposed portion of the lead frame in block 720, for example, along edge 407c and edge 407d of semiconductor device module package 400. For example, the signal pin may be soldered or sintered to a corresponding exposed portion of the lead frame, such as Figure 4C and Figure 4D In some implementations, the signal pin can be a signal lead (e.g. Figure 5 The method 700 may be formed by a signal pin 575 of the lead frame rather than a separate component coupled to the lead frame. In some implementations, the method 700 may include additional operations, such as a flux cleaning operation, a deburring operation, and / or a trimming and forming operation. In some implementations, one or more operations in the method 700 may be omitted or replaced with an alternative or different operation.

[0051] In general terms, a power module package includes: a substrate having a ceramic layer, the ceramic layer having a first main surface and a second main surface opposite to the first main surface; and a patterned metal layer disposed on the first main surface. The power module package also includes: a first plurality of semiconductor dies, the first plurality of semiconductor dies being disposed on a first portion of the patterned metal layer. The first plurality of semiconductor dies are linearly arranged along a first axis. The power module package also includes: a second plurality of semiconductor dies, the second plurality of semiconductor dies being disposed on a second portion of the patterned metal layer. The second plurality of semiconductor dies are linearly arranged along a second axis parallel to the first axis. The power module package also includes: a plurality of power terminals, the plurality of power terminals being arranged on a first edge of the power module package, wherein the first edge is parallel to the first axis and the second axis. The power module package also includes: a switch node terminal, the switch node terminal being arranged on a second edge of the power module package, wherein the second edge is opposite to and parallel to the first edge. The power module package also includes: a first plurality of signal pins, which are located on a third edge of the power module package orthogonal to the first edge and the second edge; and a second plurality of signal pins, which are located on a fourth edge of the power module package opposite to and parallel to the third edge.

[0052] Specific implementations may include one or more of the following features or aspects, alone or in combination. For example, the substrate may include a metal layer disposed on the second major surface. The power module package may include a molding compound that encapsulates the first plurality of semiconductor dies and the second plurality of semiconductor dies and partially encapsulates the substrate. The metal layer may be exposed through the molding compound.

[0053] The plurality of power terminals and the switch node terminal may be exposed through the first major surface of the molding compound.

[0054] The first major surface of the molding compound may be located at a side of the substrate corresponding to the first major surface of the substrate.

[0055] The metal layer may be exposed through the molding compound on a second major surface of the molding compound opposite to the first major surface of the molding compound.

[0056] The power module package may include a lead frame. The first plurality of signal pins and the second plurality of signal pins may be included in the lead frame. The first plurality of signal pins and the second plurality of signal pins may be coupled to the lead frame.

[0057] The power module package may include: a first plurality of conductive clips, the first plurality of conductive clips respectively coupling the first plurality of semiconductor dies to a third portion of the patterned metal layer disposed between the first portion of the patterned metal layer and the second portion of the patterned metal layer. The third portion of the patterned metal layer may be arranged along a third axis parallel to the first axis and the second axis. The power module package may include: a second plurality of conductive clips, the second plurality of conductive clips respectively coupling the second plurality of semiconductor dies to a fourth portion of the patterned metal layer disposed between the second portion of the patterned metal layer and the third portion of the patterned metal layer. The fourth portion of the patterned metal layer may be arranged along a fourth axis parallel to the first axis, the second axis, and the third axis.

[0058] In another general aspect, a power module package includes: a substrate including a patterned metal layer disposed thereon. The power module package also includes: a first plurality of semiconductor dies disposed on a first portion of the patterned metal layer. The first plurality of semiconductor dies includes a first plurality of power transistors arranged linearly along a first axis. The power module package also includes: a second plurality of semiconductor dies disposed on a second portion of the patterned metal layer. The second plurality of semiconductor dies includes a second plurality of power transistors arranged linearly along a second axis parallel to the first axis. The power module package also includes: a first plurality of conductive clips, the first plurality of conductive clips coupling the first plurality of power transistors to a third portion of the patterned metal layer disposed between the first portion of the patterned metal layer and the second portion of the patterned metal layer, respectively. The third portion of the patterned metal layer is arranged along a third axis parallel to the first axis and the second axis. The power module package also includes: a second plurality of conductive clips, the second plurality of conductive clips coupling the second plurality of power transistors to a fourth portion of the patterned metal layer disposed between the second portion of the patterned metal layer and the third portion of the patterned metal layer, respectively. A fourth portion of the patterned metal layer is arranged along a fourth axis that is parallel to the first axis, the second axis, and the third axis.

[0059] Specific implementations may include one or more of the following features or aspects, alone or in combination. For example, the power module package may include: a plurality of power terminals, the plurality of power terminals being arranged on a first edge of the power module package. The first edge may be parallel to the first axis and the second axis. The power module package may include: a switch node terminal, the switch node terminal being arranged on a second edge of the power module package. The second edge may be opposite and parallel to the first edge.

[0060] The power module package may include: a first plurality of signal pins, the first plurality of signal pins are located on a third edge of the power module package orthogonal to the first edge and the second edge. The power module package may include: a second plurality of signal pins, the second plurality of signal pins are located on a fourth edge of the power module package. The fourth edge may be opposite and parallel to the third edge.

[0061] The first plurality of power transistors may be respective high-side transistors of a half-bridge circuit, the high-side transistors comprising first respective power metal oxide semiconductor field effect transistors (MOSFETs). The second plurality of power transistors may be respective low-side transistors of the half-bridge circuit, the low-side transistors comprising second respective power MOSFETs.

[0062] The respective drain terminal of the first respective power MOSFET may be coupled to the first portion of the patterned metal layer. The respective source terminal of the first respective power MOSFET may be coupled to the third portion of the patterned metal layer via the first plurality of conductive clips. The respective drain terminal of the second respective power MOSFET may be coupled to the second portion of the patterned metal layer. The respective source terminal of the second respective power MOSFET may be coupled to the fourth portion of the patterned metal layer via the second plurality of conductive clips.

[0063] The power module package may include a high-side source sense signal lead. A first bonding wire may couple the high-side source sense signal lead to the first plurality of conductive clips. The power module package may include a high-side gate terminal signal lead. A second bonding wire may couple the high-side gate terminal signal lead to a corresponding gate terminal of the first corresponding power MOSFET.

[0064] The power module package may include a low-side source sensing signal lead. A first bonding lead may couple the low-side source sensing signal lead to the second plurality of conductive clips. The power module package may include a low-side gate terminal signal lead. A second bonding lead may couple the low-side gate terminal signal lead to a corresponding gate terminal of the second corresponding power MOSFET.

[0065] The power module package may include a positive power supply terminal coupled to a first portion of the patterned metal layer. The power module package may include a negative power supply terminal coupled to a fourth portion of the patterned metal layer. The power module package may include a switch node terminal coupled to a second portion of the patterned metal layer and a third portion of the patterned metal layer.

[0066] The positive power terminal may be coupled to the first portion of the patterned metal layer via a first conductive post. The negative power terminal may be coupled to the fourth portion of the patterned metal layer via a second conductive post. The switch node terminal may be coupled to the second portion of the patterned metal layer via a third conductive post, and coupled to the third portion of the patterned metal layer via a fourth conductive post.

[0067] The negative power terminal may be coupled to a fourth portion of the patterned metal layer via a fifth conductive pillar.

[0068] The positive power terminal may be a first positive power terminal. The power module package may include: a second positive power terminal coupled to the first portion of the patterned metal layer via the fifth conductive pillar.

[0069] In another general aspect, a method for producing a power module package includes: coupling a first plurality of semiconductor die to a first portion of a patterned metal layer and a second portion of the patterned metal layer in a substrate. The first plurality of semiconductor die are arranged linearly on the substrate along a first axis. The method also includes: coupling a second plurality of semiconductor die to a third portion of the patterned metal layer and a fourth portion of the patterned metal layer. The second plurality of semiconductor die are arranged linearly on the substrate along a second axis parallel to the first axis. The method also includes: coupling a plurality of power terminals to the substrate. The plurality of power terminals are arranged on a first edge of the power module package. The first edge is parallel to the first axis and the second axis. The method also includes: coupling a switch node terminal to the substrate. The switch node terminal is arranged on a second edge of the power module package. The second edge is opposite and parallel to the first edge. The method also includes: coupling a lead frame to the substrate, and forming corresponding wire bonds coupling the lead frame to the first plurality of semiconductor die and the second plurality of semiconductor die. The method also includes: coupling a first plurality of signal pins to corresponding portions of the lead frame. The first plurality of signal pins are located on a third edge of the power module package that is orthogonal to the first edge and the second edge. The method also includes: coupling a second plurality of signal pins to corresponding portions of the lead frame. The second plurality of signal pins are located on a fourth edge of the power module package. The fourth edge is opposite and parallel to the third edge.

[0070] It should be understood that in the foregoing description, when an element such as a layer, a region or a substrate is mentioned as being on another element, connected to another element, electrically connected to another element, coupled to another element, or electrically coupled to another element, the element may be directly on another element, connected or coupled to another element, or one or more intermediate elements may be present. On the contrary, when an element is mentioned as being directly on another element or layer, directly connected to another element or layer, or directly coupled to another element or layer, there is no intermediate element or layer. Although the term directly on, directly connected to, or directly coupled to may not be used throughout the specific embodiments, an element that is shown as being directly on an element, directly connected, or directly coupled can be mentioned in this manner. The claims of the present application may be revised to narrate the exemplary relationships described in the specification or shown in the accompanying drawings.

[0071] As used in this specification, unless the context clearly indicates a particular case, the singular form may include the plural form. In addition to the orientation shown in the drawings, spatial relative terms (e.g., above, above, above, below, below, below, below, at the top, at the bottom, etc.) are intended to cover different orientations of the device in use or operation. In some specific implementations, the relative terms above and below may include vertically above and vertically below, respectively. In some specific implementations, the term adjacent may include lateral adjacent or horizontal adjacent.

[0072] Some implementations may be implemented using various semiconductor processing and / or packaging technologies. Some implementations may be implemented using various types of semiconductor device processing technologies associated with semiconductor substrates, including but not limited to, for example, silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), etc.

[0073] Although certain features of the described specific implementations have been illustrated as described herein, those skilled in the art will now expect many modifications, alternatives, variations and equivalents. Therefore, it should be understood that the appended claims are intended to cover all such modifications and variations that fall within the scope of the specific implementation. It should be understood that these modifications and variations are presented only by way of example and not limitation, and various changes in form and detail may be made. In addition to mutually exclusive combinations, any part of the apparatus and / or method described herein may be combined in any combination. The specific implementations described herein may include various combinations and / or sub-combinations of the functions, components and / or features of the different specific implementations described.

Claims

1. A power module package (400), comprising: A substrate (105), comprising: a ceramic layer (105a) having a first major surface and a second major surface opposite to the first major surface; and A patterned metal layer (110), the patterned metal layer being disposed on the first main surface; A first plurality of semiconductor dies (120), the first plurality of semiconductor dies being disposed on a first portion (110a) of the patterned metal layer, and the first plurality of semiconductor dies being linearly arranged along a first axis (120a); A second plurality of semiconductor dies (125), the second plurality of semiconductor dies being disposed on a second portion (110b) of the patterned metal layer, and the second plurality of semiconductor dies being linearly arranged along a second axis (125a) parallel to the first axis; A plurality of power terminals (431a, 431b, 436), wherein the plurality of power terminals are arranged on a first edge (407a) of the power module package, wherein the first edge is parallel to the first axis and the second axis; a switch node terminal (441), the switch node terminal being arranged on a second edge (407b) of the power module package, the second edge being opposite to and parallel to the first edge; a first plurality of signal pins (475), the first plurality of signal pins being located on a third edge (407c) of the power module package, the third edge being orthogonal to the first edge and the second edge; and A second plurality of signal pins (475) are located on a fourth edge (407d) of the power module package, the fourth edge being opposite and parallel to the third edge.

2. The power module package according to claim 1, wherein: The substrate further includes a metal layer (415) disposed on the second major surface; and The power module package further includes a molding compound (470) that encapsulates the first plurality of semiconductor dies and the second plurality of semiconductor dies and partially encapsulates the substrate, the metal layer being exposed through the molding compound.

3. The power module package of claim 2, wherein the plurality of power terminals and the switch node terminal are exposed through the first major surface (470a) of the molding compound. 4 . The power module package according to claim 3 , wherein the first main surface of the molding compound is located on a side of the substrate corresponding to the first main surface of the substrate.

5. The power module package according to claim 3, wherein the metal layer is exposed through the molding material on a second main surface (470b) of the molding material opposite to the first main surface of the molding material.

6. The power module package according to claim 1, further comprising: A lead frame, the first plurality of signal pins (575) and the second plurality of signal pins (575) included in the lead frame.

7. The power module package according to claim 1, further comprising: A lead frame (145) to which the first plurality of signal pins (475) and the second plurality of signal pins (475) are coupled.

8. The power module package according to claim 1, further comprising: a first plurality of conductive clips (122) coupling the first plurality of semiconductor dies to a third portion (110c) of the patterned metal layer disposed between the first portion of the patterned metal layer and the second portion of the patterned metal layer, the third portion of the patterned metal layer being arranged along a third axis (121a) parallel to the first axis and the second axis; and A second plurality of conductive clips (127), the second plurality of conductive clips respectively coupling the second plurality of semiconductor tube cores with a fourth portion of the patterned metal layer arranged between the second portion of the patterned metal layer and the third portion of the patterned metal layer, the fourth portion of the patterned metal layer being arranged along a fourth axis (126a) parallel to the first axis, the second axis and the third axis.

9. A power module package (400), comprising: A substrate (105) comprising a patterned metal layer (110) disposed thereon; a first plurality of semiconductor dies (120), the first plurality of semiconductor dies being disposed on a first portion (110a) of the patterned metal layer, the first plurality of semiconductor dies comprising a first plurality of power transistors arranged linearly along a first axis (120a); a second plurality of semiconductor dies (125), the second plurality of semiconductor dies being disposed on a second portion (110b) of the patterned metal layer, the second plurality of semiconductor dies comprising a second plurality of power transistors linearly arranged along a second axis (125a) parallel to the first axis; a first plurality of conductive clips (122), the first plurality of conductive clips coupling the first plurality of power transistors respectively to a third portion (110c) of the patterned metal layer disposed between the first portion of the patterned metal layer and the second portion of the patterned metal layer, the third portion of the patterned metal layer being arranged along a third axis (121a) parallel to the first axis and the second axis; and A second plurality of conductive clips (127), the second plurality of conductive clips respectively coupling the second plurality of power transistors to a fourth portion (110d) of the patterned metal layer disposed between the second portion of the patterned metal layer and the third portion of the patterned metal layer, the fourth portion of the patterned metal layer being arranged along a fourth axis (126a) parallel to the first axis, the second axis and the third axis.

10. The power module package according to claim 9, further comprising: A plurality of power terminals (431a, 431b, 436), wherein the plurality of power terminals are arranged on a first edge (407a) of the power module package, wherein the first edge is parallel to the first axis and the second axis; and A switch node terminal (441) is arranged on a second edge (407b) of the power module package, the second edge being opposite to and parallel to the first edge.

11. The power module package according to claim 10, further comprising: a first plurality of signal pins (475), the first plurality of signal pins being located on a third edge (407c) of the power module package orthogonal to the first edge and the second edge; and A second plurality of signal pins (475) are located on a fourth edge (407d) of the power module package, the fourth edge being opposite to and parallel to the third edge.

12. The power module package according to claim 9, wherein: The first plurality of power transistors are respective high-side transistors of a half-bridge circuit, the high-side transistors comprising first respective power metal oxide semiconductor field effect transistors MOSFETs; and The second plurality of power transistors are respective low-side transistors of the half-bridge circuit, the low-side transistors comprising second respective power MOSFETs.

13. The power module package according to claim 12, wherein: a respective drain terminal of the first respective power MOSFET coupled to the first portion of the patterned metal layer; a respective source terminal of the first respective power MOSFET coupled to the third portion of the patterned metal layer via the first plurality of conductive clips; a respective drain terminal of the second respective power MOSFET coupled to the second portion of the patterned metal layer; and The respective source terminals of the second respective power MOSFETs are coupled to the fourth portion of the patterned metal layer via the second plurality of conductive clips.

14. The power module package according to claim 12, further comprising: High side source sense signal lead (145b); a first bonding wire (155) coupling the high-side source sensing signal lead with the first plurality of conductive clips; A high side gate terminal signal lead (145a); and A second bond wire (150) couples the high side gate terminal signal lead to a respective gate terminal of the first respective power MOSFET.

15. The power module package according to claim 12, further comprising: Low side source sense signal lead (145d); a first bonding wire (165) coupling the low-side source sense signal lead with the second plurality of conductive clips; Low side gate terminal signal lead (145c); and A second bond wire (160) couples the low side gate terminal signal lead to a respective gate terminal of the second respective power MOSFET.

16. The power module package according to claim 12, further comprising: a positive power terminal (431a) coupled to the first portion of the patterned metal layer; a negative power terminal (436) coupled to the fourth portion of the patterned metal layer; and A switch node terminal (441) is coupled to the second portion of the patterned metal layer and the third portion of the patterned metal layer.

17. The power module package according to claim 16, wherein: The positive power terminal is coupled to the first portion of the patterned metal layer via a first conductive pillar (430a); The negative power terminal is coupled to the fourth portion of the patterned metal layer via a second conductive pillar (435a); The switch node terminal is coupled to the second portion of the patterned metal layer via a third conductive pillar (440b); and The switch node terminal is coupled to the third portion of the patterned metal layer via a fourth conductive pillar (440a).

18. The power module package of claim 17, wherein the negative power terminal is further coupled to the fourth portion of the patterned metal layer via a fifth conductive pillar (435b).

19. The power module package according to claim 17, wherein the positive power terminal is a first positive power terminal, The power module package further comprises: A second positive power terminal (431b) is coupled to the first portion of the patterned metal layer via a fifth conductive pillar (430b).

20. A method for producing a power module package, the method comprising: coupling (705) a first plurality of semiconductor dies to a first portion of a patterned metal layer in a substrate and a second portion of the patterned metal layer, the first plurality of semiconductor dies being linearly arranged on the substrate along a first axis; coupling (710) a second plurality of semiconductor die to a third portion of the patterned metal layer and a fourth portion of the patterned metal layer, the second plurality of semiconductor die being linearly arranged on the substrate along a second axis parallel to the first axis; coupling (730) a plurality of power terminals to the substrate, the plurality of power terminals being arranged on a first edge of the power module package, the first edge being parallel to the first axis and the second axis; coupling a switch node terminal to the substrate (730), the switch node terminal being arranged on a second edge of the power module package, the second edge being opposite and parallel to the first edge; coupling a lead frame to the substrate (720); forming (725) respective wire bonds coupling the lead frame to the first plurality of semiconductor die and the second plurality of semiconductor die; coupling (740) a first plurality of signal pins to respective portions of the lead frame, the first plurality of signal pins being located on a third edge of the power module package, the third edge being orthogonal to the first edge and the second edge; and A second plurality of signal pins are coupled to corresponding portions of the lead frame (740), the second plurality of signal pins being located on a fourth edge of the power module package, the fourth edge being opposite and parallel to the third edge.

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