Method for converting ladder diagram of PLC into instruction list

Abstract

The invention relates to the field of programmable logic controller programming software, in particular to a method for converting a ladder diagram of a PLC into an instruction list, which comprises the following steps of: obtaining a mapped AOV diagram by adopting a mode of adding and deleting virtual nodes; generating a logic tree by adopting a series-parallel scanning method of dynamic priority; and after the logic tree structure is obtained, performing subsequent traversal on the logic tree according to the logic relationship described by the logic tree to generate an instruction table structure. Compared with the prior art, a complex ladder diagram is greatly simplified through a preprocessing mechanism, the scanning steps of continuous series connection or continuous parallel connection original parts can be reduced, unnecessary node scanning can be fully reduced through dynamic priority series-parallel connection scanning, and the scanning efficiency is greatly improved; in addition, the method can be widely applied to a complex ladder diagram program in the PLC, and the series-parallel scanning efficiency can be greatly improved.

Description

Technical Field

[0001] The invention relates to the field of programmable logic controller programming software, and in particular to a method for converting a ladder diagram of a PLC into an instruction table. Background Art

[0002] The industrial control programming language standard established by the International Electrotechnical Commission specifies five PLC programming languages: ladder diagram (LD), instruction list (IL), function block diagram language (FBD), sequential function flow chart language (SFC) and structured text language (ST). Compared with other programming languages, ladder diagram language has a longer development history, but it is still widely used today because its expression is intuitive and easy to master. We know that assembly language can directly control computer hardware, directly interact with the bottom layer of the computer, and is easy to be executed by the CPU of the PC. Similarly, ladder diagrams cannot be directly recognized by PLCs and need to be converted into instruction list language, which is also a language close to machine code. Therefore, in PLC technology, the process of converting ladder diagrams to statement lists is particularly important.

[0003] In order to convert a ladder diagram into a statement table in the prior art, it is necessary to first convert the ladder diagram into an Activity OnVertex (AOV) diagram, then convert the AOV diagram into a binary tree, and finally traverse the binary tree to generate an instruction table. This form of expression will cause the binary tree to be too deep, and its width will not be reasonably utilized, resulting in a large waste of tree space. The prior art can also convert the ladder diagram into a logic tree and perform series and parallel scanning on the connected components of the AOV diagram, but each time a node with an associated element is scanned, the scan needs to be restarted, which greatly reduces the scanning rate. In addition, for continuous series elements and continuous parallel elements, the traditional series and parallel scanning efficiency is not high. Summary of the invention

[0004] In order to improve the efficiency of converting a ladder diagram into an instruction table, the present invention proposes a method for converting a ladder diagram of a PLC into an instruction table, converting the ladder diagram into a vertex activity diagram, using a dynamic priority serial-parallel scanning method to generate a logic tree, and subsequently traversing the logic tree to generate an instruction table structure. The method of generating a logic tree using a dynamic priority serial-parallel scanning method specifically includes the following steps:

[0005] 101. The number of components directly connected in series or in parallel with the current component is used as the priority of the current component, and a vector set L consisting of all components is generated by sorting them according to the priority, and a tree node is generated according to each component in the vector set L;

[0006] 102. Determine whether the number of elements in the vector set L is 1, if so, end;

[0007] 103. Otherwise, a series scan is performed on the node e with the highest priority in the vector set L, and a series set Q is generated between the node and other nodes connected in series with the node;

[0008] 104. If the number of nodes in the series set Q is greater than 1, create and logical node xand and insert it into the vector set L, and delete the nodes in the vector set L that are the same as the series set Q;

[0009] 105. Update the priority of the AND logical node according to the number of nodes directly connected to the AND logical node, and increase the priority of the component node directly connected in series or in parallel with the AND logical node by 1;

[0010] 106. Generate a first tree node tand, and use the nodes in the series set Q as child nodes of the first tree node tand;

[0011] 107. Determine whether the predecessor node of node e is a virtual node. If so, perform parallel scanning, and merge the nodes whose successor nodes of the successor node of the virtual node and the successor node of node e are the same as each other into a parallel set S.

[0012] 108. If the number of nodes in the parallel set S is greater than 1, create an OR logic node xor and insert it into the vector set L, and delete the nodes in the vector set L that are the same as the parallel set S;

[0013] 109. Update the priority of the OR logic node according to the number of nodes directly connected to the OR logic node, and increase the priority of the component node directly connected in series or in parallel with the OR logic node by 1;

[0014] 110. Generate a second tree node tor, and use the nodes in the parallel set S as child nodes of the second tree node tor;

[0015] 111. Return to step 102.

[0016] Compared with the prior art, the preprocessing mechanism of the present invention greatly simplifies the complex ladder diagram, can reduce the scanning steps for continuous series or continuous parallel components, and the dynamic priority series and parallel scanning can fully reduce unnecessary node scanning, greatly improving the scanning efficiency; in addition, the present invention can be widely applied to the complex ladder diagram program in PLC, which can greatly improve the series and parallel scanning efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A flow chart of a method for converting a PLC ladder diagram into an instruction table for execution of the present invention;

[0018] Figure 2 This is an example of a ladder diagram commonly seen in this field;

[0019] Figure 3The ladder diagram after adding virtual nodes to the present invention;

[0020] Figure 4 The ladder diagram is mapped into an AOV diagram for the present invention;

[0021] Figure 5 It is the AOV image after preprocessing of the present invention;

[0022] Figure 6 The logic tree generated by converting the AOV graph in the present invention;

[0023] Figure 7 The logic tree generated after simplification of the present invention;

[0024] Figure 8 Instruction tables generated for the present invention. DETAILED DESCRIPTION

[0025] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0026] In this embodiment, a specific implementation process of a method for converting a PLC ladder diagram into an instruction table is provided, such as Figure 1 , specifically including the following steps:

[0027] S1: Obtain the mapped AOV graph by adding and deleting virtual nodes. Specifically, the following steps are included:

[0028] Save the information of the ladder diagram, including the in-and-out degree information, the pointer information pointing to the next node, and the priority relationship of each node;

[0029] Add virtual nodes at the intersection of parallel connections in the ladder diagram. The figure after adding virtual nodes is as follows Figure 3 As shown, according to the structure of the ladder diagram, the relevant information of each node (including virtual nodes) is saved;

[0030] Traverse the AOV graph and merge the virtual nodes associated with a certain virtual node into one virtual node;

[0031] Save the virtual nodes. If you encounter a situation where you need to access a virtual node, directly access its in-degree and out-degree to get the complete AOV graph.

[0032] Specifically, the formal definition of a graph is Graph = (V, R), where V is a finite non-empty set of vertices; R is a set of relationships between two vertices. If <x, y> ∈ R, then <x, y> represents an arc from vertex x to vertex y, where vertex x is the direct predecessor of vertex y, and vertex y is the direct successor of vertex x. Correspondingly, the components in the ladder diagram program of the PLC are connected together according to the rules. The components of the ladder diagram can be abstracted into vertices of the AOV diagram, and the connection relationship between the components can be abstracted into arcs of the AOV diagram.

[0033] S2: Generate a logic tree using a dynamic priority serial-parallel scanning method. Specifically, it includes the following steps:

[0034] First, the AOV graph is pre-scanned, and the number of directly connected series and parallel components of each component is used as the priority level;

[0035] Then, the AOV graph corresponding to the entire ladder diagram is decomposed according to the connected components, the vertices of the connected components and their priorities are put into the vector, and the components are taken out in order of priority and scanned in series and parallel.

[0036] As a preferred implementation scheme, pre-scanning the AOV map includes the following steps:

[0037] Traverse each node from top to bottom and from left to right, and scan each node in series and parallel respectively, find its directly connected components in series and parallel, and use the number of associated components as the priority level, and store them in a vector L, which contains the data structure of each node and the priority level of the node;

[0038] At the same time, the AOV graph is reduced, and the nodes with in-degree 1 are marked. If the predecessor node of a node is the same as the successor node of another node, they are added to the series set, merged into one node, added to the AOV graph and updated;

[0039] Among the marked nodes, all nodes with the same predecessor and successor nodes are marked, added to the parallel set, and merged into one node to add to the AOV graph and update.

[0040] As a preferred implementation scheme, the specific algorithm steps for performing a series scan on node e are as follows:

[0041] (1) Add node e itself to the series set Q;

[0042] (2) Scan backward along the successor nodes starting from node e. The scanning rule is: if the out-degree of the node is 1, add its successor node to the series set Q. Repeat this step until the condition is not met and jump to step (3), where the successor nodes are inserted after element e in sequence, that is, the elements in the series set are sorted in the series order.

[0043] (3) Scan forward from element e along the predecessor node. The scanning rule is: starting from element e, if the in-degree of the predecessor node of the element is 1 and the number of successor nodes of its predecessor node is also 1, then add the node to the series set Q, and then repeat the process from its predecessor node until the predecessor element of a certain element does not meet the conditions, then stop scanning, and the predecessor nodes are inserted in order in front of element e;

[0044] (4) If there is only the element itself in the series set Q, then exit the series scan, otherwise jump to step (5);

[0045] (5) Create logical nodes based on the scan results, including:

[0046] ① Create a logical node xand. Set the coordinates of xand directly to the coordinates of element e, set the predecessor node of xand to the predecessor node of the first element in set Q, and set the successor node of xand to the successor node of the last element in the series set Q.

[0047] ② Delete all elements in the series set Q from vector L and insert xand into vector L.

[0048] ③ Re-scan the series and parallel connection of the logical node, and use the number of directly connected series and parallel components as the priority, and update the priority of the directly connected series and parallel components at the same time. For example, if it is detected that the logical node has a directly connected series component, in addition to updating the priority of the logical node itself, the priority of the directly connected series component is increased by 1.

[0049] ④ Generate a tree node tand, and use the tree nodes corresponding to all elements in the series set Q as child nodes of tand.

[0050] As a preferred implementation scheme, the specific algorithm steps for parallel scanning of node e are as follows:

[0051] (1) First, add node e itself to the parallel set S.

[0052] (2) If the predecessor node of the component node e is a virtual node, if not, parallel scanning is performed; otherwise, it indicates that the component may have parallel components, and it is necessary to traverse the successor node set consisting of the successor nodes of the virtual node (except node e). If the successor nodes of the nodes in these successor node sets are the same as the successor nodes of the component node e, the nodes in the successor node set are added to the parallel set S, and the traversal of the successor node set is continued until there are no successor nodes, then the parallel scanning is exited.

[0053] (3) If there is only the element itself in the parallel set S, then exit the series scan; otherwise, jump to step (4).

[0054] (4) Create or logical nodes based on the scan results, including:

[0055] ① Create a logical node xor. The coordinates of xor are directly set to the coordinates of the e element, the predecessor node of xor is set to the predecessor node of any element in the parallel set S, and the successor node of xor is set to the successor node of any element in the parallel set S.

[0056] ② Delete all elements in the parallel set S in vector L and insert xor into vector L.

[0057] ③ Re-scan the logic node in series and parallel, and use the number of directly connected components in series and parallel as the priority, and update the priority of the directly connected components in series and parallel at the same time. For example, if it is detected that the logic node has a directly connected component in parallel, in addition to updating the priority of the logic node itself, the priority of the directly connected component is increased by 1.

[0058] ④ Generate a tree node tor, and use the tree nodes corresponding to all the elements in the parallel set S as the child nodes of tand. In order to correctly convert the statement table, it is necessary to sort the elements in the parallel set S from small to large according to their row numbers on the ladder diagram to ensure that the elements in the front row of the parallel branch are converted into statements first, and the elements in the back row are converted later.

[0059] The process of creating a logic tree based on serial and parallel scans includes:

[0060] (1) Generate a tree node for each element in the vector L. Initially, these nodes are leaf nodes of the logic tree and are pre-scanned.

[0061] (2) Sort the elements in vector L according to priority. If the number of elements in vector L is 1, the algorithm ends; otherwise, take the first element node e in vector L.

[0062] (3) Take out the element node e with the highest priority in the vector L and perform a series scan on it. Find all elements that have a direct series relationship with the element node e. These elements form the series set Q of e.

[0063] (4) If the number of elements in the series set Q is greater than 1, save the result of this series scan and return to step (2); otherwise, it means that there is no element directly connected in series with e at this time, update the element priority, and jump to step (5).

[0064] (5) Perform parallel scanning on the component node e. Find all components that have a direct parallel relationship with the component node e. These components constitute the parallel set S of the component node e.

[0065] (6) If the number of elements in the parallel set S is greater than 1, save the parallel scan result. Otherwise, update the element priority and return to (3).

[0066] S3: After obtaining the logic tree structure, the logic tree is subsequently traversed according to the logical relationship described by the logic tree to generate an instruction table structure. The generated logic tree is subsequently traversed, and an instruction table structure is generated during the traversal process. The access nodes of the logic tree are explained in five cases:

[0067] (1) If the component corresponding to the leaf node is an input contact, and the point is the first child of the parent node, an ID or LDI statement is generated according to the normally open or normally closed characteristics of the component.

[0068] (2) If the component corresponding to the leaf node is an input contact, and the point is not the first child of the parent node, if the parent node is an AND node, an AND or ANI statement is generated according to the normally open or normally closed characteristics of the component. If the parent node is an OR node, an OR or ORI statement is generated according to the normally open or normally closed characteristics of the component.

[0069] (3) If the element corresponding to the leaf node is an output coil, an OUT statement is generated.

[0070] (4) If a logic node has a left brother, it means that its child nodes need to be integrated into a statement block. If the parent node of the logic node is an AND node, an ANB statement is generated. If the parent node of the logic node is an OR node, an ORB statement is generated.

[0071] (5) If the logic node does not have a parent node, no statement is generated.

[0072] In order to further illustrate the scheme of the present invention, this embodiment provides Figure 2 The ladder diagram example shown in the figure is obtained by adding and deleting virtual nodes. Figure 2 The process of the AOV diagram corresponding to the ladder diagram shown specifically includes:

[0073] exist Figure 2 Add virtual nodes at the intersection of parallel connections in the ladder diagram shown. The added virtual nodes are {a, b, c, d, e, f, g, h, i}. All nodes are stored in a data structure, in which it is stipulated that arcs can only go downward or rightward;

[0074] Each node is traversed in a loop, and the associated virtual nodes are merged into one virtual node. The specific processing in this embodiment is described by taking the associated virtual nodes a, c, f, h} virtual nodes as an example, which specifically includes:

[0075] When scanning to virtual node a, delete the arc, delete the inner degree at virtual node c, delete the arc, delete the outer degree at virtual node c, and then insert the arc;

[0076] Do the same processing for the virtual node f, delete the inner degree at the virtual node f, delete the arc, delete the outer degree at the virtual node f, and then insert the arc;

[0077] Node h is processed in the same way as points c and f. In this way, {a, c, f, h} are merged into a virtual node a. The merging process of other virtual nodes is the same as above. The generated AOV graph after merging is as follows: Figure 4 shown.

[0078] After that, the data structure is updated. If the next node of the current node is a virtual node, the out-degree of the virtual node is observed. If the out-degree of the virtual node is greater than 1, the current node is pointed to the out-degree of the virtual node; if the next node of the current node is a symbol node, the loop traversal continues. In this way, a complete AOV graph can be obtained, and virtual nodes can be saved, reducing the complexity of the graph.

[0079] right Figure 4 The AOV map shown is pre-scanned and has the following steps:

[0080] The content of the initialization vector L is {0,1,2,3,4,5,6,7,8,9,10,11}, and each node is scanned in series and parallel;

[0081] When the node in-degree is only 1 during the scanning process, the node is marked as *. Figure 4 The set of nodes marked with * in is {1, 2, 3, 4, 6, 9, 10};

[0082] Find two nodes that have the same predecessor node as a node and the same successor node as another node and put them into the set. The successor node of node 2 is the same as the predecessor node of node 3. Merge them into node N1 and import them into the AOV graph. Put the two nodes into the series set Q1 according to the predecessor-successor relationship.

[0083] Find the nodes whose predecessor and successor nodes are exactly the same in the set and put them into the set. The predecessor and successor nodes of nodes 9 and 10 are exactly the same. Merge them into M1 node and import them into AOV graph, and put the two nodes into parallel set S1 in any order.

[0084] The pre-processed AOV image is as follows Figure 5 As shown, the content of the updated vector L is {0, 1, N1, 4, 5, 6, 7, 8, M1, 11}, and the priority level corresponding to each node is {1, 3, 3, 3, 2, 2, 2, 1, 1, 2}. After sorting, the logical relationship of node 1 is processed first, and then the series and parallel scanning is performed, which specifically includes:

[0085] Scan the preprocessed AOV graph, take out node 1 and scan it in series and parallel. Node n1 and node 4 are the elements directly connected in series with it. Generate the logic node xand1, update the AOV graph, and scan the logic node in series and parallel. Update the vector L. The content of vector L is updated to {0, xand1, 5, 6, 7, 8, M1, 11}. The corresponding priority levels of the nodes are {1, 1, 2, 2, 2, 1, 1, 2}. Generate the tree node tand1, where the n1 node has the series set Q1. The child nodes of the tree node are node 1, node 2, node 3 and node 4. After sorting, the logical relationship of node 5 is processed first.

[0086] Scan the AOV graph generated in the previous step, take out node 5 and scan it in series and parallel. Node 11 is the element directly connected in series with it, generate the logic node xand2, update the AOV graph, and scan the logic node in series and parallel. Update the vector L. The content of vector L is updated to {0, xand1, xand2, 6, 7, 8, M1}. The corresponding priority levels of the nodes are {1, 1, 1, 2, 2, 1, 1}. Generate the tree node tand2, whose child nodes are nodes 5 and 11. After sorting, give priority to the logical relationship of node 6.

[0087] Scan the AOV graph generated in the previous step, take out node 6 and scan it in series and parallel. Node 7 is the element directly connected in series with it, generate the logic node xand3, update the AOV graph, and scan the logic node in series and parallel. Update the vector L. The content of vector L is updated to {0, xand1, xand2, xand3, 8, M1}. The corresponding priority levels of the nodes are {1, 1, 1, 2, 1, 2}. Generate the tree node tand3, whose child nodes are nodes 6 and 7. After sorting, give priority to the logical relationship of node xand3.

[0088] Scan the AOV graph generated in the previous step, take out the node xand3 and scan it in series and parallel. The logic node m1 is the element directly connected in parallel with it, generate the logic node xor1, update the AOV graph, and scan the logic node in series and parallel. Update the vector L. The content of vector L is updated to {0,xand1,xand2,xor1,8}. The corresponding priority level of the node is {1,1,1,2,2}. Generate the tree node tor1, where the m1 node has a parallel set S1. The child nodes of the tree node are nodes xand3, node 9 and node 10. After sorting, the logical relationship of the logic node xor1 is prioritized.

[0089] Scan the AOV graph generated in the previous step, take out the logic node xor1 and scan it in series and parallel. Node 8 is the element directly connected in series with it, generate the logic node xand4, update the AOV graph, and scan the logic node in series and parallel. Update the vector L. The content of vector L is updated to {0, xand1, xand2, xand5}. The corresponding priority level of the node is {1, 2, 1, 2}. Generate the tree node tand4, whose child nodes are the logic node xor1 and node 8. After sorting, give priority to the logical relationship of the logic node xand1.

[0090] Scan the AOV graph generated in the previous step, take out the logic node xand1 and scan it in series and parallel. The logic node xand4 is the element directly connected in parallel with it, generate the logic node xor2, update the AOV graph, and scan the logic node in series and parallel. Update the vector L. The content of vector L is updated to {0,xor2,xand2}. The corresponding priority level of the node is {2,3,2}. Generate the tree node tor2, whose child nodes are the logic nodes xand1 and xand5. After sorting, give priority to the logical relationship of the logic node xor2.

[0091] Scan the AOV graph generated in the previous step, take out the logic node xor2 and scan it in series and parallel. The logic node xand2 and node 0 are directly connected in series with it. Generate the logic node xand6, update the AOV graph, and scan the logic node in series and parallel. Update the vector L. The content of vector L is updated to {xand6}. There is only one element in the set, and the scan is terminated.

[0092] The resulting logical tree is as follows Figure 6 shown.

[0093] After obtaining the logical tree structure, simplify it. The simplification rule is: for a logical node, if its logical type is the same as its parent node, directly add its child node to its parent node. For example Figure 6, tand2 and tand5 are parent-child logic nodes with the same logic, and node 5 and the output node are appended to the tand5 node. The simplified logic tree is as follows Figure 7 shown.

[0094] In S3, the specific algorithm for subsequent traversal is:

[0095] (1) First determine whether the root node is empty. If it is empty, jump to step (7) and end the current recursion. If it is not empty, execute step (2).

[0096] (2) Determine whether the current node has child nodes. If yes, access the current node. If no, continue to execute step (3).

[0097] (3) Recursively call the first child node of the current node, return to the current node after the call is completed, and continue to recurse on the next child node. Repeat this process until all child nodes are recursively traversed.

[0098] (4) Access the current node and print the data.

[0099] (5) Continue recursively returning to the previous level calling function. If there are other unprocessed child nodes, continue traversing the next child node and return to step (3). If all child nodes have been processed, jump to step (7).

[0100] (6) The recursion ends, returning to the previous level or ending the recursion.

[0101] The logical tree contains leaf nodes and logical nodes. In the subsequent traversal and statement table generation process, it is necessary to discuss the access nodes in different situations, namely:

[0102] a) If the component corresponding to the leaf node is an input contact, and the point is the first child of the parent node, generate an LD or LDI statement based on the normally open or normally closed characteristics of the component.

[0103] b) If the component corresponding to the leaf node is an input contact, and the point is not the first child of the parent node, if the parent node is an AND node, an AND or ANI statement is generated according to the normally open or normally closed characteristics of the component. If the parent node is an OR node, an OR or ORI statement is generated according to the normally open or normally closed characteristics of the component.

[0104] c) If the element corresponding to the leaf node is an output coil, an OUT statement is generated.

[0105] d) If a logic node has a left brother, it means that its child nodes need to be integrated into a statement block. If the parent node of the logic node is an AND node, an ANB statement is generated. If the parent node of the logic node is an OR node, an ORB statement is generated.

[0106] e) If the logical node does not have a parent node, no statement is generated.

[0107] This embodiment provides a specific traversal embodiment, including:

[0108] First, the subsequent traversal algorithm accesses node 5, which is a leaf node. The corresponding element is an input contact and is the first child node of its parent node. The LD instruction is generated in the first row of the instruction table.

[0109] Then, node 1 is accessed. The corresponding element is an input contact and is the first child node of its parent node. The LD instruction is generated in the second row of the instruction table.

[0110] Then, node 2 is accessed. The corresponding element is an input contact and is not the first child node of its parent node. The parent node is an AND node. An AND instruction is generated in the third row of the instruction table.

[0111] Then, we visit nodes 3 and 4 and perform the same logical processing as node 2, generating AND instructions in the fourth and fifth rows of the instruction table respectively;

[0112] Then visit the logical node tand1, which has no left sibling and does not generate any statement;

[0113] Then, node 8 is accessed, the corresponding element is an input contact and the first child node of its parent node, and the LD instruction is generated in the sixth row of the instruction table;

[0114] Then visit node 6, the corresponding element is the input contact and the first child node of its parent node, and generate the LD instruction in the seventh line of the instruction table

[0115] Then, node 7 is accessed. The corresponding element is an input contact and is not the first child node of its parent node. The parent node is an AND node. An AND instruction is generated in the eighth row of the instruction table.

[0116] Then visit the logical node tand3, which has no left brother and does not generate any statement;

[0117] Then, node 9 is accessed. The corresponding element is an input contact and is not the first child node of its parent node. The parent node is an OR node. An OR instruction is generated in the ninth row of the instruction table.

[0118] Then, node 10 is accessed. The corresponding element is an input contact and is not the first child node of its parent node. The parent node is an OR node. An OR instruction is generated in the tenth row of the instruction table.

[0119] Then, the logical node tor1 is accessed. There is a left brother whose parent node is an AND node. The ANB instruction is generated in the eleventh row of the instruction table.

[0120] Then, the logical node tand4 is accessed, and there is a left brother, whose parent node is an OR node, and an ORB instruction is generated in the twelfth line of the instruction table;

[0121] Then, the logical node tor2 is accessed. There is a left brother whose parent node is an AND node. The ANB instruction is generated in the thirteenth line of the instruction table.

[0122] Next, node 0 is accessed. The corresponding element is an input contact and is not the first child node of its parent node. The parent node is an AND node. An AND instruction is generated in the fourteenth line of the instruction table. Next, the output node is accessed. An OUT statement is generated in the fifteenth line of the instruction table.

[0123] Finally, the root logic node is accessed, which has no parent node and does not generate any statement. The instruction table generation ends here.

[0124] The final instruction table generated is as follows Figure 8 shown.

[0125] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A method for converting a ladder diagram of a PLC into an instruction table, converting a ladder diagram into a vertex activity diagram, characterized in that: A dynamic priority serial-parallel scanning method is used to generate a logic tree, and the logic tree is subsequently traversed to generate an instruction table structure. The dynamic priority serial-parallel scanning method is used to generate a logic tree, and the specific steps of the steps are as follows:

101. The number of components directly connected in series or in parallel with the current component is used as the priority of the current component, and a vector set L consisting of all components is generated by sorting them according to the priority, and a tree node is generated according to each component in the vector set L; 102. Determine whether the number of elements in the vector set L is 1, if so, end; 103. Otherwise, a series scan is performed on the node e with the highest priority in the vector set L, and a series set Q is generated between the node and other nodes connected in series with the node; 104. If the number of nodes in the series set Q is greater than 1, create and logical node xand and insert it into the vector set L, and delete the nodes in the vector set L that are the same as the series set Q; 105. Update the priority of the AND logical node according to the number of nodes directly connected to the AND logical node, and increase the priority of the component node directly connected in series or in parallel with the AND logical node by 1; 106. Generate a first tree node tand, and use the nodes in the series set Q as child nodes of the first tree node tand; 107. Determine whether the predecessor node of node e is a virtual node. If so, perform parallel scanning, and merge the nodes whose successor nodes of the successor node of the virtual node and the successor node of node e are the same as each other into a parallel set S.

108. If the number of nodes in the parallel set S is greater than 1, create an OR logic node xor and insert it into the vector set L, and delete the nodes in the vector set L that are the same as the parallel set S; 109. Update the priority of the OR logic node according to the number of nodes directly connected to the OR logic node, and increase the priority of the component node directly connected in series or in parallel with the OR logic node by 1; 110. Generate a second tree node tor, and use the nodes in the parallel set S as child nodes of the second tree node tor; 111. Return to step 102.

2. A method for converting a ladder diagram of a PLC into an instruction table according to claim 1, characterized in that: The nodes in the series set Q are arranged in a cascade order, and the predecessor node of the first node in the series set Q is used as the predecessor node of the sum logic node xand, and the successor node of the last node is used as the successor node of the sum logic node xand.

3. A method for converting a PLC ladder diagram into an instruction table according to claim 1, characterized in that: The predecessor node of any node in the parallel set S is used as the predecessor node of the OR logic node xor, and the successor node of any node is used as the successor node of the OR logic node xor.

4. A method for converting a PLC ladder diagram into an instruction table according to claim 1, characterized in that: The mapped vertex activity diagram is obtained by adding and deleting virtual nodes, including: adding virtual nodes at the intersection of parallel connections in the ladder diagram, storing all nodes in a data structure, wherein it is stipulated that arcs can only go downward or rightward, looping through each node, merging the associated virtual nodes into one virtual node, and if the next node of the current node is scanned as a virtual node, observing the out-degree size of the virtual node, if the out-degree of the virtual node is greater than 1, pointing the current node to the out-degree of the virtual node; if the next node of the current node is a component node, continuing the loop traversal.

5. A method for converting a PLC ladder diagram into an instruction table according to claim 1, characterized in that: Subsequent traversal of the logical tree involves: If the component corresponding to the leaf node is an input contact and the node is the first child node of the parent node, an ID or LDI statement is generated; If the element corresponding to the leaf node is an input contact and the node is not the first child node of the parent node, then if the parent node is an AND node, an AND or ANI statement is generated; if the parent node is an OR node, an OR or ORI statement is generated; If the element corresponding to the leaf node is an output coil, an OUT statement is generated; If a logical node has a left brother node, if the parent node of the logical node is an AND node, an ANB statement is generated; if the parent node of the logical node is an OR node, an ORB statement is generated; If the logic node does not have a parent node, no statement is generated.

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