Method and device for improving memory virtualization address substitution efficiency

Abstract

The invention relates to a memory virtualization address substitution efficiency improving method and device, and the method comprises the steps: a core analyzes the received previous address read response data, forms a current address, and sends a memory access request for the current address; after receiving the memory access request of the current address, the off-core Cache control component judges whether the generation of the next address depends on the current address or not; if yes, registering a prefetching start flag and a low address, and judging whether the prefetching request of the current address is executed or not; if the execution is finished, directly generating read response data of the current address; if the execution is not completed, merging the read request of the current address into the prefetch request of the current address, and generating read response data of the current address after receiving data of other cores or main memories; and forming a next address based on the read response data of the current address and the low address, and triggering a pre-fetching request for the next address. According to the invention, the efficiency of replacing the virtual address of the client into the physical address of the host can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of high-performance general-purpose processor microstructure design, and in particular to a method and device for improving memory virtualization address substitution efficiency. Background Art

[0002] Virtualization technology is a resource management technology that creates an abstraction layer on hardware through software, allowing multiple operating systems and applications to run simultaneously on the same physical machine and share its hardware resources such as CPU, memory, storage and network. Currently, virtualization technology has become an important support for cloud computing. By abstracting physical resources into logical resources, it makes it possible to flexibly configure and efficiently utilize resources, and it also has certain advantages in enhancing security.

[0003] Memory virtualization technology is a type of virtualization technology that allows multiple virtual machines to share the memory resources of a physical machine while ensuring that each virtual machine can run its own operating system and applications securely and independently. Memory virtualization technology can effectively improve processor resource utilization, reduce costs, and provide more flexible resource management. Since virtual machines use virtual address space and physical machines use physical address space, the core technology of memory virtualization is to quickly convert virtual addresses to physical addresses.

[0004] For the convenience of description, some terms are defined as follows:

[0005] Host: A host is a physical machine in a virtualized environment that has virtualization management software installed. It is responsible for executing the virtualization management software, managing the allocation of physical resources (such as CPU, memory, storage, and network interfaces), and providing a running environment for virtual machines.

[0006] Guest: A client machine refers to a virtual machine in a virtualized environment. It is created by the virtualization management software on the host machine. Each virtual machine can run a different operating system and install and run its own application.

[0007] GVA: Client virtual address, which refers to the instruction stream virtual address of the application on the client to access instructions or the data stream virtual address to access data;

[0008] GPA: client physical address, which refers to the physical address from the client's perspective;

[0009] HPA: Host physical address, which refers to the physical address actually mapped to the processor storage space, and is the actual physical address of the processor memory access;

[0010] GPT: Guest page table, located in the guest physical memory, maintained by the guest operating system, maps the guest virtual address GVA to the guest physical address GPA;

[0011] APT: The host's virtual machine monitor (Hypervisor) manages the page table, which is located in the host's physical memory and maintained by the Hypervisor, mapping the client physical address GPA to the host physical address HPA.

[0012] like Figure 1 As shown in the figure, the current mainstream hardware-assisted memory virtualization technology is that both the client and the host adopt page-based virtualization management, which means that the client virtual address GVA must go through two layers of page table substitution to obtain the real physical address HPA. First, the client virtual address GVA is substituted by the client page table GPT to obtain the virtual machine physical address GPA. This process is called traditional paging. Secondly, the client physical address GPA is substituted by the hypervisor management page table APT to obtain the host physical address HPA. This process is called additional paging.

[0013] As the scale of processor system hardware and software increases, the client virtual address space is getting larger and larger, and the effective bit width of the virtual address is getting wider and wider. For this reason, most processors use four-level or five-level page tables for management. Taking four-level page table management as an example, the binary representation of a client virtual address GVA (no more than 64 bits) is divided into five address areas, as shown in Table 1:

[0014] Table 1 Client virtual address table

[0015] PGDIndex PUDIndex PMDIndex PTEIndex Pageoffset

[0016] Among them, PGD Index is the index address of accessing the client page table global directory (Page GlobalDirectory, PGD, hereinafter referred to as the first-level GPT page table directory) during page table replacement, PUD Index is the index address of accessing the client page table upper directory (Page Upper Directory, PUD, hereinafter referred to as the second-level GPT page table directory) during page table replacement, PMD Index is the index address of accessing the client page table intermediate directory (Page Middle Directory, PMD, hereinafter referred to as the third-level GPT page table directory) during page table replacement, PTE Index is the index address of accessing the client page table entry (Page Table Entry, PTE, hereinafter referred to as the fourth-level GPT page table) during page table replacement, and Page offset is the offset address of the GVA address within the page. The address bit width of each area is related to the page granularity size. Usually, a page table entry occupies 64 bits in the main memory. Therefore, the bit widths of PGD Index, PUD Index, PMD Index and PTE Index are the same, and are 3 bits less than the bit width of Pageoffset. For example, when the page size is 4KB, the Page offset is 12 bits, the other fields are 9 bits each, and the GVA is 48 bits in total. When the page size is 8KB, the Page offset is 13 bits, the other fields are 10 bits each, and the GVA is 53 bits in total.

[0017] The client physical address is essentially a virtual address mapped to the host machine, and is also managed using a four-level page table. The binary representation of a client physical address GPA (no more than 64 bits) is divided into five address areas, as shown in Table 2:

[0018] Table 2 Client physical address table

[0019] APGDIndex APUDIndex APMD Index APTEIndex APageoffset

[0020] Among them, APGD Index is the index address of accessing the host machine page table global directory (Additional PageGlobal Directory, APGD, hereinafter referred to as the first-level APT page table directory) during page table replacement, APUD Index is the index address of accessing the host machine page table upper directory (Additional Page Upper Directory, APUD, hereinafter referred to as the second-level APT page table directory) during page table replacement, APMD Index is the index address of accessing the host machine page table intermediate directory (Additional Page Middle Directory, APMD, hereinafter referred to as the third-level APT page table directory) during page table replacement, APTE Index is the index address of accessing the host machine page table entry (Additional Page Table Entry, APTE, hereinafter referred to as the fourth-level APT page table) during page table replacement, and APage offset is the offset address of the GPA address within the page. Similarly, the bit widths of APUD Index, APMD Index, and APTE Index are the same, and are 3 bits less than the bit width of APage offset. The bit width of APGDIndex is determined according to the total address bit width of GPA. For example, when the page size is 4KB, the APage offset is 12 bits, the other fields are 9 bits each, and the GPA is 48 bits in total. When the page size is 8KB, the APage offset is 13 bits, the APGD Index field is 5 bits, the other fields are 10 bits each, and the GPA is 48 bits in total.

[0021] Figure 2 A schematic diagram of the GPA->HPA substitution is described. Figure 2 In the register, APTP is the register that stores the base address of the first-level APT page table directory, which is essentially the physical address of the host machine. Since the page table itself must be bounded according to the page granularity, APTP only stores the high bits of the page address where the first-level APT page table directory is located, and does not include the offset address within the page. It takes 9 steps for a GPA address to query the page table directory level by level and finally obtain the HPA address.

[0022] Figure 3 A schematic diagram of the GVA->GPA substitution is described. Figure 3In the , PTBR is the base address of the first-level GPT page table directory, which is a client physical address (GPA). Similar to APTP, PTBR only stores the high bits of the page address where the first-level GPT page table directory is located, and does not contain the offset address within the page. The addresses stored in the GPT page table directory and the GPT page table are also client physical addresses (GPA). Therefore, when querying the GPT page table directory or the GPT page table, address conversion from GPA to HPA is required. In memory virtualization technology, it takes 24 steps to replace a client virtual address (GVA) with a host physical address (HPA).

[0023] It can be seen that a client virtual address GVA needs to perform 24 memory access operations to replace the corresponding host physical address HPA, and the execution delay of this process is very large. To this end, the current processor provides some optimization methods, which significantly reduce the number of memory access operations and reduce the delay overhead of address replacement by adding a buffer to store a certain level of address conversion relationship. For example: the mapping relationship between GVA and HPA is stored in the address replacement buffer (TLB); the mapping relationship between GPA and HPA is also stored in the additional address replacement buffer (ATLB); the first, second, and third level GPT page table directory cache (Page Structure Cache, PSC) is added to store the mapping relationship between the client virtual address GVA and the GPT page table directory; the first, second, and third level APT page table directory cache (APT Page Structure Cache, APSC) is added to store the mapping relationship between the client physical address GPA and the APT page table directory. When the address replacement buffer or a certain level of page table directory buffer is hit, the number of memory access operations can be effectively reduced and the efficiency of address replacement can be improved.

[0024] Although current processors have adopted a number of technologies to accelerate the efficiency of replacing client virtual addresses (GVA) with host physical addresses (HPA), when the client virtual address (GVA) does not hit the address translation buffer (TLB, ATLB) or the page table directory buffer (PSC, APSC), multiple read operations must still be performed on the main memory to obtain the final host physical address page table. The specific number of main memory reads is closely related to the hit rate of the address substitution buffer and the page table directory buffer.

[0025] On the one hand, chip architecture is becoming more and more complex, the number of cores integrated in the chip is increasing, the memory space supported by the chip is also increasing, and the overhead of transmitting main memory read requests and responses and the overhead of data consistency processing are also increasing. Especially in the multi-chip integrated architecture, various requests and responses extended by a read memory access operation will also be transmitted across chips multiple times, and the memory access cost will rise sharply. On the other hand, in the face of big data applications, programs access cross-page granularity more frequently, and the hit rate that can be achieved by the address translation buffer (TLB, ATLB) and page table directory buffer (PSC, APSC) is very limited. The addresses of the page table directories at all levels themselves do not have obvious regularity, so the original data prefetching mechanism in the processor cannot cope with it. A large number of page table directory accesses can only be read from the main memory. Therefore, the time overhead of address substitution is very large, which will eventually affect the overall performance of the program. Summary of the invention

[0026] The technical problem to be solved by the present invention is to provide a method and device for improving the efficiency of memory virtualization address substitution, which can reduce the delay overhead of querying the page table directory and the page table when the address substitution buffer or the page table directory buffer is off target, and improve the efficiency of replacing the client virtual address with the host physical address.

[0027] The technical solution adopted by the present invention to solve the technical problem is: to provide a method for improving the efficiency of memory virtualization address substitution, comprising the following steps:

[0028] The core parses the received previous address read response data, forms the current address based on the parsed data, and issues a memory access request for the current address; the memory access request carries a prefetch start flag and a low-order address;

[0029] After receiving the memory access request of the current address, the external cache control component determines whether the generation of the next address depends on the read response data of the current address according to the pre-fetch start flag;

[0030] If the generation of the next address depends on the read response data of the current address, the external cache control component stores the pre-fetch start flag and the low-order address, and queries the external cache to determine whether the pre-fetch request for the current address has been completed;

[0031] If the pre-fetch request for the current address has been executed, the off-core cache control component directly generates the read response data of the current address;

[0032] If the prefetch request for the current address has not been completed, the off-core cache control component merges the read request for the current address into the prefetch request for the current address, and generates read response data for the current address after receiving data from other cores or main memory;

[0033] The off-core cache control component forms a next address based on the read response data of the current address and the low-order address, and triggers a pre-fetch request for the next address.

[0034] The prefetch start flag is set to 2 bits; when the prefetch start flag is "00", it means that the external core cache prefetch is not started; when the prefetch start flag is "10", it means that the external core cache read prefetch is started, and the latest copy of the corresponding address is stored in the external core cache, and there is no copy of the address in the cache inside other cores, or there is a shared read copy of the address; when the prefetch start flag is "11", it means that the external core cache write prefetch is started, and the latest copy of the corresponding address is stored in the external core cache, and there is no copy of the address inside other cores.

[0035] The method for improving memory virtualization address substitution efficiency also includes:

[0036] If the generation of the next address does not depend on the read response data of the current address, the external cache control component queries the external cache to determine whether the prefetch request for the current address has been executed;

[0037] If the pre-fetch request for the current address has been executed, the off-core cache control component directly generates the read response data of the current address;

[0038] If the prefetch request for the current address has not been completed, the off-core cache control component merges the read request for the current address into the prefetch request for the current address, and generates read response data for the current address after receiving data from other cores or main memory.

[0039] When the current address is the first address, the external cache control component, after receiving the memory access request of the current address, registers the pre-fetch start flag and the low-order address carried by the memory access request of the current address, and queries the external cache to determine whether the read request of the current address hits the external cache;

[0040] If the read request of the current address hits the off-core cache, the off-core cache control component directly generates the read response data of the current address and returns it to the core;

[0041] If the read request of the current address does not hit the off-core cache, the off-core cache control component reads the current address, parses the read response data of the current address from the data read from the current address, and returns it to the core.

[0042] The technical solution adopted by the present invention to solve the technical problem is: to provide a device for improving the efficiency of memory virtualization address substitution, comprising:

[0043] A parsing and sending module, used to control the core to parse the received previous address read response data, form a current address based on the parsed data, and issue a memory access request for the current address; the memory access request carries a pre-fetch start flag and a low-order address;

[0044] A first receiving and judging module is used to control the external cache control component to judge whether the generation of the next address depends on the read response data of the current address according to the prefetch start flag after receiving the memory access request of the current address;

[0045] A register determination module, used for controlling the external cache control component to register the pre-fetch start flag and the low-order address when the generation of the next address depends on the read response data of the current address, and querying the external cache to determine whether the pre-fetch request for the current address has been executed;

[0046] A first generating module, used for controlling the external cache control component to directly generate read response data of the current address when the pre-fetch request for the current address has been executed;

[0047] The second generating module is used for controlling the external cache control component to merge the read request of the current address into the pre-fetch request of the current address when the pre-fetch request of the current address is not completed, and generating the read response data of the current address after receiving the data of other cores or main memory;

[0048] The pre-fetch request triggering module is used to control the external cache control component to form a next address based on the read response data of the current address and the low-order address, and trigger a pre-fetch request for the next address.

[0049] The prefetch start flag is set to 2 bits; when the prefetch start flag is "00", it means that the external core cache prefetch is not started; when the prefetch start flag is "10", it means that the external core cache read prefetch is started, and the latest copy of the corresponding address is stored in the external core cache, and there is no copy of the address in the cache inside other cores, or there is a shared read copy of the address; when the prefetch start flag is "11", it means that the external core cache write prefetch is started, and the latest copy of the corresponding address is stored in the external core cache, and there is no copy of the address inside other cores.

[0050] The memory virtualization address substitution efficiency improving device further comprises:

[0051] A pre-fetch request execution judgment module, used for controlling the external cache control component to query the external cache to judge whether the pre-fetch request for the current address has been executed when the generation of the next address does not depend on the read response data of the current address;

[0052] A third generating module is used to control the external cache control component to directly generate the read response data of the current address when the pre-fetch request for the current address has been executed;

[0053] The fourth generation module is used to control the off-core cache control component to merge the read request of the current address into the prefetch request of the current address when the prefetch request for the current address has not been executed, and generate the read response data of the current address after receiving the data from other cores or main memory.

[0054] When the current address is the first address, the method further includes:

[0055] A second receiving and judging module is used for registering the pre-fetch start flag and the low-order address carried by the memory access request of the current address after the external-core cache control component receives the memory access request of the current address, and querying the external-core cache to judge whether the read request of the current address hits the external-core cache;

[0056] A fifth generating module, configured to control the external cache control component to directly generate the read response data of the current address and return it to the core when the read request of the current address hits the external cache;

[0057] The sixth generation module is used to control the off-core cache control component to read the current address when the read request of the current address does not hit the off-core cache, and parse the read response data from the data read from the current address and return it to the core.

[0058] The technical solution adopted by the present invention to solve its technical problem is: to provide an electronic device, including a memory, a processor and a computer program stored in the memory and executable on the processor, and the processor implements the steps of the above-mentioned method for improving the efficiency of memory virtualization address substitution when executing the computer program.

[0059] The technical solution adopted by the present invention to solve its technical problem is: providing a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the above-mentioned method for improving the efficiency of memory virtualization address substitution are implemented.

[0060] Beneficial Effects

[0061] Due to the adoption of the above-mentioned technical scheme, the present invention has the following advantages and positive effects compared with the prior art: the present invention makes full use of the address dependencies in the page table directories at all levels and the page table query process, as well as the off-core cache commonly possessed by current high-performance processors, and adds a small amount of control logic in the core and outside the core, so that the off-core cache can pre-fetch the address to be accessed under the prompt of the core, and store the data in the off-core cache in advance, so as to shorten the subsequent memory access delay to the address, make up for the performance bottleneck caused by the address substitution buffer or a certain level of page table directory buffer missing the target, and better support memory virtualization technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] Figure 1 It is an overview diagram of memory virtualization design in the prior art;

[0063] Figure 2 It is a schematic diagram of GPA address substitution in the prior art;

[0064] Figure 3 It is a schematic diagram of GVA address substitution in the prior art;

[0065] Figure 4 It is a flow chart of a method for improving memory virtualization address substitution efficiency according to a first embodiment of the present invention. DETAILED DESCRIPTION

[0066] The present invention will be further described below in conjunction with specific embodiments. It should be understood that these embodiments are only used to illustrate the present invention and are not intended to limit the scope of the present invention. In addition, it should be understood that after reading the content taught by the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms fall within the scope limited by the appended claims of the application equally.

[0067] The first embodiment of the present invention relates to a method for improving the efficiency of memory virtualization address replacement. The method utilizes the existing memory virtualization technology. When a client virtual address (GVA) is replaced with a host physical address (HPA), except for addresses Addr1, Addr6, Addr11, Addr16 and Addr21, the other 19 memory access addresses have a similar chain access pattern, that is, the data obtained in the previous memory access participates in the address generation of the next memory access, and the generation method is fixed. When the core issues an access to the page table directory or page table, the special prefetch start flag and other information involved in the prefetch address generation are carried to the off-core cache control component.

[0068] In this implementation, the prefetch start flag can be set to 2 bits. When the prefetch start flag is 2'b00, it indicates that the external cache prefetch is not started; when the prefetch start flag is 2'b10, it indicates that the external cache read prefetch is started, and the latest copy of the corresponding address is stored in the external cache. There is no copy of the address in the cache inside other cores, or there is a shared read copy of the address; when the prefetch start flag is 2'b11, it indicates that the external cache write prefetch is started, and the latest copy of the corresponding address is stored in the external cache. There is no copy of the address inside other cores.

[0069] The generation of the prefetch address only requires the core to carry the page offset address as the low-order address to the cache control unit outside the core. For example, when the page granularity is 4KB, only 12 bits of low-order address are carried; when the page granularity is 8KB, only 13 bits of low-order address are carried.

[0070] like Figure 4 As shown, the method for improving the efficiency of memory virtualization address substitution of this embodiment specifically includes the following steps:.

[0071] Step 1, the core parses the received previous address read response data, forms the current address based on the parsed data, and issues a memory access request for the current address; the memory access request carries a prefetch start flag and a low-order address;

[0072] Step 2, after receiving the memory access request of the current address, the external cache control component determines whether the generation of the next address depends on the read response data of the current address according to the prefetch start flag;

[0073] Step 3, if the generation of the next address depends on the read response data of the current address, the external cache control component stores the prefetch start flag and the low-order address, and queries the external cache to determine whether the prefetch request for the current address has been completed;

[0074] Step 4: If the pre-fetch request for the current address has been completed, the off-core cache control component directly generates read response data for the current address;

[0075] Step 5, if the prefetch request for the current address has not been completed, the off-core cache control component merges the read request for the current address into the prefetch request for the current address, and generates read response data for the current address after receiving data from other cores or main memory;

[0076] Step 6: The external cache control component forms a next address based on the read response data of the current address and the low-order address, and triggers a pre-fetch request for the next address.

[0077] It is not difficult to find that in this embodiment, when the off-core cache control component receives the response data of the page table directory or the page table memory access request, it directly parses its data according to the agreed page table format, generates the next-level page table directory or the page table memory access address, and triggers the pre-fetch request for the address, and pre-fetches the data into the off-core cache in advance. After the core receives the response data of the page table directory or the page table memory access request, it also parses its data according to the agreed page table format, generates the next-level page table directory or the page table memory access address, and sends it to the off-core cache. During this period of time, the pre-fetch request for the next-level page table directory or the page table memory access address has begun to execute, so when the read request for the next-level page table directory or the page table memory access address sent by the core is received, the pre-fetch request may have been executed, and the data required for the read request has been loaded into the off-core cache. Even if the pre-fetch request has not been executed, the read request of the same address can be merged into the pre-fetch request, and once the required data is loaded into the off-core cache, the response can be returned to the core. It can be seen from this that prefetching the next-level page table directory or page table access address that is clearly about to be accessed can always reduce the latency of actually reading the address, thereby speeding up the entire page table directory and page table query process.

[0078] In addition, when the core issues a memory access request to address Addr24, if the memory access request that triggers this round of virtual-real address substitution is a read type, it carries the prefetch start flag 2'b10; if the memory access request that triggers this round of virtual-real address substitution is a write type, it carries the prefetch start flag 2'b11. It also carries the low-order address GVA[Page offset]. After the read response data of address Addr24 is generated outside the core, it is returned to the core. At the same time, the page number is parsed according to the page table format agreed upon by the software and hardware, recorded as PTE_APTE, and concatenated with the carried low-order address GVA[Page offset] to form the host physical address HPA, and trigger a prefetch request for the address HPA. When the core receives the read response data of Addr24, it also forms HPA according to the same agreed rules. At this point, GVA is successfully substituted to obtain HPA, and a read or write access request to HPA is issued according to the original memory access request type.

[0079] In the method for improving the efficiency of memory virtualization address replacement of the present embodiment, the core can set a state machine for control. When issuing read requests for read addresses Addr1, Addr2, Addr3, Addr4, Addr6, Addr7, Addr8, Addr9, Addr11, Addr12, Addr13, Addr14, Addr16, Addr17, Addr18, Addr19, Addr21, Addr22, Addr23, and Addr24, they all need to carry a special prefetch start flag and other information involved in the generation of prefetch addresses.

[0080] When a read request is issued for read addresses Addr1, Addr6, Addr11, Addr16, and Addr21, since the generation of these addresses does not depend on the previous address, they can be regarded as the first address. Therefore, after receiving the memory access request for the first address, the external cache control component registers the pre-fetch start flag and the low-order address carried by the memory access request for the first address, and queries the external cache to determine whether the read request for the first address hits the external cache; if it hits the external cache, the external cache control component directly generates the read response data of the first address and returns it to the core; if it does not hit the external cache, the external cache control component reads the current address of this type, and parses the read response data of the current address from the data read from the first address and returns it to the core. After completion, the next address is formed based on the read response data of the first address and the low-order address, triggering a pre-fetch request for the next address.

[0081] When a read request is issued for read addresses Addr5, Addr10, Addr15, and Addr20, since the generation of the next address does not depend on the read response data of the current address, the core carries the pre-fetch start flag 2'b00 when issuing a memory access request for the address. At this time, the external cache control component can know that the generation of the next address does not depend on the current address. At this time, the external cache control component queries the external cache to determine whether the pre-fetch request for the current address has been completed; if the pre-fetch request for the current address has been completed, the external cache control component directly generates the read response data of the current address; if the pre-fetch request for the current address has not been completed, the external cache control component merges the read request of the current address into the pre-fetch request for the current address, and generates the read response data of the current address after receiving data from other cores or main memory. This process does not generate a pre-fetch request.

[0082] The following uses the complete 24 steps of replacing a client virtual address (GVA) with a host physical address (HPA) in memory virtualization technology as an example to further illustrate the detailed process of core-guided off-core cache prefetching. For the convenience of description, the following symbols and expressions are used as an example:

[0083] (1) Square brackets indicate a region of the address to be taken, such as: GPA[APGD Index] indicates the APGDIndex domain of the GPA address to be taken;

[0084] (2) The curly brackets and commas together indicate the bit-wise concatenation of different addresses. For example, assuming that the APGD Index field is 9 bits, {GPA[APGD Index],3'b0} means concatenating GPA[APGD Index] with 3 bits of 0, which is equivalent to shifting GPA[APGDIndex] left by 3 bits and appending 0.

[0085] In this embodiment, the page granularity is 8KB, the Page offset and APage offset are both 13 bits, the APGDIndex field is 5 bits, the other fields are all 10 bits, the client virtual address (GVA) is 53 bits in total, the client physical address (GPA) and the host physical address (HPA) are both 48 bits.

[0086] Specifically, the base address of the first-level APT page table directory APTP[47:13]={0x0,0x0,0xA0,0xFF} (the high-order address has 35 bits in total, represented here as the bit-wise concatenation of 5 / 10 / 10 / 10 bits), that is, APTP[47:13]=0x280FF.

[0087] The base address of the first-level GPT page table directory is PTBR[47:13] = {0x1, 0x2, 0x3, 0x4} (the high-order address has a total of 35 bits, which is represented here as the bitwise concatenation of 5 / 10 / 10 / 10 bits), that is, PTBR[47:13] = 0x40200C04. Among them, PTBR[APGDIndex] = 0x1, PTBR[APUD Index] = 0x2, PTBR[APMD Index] = 0x3, and PTBR[APTE Index] = 0x4.

[0088] The client virtual address is GVA[52:13]={0x5,0xA,0xF,0x14} (the high-order address is 40 bits in total, here represented by the bitwise concatenation of 10 / 10 / 10 / 10 bits), that is, GVA[52:13]=0x140A03C14. Among them, GVA[PGD Index]=0x5, GVA[PUD Index]=0xA, GVA[PMD Index]=0xF, GVA[PTE Index]=0x14. In addition, GVA[Page offset]=0x0.

[0089] The detailed process of address substitution and core-directed out-of-core cache prefetching is as follows:

[0090] 1) When the core issues a memory access request to address Addr1, it carries the prefetch start flag 2'b10 and the low address {PTBR[APUD Index], 3b'0} = 0x10. When the off-core cache control component receives the memory access request to address Addr1, it registers the prefetch start flag and the low address (0x10) it carries, and queries the off-core cache. If a hit is found, the read response data of address Addr1 is directly generated and returned to the core; if a hit is not found, the memory address 1 (Addr1) is read, Addr1[47:0] = {APTP, PTBR[APGD Index], 3'b0} = 0x501FE008, and the data read from Addr1 is parsed to obtain PTBR_APUD_Base, which is returned to the core. In this embodiment, PTBR_APUD_Base[47:13] = {0x0, 0x0, 0xA1, 0x1} = 0x28401. The off-core cache control component concatenates PTBR_APUD_Base and the low-order address 0x10 carried by address Addr1 to form address Addr2, where Addr2={PTBR_APUD_Base, PTBR[APUD Index], 3'b0}=0x50802010, and triggers a prefetch request for address Addr2.

[0091] 2) The core receives the read response data of address Addr1, and parses its data according to the page table format agreed upon by the software and hardware, splices it to form address Addr2, and issues a memory access request to address Addr2, carrying the prefetch start flag 2'b10 and the low address {PTBR[APMD Index], 3b'0} = 0x18. When the off-core cache control unit receives the memory access request to address Addr2, it registers the prefetch start flag and the low address ({0x18) it carries, and queries the off-core cache. If the prefetch request for address Addr2 has been executed, the read request for address Addr2 hits the off-core cache, and the read response data of address Addr2 can be directly generated; if the prefetch request for address Addr2 has not been executed, the read request for address Addr2 is merged into the prefetch request for Addr2. After receiving data from other cores or main memory, the read response data of address Addr2 is generated, and the data read from Addr2 is parsed to obtain PTBR_APMD_Base. In this embodiment, PTBR_APMD_Base[47:13]={0x0,0x0,0xA2,0x2}=0x28802. The off-core cache control component concatenates PTBR_APMD_Base and the low-order address 0x18 carried by address Addr2 to form address Addr3, where Addr3={PTBR_APMD_Base, PTBR[APMDIndex], 3'b0}=0x51004018, and triggers a prefetch request for address Addr3.

[0092] 3) The core receives the read response data of address Addr2, and parses its data according to the page table format agreed upon by the software and hardware, concatenates it to form address Addr3, and issues a memory access request to address Addr3, carrying the prefetch enable flag 2'b10 and the low-order address {PTBR[APTE Index], 3b'0} = 0x20. When the off-core cache control unit receives the memory access request to address Addr3, it registers the prefetch enable flag and the low-order address (0x20) it carries, and queries the off-core cache. If the prefetch request for address Addr3 has been completed, the read request for address Addr3 hits the off-core cache, and the read response data for address Addr3 can be directly generated; if the prefetch request for address Addr3 has not been completed, the read request for address Addr3 is merged into the prefetch request for Addr3, and after receiving data from other cores or main memory, the read response data for address Addr3 is generated, and the data read from Addr3 is parsed to obtain PTBR_APTE_Base. In this embodiment, PTBR_APTE_Base[47:13]={0x0,0x0,0xA3,0x3}=0x28C03. The off-core cache control component concatenates PTBR_APTE_Base with the low-order address 0x20 carried by address Addr3 to form address Addr4, Addr4={PTBR_APTE_Base,PTBR[APTE Index],3'b0}=0x51806020, and triggers the prefetch request for address Addr4.

[0093] 4) The core receives the read response data of address Addr3, and parses its data according to the page table format agreed upon by the software and hardware, splices it to form address Addr4, and issues a memory access request to address Addr4, carrying the prefetch enable flag 2'b10 and the low-order address {GVA[PGD Index]], 3b'0} = 0x28. When the off-core cache control unit receives the memory access request to address Addr4, it registers the prefetch enable flag and the low-order address (0x28) it carries, and queries the off-core cache. If the prefetch request for address Addr4 has been completed, the read request for address Addr4 hits the off-core cache, and the read response data of address Addr4 can be directly generated; if the prefetch request for address Addr4 has not been completed, the read request for address Addr4 is merged into the prefetch request for Addr4, and after receiving the data from other cores or main memory, the read response data of address Addr4 is generated, and the data read from Addr4 is parsed to obtain PTBR_APTE. In this embodiment, PTBR_APTE[47:13]={0x0,0x0,0xA4,0x4}=0x29004. The off-core cache control component concatenates PTBR_APTE with the low-order address 0x28 carried by address Addr4 to form address Addr5, Addr5={PTBR_APTE,GVA[PGD Index],3'b0}=0x52008028, and triggers the prefetch request for address Addr5.

[0094] 5) The core receives the read response data of address Addr4, and parses its data according to the page table format agreed upon by the software and hardware, splices it to form address Addr5, and issues a memory access request to address Addr5. Since the generation of address Addr6 does not directly depend on address Addr5, when the core issues a memory access request to address Addr5, it carries the prefetch start flag 2'b00; the off-core cache control component sees that the start prefetch flag is 2'b00, does not parse the read response data, and does not generate a corresponding prefetch request. When the off-core cache control component receives a memory access request to address Addr5, it queries the off-core cache. If the prefetch request for address Addr5 has been completed, the read request for address Addr5 hits the external cache, and the read response data for address Addr5 can be directly generated; if the prefetch request for address Addr5 has not been completed, the read request for address Addr5 is merged into the prefetch request for Addr5, and after receiving data from other cores or main memory, the read response data for address Addr5 is generated, and the page number is parsed from the data read from Addr5, which is recorded as PUD_Base. In this embodiment, PUD_Base[47:13]={0x6,0x7,0x8,0x9}=0x180702009. The external cache control component cannot obtain address Addr6 at this time, so no prefetch request is generated.

[0095] Since the processing flow of addresses Addr6 to Addr10, Addr11 to Addr15, Addr16 to Addr20, and Addr21 to Addr23 is similar to the processing flow of Addr1 to Addr5, for simplicity, in the subsequent steps of Addr6 to Addr23, only the parsed data obtained by reading and accessing the memory address is briefly described.

[0096] 6) Read access memory address 6 (Addr6), Addr6 = {APTP, PUD_Base [APGD Index], 3'b0} = 0x501FE030, and parse the data read from Addr6 to obtain PUD_Base_APUD_Base. In this embodiment, PUD_Base_APUD_Base [47:13] = {0x0, 0x0, 0xA1, 0x6} = 0x28406;

[0097] 7) Read access memory address 7 (Addr7), Addr7 = {PUD_Base_APUD_Base, PUD_Base[APUDIndex], 3'b0} = 0x5080C038, and parse the data read from Addr7 to obtain PUD_Base_APMD_Base. In this embodiment, PUD_Base_APMD_Base[47:13] = {0x0, 0x0, 0xA7, 0x7} = 0x29C07;

[0098] 8) Read access memory address 8 (Addr8), Addr8 = {PUD_Base_APMD_Base, PUD_Base[APMDIndex], 3'b0} = 0x5380E040, and parse the data read from Addr8 to obtain PUD_Base_APTE_Base. In this embodiment, PUD_Base_APTE_Base[47:13] = {0x0, 0x0, 0xA8, 0x8} = 0x2A008;

[0099] 9) Read access memory address 9 (Addr9), Addr9 = {PUD_Base_APTE_Base, PUD_Base[APTEIndex], 3'b0} = 0x54010048, and parse the data read from Addr9 to obtain PUD_Base_APTE. In this embodiment, PUD_Base_APTE[47:13] = {0x0, 0x0, 0xA9, 0x9} = 0x2A409;

[0100] 10) Read access to memory address 10 (Addr10), Addr10 = {PUD_Base_APTE, GVA [PUD Index], 3'b0} = 0x54812050, the data read from Addr10 is parsed to obtain the page number, recorded as PMD_Base, in this embodiment, PMD_Base [47:13] = {0xB, 0xC, 0xD, 0xE} = 0x2C0C0340E;

[0101] 11) Read access memory address 11 (Addr11), Addr11 = {APTP, PMD_Base [APGD Index], 3'b0} = 0x501FE058, and parse the page number read from Addr11 to obtain PMD_Base_APUD_Base. In this embodiment, PMD_Base_APUD_Base [47:13] = {0x0, 0x0, 0xA1, 0xB} = 0x2840B;

[0102] 12) Read access memory address 12 (Addr12), Addr12 = {PMD_Base_APUD_Base, PMD_Base[APUDIndex], 3'b0} = 0x50816060, and parse the data read from Addr12 to obtain PMD_Base_APMD_Base. In this embodiment, PMD_Base_APMD_Base[47:13] = {0x0, 0x0, 0xAC, 0xC} = 0x2B00C;

[0103] 13) Read access memory address 13 (Addr13), Addr13 = {PMD_Base_APMD_Base, PMD_Base[APMDIndex], 3'b0} = 0x56018068, and parse the data read from Addr13 to obtain PMD_Base_APTE_Base. In this embodiment, PMD_Base_APTE_Base[47:13] = {0x0, 0x0, 0xAD, 0xD} = 0x2B40D;

[0104] 14) Read access memory address 14 (Addr14), Addr14 = {PMD_Base_APTE_Base, PMD_Base[APTEIndex], 3'b0} = 0x5681A070, and parse the data read from Addr14 to obtain PMD_Base_APTE. In this embodiment, PMD_Base_APTE[47:13] = {0x0, 0x0, 0xAE, 0xE} = 0x2B80E;

[0105] 15) Read access to memory address 15 (Addr15), Addr15 = {PMD_Base_APTE, GVA [PMD Index], 3'b0} = 0x5701C078, the data read from Addr15 is parsed to obtain the page number, recorded as PTE_Base, in this embodiment, PTE_Base [47:13] = {0x10, 0x11, 0x12, 0x13} = 0x401104813;

[0106] 16) Read access memory address 16 (Addr16), Address16 = {APTP, PTE_Base [APGD Index], 3'b0} = 0x501FE080, and parse the data read from Addr16 to obtain PTE_Base_APUD_Base. In this embodiment, PTE_Base_APUD_Base [47:13] = {0x0, 0x0, 0xA1, 0x10} = 0x28410;

[0107] 17) Read access memory address 17 (Addr17), Addr17 = {PTE_Base_APUD_Base, PTE_Base[APUDIndex], 3'b0} = 0x50820088, and parse the data read from Addr17 to obtain PTE_Base_APMD_Base. In this embodiment, PTE_Base_APMD_Base[47:13] = {0x0, 0x0, 0xB1, 0x11} = 0x2C411;

[0108] 18) Read access memory address 18 (Addr18), Addr18 = {PTE_Base_APMD_Base, PTE_Base[APMDIndex], 3'b0} = 0x58822090, and parse the data read from Addr18 to obtain PTE_Base_APTE_Base. In this embodiment, PTE_Base_APTE_Base[47:13] = {0x0, 0x0, 0xB2, 0x12} = 0x2C812;

[0109] 19) Read access memory address 19 (Addr19), Addr19 = {PTE_Base_APTE_Base, PTE_Base[APTEIndex], 3'b0} = 0x59024098, and parse the data read from Addr19 to obtain PTE_Base_APTE. In this embodiment, PTE_Base_APTE[47:13] = {0x0, 0x0, 0xB3, 0x13} = 0x2CC13;

[0110] 20) Read access to memory address 20 (Addr20), Addr20 = {PTE_Base_APTE, GVA [PTE Index], 3'b0} = 0x598260A0, the data read from Addr20 is parsed to obtain the page number, recorded as PTE, in this embodiment, PTE [47:13] = {0x15, 0x16, 0x17, 0x18} = 0x541605C18;

[0111] 21) Read access to memory address 21 (Addr21), Addr21 = {APTP, PTE [APGD Index], 3'b0} = 0x501FE0A8, and parse the data read from Addr21 to obtain PTE_APUD_Base. In this embodiment, PTE_APUD_Base [47:13] = {0x0, 0x0, 0xA1, 0x15} = 0x28415;

[0112] 22) Read access memory address 22 (Addr22), Addr22 = {PTE_APUD_Base, PTE[APUD Index], 3'b0} = 0x5082A0B0, and parse the data read from Addr22 to obtain PTE_APMD_Base. In this embodiment, PTE_APMD_Base[47:13] = {0x0, 0x0, 0xB6, 0x16} = 0x2D816;

[0113] 23) Read access memory address 23 (Addr23), Addr23 = {PTE_APMD_Base, PTE[APMD Index], 3'b0} = 0x5B02C0B8, and parse the data read from Addr23 to obtain PTE_APTE_Base. In this embodiment, PTE_APTE_Base[47:13] = {0x0, 0x0, 0xB7, 0x17} = 0x2DC17;

[0114] 24) The core receives the read response data of address Addr23, parses its data according to the page table format agreed upon by the software and hardware, and splices it to form address Addr24, Addr24 = {PTE_APTE_Base, PTE[APTE Index], 3'b0} = 0x5B82E0C0, and issues a memory access request for address Addr24, carrying the prefetch start flag and the low address GVA[Page offset] = 0x0. If the memory access request that triggers this round of virtual-real address substitution is a read type, it carries the prefetch start flag 2'b10; if the memory access request that triggers this round of virtual-real address substitution is a write type, it carries the prefetch start flag 2'b11. When the off-core cache control component receives the memory access request for address Addr24, it queries the off-core cache. If it hits, the read response data of address Addr24 is directly generated and returned to the core; if it does not hit, the memory address 24 (Addr24) is read and accessed, and the data read from Addr24 is parsed to obtain PTE_APTE, which is returned to the core. In this embodiment, PTE_APTE[47:13]={0x0,0x0,0xB8,0x18}=0x2E018. The off-core cache control component forms the host physical address HPA by splicing PTE_APTE with the low address 0x0 carried by address Addr24, and HPA={PTE_APTE,GVA[Page offset]}=0x5C030000, and triggers a prefetch request for address HPA. When the core receives the read response data of Addr24, it also forms HPA according to the same agreed rules. At this point, GVA is finally replaced to obtain HPA, and a read or write access request to HPA is issued according to the original memory access request type.

[0115] It is not difficult to find that the present invention makes full use of the address dependencies in the page table directories at all levels and the page table query process, as well as the off-core cache commonly possessed by current high-performance processors. By adding a small amount of control logic in the core and outside the core, the off-core cache is allowed to pre-fetch the address to be accessed under the prompt of the core, and store the data in the off-core cache in advance, so as to shorten the subsequent memory access delay to the address, make up for the performance bottleneck caused by the address substitution buffer or a certain level of page table directory buffer being off-target, and better support memory virtualization technology.

[0116] A second embodiment of the present invention relates to a device for improving memory virtualization address substitution efficiency, comprising:

[0117] A parsing and sending module, used to control the core to parse the received previous address read response data, form a current address based on the parsed data, and issue a memory access request for the current address; the memory access request carries a pre-fetch start flag and a low-order address;

[0118] A first receiving and judging module is used to control the external cache control component to judge whether the generation of the next address depends on the read response data of the current address according to the prefetch start flag after receiving the memory access request of the current address;

[0119] A register determination module, used for controlling the external cache control component to register the pre-fetch start flag and the low-order address when the generation of the next address depends on the read response data of the current address, and querying the external cache to determine whether the pre-fetch request for the current address has been executed;

[0120] A first generating module, used for controlling the external cache control component to directly generate read response data of the current address when the pre-fetch request for the current address has been executed;

[0121] The second generating module is used for controlling the external cache control component to merge the read request of the current address into the pre-fetch request of the current address when the pre-fetch request of the current address is not completed, and generating the read response data of the current address after receiving the data of other cores or main memory;

[0122] The pre-fetch request triggering module is used to control the external cache control component to form a next address based on the read response data of the current address and the low-order address, and trigger a pre-fetch request for the next address.

[0123] The prefetch start flag is set to 2 bits; when the prefetch start flag is "00", it means that the external core cache prefetch is not started; when the prefetch start flag is "10", it means that the external core cache read prefetch is started, and the latest copy of the corresponding address is stored in the external core cache, and there is no copy of the address in the cache inside other cores, or there is a shared read copy of the address; when the prefetch start flag is "11", it means that the external core cache write prefetch is started, and the latest copy of the corresponding address is stored in the external core cache, and there is no copy of the address inside other cores.

[0124] The memory virtualization address substitution efficiency improving device further comprises:

[0125] A pre-fetch request execution judgment module, used for controlling the external cache control component to query the external cache to judge whether the pre-fetch request for the current address has been executed when the generation of the next address does not depend on the read response data of the current address;

[0126] A third generating module is used to control the external cache control component to directly generate the read response data of the current address when the pre-fetch request for the current address has been executed;

[0127] The fourth generation module is used to control the off-core cache control component to merge the read request of the current address into the prefetch request of the current address when the prefetch request for the current address has not been executed, and generate the read response data of the current address after receiving the data from other cores or main memory.

[0128] When the current address is the first address, the method further includes:

[0129] A second receiving and judging module is used for registering the pre-fetch start flag and the low-order address carried by the memory access request of the current address after the external-core cache control component receives the memory access request of the current address, and querying the external-core cache to judge whether the read request of the current address hits the external-core cache;

[0130] A fifth generating module, configured to control the external cache control component to directly generate the read response data of the current address and return it to the core when the read request of the current address hits the external cache;

[0131] The sixth generation module is used to control the off-core cache control component to read the current address when the read request of the current address does not hit the off-core cache, and parse the read response data from the data read from the current address and return it to the core.

[0132] A third embodiment of the present invention relates to an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the method for improving the efficiency of memory virtualization address substitution of the first embodiment when executing the computer program.

[0133] A fourth embodiment of the present invention relates to a computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the steps of the method for improving the efficiency of memory virtualization address substitution of the first embodiment are implemented.

[0134] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) that contain computer-usable program code.

[0135] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0136] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction method, which is implemented in the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0137] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1The steps for the functions specified in one or more boxes.

[0138] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A method for improving memory virtualization address substitution efficiency, characterized in that: The following steps are involved: The core parses the received previous address read response data, forms the current address based on the parsed data, and issues a memory access request for the current address; the memory access request carries a prefetch start flag and a low-order address; After receiving the memory access request of the current address, the external cache control component determines whether the generation of the next address depends on the read response data of the current address according to the pre-fetch start flag; If the generation of the next address depends on the read response data of the current address, the external cache control component stores the pre-fetch start flag and the low-order address, and queries the external cache to determine whether the pre-fetch request for the current address has been completed; If the pre-fetch request for the current address has been executed, the external cache control component directly generates the read response data of the current address; If the prefetch request for the current address has not been completed, the off-core cache control component merges the read request for the current address into the prefetch request for the current address, and generates read response data for the current address after receiving data from other cores or main memory; The off-core cache control component forms a next address based on the read response data of the current address and the low-order address, and triggers a pre-fetch request for the next address.

2. The method for improving memory virtualization address substitution efficiency according to claim 1, characterized in that: The prefetch start flag is set to 2 bits; when the prefetch start flag is "00", it means that the prefetch of the external core cache is not started; when the prefetch start flag is "10", it means that the prefetch of the external core cache is started, and the latest copy of the corresponding address is stored in the external core cache, and there is no copy of the address in the internal cache of other cores, or there is a shared read copy of the address; When the prefetch start flag is "11", it means that the off-core cache write prefetch is started. The latest copy of the corresponding address is stored in the off-core cache, and there is no copy of the address in other cores.

3. The method for improving memory virtualization address substitution efficiency according to claim 1, characterized in that: Also includes: If the generation of the next address does not depend on the read response data of the current address, the external cache control component queries the external cache to determine whether the prefetch request for the current address has been executed; If the pre-fetch request for the current address has been executed, the external cache control component directly generates the read response data of the current address; If the prefetch request for the current address has not been completed, the off-core cache control component merges the read request for the current address into the prefetch request for the current address, and generates read response data for the current address after receiving data from other cores or main memory.

4. The method for improving memory virtualization address substitution efficiency according to claim 1, characterized in that: When the current address is the first address, the external cache control component, after receiving the memory access request of the current address, registers the pre-fetch start flag and the low-order address carried by the memory access request of the current address, and queries the external cache to determine whether the read request of the current address hits the external cache; If the read request of the current address hits the off-core cache, the off-core cache control component directly generates the read response data of the current address and returns it to the core; If the read request of the current address does not hit the off-core cache, the off-core cache control component reads the current address, parses the read response data of the current address from the data read from the current address, and returns it to the core.

5. A device for improving memory virtualization address substitution efficiency, characterized in that: include: A parsing and sending module, used to control the core to parse the received previous address read response data, form a current address based on the parsed data, and issue a memory access request for the current address; the memory access request carries a pre-fetch start flag and a low-order address; The first receiving and judging module is used to control the external cache control component to receive the memory access request of the current address. Determining whether generation of a next address depends on read response data of the current address according to the prefetch start flag; A register determination module, used for controlling the external cache control component to register the pre-fetch start flag and the low-order address when the generation of the next address depends on the read response data of the current address, and querying the external cache to determine whether the pre-fetch request for the current address has been executed; A first generating module, used for controlling the external cache control component to directly generate read response data of the current address when the pre-fetch request for the current address has been executed; The second generating module is used for controlling the external cache control component to merge the read request of the current address into the pre-fetch request of the current address when the pre-fetch request of the current address is not completed, and generating the read response data of the current address after receiving the data of other cores or main memory; The pre-fetch request triggering module is used to control the external cache control component to form a next address based on the read response data of the current address and the low-order address, and trigger a pre-fetch request for the next address.

6. The device for improving memory virtualization address substitution efficiency according to claim 5, characterized in that: The prefetch start flag is set to 2 bits; when the prefetch start flag is "00", it means that the prefetch of the external core cache is not started; when the prefetch start flag is "10", it means that the prefetch of the external core cache is started, and the latest copy of the corresponding address is stored in the external core cache, and there is no copy of the address in the internal cache of other cores, or there is a shared read copy of the address; When the prefetch start flag is "11", it means that the off-core cache write prefetch is started. The latest copy of the corresponding address is stored in the off-core cache, and there is no copy of the address in other cores.

7. The device for improving memory virtualization address substitution efficiency according to claim 5, characterized in that: Also includes: A pre-fetch request execution judgment module, used for controlling the external cache control component to query the external cache to judge whether the pre-fetch request for the current address has been executed when the generation of the next address does not depend on the read response data of the current address; A third generating module is used to control the external cache control component to directly generate the read response data of the current address when the pre-fetch request for the current address has been executed; The fourth generation module is used to control the off-core cache control component to merge the read request of the current address into the prefetch request of the current address when the prefetch request for the current address has not been executed, and generate the read response data of the current address after receiving the data from other cores or main memory.

8. The device for improving memory virtualization address substitution efficiency according to claim 5, characterized in that: When the current address is the first address, the method further includes: A second receiving and judging module is used for registering the pre-fetch start flag and the low-order address carried by the memory access request of the current address after the external-core cache control component receives the memory access request of the current address, and querying the external-core cache to judge whether the read request of the current address hits the external-core cache; A fifth generating module, configured to control the external cache control component to directly generate the read response data of the current address and return it to the core when the read request of the current address hits the external cache; The sixth generation module is used to control the off-core cache control component to read the current address when the read request of the current address does not hit the off-core cache, and parse the read response data from the data read from the current address and return it to the core.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the steps of the method for improving the efficiency of memory virtualization address substitution as described in any one of claims 1-4 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method for improving the efficiency of memory virtualization address substitution as described in any one of claims 1 to 4 are implemented.

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