A de-emphasis device, a de-emphasis method and a core particle integrated system

Abstract

The application provides a de-emphasis device, a de-emphasis method and a chip integrated system, and the de-emphasis device comprises a main-tap data logic module, a balance-tap data logic module, a drive switch logic module, a main-tap drive stage and a balance drive stage. The main-tap data logic module forms main-tap data according to to-be-transmitted data; the balance-tap data logic module forms balance-tap data according to the to-be-transmitted data, the balance-tap data is opposite to the main-tap data, and the balance-tap data and the main-tap data exist in a unit interval; the drive switch logic module generates a drive switch signal according to the main-tap data and the balance-tap data, and the drive switch signal is valid when the tap data and the balance-tap data are the same and is invalid when the tap data and the balance-tap data are opposite; the main-tap drive stage is enabled by the main-tap data; and the balance drive stage is driven by the balance-tap data and is enabled or closed by the drive switch signal. The de-emphasis device, the de-emphasis method and the chip integrated system provided by the application can save the power consumption of a transmitter.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and specifically relates to a de-weighting device, a de-weighting method, and a chip integration system. Background Technology

[0002] With the increasing demands for computing power in high-performance computing, chiplet-integrated systems are needed to meet these requirements. The transmitter driver stage is a crucial component of the physical layer of the high-speed interconnect interface between chipslets. Given the low-pass characteristics of the channel, the driver stage of a high-speed interface transmitter typically possesses a certain leveling capability. Among these, de-emphasis technology has become the most commonly used leveling technique due to its simplicity and practicality.

[0003] In the de-emphasis device, the main tap path and the equalization path are configured with independent driver stages, and all driver stages are connected in parallel to drive the channel. In this case, the driving directions of the main tap path and the equalization path for their respective driver stages may be opposite. If the driver stage of the main tap path is pulled up while the driver stage of the equalization path is pulled down, a short-circuit current will be generated inside the transmitter driver stage. Although the short-circuit current helps the transmitter achieve equalization, it does not actually drive the channel or the receiver at the other end; instead, it is consumed within the transmitter driver stage, thus increasing the transmitter's ineffective power consumption and limiting the overall energy efficiency of the high-speed interface. Summary of the Invention

[0004] The purpose of this invention is to provide a de-weighting device, a de-weighting method, and a core-integrated system, which can solve the problem of short-circuit current generated inside the transmitter driver stage, limiting the energy efficiency of high-speed interfaces.

[0005] To achieve the above objectives, the present invention provides a weight removal device, comprising at least:

[0006] The main tap data logic module generates main tap data based on the data to be transmitted.

[0007] The equalization tap data logic module generates equalization tap data based on the data to be transmitted. The equalization tap data is inversely related to the main tap data, and there is a unit interval between the equalization tap data and the main tap data.

[0008] The drive switch logic module generates a drive switch signal based on the main tap data and the equalization tap data. The drive switch signal is valid when the tap data and the equalization tap data are the same, and invalid when the tap data and the equalization tap data are opposite.

[0009] The master tap driver stage is enabled and driven by the master tap data.

[0010] The equalization drive stage is driven by the equalization tap data and is enabled or disabled by the drive switch signal.

[0011] In one embodiment of the present invention, the equalization tap data logic module includes a pre-tap data logic module, which generates pre-tap data based on the data to be transmitted. The pre-tap data is inversely related to the main tap data and is one unit interval ahead of the main tap data.

[0012] In one embodiment of the present invention, the drive switch logic module includes a pre-tap drive switch logic module, which performs logical operations on the main tap data and the pre-tap data to generate a pre-tap drive switch signal.

[0013] In one embodiment of the present invention, the equalization drive stage includes a pre-tap drive stage, which is electrically connected to the output terminal of the pre-tap data logic module and the output terminal of the pre-tap drive switch logic module. The pre-tap drive stage is driven by the pre-tap data and controlled to be enabled or disabled by the pre-tap drive switch signal.

[0014] In one embodiment of the present invention, if the pre-tap data and the main tap data are the same, the pre-tap drive switch logic module outputs a valid pre-tap drive switch signal, and the pre-tap drive stage is enabled and driven by the pre-tap data output by the pre-tap data logic module.

[0015] In one embodiment of the present invention, the equalization tap data logic module includes a post-tap data logic module, which generates post-tap data based on the data to be transmitted. The post-tap data is inversely related to the main tap data and is delayed by one unit interval compared to the main tap data.

[0016] In one embodiment of the present invention, the drive switch logic module includes a back tap drive switch logic module, which performs logical operations on the main tap data and the back tap data to generate a back tap drive switch signal.

[0017] In one embodiment of the present invention, the equalization drive stage includes a back-tap drive stage, which is electrically connected to the output terminal of the back-tap data logic module and the output terminal of the back-tap drive switch logic module. It is driven by the back-tap data and controlled to be enabled or disabled by the back-tap drive switch signal.

[0018] In one embodiment of the present invention, if the back tap data and the main tap data are the same, the back tap drive switch logic module outputs a valid back tap drive switch signal, and the back tap drive stage is enabled and driven by the back tap data output by the back tap data logic module.

[0019] In one embodiment of the present invention, the main tap data logic module includes a first trigger, the input terminal of the first trigger is input to the data to be transmitted, and the output terminal of the first trigger is output to the main tap data;

[0020] The main tap drive stage includes a first source series termination driver, which is connected in series between the power supply and the ground terminal, and the control terminal of the control tube in the first source series termination driver is controlled by the main tap data.

[0021] In one embodiment of the present invention, the equalization tap data logic module includes a pre-tap data logic module, the pre-tap data logic module includes a first inverter, the input terminal of the first inverter receives the data to be transmitted, and the output terminal of the first inverter outputs the pre-tap data.

[0022] In one embodiment of the present invention, the driving switch logic module includes a pre-tap driving switch logic module, the pre-tap driving switch logic module comprising:

[0023] A first XOR gate, the input of which is electrically connected to the output of the pre-tap data logic module and the output of the main tap data logic module, and the output of which outputs a first pre-tap drive switch signal; and

[0024] The third inverter has its input terminal electrically connected to the output terminal of the first XOR gate, and its output terminal outputs a second pre-tap drive switch signal.

[0025] In one embodiment of the present invention, the equalization drive stage includes a pre-tap drive stage, which includes a first control switch, a second source series terminal driver, and a second control switch connected in series. The first control switch, the second source series terminal driver, and the second control switch are connected in series between a power supply and a ground terminal. The control terminal of the control transistor in the second source series terminal driver is controlled by the main tap data. The first control switch is controlled by the first pre-tap drive switch signal, and the second control switch is controlled by the second pre-tap drive switch signal.

[0026] In one embodiment of the present invention, the equalization tap data logic module includes a back tap data logic module, the back tap data logic module includes a second flip-flop and a second inverter, the input terminal of the second flip-flop is electrically connected to the output terminal of the first flip-flop, the input terminal of the second inverter is electrically connected to the output terminal of the second flip-flop, and the output terminal of the second inverter outputs the back tap data.

[0027] In one embodiment of the present invention, the driving switch logic module includes a back-tap driving switch logic module, the back-tap driving switch logic module comprising:

[0028] A second XOR gate, the input of which is electrically connected to the output of the back-tap data logic module and the output of the main-tap data logic module, and the output of which outputs a first back-tap drive switch signal; and

[0029] The fourth inverter has its input terminal electrically connected to the output terminal of the second XOR gate, and its output terminal outputs a second back-tap drive switch signal.

[0030] In one embodiment of the present invention, the equalization drive stage includes a back-tap drive stage, which includes a third control switch, a third source series terminal driver, and a fourth control switch connected in series. The third control switch, the third source series terminal driver, and the fourth control switch are connected in series between the power supply and the ground terminal. The control terminal of the control transistor in the third source series terminal driver is controlled by the main tap data. The third control switch is controlled by the first back-tap drive switch signal, and the fourth control switch is controlled by the second back-tap drive switch signal.

[0031] The present invention also provides a method for removing excess weight, comprising the following steps:

[0032] The master tap data is generated using the master tap data logic module;

[0033] Balanced tap data is generated using a balanced tap data logic module. The balanced tap data is the inverse of the main tap data, and there is a unit interval between the balanced tap data and the main tap data.

[0034] A drive switch signal is generated using a drive switch logic module. The drive switch signal is valid when the tap data and the equalization tap data are the same, and invalid when the tap data and the equalization tap data are opposite.

[0035] Enable the main tap driver stage using the aforementioned main tap data; and

[0036] The equalization driver stage is driven using the equalization tap data, and the equalization driver stage is enabled or disabled using the drive switch signal.

[0037] The present invention also provides a core-integrated system comprising multiple cores, wherein the deweighting device as described in any of the preceding claims is disposed in the transmitter of the cores.

[0038] In summary, the de-emphasis device, de-emphasis method, and chip-integrated system provided by this invention compare the main tap data output by the main tap data logic module in the main path with the equalization tap data logic module output by the equalization tap data logic module in the equalization path to generate a drive switch signal. This signal enables the equalization drive stage in the equalization path, thereby preventing the equalization drive stage in the equalization path from driving in the opposite direction to the main drive stage in the main path, eliminating short-circuit current within the drive stage, and thus saving transmitter power consumption. Furthermore, the module generating the drive switch signal in this invention is constructed using CMOS circuitry, resulting in simple logic, no static operating current, and a negligible impact on the overall transmitter power consumption. In addition, the de-emphasis device proposed in this invention has a wide range of applications, allowing for greater reuse of existing circuit modules, which helps reduce design complexity and shorten the development cycle. Attached Figure Description

[0039] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is a structural block diagram of the weight removal device in one embodiment of this application.

[0041] Figure 2 This is a signal waveform diagram of the de-emphasis device in one embodiment of this application.

[0042] Figure 3 This is a circuit diagram of the weight removal device in one embodiment of this application.

[0043] Label Explanation:

[0044] 1011, Pre-tap data logic module; 1012, Main tap data logic module; 1013, Rear tap data logic module; 1021, Pre-tap drive switch logic module; 1022, Rear tap drive switch logic module; 1031, Pre-tap drive stage; 1032, Main tap drive stage; 1033, Rear tap drive stage; 201, First source series termination driver; 202, Second source series termination driver; 203, Third source series termination driver. Detailed Implementation

[0045] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure of this application.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0047] In the description of this invention, it should be understood that the terms "center," "upper," "lower," "front," "rear," "left," and "right," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0048] As the computational power requirements of high-performance computing (HPC) continue to increase, systems using single-chip solutions are increasingly unable to meet the performance demands. Simultaneously, the area of ​​single computing chips capable of providing significant computing power is growing, posing a considerable challenge to chip yield. In this context, chip-integrated systems have become a crucial means of addressing the challenges of HPC. In chip-integrated systems, high-frequency data interaction is required between different chips to complete related calculations; therefore, the high-speed interconnect interface for data transmission between chips becomes one of the most important components of the chip-integrated system. The physical layer of the high-speed interconnect directly processes high-speed data, and its performance directly affects the data transmission efficiency of the high-speed interconnect. The transmitter driver stage is a crucial component of the physical layer of the high-speed interconnect interface between chips. Given the low-pass characteristics of the channel, the driver stage of the high-speed interface transmitter typically possesses a certain leveling capability, with de-emphasis technology being the most commonly used equalization technique due to its simplicity and practicality.

[0049] Please see Figure 1As shown, in one embodiment of the present invention, a de-emphasis device, a de-emphasis method, and a chip integration system are provided. The de-emphasis device is disposed in the chip integration system and located within the transmitter of the chip. Specifically, the de-emphasis device is disposed in the physical layer of the high-speed data transmission interface transmitter between chips. Of course, the de-emphasis device can also be used in other circuits and systems that require this function.

[0050] For details, please refer to Figure 1 As shown, in one embodiment of the present invention, the de-emphasis device includes a data logic module, a drive switch logic module, and a drive stage. The data logic module includes a main tap data logic module 1012 and an equalization tap data logic module. The main tap data logic module 1012 generates main tap data D_MAIN based on the data to be transmitted, D_IN. The equalization tap data logic module generates equalization tap data based on the data to be transmitted, D_IN. The equalization tap data is inversely related to the main tap data D_MAIN, and a unit interval is provided between the equalization tap data and the main tap data D_MAIN. The drive switch logic module generates a drive switch signal based on the main tap data D_MAIN and the equalization tap data. The drive switch signal is valid when the tap data and the equalization tap data are the same, and invalid when the tap data and the equalization tap data are opposite. The driver stage includes a main tap driver stage 1032 and an equalization driver stage. The main tap driver stage 1032 is enabled and driven by the main tap data D_MAIN, and the equalization driver stage is driven by the equalization tap data and is enabled or disabled by the driver switch signal.

[0051] Please see Figure 1 and Figure 2 As shown, in one embodiment of the present invention, the equalization tap data logic module includes a pre-tap data logic module 1011. The pre-tap data logic module 1011 receives the data to be transmitted, D_IN, and forms pre-tap data D_PRE based on the data to be transmitted, D_IN. Figure 2 As shown, in this embodiment, the pre-tap data D_PRE is out of phase with the main tap data D_MAIN, and the pre-tap data D_PRE is one unit interval ahead of the main tap data D_MAIN.

[0052] Please see Figure 1 and Figure 2 As shown, in one embodiment of the present invention, the equalization tap data logic module includes a post-tap data logic module 1013. The post-tap data logic module 1013 receives the data to be transmitted, D_IN, and forms post-tap data D_POST based on the data to be transmitted, D_IN. Figure 2 As shown, in this embodiment, the subsequent tap data D_POST is out of phase with the main tap data D_MAIN, and the subsequent tap data D_POST is delayed by one unit interval compared to the main tap data D_MAIN.

[0053] Please see Figure 1 and Figure 2 As shown, in one embodiment of the present invention, the drive switch logic module includes a pre-tap drive switch logic module 1021. The pre-tap drive switch logic module 1021 is electrically connected to the output terminal of the pre-tap data logic module 1011 and the output terminal of the main tap data logic module 1012, and performs logical operations on the main tap data D_MAIN and the pre-tap data D_PRE to generate a pre-tap drive switch signal SW_PRE. Combined with... Figure 2 As shown, the pre-tap drive switch signal SW_PRE is valid when the main tap data D_MAIN and the pre-tap data D_PRE are the same, enabling the pre-tap drive stage 1031. The pre-tap drive switch signal SW_PRE is invalid when the main tap data D_MAIN and the pre-tap data D_PRE are opposite, disabling the pre-tap drive stage 1031.

[0054] Please see Figure 1 and Figure 2 As shown, in one embodiment of the present invention, the drive switch logic module includes a back-tap drive switch logic module 1022. The back-tap drive switch logic module 1022 is electrically connected to the output terminal of the back-tap data logic module 1013 and the output terminal of the main-tap data logic module 1012, performing logical operations on the main-tap data D_MAIN and the back-tap data D_POST to generate a back-tap drive switch signal SW_POST. Combined with... Figure 2 As shown, the back tap drive switch signal SW_POST is valid when the main tap data D_MAIN and the back tap data D_POST are the same, enabling the back tap drive stage 1033. The back tap drive switch signal SW_POST is invalid when the main tap data D_MAIN and the back tap data D_POST are opposite, disabling the back tap drive stage 1033.

[0055] Please see Figure 1 and Figure 2 As shown, in one embodiment of the present invention, the equalization drive stage includes a pre-tap drive stage 1031. The pre-tap drive stage 1031 is electrically connected to the output terminal of the pre-tap data logic module 1011 and the output terminal of the pre-tap drive switch logic module 1021, is driven by pre-tap data D_PRE, and is enabled or disabled by the pre-tap drive switch signal SW_PRE. (In conjunction with...) Figure 2As shown, the pre-tap drive stage 1031 is enabled when the pre-tap data logic module 1011 outputs pre-tap data D_PRE and the pre-tap drive switch logic module 1021 outputs a valid pre-tap drive switch signal SW_PRE. The pre-tap drive stage 1031 is disabled when the pre-tap data logic module 1011 does not output pre-tap data D_PRE or the pre-tap drive switch logic module 1021 outputs an invalid pre-tap drive switch signal SW_PRE. When the pre-tap drive stage 1031 is disabled, its output is in a high-impedance state.

[0056] Please see Figure 1 and Figure 2 As shown, in one embodiment of the present invention, the equalization drive stage includes a back-tap drive stage 1033. The back-tap drive stage 1033 is electrically connected to the output terminal of the back-tap data logic module 1013 and the output terminal of the back-tap drive switch logic module 1022, is driven by the back-tap data D_POST, and is enabled or disabled by the back-tap drive switch signal SW_POST. (In conjunction with...) Figure 2 As shown, when the back-tap data logic module 1013 outputs back-tap data D_POST and the back-tap drive switch logic module 1022 outputs a valid back-tap drive switch signal SW_POST, the back-tap drive stage 1033 is turned on. When the back-tap data logic module 1013 does not output back-tap data D_POST or the back-tap drive switch logic module 1022 outputs an invalid back-tap drive switch signal SW_POST, the back-tap drive stage 1033 is turned off. And when the back-tap drive stage 1033 is turned off, its output is in a high-impedance state.

[0057] Please note that you should refer to [link / reference]. Figure 1 As shown, the main de-emphasis path includes a main tap data logic module 1012 and a main tap driver stage 1032, and the de-emphasis equalization path includes an equalization tap data logic module, an equalization tap driver switch logic module, and an equalization driver stage. In this application, one equalization path or two equalization paths can be configured. When one equalization path is configured, it can be a pre-tap path including a pre-tap data logic module 1011, a pre-tap driver switch logic module 1021, and a pre-tap driver stage 1031. Alternatively, it can be a post-tap path including a post-tap data logic module 1013, a post-tap driver switch logic module 1022, and a post-tap driver stage 1033. When two equalization paths are set, that is, the de-weighting device simultaneously sets a pre-tap path including a pre-tap data logic module 1011, a pre-tap drive switch logic module 1021 and a pre-tap drive stage 1031, and a rear-tap path including a rear-tap data logic module 1013, a rear-tap drive switch logic module 1022 and a rear-tap drive stage 1033.

[0058] Please see Figure 1 and Figure 2 As shown, in the channel where the de-emphasis device provided in this application is located, the data receiving end is equipped with a termination circuit. At this time, by controlling the opening and closing of the pre-tap drive stage 1031 and the post-tap drive stage 1033, the driving capability of the overall drive stage output by the de-emphasis device can be adjusted, thereby achieving the equalization effect without generating short-circuit current.

[0059] For details, please refer to Figure 1 and Figure 2 As shown, when the de-emphasis device provided in this application is used to implement the de-emphasis method, the main tap data logic module 1012 forms main tap data D_MAIN based on the data to be transmitted D_IN. The equalization tap data logic module forms equalization tap data based on the data to be transmitted D_IN. The equalization tap data is out of phase with the main tap data D_MAIN, and a unit interval is set between the equalization tap data and the main tap data D_MAIN. The drive switch logic module generates a drive switch signal based on the main tap data D_MAIN and the equalization tap data. The drive switch signal is valid when the tap data and the equalization tap data are the same, and invalid when the tap data and the equalization tap data are opposite. The drive stage includes a main tap drive stage 1032 and an equalization drive stage. The main tap drive stage 1032 is enabled and driven by the main tap data D_MAIN, and the equalization drive stage is driven by the equalization tap data and is controlled to be enabled or disabled by the drive switch signal.

[0060] Please see Figure 1 and Figure 2 As shown, in one embodiment of the present invention, the equalization path in the de-emphasis device is inactive, and only the main path independently drives the channel. At this time, neither the pre-tap path nor the post-tap path has an output, and only the main path independently drives the channel. Specifically, in some embodiments, the pre-tap data D_PRE output by the pre-tap data logic module 1011 is opposite to the main tap data D_MAIN output by the main tap data logic module 1012, the pre-tap drive switch logic module 1021 outputs an invalid pre-tap drive switch signal SW_PRE, and the pre-tap drive stage 1031 is turned off. In some embodiments, the post-tap data D_POST output by the post-tap data logic module 1013 is opposite to the main tap data D_MAIN output by the main tap data logic module 1012, the drive switch logic module outputs an invalid post-tap drive switch signal SW_POST, and the post-tap drive stage 1033 is turned off. The main tap driver stage 1032 is enabled and driven by the main tap data D_MAIN output from the main tap data logic module 1012, and the channel is driven independently by the main tap driver stage 1032. At this time, the online data output by the deemphasis device is as follows: Figure 2 As shown in section a.

[0061] Please see Figure 1 and Figure 2 As shown, in one embodiment of the present invention, an equalization path is provided in the de-emphasis device, which is a pre-tap path including a pre-tap data logic module 1011, a pre-tap drive switch logic module 1021, and a pre-tap drive stage 1031. At this time, if the pre-tap data D_PRE output by the pre-tap data logic module 1011 is the same as the main tap data D_MAIN output by the main tap data logic module 1012, the pre-tap drive switch logic module 1021 outputs a valid pre-tap drive switch signal SW_PRE, and the pre-tap drive stage 1031 is enabled and driven by the pre-tap data D_PRE output by the pre-tap data logic module 1011. Simultaneously, the main tap drive stage 1032 is enabled and driven by the main tap data D_MAIN output by the main tap data logic module 1012. The pre-tap driver stage 1031 and the main tap driver stage 1032 have the same driving direction and superimposed driving capabilities, so the channel is jointly driven by the pre-tap driver stage 1031 and the main tap driver stage 1032. At this time, the online data output by the deemphasis device is as follows: Figure 2 As shown in section b. If the pre-tap data D_PRE output by the pre-tap data logic module 1011 is opposite to the main tap data D_MAIN output by the main tap data logic module 1012, then the pre-tap drive switch logic module 1021 outputs an invalid pre-tap drive switch signal SW_PRE, and the pre-tap drive stage 1031 is turned off. The main tap drive stage 1032 is enabled and driven by the main tap data D_MAIN output by the main tap data logic module 1012, and the channel is driven independently by the main tap drive stage 1032. At this time, the online data output by the deemphasis device is as follows: Figure 2 As shown in section a. Therefore, the pre-tap path has two operating states. In the two operating states, the de-emphasis device can provide different driving capabilities, and can generate different signal swings when there is a termination circuit at the receiving end, thereby achieving the equalization effect.

[0062] Please see Figure 1 and Figure 2As shown, in one embodiment of the present invention, an equalization path is provided in the de-emphasis device, which is a back-tap path including a back-tap data logic module 1013, a back-tap drive switch logic module 1022, and a back-tap drive stage 1033. At this time, if the back-tap data D_POST output by the back-tap data logic module 1013 is the same as the main-tap data D_MAIN output by the main-tap data logic module 1012, the back-tap drive switch logic module 1022 outputs a valid back-tap drive switch signal SW_POST, and the back-tap drive stage 1033 is enabled and driven by the back-tap data D_POST output by the back-tap data logic module 1013. Simultaneously, the main-tap drive stage 1032 is enabled and driven by the main-tap data D_MAIN output by the main-tap data logic module 1012. The back-tap driver stage 1033 and the main-tap driver stage 1032 have the same driving direction and their driving capabilities are superimposed. The channel is jointly driven by the back-tap driver stage 1033 and the main-tap driver stage 1032. At this time, the online data output by the deemphasis device is as follows: Figure 2 As shown in section c. If the back tap data D_POST output by the back tap data logic module 1013 is opposite to the main tap data D_MAIN output by the main tap data logic module 1012, then the back tap drive switch logic module 1022 outputs an invalid back tap drive switch signal SW_POST, and the back tap drive stage 1033 is turned off. The main tap drive stage 1032 is enabled and driven by the main tap data D_MAIN output by the main tap data logic module 1012, and the channel is driven independently by the main tap drive stage 1032. At this time, the online data output by the deemphasis device is as follows: Figure 2 As shown in section a. Therefore, the post-tap path has two operating states. In these two operating states, the de-emphasis device can provide different driving capabilities, and with a termination circuit at the receiving end, it can generate different signal swings, thereby achieving a balancing effect.

[0063] Please see Figure 1 and Figure 2As shown, in one embodiment of the present invention, two equalization paths are provided in the de-emphasis device. One path includes a pre-tap data logic module 1011, a pre-tap drive switch logic module 1021, and a pre-tap drive stage 1031; the other path includes a post-tap data logic module 1013, a post-tap drive switch logic module 1022, and a post-tap drive stage 1033. If the pre-tap data D_PRE output by the pre-tap data logic module 1011 is the same as the main tap data D_MAIN output by the main tap data logic module 1012, the pre-tap drive switch logic module 1021 outputs a valid pre-tap drive switch signal SW_PRE, and the pre-tap drive stage 1031 is enabled and driven by the pre-tap data D_PRE output by the pre-tap data logic module 1011. The back-tap data D_POST output by the back-tap data logic module 1013 is the same as the main-tap data D_MAIN output by the main-tap data logic module 1012. The drive switch logic module outputs a valid back-tap drive switch signal SW_POST, and the back-tap drive stage 1033 is enabled and driven by the back-tap data D_POST output by the back-tap data logic module 1013. Simultaneously, the main-tap drive stage 1032 is enabled and driven by the main-tap data D_MAIN output by the main-tap data logic module 1012. The driving directions of the pre-tap drive stage 1031, the back-tap drive stage 1033, and the main-tap drive stage 1032 are the same, and their driving capabilities are superimposed. The channel is jointly driven by the pre-tap drive stage 1031, the back-tap drive stage 1033, and the main-tap drive stage 1032. At this time, the online data output by the de-emphasis device is as follows: Figure 2 As shown in section d. If the pre-tap data D_PRE output by the pre-tap data logic module 1011 is the same as the main tap data D_MAIN output by the main tap data logic module 1012, and the post-tap data D_POST output by the post-tap data logic module 1013 is opposite to the main tap data D_MAIN output by the main tap data logic module 1012, then the online data output by the deemphasis device is as follows. Figure 2 As shown in section b. If the pre-tap data D_PRE output by the pre-tap data logic module 1011 is opposite to the main tap data D_MAIN output by the main tap data logic module 1012, and the post-tap data D_POST output by the post-tap data logic module 1013 is the same as the main tap data D_MAIN output by the main tap data logic module 1012, then the online data output by the deemphasis device is as follows. Figure 2 As shown in section c. If the pre-tap data D_PRE output by the pre-tap data logic module 1011 is opposite to the main tap data D_MAIN output by the main tap data logic module 1012, and the post-tap data D_POST output by the post-tap data logic module 1013 is opposite to the main tap data D_MAIN output by the main tap data logic module 1012, then the online data output by the deemphasis device is as follows. Figure 2 As shown in section a. Therefore, setting up two equalization paths can provide greater driving capability, thereby generating a larger signal swing. At this time, as... Figure 2 As shown, the online data waveform output by the transmitter has a de-emphasis equalization effect, and no short-circuit current is generated inside the drive stage under the control of the drive switch signal.

[0064] Please see Figure 3 As shown, in one embodiment of the present invention, the pre-tap data logic module 1011, the main tap data logic module 1012, and the post-tap data logic module 1013 first use flip-flops to achieve a phase shift of one unit interval between data points, and then use inverters to invert the pre-tap data D_PRE, the main tap data D_MAIN, and the post-tap data D_POST. Specifically, the pre-tap data logic module 1011 includes a first inverter N1, the input of which is the data to be transmitted D_IN, and the output of which is the pre-tap data D_PRE. The pre-tap data logic module 1011 inverts the data to be transmitted D_IN to form the pre-tap data D_PRE. The main tap data logic module 1012 includes a first flip-flop D1, the input of which is the data to be transmitted D_IN, and the output of which is the main tap data D_MAIN. The main tap data logic module 1012 delays the data to be transmitted, D_IN, by one unit interval to form the main tap data, D_MAIN. The post-tap data logic module 1013 includes a second flip-flop D2 and a second inverter N2. The input of the second flip-flop D2 is electrically connected to the output of the first flip-flop D1, and the input of the second inverter N2 is electrically connected to the output of the second flip-flop D2. The output of the second inverter N2 outputs the post-tap data, D_POST. The post-tap data logic module 1013 delays the main tap data, D_MAIN, by one unit interval and then inverts it to form the post-tap data, D_POST.

[0065] Please see Figure 3As shown, in one embodiment of the present invention, the pre-tap drive switch logic module 1021 and the post-tap drive switch logic module 1022 are implemented using XOR gates. Furthermore, in this embodiment, since the pre-tap drive stage 1031 and the post-tap drive stage 1033 require two opposite drive switch signals, inverters are also included in the pre-tap drive switch logic module 1021 and the post-tap drive switch logic module 1022. Specifically, the pre-tap drive switch logic module 1021 includes a first XOR gate L1 and a third inverter N3. The input of the first XOR gate L1 is electrically connected to the output of the pre-tap data logic module 1011 and the output of the main tap data logic module 1012, and the output of the first XOR gate L1 outputs a first pre-tap drive switch signal SW_PRE_a. The input of the third inverter N3 is electrically connected to the output of the first XOR gate L1, and the output of the third inverter N3 outputs a second pre-tap drive switch signal SW_PRE_b. The back-tap drive switch logic module 1022 includes a second XOR gate L2 and a fourth inverter N4. The input of the second XOR gate L2 is electrically connected to the output of the back-tap data logic module 1013 and the output of the main-tap data logic module 1012, and the output of the second XOR gate L2 outputs a first back-tap drive switch signal SW_POST_a. The input of the fourth inverter N4 is electrically connected to the output of the second XOR gate L2, and the output of the fourth inverter N4 outputs a second back-tap drive switch signal SW_POST_b.

[0066] Please see Figure 3 As shown, in one embodiment of the present invention, the master tap driver stage 1032 includes a source-series-terminated (SST) driver, which is a first source-series-terminated driver 202. The first source-series-terminated driver 202 is connected in series between the power supply and the ground terminal, and the control terminal of the control transistor in the first source-series-terminated driver 202 is controlled by the master tap data D_MAIN.

[0067] Please see Figure 3 As shown, in one embodiment of the present invention, the source-series termination driver includes a first control transistor M1, a first resistor R1, a second resistor R2, and a second control transistor M2 connected in series. The power supply, the first control transistor M1, the first resistor R1, the second resistor R2, the second control transistor M2, and the ground terminal are connected in series. The first control transistor M1 and the second control transistor M2 are NMOS transistors, and the control terminals of the first control transistor M1 and the second control transistor M2 are controlled by the main tap data D_MAIN. The model of the first control transistor M1 and the second control transistor M2, as well as the resistance values ​​of the first resistor R1 and the second resistor R2, are set according to the driving capability of the driver stage.

[0068] Please see Figure 3As shown, in one embodiment of the present invention, the pre-tap drive stage 1031 and the post-tap drive stage 1033 include a source-series termination driver and two control switches. The pre-tap drive stage 1031 includes a first control switch MP1, a second source-series termination driver 201, and a second control switch MN1 connected in series. The first control switch MP1 is a PMOS, and the second control switch MN1 is an NMOS. The first control switch MP1, the second source-series termination driver 201, and the second control switch MN1 are connected in series between the power supply and ground. The control terminal of the control transistor in the second source-series termination driver 201 is controlled by the main tap data D_MAIN, the control terminal of the first control switch MP1 is controlled by the first pre-tap drive switch signal SW_PRE_a, and the control terminal of the second control switch MN1 is controlled by the second pre-tap drive switch signal SW_PRE_b. The post-tap drive stage 1033 includes a third control switch MP2, a third source-series termination driver 203, and a fourth control switch MN2 connected in series. In this configuration, the third control switch MP2 is a PMOS, and the fourth control switch MN2 is an NMOS. The third control switch MP2, the third source-series termination driver 203, and the fourth control switch MN2 are connected in series between the power supply and the ground terminal. The control terminal of the control transistor in the third source-series termination driver 203 is controlled by the main tap data D_MAIN, the control terminal of the third control switch MP2 is controlled by the first post-tap drive switch signal SW_POST_a, and the control terminal of the fourth control switch MN2 is controlled by the second post-tap drive switch signal SW_POST_b.

[0069] In summary, the present invention provides a de-weighting device, a de-weighting method, and a core-integrated system. The de-weighting device includes a main tap data logic module, an equalization tap data logic module, a drive switch logic module, a main tap drive stage, and an equalization drive stage. The main tap data logic module generates main tap data based on the data to be transmitted. The equalization tap data logic module generates equalization tap data based on the data to be transmitted; the equalization tap data is inversely related to the main tap data, and there is a unit interval between them. The drive switch logic module generates a drive switch signal based on the main tap data and the equalization tap data; the drive switch signal is valid when the tap data and the equalization tap data are the same, and invalid when they are opposite. The main tap drive stage is enabled and driven by the main tap data. The equalization drive stage is driven by the equalization tap data and is controlled to be enabled or disabled by the drive switch signal.

[0070] The embodiments of the present invention disclosed above are merely illustrative of the invention. The embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A weight removal device, characterized in that, At least including: The main tap data logic module generates main tap data based on the data to be transmitted. The equalization tap data logic module generates equalization tap data based on the data to be transmitted. The equalization tap data is inversely related to the main tap data, and there is a unit interval between the equalization tap data and the main tap data. The drive switch logic module generates a drive switch signal based on the main tap data and the equalization tap data. The drive switch signal is valid when the tap data and the equalization tap data are the same, and invalid when the tap data and the equalization tap data are opposite. The master tap driver stage is enabled and driven by the master tap data. The equalization drive stage is driven by the equalization tap data and is enabled or disabled by the drive switch signal.

2. The weight removal device according to claim 1, characterized in that, The equalization tap data logic module includes a pre-tap data logic module. The pre-tap data logic module generates pre-tap data based on the data to be transmitted. The pre-tap data is inversely related to the main tap data and is one unit interval ahead of the main tap data.

3. The weight removal device according to claim 2, characterized in that, The drive switch logic module includes a pre-tap drive switch logic module, which performs logical operations on the main tap data and the pre-tap data to generate a pre-tap drive switch signal.

4. The weight removal device according to claim 3, characterized in that, The equalization drive stage includes a pre-tap drive stage, which is electrically connected to the output of the pre-tap data logic module and the output of the pre-tap drive switch logic module. It is driven by the pre-tap data and controlled to be enabled or disabled by the pre-tap drive switch signal.

5. The weight removal device according to claim 4, characterized in that, If the pre-tap data and the main tap data are the same, the pre-tap drive switch logic module outputs a valid pre-tap drive switch signal, and the pre-tap drive stage is enabled and driven by the pre-tap data output by the pre-tap data logic module.

6. The weight removal device according to claim 1, characterized in that, The equalization tap data logic module includes a post-tap data logic module, which generates post-tap data based on the data to be transmitted. The post-tap data is inversely related to the main tap data and is delayed by one unit interval compared to the main tap data.

7. The weight removal device according to claim 6, characterized in that, The drive switch logic module includes a back tap drive switch logic module, which performs logical operations on the main tap data and the back tap data to generate a back tap drive switch signal.

8. The weight removal device according to claim 7, characterized in that, The equalization drive stage includes a back-tap drive stage, which is electrically connected to the output of the back-tap data logic module and the output of the back-tap drive switch logic module. It is driven by the back-tap data and controlled to be enabled or disabled by the back-tap drive switch signal.

9. The weight removal device according to claim 8, characterized in that, If the back tap data and the main tap data are the same, the back tap drive switch logic module outputs a valid back tap drive switch signal, and the back tap drive stage is enabled and driven by the back tap data output by the back tap data logic module.

10. The weight removal device according to claim 1, characterized in that, The main tap data logic module includes a first trigger, the input terminal of which receives the data to be transmitted, and the output terminal of the first trigger outputs the main tap data; The main tap drive stage includes a first source series termination driver, which is connected in series between the power supply and the ground terminal, and the control terminal of the control tube in the first source series termination driver is controlled by the main tap data.

11. A weight removal device according to claim 10, characterized in that, The equalization tap data logic module includes a pre-tap data logic module, which includes a first inverter. The input terminal of the first inverter receives the data to be transmitted, and the output terminal of the first inverter outputs the pre-tap data.

12. The weight removal device according to claim 11, characterized in that, The drive switch logic module includes a pre-tap drive switch logic module, which includes: A first XOR gate, the input of which is electrically connected to the output of the pre-tap data logic module and the output of the main tap data logic module, and the output of which outputs a first pre-tap drive switch signal; and The third inverter has its input terminal electrically connected to the output terminal of the first XOR gate, and its output terminal outputs a second pre-tap drive switch signal.

13. The weight removal device according to claim 12, characterized in that, The equalization drive stage includes a pre-tap drive stage, which includes a first control switch, a second source series terminal driver, and a second control switch connected in series. The first control switch, the second source series terminal driver, and the second control switch are connected in series between the power supply and the ground terminal. The control terminal of the control transistor in the second source series terminal driver is controlled by the main tap data. The first control switch is controlled by the first pre-tap drive switch signal, and the second control switch is controlled by the second pre-tap drive switch signal.

14. The weight removal device according to claim 10, characterized in that, The balanced tap data logic module includes a back tap data logic module, which includes a second flip-flop and a second inverter. The input of the second flip-flop is electrically connected to the output of the first flip-flop, and the input of the second inverter is electrically connected to the output of the second flip-flop. The output of the second inverter outputs the back tap data.

15. A weight removal device according to claim 14, characterized in that, The drive switch logic module includes a back-tap drive switch logic module, which includes: A second XOR gate, the input of which is electrically connected to the output of the back-tap data logic module and the output of the main-tap data logic module, and the output of which outputs a first back-tap drive switch signal; and The fourth inverter has its input terminal electrically connected to the output terminal of the second XOR gate, and its output terminal outputs a second back-tap drive switch signal.

16. A weight removal device according to claim 15, characterized in that, The equalization drive stage includes a back-tap drive stage, which includes a third control switch, a third source series terminal driver, and a fourth control switch connected in series. The third control switch, the third source series terminal driver, and the fourth control switch are connected in series between the power supply and the ground terminal. The control terminal of the control transistor in the third source series terminal driver is controlled by the main tap data. The third control switch is controlled by the first back-tap drive switch signal, and the fourth control switch is controlled by the second back-tap drive switch signal.

17. A method for removing emphasis, characterized in that, Includes the following steps: The master tap data is generated using the master tap data logic module; Balanced tap data is generated using a balanced tap data logic module. The balanced tap data is the inverse of the main tap data, and there is a unit interval between the balanced tap data and the main tap data. A drive switch signal is generated using a drive switch logic module. The drive switch signal is valid when the tap data and the equalization tap data are the same, and invalid when the tap data and the equalization tap data are opposite. The master tap data is used to enable the master tap driver stage; as well as The equalization driver stage is driven using the equalization tap data, and the equalization driver stage is enabled or disabled using the drive switch signal.

18. A chip-integrated system, characterized in that, It includes multiple cores, and the deweighting device as described in any one of claims 1 to 16 is disposed in the transmitter of the cores.

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