Double-Bank attribute adjustment method and system, terminal and readable storage medium

Abstract

The invention is suitable for the field of chips, and provides a double-Bank attribute adjustment method and system, a terminal and a readable storage medium, and the method comprises the steps: determining a target address of a target Bank and an associated reference address based on attribute adjustment information; checking whether address conflict exists between the target address and the reference address or not; and under the condition that the address conflict does not exist, based on the attribute adjustment information, adjusting a target Bank space length address of the target Bank to the target address, or adjusting a target space operation authority corresponding to the target address. According to the scheme, a safe and efficient double-Bank attribute adjusting method is provided, and the technical problem that an attribute adjusting scheme is lacked in the double-Bank using process is solved.

Description

Technical Field

[0001] The present application relates to the field of chips, and in particular to a dual-Bank attribute adjustment method, system, terminal and readable storage medium. Background Art

[0002] A dual-core chip refers to a chip that is packaged with two central processing unit (CPU) cores. In order to support the efficient operation of dual-core chips, an embedded flash memory (Embedded Flash) is usually integrated inside the chip. The Flash is an important component of the chip and is responsible for storing programs and data. In order to ensure the independence and security of data processing between the two CPU cores in the dual-core architecture, the Flash is partitioned to ensure that each CPU core has an exclusive storage space, namely a storage body (Bank). That is, the Flash has a first bank corresponding to the first CPU core and a second bank corresponding to the second CPU core, which is called a dual bank.

[0003] The space length addresses of the dual banks and the space operation permissions of each address segment within the space length addresses are pre-defined in the chip design stage, and once configured, they are usually fixed. In the subsequent use process, there is a lack of dual bank attribute adjustment solutions. Summary of the invention

[0004] The embodiments of the present application provide a dual-bank attribute adjustment method, system, terminal and readable storage medium to solve the problem of lack of dual-bank attribute adjustment scheme in the process of using dual banks in the prior art.

[0005] A first aspect of an embodiment of the present application provides a dual-bank attribute adjustment method, including:

[0006] Based on the attribute adjustment information, determine the target address and the associated reference address of the target Bank; the target Bank is the first Bank corresponding to the first CPU core or the second Bank corresponding to the second CPU core in the dual-core chip, and the first Bank and the second Bank both correspond to a Bank space length address and space operation permissions corresponding to each address segment in the Bank space length address; the target address is the expected Bank space length address given by the attribute adjustment information, or the target address is one or more address segments corresponding to the target space operation permissions given by the attribute adjustment information; the reference address is the space length address of the first Bank and / or the second Bank used for address verification with the target address;

[0007] Checking whether there is an address conflict between the target address and the reference address;

[0008] In the absence of the address conflict, based on the attribute adjustment information, the target Bank space length address of the target Bank is adjusted to the target address, or the target space operation authority corresponding to the target address is adjusted.

[0009] A second aspect of an embodiment of the present application provides a dual-bank attribute adjustment system, including:

[0010] A determination module, used for determining a target address and an associated reference address of a target Bank based on attribute adjustment information; the target Bank is a first Bank corresponding to a first CPU core or a second Bank corresponding to a second CPU core in a dual-core chip, and both the first Bank and the second Bank correspond to a Bank space length address and space operation permissions corresponding to each address segment in the Bank space length address; the target address is an expected Bank space length address given by the attribute adjustment information, or the target address is one or more address segments corresponding to the target space operation permissions given by the attribute adjustment information; the reference address is a space length address of the first Bank and / or the second Bank used for address verification with the target address;

[0011] A checking module, used for checking whether there is an address conflict between the target address and the reference address;

[0012] An adjustment module is used to adjust the target Bank space length address of the target Bank to the target address based on the attribute adjustment information when there is no address conflict, or to adjust the target space operation authority corresponding to the target address.

[0013] A third aspect of an embodiment of the present application provides a terminal, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the method described in the first aspect when executing the computer program.

[0014] A fourth aspect of an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the method described in the first aspect are implemented.

[0015] A fifth aspect of the present application provides a computer program product, which, when executed on a terminal, enables the terminal to execute the steps of the method described in the first aspect.

[0016] As can be seen from the above, when dealing with the dual-Bank attribute adjustment problem, the present application first determines the target Bank and the target address and the associated reference address of the target Bank based on the attribute adjustment information. Among them, the target Bank is the first Bank corresponding to the first CPU core or the second Bank corresponding to the second CPU core in the dual-core chip, and both the first Bank and the second Bank correspond to the Bank space length address and the space operation rights corresponding to each address segment in the Bank space length address; the target address is the expected Bank space length address given by the attribute adjustment information, or the target address is one or more address segments corresponding to the target space operation rights given by the attribute adjustment information; the reference address is the space length address of the first Bank and / or the second Bank used for address verification with the target address. Subsequently, by address comparison, it is checked whether there is an address conflict between the target address and the reference address, and the address conflict is discovered in time, thereby preventing data loss and other problems caused by address conflicts, and ensuring the stability and security of the Bank space. After confirming that there is no address conflict, attribute adjustment is performed based on the attribute adjustment information. If the attribute adjustment information indicates that the Bank space length address of the target Bank is adjusted, the target Bank space length address of the target Bank is adjusted to the target address. If the attribute adjustment information indicates that the space operation permission of the target bank is to be adjusted, the target space operation permission corresponding to the target address is adjusted. This series of steps provides a complete, safe and efficient dual-bank attribute adjustment method, which effectively solves the problem of lack of attribute adjustment scheme in the process of using dual banks and provides strong support for the flexible use and management of dual banks. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1 is a flow chart of a dual-Bank attribute adjustment method provided in an embodiment of the present application;

[0019] Figure 2 This is a schematic diagram of a Flash storage space under dual banks provided in an embodiment of the present application;

[0020] Figure 3 This is a schematic diagram of the interaction between the CPU core and the Flash storage space under a dual-Bank provided by an embodiment of the present application;

[0021] Figure 4is a schematic diagram of a circuit interaction for executing a read command provided in an embodiment of the present application;

[0022] Figure 5 is a read command execution flow chart provided by an embodiment of the present application;

[0023] Figure 6 It is a circuit interaction diagram for executing erase / program commands provided in an embodiment of the present application;

[0024] Figure 7 is an erase / program command execution flow chart provided in an embodiment of the present application;

[0025] Figure 8 It is a structural diagram of a dual-Bank attribute adjustment system provided in an embodiment of the present application;

[0026] Fig. 9 It is a structural diagram of a terminal provided in an embodiment of the present application. DETAILED DESCRIPTION

[0027] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0028] It should be understood that when used in this specification and the appended claims, the term "comprising" indicates the presence of described features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0029] It should also be understood that the terms used in this application specification are only for the purpose of describing specific embodiments and are not intended to limit the application. As used in this application specification and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms.

[0030] It should be further understood that the term “and / or” used in the specification and appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0031] As used in this specification and the appended claims, the term "if" may be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined" or "if [described condition or event] is detected" may be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]," depending on the context.

[0032] In a specific implementation, the terminal described in the embodiments of the present application includes, but is not limited to, other portable devices such as mobile phones, laptop computers, or tablet computers with touch-sensitive surfaces (e.g., touch screen displays and / or touch pads). It should also be understood that in some embodiments, the device is not a portable communication device, but a desktop computer with a touch-sensitive surface (e.g., touch screen displays and / or touch pads).

[0033] In the following discussion, a terminal including a display and a touch-sensitive surface is described. However, it should be understood that the terminal may include one or more other physical user interface devices such as a physical keyboard, mouse and / or joystick.

[0034] The terminal supports various applications, such as one or more of the following: a drawing application, a presentation application, a word processing application, a website creation application, a disk burning application, a spreadsheet application, a game application, a telephone application, a video conferencing application, an email application, an instant messaging application, a workout support application, a photo management application, a digital camera application, a digital camcorder application, a web browsing application, a digital music player application, and / or a digital video player application.

[0035] Various applications that can be executed on the terminal can use at least one common physical user interface device such as a touch-sensitive surface. One or more functions of the touch-sensitive surface and corresponding information displayed on the terminal can be adjusted and / or changed between applications and / or within corresponding applications. In this way, the common physical architecture of the terminal (e.g., the touch-sensitive surface) can support various applications with user interfaces that are intuitive and transparent to the user.

[0036] It should be understood that the size of the serial numbers of the steps in this embodiment does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present application.

[0037] In order to illustrate the technical solution described in this application, a specific embodiment is provided below for illustration.

[0038] See also Figure 1 , Figure 1 1 is a flow chart of a dual-Bank attribute adjustment method provided in an embodiment of the present application. Figure 1 As shown, a dual-Bank attribute adjustment method comprises the following steps:

[0039] Step 101, based on the attribute adjustment information, determine the target address and the associated reference address of the target Bank; the target Bank is the first Bank corresponding to the first CPU core or the second Bank corresponding to the second CPU core in the dual-core chip, and the first Bank and the second Bank both correspond to a Bank space length address and space operation permissions corresponding to each address segment in the Bank space length address; the target address is the expected Bank space length address given by the attribute adjustment information, or the target address is one or more address segments corresponding to the target space operation permissions given by the attribute adjustment information; the reference address is the space length address of the first Bank and / or the second Bank used for address verification with the target address.

[0040] Dual-core chips, such as dual-core electric meter chips, have two CPU cores, namely the first CPU core and the second CPU core. The first CPU core corresponds to the first bank, and the second CPU core corresponds to the second bank. The first bank corresponds to the first bank space length address and the space operation permissions of each address segment within the first bank space length address. The second bank corresponds to the second bank space length address and the space operation permissions of each address segment within the second bank space length address.

[0041] The first bank space length address refers to the space address and space size of the first bank in the Flash, and the second bank space length address refers to the space address and space size of the second bank.

[0042] In some embodiments, when the Bank attribute, which is a Bank space length address, is adjusted, the Bank space address changes, and the Bank space size increases, decreases, or remains unchanged.

[0043] In the present application, before the dual-core chip is officially put into operation, the first Bank space length address of the first Bank corresponding to the first CPU core and the space operation permissions of each address segment within the first Bank space length address, as well as the second Bank space length address of the second Bank corresponding to the second CPU core and the space operation permissions of each address segment within the second Bank space length address are pre-configured.

[0044] In some embodiments, these configured attribute information is stored in a register. Therefore, before determining the target address of the target Bank and the associated reference address based on the attribute adjustment information, it also includes: creating a register for storing the Bank space length addresses corresponding to the first Bank and the second Bank respectively and the space operation permissions corresponding to each address segment in the Bank space length address.

[0045] In some embodiments, a register is created in the Flash controller to store the first bank space length address of the first bank, the second bank space length address of the second bank, and the space operation permissions corresponding to each address segment in each bank space length address.

[0046] In some embodiments, two types of registers are created, one is a region management register for storing Bank space length addresses, and the other is a permission management register for storing space operation permission configuration information.

[0047] In some embodiments, the first CPU core is determined as a secure CPU core, and Flash responds to the region management register creation instruction of the secure CPU core, creates a region management register in the Flash controller, and stores the first Bank space length address and the second Bank space length address. In response to the permission management register creation instruction of the first CPU core, a first permission management register is created in the Flash controller, and the first permission management register is used to store the space operation permissions corresponding to each address segment within the first Bank space length address, that is, the first space operation permissions. In response to the permission management register creation instruction of the second CPU core, a second permission management register is created in the Flash controller, and the second permission management register is used to store the space operation permissions corresponding to each address segment within the second Bank space length address, that is, the second space operation permissions.

[0048] In some embodiments, according to the usage requirements of each CPU core, the Flash storage space of the Flash in the dual-core chip is pre-divided, and a Bank space is configured for each CPU core. The first Bank starting address CPU1_start_addr, the first Bank ending address CPU1_end_addr, the second Bank starting address CPU2_start_addr, and the second Bank ending address CPU2_end_addr of the first Bank are defined in the Flash storage space, and the first Bank corresponding to the first CPU core and the second Bank corresponding to the second CPU core are obtained. The first Bank is a Bank with continuous spatial addresses, and the second Bank is also a Bank with continuous spatial addresses. Among them, CPU1_start_addr-CPU1_end_addr is the first Bank space length address of the first Bank, and CPU2_start_addr-CPU2_end_addr is the second Bank space length address of the second Bank.

[0049] In some embodiments, the first Bank and the second Bank are banks with continuous addresses but non-overlapping spaces, or the first Bank and the second Bank are banks with non-continuous addresses and non-overlapping spaces.

[0050] In some implementations, the bank space is divided according to a set granularity, such as a set granularity of 8KB. The set granularity is a granularity obtained by considering customer needs and circuit costs. The space size of each bank is a positive integer multiple of the set granularity. The space division based on the set granularity can improve the refinement of chip management.

[0051] In some embodiments, the first bank space length address of the first bank and the second bank space length address of the second bank are stored in a region management register, and the region management register provides support for bank region management. When adjusting attributes and performing operations such as reading and writing, address comparison is implemented. When adjusting attributes, the space length address attribute can be adjusted by directly changing the defined attribute information stored in the register.

[0052] After determining the bank corresponding to each CPU core, configure the space operation permissions of each address segment in each bank. The space operation permissions include read permission (Read), write permission (Write), erase permission (Erase) and program permission (Program).

[0053] In some embodiments, the first space operation permission of each address segment within the first Bank space length address of the first Bank is stored in a first permission management register, and the second space operation permission of each address segment within the second Bank space length address of the second Bank is stored in a second permission management register. Independent permission management registers allow independent configuration and management of the address segments of each Bank, and store the space operation permissions of different Banks in independent permission management registers to implement partitioned permission management. When the dual-core chip is upgraded, expanded or modified, permission adjustments can be made more flexibly without affecting the normal operation of another Bank, effectively preventing potential permission leakage or cross-border access and improving security. At the same time, storing permission information in registers can speed up the permission checking process, reduce delays caused by permission checking, optimize access control logic, and improve the overall performance of the chip.

[0054] Through the bank space configuration and the permission configuration of each address segment in the bank space, scientific and efficient management of the Flash storage space and bank resources is achieved.

[0055] like Figure 2 As shown, Figure 2 FIG. 1 is a schematic diagram of a Flash storage space under a dual-Bank provided in an embodiment of the present application. Figure 2 It can be seen that the Flash storage space includes the first bank, the second bank and free space.

[0056] also, Figure 2 Also shown are the first Bank start address CPU1_start_addr and the first Bank end address CPU1_end_addr of the first Bank, the second Bank start address CPU2_start_addr and the second Bank end address CPU2_end_addr of the second Bank, as well as the space operation permissions of each address segment in the first Bank and the second Bank. Figure 2 CPU1_start_addr-CPU1_end_addr is the first bank space length address of the first bank, and CPU2_start_addr-CPU2_end_addr is the second bank space length address of the second bank. This diagram only shows the configuration of the erase permission and programming permission, where "erasable / programmable" means that the corresponding address segment can implement the erase operation and programming operation, that is, the erase permission and programming permission are configured, and "non-erasable / programmable" means that the corresponding address segment cannot implement the erase operation and programming operation, that is, the erase permission and programming permission are not configured.

[0057] in, Figure 2The first Bank start address CPU1_start_addr and the first Bank end address CPU1_end_addr of the first Bank, the second Bank start address CPU2_start_addr and the second Bank end address CPU2_end_addr of the second Bank, and the erase and programming permissions of each address segment in the first Bank and the second Bank are all stored in registers.

[0058] like Figure 3 As shown, Figure 3 This is a schematic diagram of the interaction between a CPU core and a Flash storage space under a dual-Bank provided by an embodiment of the present application. Each CPU core has its corresponding register and Bank space. Figure 3 In the first Bank, the first Bank start address CPU1_start_addr and the first Bank end address CPU1_end_addr, the second Bank start address CPU2_start_addr and the second Bank end address CPU2_end_addr of the second Bank are stored in the regional management register. The erase programming permission configuration information of each address segment in the first Bank is stored in the first permission management register. The erase programming permission configuration information of each address segment in the second Bank is stored in the second permission management register. The Flash controller performs attribute control on the first Bank and the second Bank in the Flash storage space through registers.

[0059] When adjusting the properties in the future, you can simply modify the relevant property configuration information in the register.

[0060] When executing commands such as read commands and erase / program commands, the attribute configuration information in the register is required. The following two example scenarios are introduced.

[0061] The first example scenario: read command scenario. In the following example scenario, the read permissions of each address segment of the Bank are the inherent configured permissions of each address segment of the Bank. In the process of responding to the read command, no read permission check is required.

[0062] like Figure 4 As shown, Figure 4 This is a circuit interaction diagram for executing a read command provided in an embodiment of the present application.

[0063] When the Flash controller receives a read command from the first CPU core or the second CPU core, it decomposes the read command to obtain a read command signal and an address signal, wherein the address signal contains an access address. Subsequently, the read command signal is transmitted to the address comparison unit and the command generation unit. The address comparison unit is stimulated by the read command signal, which is an enable signal, to start the address comparison function and compare the received address signal with the address transmitted by the regional management register. If the read command comes from the first CPU core, the object of comparison is the first Bank space length address in the information transmitted by the regional management register. If the read command comes from the second CPU core, the object of comparison is the second Bank space length address in the information transmitted by the regional management register. In addition, the address signal is also transmitted to the Flash signal control unit.

[0064] When the address signal is within the bank space length address of the bank corresponding to the source CPU core, the address signal is determined to be valid, and the address valid signal is transmitted to the command generation unit and the output data generation unit. At this time, the command generation unit determines that the read command signal is valid and transmits the read command valid signal to the Flash signal control unit.

[0065] At this time, the Flash signal control unit receives the address signal and the read command valid signal transmitted by the command generation unit, and controls the corresponding signal circuit through the Flash control signal to read the data corresponding to the access address from the Flash storage space, that is, to obtain the Flash output data, and transmit the Flash output data to the output data generation unit. Finally, the output data generation unit sends the Flash output data as output data to the corresponding source CPU core - the first CPU core or the second CPU core, that is, completes the read command.

[0066] When the address signal is not within the bank space length address of the bank corresponding to its source CPU core, it indicates that the address signal is invalid, and the command generation unit and the output data generation unit cannot receive the address valid signal. At this time, the command generation unit cannot generate and output the read command valid signal to the Flash signal control unit. The Flash signal control unit receives the address signal but does not receive the read command valid signal. The Flash signal control unit does not start and does not execute the read command operation. The output data generation unit generates false data, such as all-0 data, and sends it to the corresponding source CPU core as output data, which not only avoids erroneous operations but also ensures the integrity of the read command execution.

[0067] like Figure 5 As shown, Figure 5 This is a read command execution flow chart provided in an embodiment of the present application. Figure 5The execution process of the read command is clearly shown. The access address is the address indicated by the address signal, the specified area is the bank space length address of the bank corresponding to the source CPU that sends the read command - the first CPU core or the second CPU core, and the data corresponding to the address signal is the Flash output data.

[0068] The bank space length addresses corresponding to the first CPU core and the second CPU core are managed separately through the area management register, thus realizing the fine division and efficient management of the Flash storage space. This management method enables the CPU core to accurately and quickly access its corresponding storage area, thus improving the efficiency of data access.

[0069] The design of the address comparison unit and register effectively prevents illegal data reading or out-of-bounds data reading, enhancing the security and stability of the Bank.

[0070] Second example scenario: Erase / Program commands.

[0071] like Figure 6 As shown, Figure 6 It is a circuit interaction diagram for executing erase / program commands provided in an embodiment of the present application.

[0072] When the Flash controller receives the erase / program command from the first CPU core or the second CPU core, it decomposes the erase / program command to obtain the erase / program command signal and the address signal. Subsequently, the erase / program command signal is transmitted to the address comparison unit and the command generation unit. The address comparison unit is stimulated by the enable signal of the erase / program command signal to start the address comparison function and compare the received address signal with the address transmitted by the regional management register. Similarly, if the erase / program command comes from the first CPU core, the object of comparison is the first Bank space length address in the information transmitted by the regional management register. If the erase / program command comes from the second CPU core, the object of comparison is the second Bank space length address in the information transmitted by the regional management register. At the same time, the address signal is also transmitted to the Flash signal control unit. If the command is specifically a programming command, the decomposition of the programming command will also obtain a data signal, which is transmitted to the Flash signal control unit together with the address signal.

[0073] When the address signal is within the bank space length address of the bank corresponding to the source CPU core, the address signal is determined to be valid, and the address valid signal is transmitted to the permission checking unit. At this time, the permission checking unit receives the address signal and the address valid signal, and checks whether the access address indicated by the address signal is equipped with erase / programming permission based on the space operation permission configuration information transmitted by the permission management register corresponding to the source CPU. If equipped, the permission valid signal is transmitted to the command generation unit. In this case, the command generation unit determines that the erase / programming command signal is valid, and transmits the erase / programming command valid signal to the Flash signal control unit. The Flash signal control unit receives the address signal and the erase / programming command valid signal transmitted by the command generation unit, that is, the erase / programming command is valid. The Flash signal control unit controls the corresponding signal circuit through the Flash control signal to perform programming / erasing operations on the address segment of the access address corresponding to the address signal in the Flash storage space, that is, to erase the data in the address segment of the access address corresponding to the address signal in the Flash storage space, or to write the data signal to the address segment of the access address corresponding to the address signal in the Flash storage space through the programming operation.

[0074] When the address signal is not within the bank space length address of the bank corresponding to its source CPU core, the address signal is invalid, that is, the erase / program command is invalid, and the permission check unit, command generation unit and Flash signal control unit will not be enabled.

[0075] When the address segment of the access address corresponding to the address signal does not have the erase / program permission, the erase / program permission signal is invalid, that is, the erase / program command is invalid, and the command generation unit and the Flash signal control unit will not be enabled.

[0076] like Figure 7 As shown, Figure 7 This is an erase / program command execution flow chart provided in an embodiment of the present application. Figure 7 The execution process of the erase / program command is shown. The access address is the address indicated by the address signal, and the specified area is the bank space length address of the bank corresponding to the source CPU that sends the erase / program command, the first CPU core or the second CPU core.

[0077] Through strict address verification and permission checking mechanisms, problems such as operation failure or system crash caused by address errors or insufficient permissions are effectively avoided, improving the reliability and stability of chip operation.

[0078] This application can adjust the Bank attributes during the use of the first Bank and the second Bank.

[0079] When attribute adjustment information is received, the target Bank to be adjusted is determined based on the source of the attribute adjustment information, the target address corresponding to the attribute to be adjusted of the target Bank is determined from the attribute adjustment information, and the reference address required for verification is determined according to the attribute to be adjusted of the target Bank.

[0080] Different attributes to be adjusted correspond to different types of target addresses. If the current attribute to be adjusted is a space length address, the target address is the expected Bank space length address given by the attribute adjustment information. If the current attribute to be adjusted is a space operation permission, the target address is one or more address segments corresponding to the target space operation permission given by the attribute adjustment information.

[0081] Different attributes to be adjusted correspond to different reference addresses. If the attribute to be adjusted is the space length address, the reference address is the used space length address of the target Bank and the Bank space length address of another Bank. If the attribute to be adjusted is the space operation permission, the reference address is the Bank space length address of the target Bank. Among them, the address segment corresponding to the used space length address stores data information.

[0082] In some embodiments, the target Bank is the first Bank, and the target address and the associated reference address of the target Bank are determined based on the attribute adjustment information, including: if the attribute adjustment information indicates an adjustment to the first Bank space length address of the first Bank, then extracting the expected Bank space length address from the attribute adjustment information, and obtaining the used first space length address of the first Bank and the second Bank space length address of the second Bank as the reference address.

[0083] In some embodiments, the target Bank is the second Bank, and the target address and the associated reference address of the target Bank are determined based on the attribute adjustment information, including: if the attribute adjustment information indicates to adjust the second Bank space length address of the second Bank, then extracting the expected Bank space length address from the attribute adjustment information, and obtaining the used second space length address of the second Bank and the first Bank space length address of the first Bank as the reference address.

[0084] In some embodiments, the target Bank is the first Bank, and the target address and the associated reference address of the target Bank are determined based on the attribute adjustment information, including: if the attribute adjustment information indicates an adjustment to the first space operation authority of the first Bank, then extracting the one or more address segments from the attribute adjustment information, and determining the first Bank space length address of the first Bank as the reference address.

[0085] In some embodiments, the target Bank is the second Bank, and the target address and the associated reference address of the target Bank are determined based on the attribute adjustment information, including: if the attribute adjustment information indicates an adjustment to the second space operation authority of the second Bank, then extracting the one or more address segments from the attribute adjustment information, and determining the second Bank space length address of the second Bank as the reference address.

[0086] In some embodiments, the attribute adjustment information may include two different attributes to be adjusted at the same time. The adjustment priority of the target Bank space length address of the target Bank is higher than the adjustment priority of the target space operation authority. The target address and the associated reference address of the target Bank are determined based on the attribute adjustment information, including: when the attribute adjustment information is received for the first time, if the attribute adjustment information indicates to adjust the target Bank space length address of the target Bank, and adjust the target space operation authority of the target Bank, then determine the expected Bank space length address in the attribute adjustment information as the first target address, and determine the used space length address of the target Bank and the Bank space length address of another Bank as the first reference address; when the target Bank space length address of the target Bank is adjusted to the first target address, determine the one or more address segments corresponding to the target space operation authority in the attribute adjustment information as the second target address, and determine the first target address as the second reference address; or, when there is an address conflict between the first target address and the first reference address, determine the one or more address segments corresponding to the target space operation authority in the attribute adjustment information as the second target address, and determine the target Bank space length address of the target Bank as the second reference address.

[0087] When the target Bank is the first Bank, the other Bank is the second Bank; when the target Bank is the second Bank, the other Bank is the first Bank.

[0088] After receiving the attribute adjustment information for the first time, when it is detected that the attribute adjustment information requires adjustment of the Bank space length address of the target Bank and the space operation permissions of certain address segments, it is necessary to follow the principle that the adjustment priority of the target Bank space length address of the target Bank is higher than the adjustment priority of the target space operation permissions. At this time, the adjustment confirmation of the attribute of the target Bank space length address is first performed, that is, the target address and reference address under this attribute are determined, and the first target address, that is, the expected Bank space length address and the first reference address are obtained, and step 102 is executed. If there is no address conflict, step 103 is executed. If there is an address conflict, no adjustment is made.

[0089] When the target Bank space length address of the target Bank is adjusted to the first target address, or when there is an address conflict between the first target address and the first reference address, the adjustment confirmation of the attribute of the space operation authority of the target Bank is performed, that is, the target address and reference address under the attribute of the space operation authority are determined, and for the convenience of distinction, they are referred to as the second target address and the second reference address. Among them, the second target address is the one or more address segments, and the second reference address is the current Bank space length address of the target Bank.

[0090] In the case where there is an address conflict between the first target address and the first reference address, the space length address of the target Bank has not changed. In this case, the current Bank space length address of the target Bank is still the target Bank space length address, that is, the second reference address is the target Bank space length address. In the case where the target Bank space length address of the target Bank is adjusted to the first target address, the Bank space length address of the target Bank changes from the original target Bank space length address to the expected Bank space length address. In this case, the current Bank space length address of the target Bank is the expected Bank space length address, that is, the second reference address is the expected Bank space length address.

[0091] When the attribute adjustment information includes adjusting both attributes of the target Bank, the Bank space length address is adjusted and confirmed first to provide the correct reference address for the subsequent adjustment and confirmation process of the space operation authority, and then the adjustment and confirmation of the space operation authority are carried out in a timely manner to ensure data security and improve chip operation efficiency. Through a clear operation sequence and a timely confirmation mechanism, operation confusion or data errors caused by improper attribute adjustment sequence are avoided, and the stability and reliability of attribute adjustment are enhanced.

[0092] Step 102: Check whether there is an address conflict between the target address and the reference address.

[0093] After obtaining the target address and the reference address, an address comparison is performed to check whether there is an address conflict, that is, to check whether the attribute adjustment operation is compliant.

[0094] Before adjusting the bank space length address attribute, check whether the adjustment operation will cause data loss in the original bank space of the target bank, and whether it will occupy the bank space of another bank. The attribute adjustment operation can be performed only when data is not lost and space is not occupied.

[0095] In some embodiments, the target Bank is the first Bank, and the attribute to be adjusted is the Bank space length address of the target Bank, and the checking whether there is an address conflict between the target address and the reference address includes: checking whether the expected Bank space length address includes the used first space length address of the first Bank, and checking whether the expected Bank space length address is located within the second Bank space length address of the second Bank; if the expected Bank space length address includes the used first space length address of the first Bank, and the expected Bank space length address is not located within the second Bank space length address of the second Bank, it is determined that there is no address conflict, and the attribute adjustment operation can be performed. Otherwise, it is not performed.

[0096] In some embodiments, the target Bank is the second Bank, and the attribute to be adjusted is the Bank space length address of the target Bank, and the checking whether there is an address conflict between the target address and the reference address includes: checking whether the expected Bank space length address includes the used second space length address of the second Bank, and checking whether the expected Bank space length address is located within the first Bank space length address of the first Bank; if the expected Bank space length address includes the used second space length address of the second Bank, and the expected Bank space length address is not located within the first Bank space length address of the first Bank, it is determined that there is no address conflict, and the attribute adjustment operation can be performed. Otherwise, it is not performed.

[0097] The address segments involved in the configuration and adjustment of the bank's space operation permissions cannot exceed the address range limited by the bank's bank space length address. Before adjusting the space operation permissions attribute, check whether the address segment to be adjusted is within the bank space length address of the target bank.

[0098] In some embodiments, the target Bank is the first Bank, the attribute to be adjusted is the space operation permission of the target Bank, and the checking whether there is an address conflict between the target address and the reference address includes: checking whether the one or more address segments are located within the first Bank space length address of the first Bank; if so, it is determined that there is no address conflict, and the attribute adjustment operation can be performed. Otherwise, it is not performed.

[0099] In some embodiments, the target Bank is the second Bank, and the attribute to be adjusted is the spatial operation permission of the target Bank, and the checking whether there is an address conflict between the target address and the reference address includes: checking whether the one or more address segments are located within the second Bank space length address of the second Bank; if so, it is determined that there is no address conflict, and the attribute adjustment operation can be performed. Otherwise, it is not performed.

[0100] Step 103, in the absence of the address conflict, based on the attribute adjustment information, the target Bank space length address of the target Bank is adjusted to the target address, or the target space operation authority corresponding to the target address is adjusted.

[0101] In the absence of address conflicts, the corresponding properties of the target Bank can be adjusted, thus achieving dynamic adjustment of the Bank space length address and the Bank space operation permissions.

[0102] If the instruction is to adjust the bank space length address of the target bank, and there is no conflict between the target address and the reference address, the bank space length address is adjusted. For example, if the target bank space length address of the target bank is address1-addres332 and the expected bank space length address is address64-address490, the bank space length address of the target bank is adjusted from address1-addres332 to address64-address490.

[0103] If the instruction is to adjust the space operation permission of the target Bank, and there is no conflict between the target address and the reference address, the space operation permission of the corresponding address segment is adjusted. The adjustment of space operation permission is permission enabling or permission disabling. For example, "0" means permission disabling, and "1" means permission enabling. The target address is address segment A and address segment B. The erase / programming permission of address segment A and address segment B is changed to disabled. Then the erase and programming permission of address segment A and address segment B is changed from the original "1" to "0". In actual applications, when the permissions of certain address segments are turned off, that is, changed to non-erasable programming, the data in these address segments in the Flash will not be able to be erased or programmed, that is, the data stored in these address segments cannot be changed, which ensures data security.

[0104] In some embodiments, the configuration information of the Bank space length address and the space operation permissions is stored in a register, and in the absence of the address conflict, based on the attribute adjustment information, the target Bank space length address of the target Bank is adjusted to the target address, or the target space operation permissions corresponding to the target address are adjusted, including: in the absence of the address conflict, the target Bank space length address of the target Bank in the register is changed to the expected Bank space length address, or the target space operation permissions corresponding to the one or more address segments of the target Bank in the register are modified.

[0105] Adjusting the dual-bank attribute configuration information in the register makes it easier to adjust the attribute. After the dual-bank attribute adjustment, the register transmits the updated attribute configuration information to the address comparison unit to perform more accurate or efficient memory access control according to the new configuration, thereby improving the flexibility and responsiveness of chip applications.

[0106] The present application provides a dual-Bank attribute adjustment method, which can also adjust the attributes of the dual-Bank during the use of the dual-core chip, greatly improving the flexibility and security of the dual-core chip application.

[0107] In the embodiment of the present application, when dealing with the dual-Bank attribute adjustment problem, firstly, based on the attribute adjustment information, the target Bank and the target address and the associated reference address of the target Bank are determined. Among them, the target Bank is the first Bank corresponding to the first CPU core or the second Bank corresponding to the second CPU core in the dual-core chip, and both the first Bank and the second Bank correspond to the Bank space length address and the space operation authority corresponding to each address segment in the Bank space length address; the target address is the expected Bank space length address given by the attribute adjustment information, or the target address is one or more address segments corresponding to the target space operation authority given by the attribute adjustment information; the reference address is the space length address of the first Bank and / or the second Bank used for address verification with the target address. Subsequently, by address comparison, it is checked whether there is an address conflict between the target address and the reference address, and the address conflict is discovered in time, so as to prevent data loss and other problems caused by address conflicts, and ensure the stability and security of the Bank space. After confirming that there is no address conflict, the attribute adjustment is performed based on the attribute adjustment information. If the attribute adjustment information indicates that the Bank space length address of the target Bank is adjusted, the target Bank space length address of the target Bank is adjusted to the target address. If the attribute adjustment information indicates that the space operation permission of the target bank is to be adjusted, the target space operation permission corresponding to the target address is adjusted. This series of steps provides a complete, safe and efficient dual-bank attribute adjustment method, which effectively solves the problem of lack of attribute adjustment scheme in the process of using dual banks and provides strong support for the flexible use and management of dual banks.

[0108] See also Figure 8 , Figure 8 This is a structural diagram of a dual-Bank attribute adjustment system provided in an embodiment of the present application. For ease of explanation, only the parts related to the embodiment of the present application are shown.

[0109] The dual-bank attribute adjustment system 800 includes: a determination module 801 , a verification module 802 , and an adjustment module 803 .

[0110] Determination module 801 is used to determine the target address and the associated reference address of the target Bank based on the attribute adjustment information; the target Bank is the first Bank corresponding to the first CPU core or the second Bank corresponding to the second CPU core in the dual-core chip, and the first Bank and the second Bank both correspond to a Bank space length address and space operation permissions corresponding to each address segment in the Bank space length address; the target address is the expected Bank space length address given by the attribute adjustment information, or the target address is one or more address segments corresponding to the target space operation permissions given by the attribute adjustment information; the reference address is the space length address of the first Bank and / or the second Bank used for address verification with the target address.

[0111] The checking module 802 is used to check whether there is an address conflict between the target address and the reference address.

[0112] The adjustment module 803 is used to adjust the target Bank space length address of the target Bank to the target address based on the attribute adjustment information when there is no address conflict, or to adjust the target space operation authority corresponding to the target address.

[0113] In some embodiments, the target Bank is the first Bank, and the determination module is specifically configured to:

[0114] If the attribute adjustment information indicates to adjust the first Bank space length address of the first Bank, the expected Bank space length address is extracted from the attribute adjustment information, and the used first space length address of the first Bank and the second Bank space length address of the second Bank are obtained as the reference address.

[0115] In some embodiments, the inspection module is specifically used to:

[0116] Verify whether the expected Bank space length address includes the used first space length address of the first Bank, and verify whether the expected Bank space length address is within the second Bank space length address of the second Bank;

[0117] If the expected Bank space length address includes the used first space length address of the first Bank, and the expected Bank space length address is not located within the second Bank space length address of the second Bank, it is determined that the address conflict does not exist.

[0118] In some embodiments, the target Bank is the first Bank, and the determination module is further configured to:

[0119] If the attribute adjustment information indicates that the first space operation permission of the first Bank is adjusted, the one or more address segments are extracted from the attribute adjustment information, and the first Bank space length address of the first Bank is determined as the reference address.

[0120] In some embodiments, the inspection module is further configured to:

[0121] Checking whether the one or more address segments are located within the first Bank space length address of the first Bank;

[0122] If so, it is determined that the address conflict does not exist.

[0123] In some embodiments, the adjustment priority of the target Bank space length address of the target Bank is higher than the adjustment priority of the target space operation permission, and the determination module is further used to:

[0124] In the case where the attribute adjustment information is received for the first time, if the attribute adjustment information indicates to adjust the target Bank space length address of the target Bank, and to adjust the target space operation authority of the target Bank, then determine the expected Bank space length address in the attribute adjustment information as the first target address, and determine the used space length address of the target Bank and the Bank space length address of another Bank as the first reference address;

[0125] When the target Bank space length address of the target Bank is adjusted to the first target address, the one or more address segments corresponding to the target space operation authority in the attribute adjustment information are determined to be the second target address, and the first target address is determined to be the second reference address; or, when there is an address conflict between the first target address and the first reference address, the one or more address segments corresponding to the target space operation authority in the attribute adjustment information are determined to be the second target address, and the target Bank space length address of the target Bank is determined to be the second reference address.

[0126] In some embodiments, the dual-Bank attribute adjustment system further includes a creation module, wherein the creation module is used to:

[0127] Create a register for storing the bank space length addresses corresponding to the first bank and the second bank respectively and the space operation permissions corresponding to each address segment in the bank space length address;

[0128] In some embodiments, the adjustment module is specifically used to:

[0129] In the absence of the address conflict, the target Bank space length address of the target Bank in the register is changed to the expected Bank space length address, or the target space operation permissions corresponding to the one or more address segments of the target Bank in the register are modified.

[0130] The dual-bank attribute adjustment system provided in the embodiment of the present application can implement each process of the embodiment of the above-mentioned dual-bank attribute adjustment method, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0131] Fig. 9 is a structural diagram of a terminal provided in an embodiment of the present application. As shown in the figure, the terminal 9 of this embodiment includes: at least one processor 90 ( Fig. 9 Only one is shown in the figure), a memory 91, and a computer program 92 stored in the memory 91 and executable on the at least one processor 90, wherein the processor 90 implements the steps of any of the above-mentioned method embodiments when executing the computer program 92.

[0132] The terminal 9 may be a computing device such as a desktop computer, a notebook, a PDA, or a cloud server. The terminal 9 may include, but is not limited to, a processor 90 and a memory 91. Those skilled in the art will appreciate that Fig. 9 It is only an example of terminal 9 and does not constitute a limitation on terminal 9. It may include more or fewer components than shown in the figure, or a combination of certain components, or different components. For example, the terminal may also include input and output devices, network access devices, buses, etc.

[0133] The processor 90 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.

[0134] The memory 91 may be an internal storage unit of the terminal 9, such as a hard disk or memory of the terminal 9. The memory 91 may also be an external storage device of the terminal 9, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the terminal 9. Further, the memory 91 may also include both an internal storage unit of the terminal 9 and an external storage device. The memory 91 is used to store the computer program and other programs and data required by the terminal. The memory 91 may also be used to temporarily store data that has been output or is to be output.

[0135] The technicians in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated in a processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0136] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0137] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0138] In the embodiments provided in the present application, it should be understood that the disclosed devices / terminals and methods can be implemented in other ways. For example, the device / terminal embodiments described above are only schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0139] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0140] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0141] If the integrated module / unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the processes in the above-mentioned embodiment method, and can also be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, U disk, mobile hard disk, disk, optical disk, computer memory, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), electric carrier signal, telecommunication signal and software distribution medium. It should be noted that the content contained in the computer-readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electric carrier signals and telecommunication signals.

[0142] The present application implements all or part of the processes in the above-mentioned embodiment method, and may also be implemented through a computer program product. When the computer program product runs on a terminal, the terminal can implement the steps in the above-mentioned method embodiments when executing the computer program product.

[0143] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A dual-bank attribute adjustment method, characterized in that: The method comprises: Based on the attribute adjustment information, determine the target address and the associated reference address of the target Bank; the target Bank is the first Bank corresponding to the first CPU core or the second Bank corresponding to the second CPU core in the dual-core chip, and the first Bank and the second Bank both correspond to a Bank space length address and space operation permissions corresponding to each address segment in the Bank space length address; the target address is the expected Bank space length address given by the attribute adjustment information, or the target address is one or more address segments corresponding to the target space operation permissions given by the attribute adjustment information; the reference address is the space length address of the first Bank and / or the second Bank used for address verification with the target address; Checking whether there is an address conflict between the target address and the reference address; In the absence of the address conflict, based on the attribute adjustment information, the target Bank space length address of the target Bank is adjusted to the target address, or the target space operation authority corresponding to the target address is adjusted.

2. The method according to claim 1, characterized in that The target Bank is the first Bank, and determining a target address and an associated reference address of the target Bank based on the attribute adjustment information includes: If the attribute adjustment information indicates to adjust the first Bank space length address of the first Bank, the expected Bank space length address is extracted from the attribute adjustment information, and the used first space length address of the first Bank and the second Bank space length address of the second Bank are obtained as the reference address.

3. The method according to claim 2, characterized in that The checking whether there is an address conflict between the target address and the reference address includes: Verify whether the expected Bank space length address includes the used first space length address of the first Bank, and verify whether the expected Bank space length address is within the second Bank space length address of the second Bank; If the expected Bank space length address includes the used first space length address of the first Bank, and the expected Bank space length address is not located within the second Bank space length address of the second Bank, it is determined that the address conflict does not exist.

4. The method according to claim 1, characterized in that The target Bank is the first Bank, and determining a target address and an associated reference address of the target Bank based on the attribute adjustment information includes: If the attribute adjustment information indicates that the first space operation permission of the first Bank is adjusted, the one or more address segments are extracted from the attribute adjustment information, and the first Bank space length address of the first Bank is determined as the reference address.

5. The method according to claim 4, characterized in that The checking whether there is an address conflict between the target address and the reference address includes: Checking whether the one or more address segments are located within the first Bank space length address of the first Bank; If so, it is determined that the address conflict does not exist.

6. The method according to claim 1, characterized in that The adjustment priority of the target Bank space length address of the target Bank is higher than the adjustment priority of the target space operation authority, and the determination of the target address and the associated reference address of the target Bank based on the attribute adjustment information includes: In the case where the attribute adjustment information is received for the first time, if the attribute adjustment information indicates to adjust the target Bank space length address of the target Bank, and to adjust the target space operation authority of the target Bank, then determine the expected Bank space length address in the attribute adjustment information as the first target address, and determine the used space length address of the target Bank and the Bank space length address of another Bank as the first reference address; When the target Bank space length address of the target Bank is adjusted to the first target address, the one or more address segments corresponding to the target space operation authority in the attribute adjustment information are determined to be the second target address, and the first target address is determined to be the second reference address; or, when there is an address conflict between the first target address and the first reference address, the one or more address segments corresponding to the target space operation authority in the attribute adjustment information are determined to be the second target address, and the target Bank space length address of the target Bank is determined to be the second reference address.

7. The method according to claim 1, characterized in that Before determining the target address of the target Bank and the associated reference address based on the attribute adjustment information, the method further includes: Create a register for storing the bank space length addresses corresponding to the first bank and the second bank respectively and the space operation permissions corresponding to each address segment in the bank space length address; In the case where the address conflict does not exist, adjusting the target Bank space length address of the target Bank to the target address based on the attribute adjustment information, or adjusting the target space operation permission corresponding to the target address, includes: In the absence of the address conflict, the target Bank space length address of the target Bank in the register is changed to the expected Bank space length address, or the target space operation permissions corresponding to the one or more address segments of the target Bank in the register are modified.

8. A dual-bank attribute adjustment system, characterized in that: include: A determination module, used for determining a target address and an associated reference address of a target Bank based on the attribute adjustment information; The target Bank is the first Bank corresponding to the first CPU core or the second Bank corresponding to the second CPU core in the dual-core chip, and both the first Bank and the second Bank correspond to a Bank space length address and space operation permissions corresponding to each address segment in the Bank space length address; the target address is the expected Bank space length address given by the attribute adjustment information, or the target address is one or more address segments corresponding to the target space operation permissions given by the attribute adjustment information, and the reference address is the space length address of the first Bank and / or the second Bank used for address verification with the target address; A checking module, used for checking whether there is an address conflict between the target address and the reference address; An adjustment module is used to adjust the target Bank space length address of the target Bank to the target address based on the attribute adjustment information when there is no address conflict, or to adjust the target space operation authority corresponding to the target address.

9. A terminal comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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