SRAM in-memory multiplication operation circuit and module, SRAM and electronic device

Abstract

The present application relates to an in-memory multiplication circuit and module of an SRAM, an SRAM and an electronic device, wherein the in-memory multiplication circuit includes a storage part and a weighting part, the storage part includes eight storage units, each storage unit has an analog input terminal and an analog output terminal and is used to store a single-bit weight, each storage unit turns on the analog input terminal and the analog output terminal when the single-bit weight stored in itself is 1, and turns off the analog input terminal and the analog output terminal when the single-bit weight stored in itself is 0; the weighting part includes a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor and an eleventh capacitor. The number and total capacitance of the capacitors used are both less, which reduces the circuit area overhead and solves the problem of large area overhead of the in-memory multiplication circuit of the current charge domain-based SRAM.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and in particular to an in-memory multiplication operation circuit and module of an SRAM, an SRAM, and an electronic device. Background Art

[0002] In-memory computing technology overcomes the "memory wall" problem of the traditional von Neumann architecture. Its core advantage lies in the ability to perform computations directly within the memory. This innovation reduces the transmission bottleneck between storage and computing units, improves computing efficiency, and opens new development opportunities in fields such as artificial intelligence and visual recognition. With technological advancements, in-memory computing has rapidly developed in related applications, and the research community is increasingly demanding its performance.

[0003] For high-precision analog weighted in-memory multiplication calculations, the current in-memory multiplication circuit based on charge-domain SRAM (static random access memory) still needs to rely on a large number of capacitor combinations to implement, which greatly increases the circuit area overhead. Summary of the Invention

[0004] The present invention provides an SRAM in-memory multiplication circuit and module, an SRAM and an electronic device to solve the problem of large area overhead of the current charge domain-based SRAM in-memory multiplication circuit.

[0005] In a first aspect, the present invention provides an SRAM in-memory multiplication circuit, comprising:

[0006] a storage portion comprising eight storage cells, each of the storage cells having an analog input terminal and an analog output terminal and being used to store a single-bit weight, each of the storage cells switching on the analog input terminal and the analog output terminal when the single-bit weight stored therein is 1 and disconnecting the analog input terminal and the analog output terminal when the single-bit weight stored therein is 0, the analog input terminals of the eight storage cells being connected to the same analog input line;

[0007] a weighted portion, comprising a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, and an eleventh capacitor;

[0008] Among them, the analog output ends of the eight storage units are respectively connected to the first plates of the first capacitor to the eighth capacitor, the second plates of the first capacitor and the second capacitor are connected to the first plate of the ninth capacitor, the second plates of the third capacitor and the fourth capacitor are connected to the second plate of the ninth capacitor, the second plates of the fifth capacitor and the sixth capacitor are connected to the first plate of the tenth capacitor, the second plates of the seventh capacitor and the eighth capacitor are connected to the second plate of the tenth capacitor, the second plate of the ninth capacitor is also connected to the first plate of the eleventh capacitor, and the second plate of the tenth capacitor is also connected to the second plate of the eleventh capacitor and constitutes the output node of the in-memory multiplication circuit of the SRAM.

[0009] In a second aspect, the present invention provides an in-memory computing circuit, comprising:

[0010] A multiplication circuit, which is the in-memory multiplication circuit of the SRAM described in the first aspect;

[0011] The accumulation circuit is used to accumulate the weighted multiplication calculation results of the plurality of analog quantities respectively performed by the multiplication circuit.

[0012] In a third aspect, the present invention provides an SRAM in-memory multiplication operation module, which encapsulates the SRAM in-memory multiplication operation circuit described in the first aspect and has:

[0013] A first pin connected to the analog quantity input line, used for receiving the analog quantity to be calculated by weighted multiplication;

[0014] The second pin connected to the output node of the in-memory multiplication circuit of the SRAM is used to output the weighted multiplication calculation result of the analog quantity.

[0015] In a fourth aspect, the present invention provides a static random access memory (SRAM), which implements weighted in-memory multiplication calculation of analog quantities through the in-memory multiplication circuit of the SRAM described in the first aspect.

[0016] In a fifth aspect, the present invention provides an electronic device comprising a memory and a processor, wherein the memory is the static random access memory described in the fourth aspect.

[0017] Compared to related technologies, the SRAM in-memory multiplication circuit provided by the present invention can perform multiplication calculations of analog quantities and eight-bit weights. More importantly, the weighting portion of this circuit has a relatively simple structure, implemented using only 11 capacitors. Compared to existing in-memory multiplication circuits, the number and total capacitance of the capacitors used are both reduced, reducing circuit area overhead and resolving the large area overhead of current charge-domain SRAM in-memory multiplication circuits.

[0018] The details of one or more embodiments of the present application are set forth in the following drawings and description to make other features, objects, and advantages of the present application more readily apparent. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 Schematic diagram of an in-memory multiplication circuit of an SRAM provided in an embodiment of the present invention;

[0020] Figure 2 is a schematic diagram of a storage unit provided in one embodiment of the present invention;

[0021] Figure 3 Schematic diagram of an in-memory multiplication operation module of an SRAM provided in an embodiment of the present invention;

[0022] Figure 4 This is a simulation diagram of input and output signals of the in-memory multiplication circuit of the SRAM in the first example performing multiplication calculation of an analog signal and an eight-bit digital signal;

[0023] Figure 5 This is a simulation diagram of input and output signals of the in-memory multiplication circuit of the SRAM in the second example performing multiplication calculations of analog signals and eight-bit digital signals. DETAILED DESCRIPTION

[0024] In order to more clearly understand the purpose, technical solutions and advantages of the present application, the present application is described and illustrated below in conjunction with the accompanying drawings and embodiments.

[0025] Unless otherwise defined, technical or scientific terms used in this application shall have the ordinary meanings as understood by persons of ordinary skill in the art to which this application belongs. The terms "a," "an," "the," "these," and similar expressions in this application do not denote limitations on quantity and may be singular or plural. The terms "comprise," "include," "have," and any variations thereof, as used in this application, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or device comprising a series of steps or modules (units) is not limited to the listed steps or modules (units) but may include unlisted steps or modules (units) or other steps or modules (units) inherent to the process, method, product, or device. The terms "connected," "connected," "coupled," and similar expressions used in this application are not limited to physical or mechanical connections but may include electrical connections, whether direct or indirect. As used in this application, "plurality" means two or more. "And / or" describes an association between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can mean: A exists alone; A and B exist simultaneously; or B exists alone. Generally, the character " / " indicates that the objects in the preceding and following relationship are in an "or" relationship. The terms "first", "second", "third", etc. involved in this application are only used to distinguish similar objects and do not represent a specific ordering of the objects.

[0026] In an embodiment of the present invention, a multiplication circuit in an SRAM is provided. Figure 1 Schematic diagram of an in-memory multiplication circuit of an SRAM provided in an embodiment of the present invention.

[0027] like Figure 1 As shown, the in-memory multiplication circuit includes a storage part and a weighting part.

[0028] The storage part includes eight storage units, each storage unit has an analog input terminal and an analog output terminal and is used to store a single-bit weight. Each storage unit turns on the analog input terminal and the analog output terminal when the single-bit weight stored in the unit is 1, and turns off the analog input terminal and the analog output terminal when the single-bit weight stored in the unit is 0. The analog input terminals of the eight storage units are connected to the same analog input line VIN.

[0029] It should be noted that the storage unit may adopt a currently mature storage unit. Figure 2 Schematic diagram of a storage unit provided in one embodiment of the present invention. Figure 2Each storage unit may include a storage subunit and a transmission unit. The storage subunit has a first storage node Q and a second storage node QB. The transmission unit includes a first NMOS transistor N1, a second NMOS transistor N2, and a first PMOS transistor P1. The drain of the first NMOS transistor N1 and the source of the first PMOS transistor P1 are connected to form an analog input terminal. The source of the first NMOS transistor N1, the drain of the first PMOS transistor P1, and the drain of the second NMOS transistor N2 are connected to form an analog output terminal. The gate of the first NMOS transistor N1 is connected to the first storage node Q, the gate of the first PMOS transistor P1 is connected to the second storage node QB, the gate of the second NMOS transistor N2 is connected to the second storage node QB, and the source of the second NMOS transistor N2 is grounded to VSS. In the storage subunit, a high level at the first storage node Q and a low level at the second storage node QB indicate that the stored single-bit weight is 1. A low level at the first storage node Q and a high level at the second storage node QB indicate that the stored single-bit weight is 0.

[0030] In the above-mentioned transmission unit, the first NMOS transistor N1 and the first PMOS transistor P1 form a transmission gate, and the second NMOS transistor N2 serves as a switching device. When the single-bit weight stored in the storage subunit is 1, the first storage node Q is at a high level and the second storage node QB is at a low level. At this time, the transmission gate is turned on and the second NMOS transistor N2 is turned off. The potential of the analog output terminal and the analog input terminal is the same, that is, the analog signal VIN received by the analog input terminal is transmitted to the analog output terminal. At this time, the corresponding capacitor upper plate is charged to the analog potential VIN, realizing the single-bit multiplication operation of 1*VIN=VIN. When the single-bit weight stored in the storage subunit is 0, the first storage node Q is at a low level and the second storage node QB is at a high level. At this time, the transmission gate is turned off and the second NMOS transistor N2 is turned on. The analog output terminal is grounded and the corresponding potential is 0, that is, the analog signal VIN received by the analog input terminal is not transmitted to the analog output terminal. At this time, the corresponding upper plate of the capacitor cannot be charged and the potential is 0, thereby completing the single-bit multiplication operation of 0*VIN=0.

[0031] Among them, the storage subunit includes a third NMOS transistor N3, a fourth NMOS transistor N4, a first inverter I1 and a second inverter I2. The first inverter I1 and the second inverter I2 are cross-coupled to form a first storage node Q and a second storage node QB. The source and drain of the third NMOS transistor N3 are respectively connected to the first storage node Q and the first bit line BL, the source and drain of the fourth NMOS transistor N4 are respectively connected to the second storage node QB and the second bit line BLB, and the gates of the third NMOS transistor N3 and the fourth NMOS transistor N4 are both connected to the word line WL.

[0032] Since each inverter is composed of two devices, the memory cell used in this embodiment is a 9T-SRAM cell (9T-cell). Accordingly, in other embodiments, the memory cell can adopt other structures, as long as the memory cell turns on the analog input terminal and the analog output terminal when the single-bit weight stored in the memory cell is 1, and turns off the analog input terminal and the analog output terminal when the single-bit weight stored in the memory cell is 0.

[0033] The weighted portion includes a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9, a tenth capacitor C10, and an eleventh capacitor C11. The analog output terminals of the eight storage cells are respectively connected to the first plates of the first to eighth capacitors C1 to C8, the second plates of the first and second capacitors C1 and C2 are connected to the first plate of the ninth capacitor C9, the second plates of the third and fourth capacitors C3 and C4 are connected to the second plate of the ninth capacitor C9, the second plates of the fifth and sixth capacitors C5 and C6 are connected to the first plate of the tenth capacitor C10, the second plates of the seventh and eighth capacitors C7 and C8 are connected to the second plate of the tenth capacitor C10, the second plate of the ninth capacitor C9 is also connected to the first plate of the eleventh capacitor C11, and the second plate of the tenth capacitor C10 is also connected to the second plate of the eleventh capacitor C11, forming an output node VOUT of the in-memory multiplication circuit of the SRAM.

[0034] The single-bit weights stored in the eight storage units constitute an eight-bit weight in reverse order. For example, the eight storage units can be defined as the first storage unit to the eighth storage unit, with the first storage unit correspondingly connected to the first capacitor C1, the second storage unit correspondingly connected to the second capacitor C2, and so on, the eighth storage unit correspondingly connected to the eighth capacitor C8. The first storage unit to the eighth storage unit then store the eight-bit weights from the lowest weight to the highest weight in sequence.

[0035] The first capacitor C1, the third capacitor C3, the fifth capacitor C5, the seventh capacitor C7, the ninth capacitor C9, and the tenth capacitor C10 have the same capacitance. The second capacitor C2, the fourth capacitor C4, the sixth capacitor C6, and the eighth capacitor C8 have capacitances twice that of the first capacitor C1. The capacitance of the eleventh capacitor C11 is one-quarter that of the first capacitor C1. Assuming that the capacitance of the first capacitor C1, the third capacitor C3, the fifth capacitor C5, the seventh capacitor C7, the ninth capacitor C9, and the tenth capacitor C10 is C, the capacitance of the second capacitor C2, the fourth capacitor C4, the sixth capacitor C6, and the eighth capacitor C8 is 2C, and the capacitance of the eleventh capacitor C11 is 1 / 4C.

[0036] In the aforementioned in-memory multiplication circuit, all memory cells in the same row share the same word line WL. When the potential of the analog input line VIN is constantly 0 and the potential of the word line is 1, the in-memory multiplication circuit is in read / write mode, and data is read and written via the first bit line BL and the second bit line BLB. When the potential of the analog input line VIN is not constantly 0 and the potential of the word line WL is 0, the in-memory multiplication circuit is in calculation mode.

[0037] For the first capacitor C1 to the eighth capacitor C8 in the calculation mode, the relationship between the top plate potential of each capacitor and the output node potential of the in-memory multiplication circuit is described as follows.

[0038] When the upper plate potential of the eighth capacitor C8 is the analog value VIN and the upper plate potentials of the other capacitors are 0 (the single-bit weight stored in the storage unit corresponding to the eighth capacitor C8 is 1, and the single-bit weight stored in the other storage units is 0), according to the capacitor voltage division relationship, it can be obtained:

[0039]

[0040] The derivation process is as follows: When the top plate potential of the eighth capacitor C8 is the analog value VIN, the value of VOUT is equal to the voltage divider of the capacitance of C8 relative to the total capacitance at the output point VOUT. Therefore, in the numerator, 2C represents the capacitance of C8; in the denominator, 15C / 64 represents the equivalent capacitance of C1, C2, C3, C4, C9, and C11 at the output point VOUT, 3C / 4 represents the equivalent capacitance of C5, C6, and C10 at the output point VOUT, C represents the capacitance of C7, and 2C represents the capacitance of C8.

[0041] When the upper plate potential of the seventh capacitor C7 is the analog value VIN and the upper plate potentials of the other capacitors are 0 (the single-bit weight stored in the storage unit corresponding to the seventh capacitor C7 is 1, and the single-bit weight stored in the other storage units is 0), according to the capacitor voltage division relationship, it can be obtained:

[0042]

[0043] The derivation process is as follows: When the top plate potential of capacitor C7 is equal to the analog value VIN, the value of VOUT is equal to the voltage divider of C7's capacitance relative to the total capacitance at the VOUT output point. Therefore, in the numerator of the above formula, C represents the capacitance of C7; in the denominator, 15C / 64 represents the equivalent capacitance of C1, C2, C3, C4, C9, and C11 at the VOUT output point, 3C / 4 represents the equivalent capacitance of C5, C6, and C10 at the VOUT output point, C represents the capacitance of C7, and 2C represents the capacitance of C8.

[0044] When the upper plate potential of the sixth capacitor C6 is the analog value VIN and the upper plate potentials of the other capacitors are 0 (the single-bit weight stored in the storage unit corresponding to the sixth capacitor C6 is 1, and the single-bit weight stored in the other storage units is 0), according to the capacitor voltage division relationship, it can be obtained:

[0045]

[0046] The derivation process is: when the upper plate potential of the sixth capacitor C6 is the analog value VIN, first calculate the voltage value output by the lower plate of C6. For the first part:

[0047]

[0048] In the numerator of the above formula, 2C represents the capacitance value of C6; in the denominator, represents the equivalent capacitance of C1, C2, C3, C4, C7, C8, C9, C10, and C11 at the lower plate of C6, C represents the capacitance of C5, and 2C represents the capacitance of C6. Therefore, the first part represents the voltage output by the lower plate of C6 when the upper plate potential of the sixth capacitor C6 is the analog value VIN, that is, the input to the left plate of C10.

[0049] Then, this is equivalent to inputting to the left plate of C10:

[0050]

[0051] The value of VOUT is equal to the voltage divided by the capacitance of C10 relative to the total capacitance at the VOUT output point. So, for the second part In the numerator, C represents the capacitance value of C10; in the denominator, 15C / 64 represents the equivalent capacitance value of C1, C2, C3, C4, C9, and C11 at the VOUT output point, 2C represents the capacitance value of C8, and the two Cs represent the capacitance values ​​of C7 and C10 respectively.

[0052] When the top plate potential of the fifth capacitor C5 is the analog value VIN and the top plate potentials of the other capacitors are 0 (the single-bit weight stored in the storage unit corresponding to the fifth capacitor C5 is 1, and the single-bit weight stored in the other storage units is 0), according to the capacitor voltage division relationship, we can obtain:

[0053]

[0054] The derivation process is: when the potential of the upper plate of the fifth capacitor C5 is the analog value VIN, first calculate the voltage value output by the lower plate of C5. For the first part:

[0055]

[0056] In the numerator, C represents the capacitance value of C5; in the denominator, represents the equivalent capacitance of C1, C2, C3, C4, C7, C8, C9, C10, and C11 at the lower plate of C5, C represents the capacitance of C5, and 2C represents the capacitance of C6. Therefore, the first part represents the voltage output by the lower plate of capacitor C5 when the upper plate potential of the fifth capacitor C5 is the analog value VIN, that is, the input to the left plate of C10.

[0057] Then, this is equivalent to inputting to the left plate of C10:

[0058]

[0059] The value of VOUT is equal to the voltage divided by the capacitance of C10 relative to the total capacitance at the VOUT output point. So, for the second part In the numerator, C represents the capacitance value of C10; in the denominator, 15C / 64 represents the equivalent capacitance value of C1, C2, C3, C4, C9, and C11 at the VOUT output point, 2C represents the capacitance value of C8, and the two Cs represent the capacitance values ​​of C7 and C10 respectively.

[0060] When the upper plate potential of the fourth capacitor C4 is the analog value VIN and the upper plate potentials of the other capacitors are 0 (the single-bit weight stored in the storage unit corresponding to the fourth capacitor C4 is 1, and the single-bit weight stored in the other storage units is 0), according to the capacitor voltage division relationship, it can be obtained:

[0061]

[0062] The derivation process is: when the upper plate potential of the fourth capacitor C4 is the analog value VIN, first calculate the voltage value output by the lower plate of C4. In the numerator, 2C represents the capacitance value of C4; in the denominator, 15C / 64 represents the equivalent capacitance value of C5, C6, C7, C8, C10, and C11 at the lower plate point of C4, 3C / 4 represents the equivalent capacitance value of C1, C2, and C9 at the lower plate point of C4, C represents the capacitance value of C3, and 2C represents the capacitance value of C4. Therefore, Represents the voltage value output by the lower plate of C4 when the upper plate potential of the fourth capacitor C4 is the analog value VIN, that is, the voltage input to the left plate of C11 .

[0063] Then, this is equivalent to inputting the left plate of C11 , the value of VOUT is equal to the voltage divided by the capacitance of C11 relative to the total capacitance at the VOUT output point. So, for the second part In the numerator, C / 4 represents the capacitance value of C11; in the denominator, 15C / 4 represents the equivalent capacitance value of C5, C6, C7, C8, and C10 at the VOUT output point, and C / 4 represents the capacitance value of C11.

[0064] When the upper plate potential of the third capacitor C3 is the analog value VIN and the upper plate potentials of the other capacitors are 0 (the single-bit weight stored in the storage unit corresponding to the third capacitor C3 is 1, and the single-bit weight stored in the other storage units is 0), according to the capacitor voltage division relationship, it can be obtained:

[0065]

[0066] The derivation process is: when the upper plate potential of the third capacitor C3 is the analog value VIN, first calculate the voltage value output by the lower plate of C3. In the numerator, C represents the capacitance value of C3; in the denominator, 15C / 64 represents the equivalent capacitance value of C5, C6, C7, C8, C10, and C11 at the lower plate point of C3, 3C / 4 represents the equivalent capacitance value of C1, C2, and C9 at the lower plate point of C3, C represents the capacitance value of C3, and 2C represents the capacitance value of C4. Therefore, Represents the voltage value output by the lower plate of C3 when the upper plate potential of the third capacitor C3 is the analog value VIN, that is, the voltage input to the left plate of C11 .

[0067] Then, this is equivalent to inputting the left plate of C11 , the value of VOUT is equal to the voltage divided by the capacitance of C11 relative to the total capacitance at the VOUT output point. So, for the second part In the numerator, C / 4 represents the capacitance value of C11; in the denominator, 15C / 4 represents the equivalent capacitance value of C5, C6, C7, C8, and C10 at the VOUT output point, and C / 4 represents the capacitance value of C11.

[0068] When the upper plate potential of the second capacitor C2 is the analog value VIN and the upper plate potentials of the other capacitors are 0 (the single-bit weight stored in the storage unit corresponding to the second capacitor C2 is 1, and the single-bit weight stored in the other storage units is 0), according to the capacitor voltage division relationship, it can be obtained:

[0069]

[0070] The derivation process is: when the potential of the upper plate of the second capacitor C2 is the analog value VIN, first calculate the voltage value output by the lower plate of C2. For the first part:

[0071]

[0072] In the numerator, 2C represents the capacitance value of C2; in the denominator, represents the equivalent capacitance of C3, C4, C5, C6, C7, C8, C9, C10, and C11 at the lower plate of C2, C represents the capacitance of C1, and 2C represents the capacitance of C2. Therefore, the first part represents the voltage output by the lower plate of capacitor C2 when the upper plate potential of capacitor C2 is the analog value VIN, which is the input to the left plate of C9.

[0073] Then, this is equivalent to inputting to the left plate of C9:

[0074]

[0075] The output voltage of the right plate of C9 is equal to the voltage divided by the capacitance of C9 relative to the total capacitance at the point of the right plate of C9. In the numerator, C represents the capacitance of C9; in the denominator, 15C / 64 represents the equivalent capacitance of C5, C6, C7, C8, C10, and C11 at the point on C9's right plate. 2C represents the capacitance of C4, and the two Cs represent the capacitances of C3 and C9, respectively. Therefore, the product of the first and second parts represents the voltage output of C9's right plate, which is the input to C11's left plate.

[0076] Finally, this is equivalent to inputting the left plate of C11:

[0077]

[0078] The value of VOUT is equal to the voltage divided by the capacitance of C11 relative to the total capacitance at the VOUT output point. In the numerator, C / 4 represents the capacitance value of C11; in the denominator, 15C / 4 represents the equivalent capacitance value of C5, C6, C7, C8, and C10 at the VOUT output point, and C / 4 represents the capacitance value of C11.

[0079] When the upper plate potential of the first capacitor C1 is the analog value VIN and the upper plate potentials of the other capacitors are 0 (the single-bit weight stored in the storage unit corresponding to the first capacitor C1 is 1, and the single-bit weight stored in the other storage units is 0), according to the capacitor voltage division relationship, we can obtain:

[0080]

[0081] The derivation process is: when the potential of the upper plate of the first capacitor C1 is the analog value VIN, first calculate the voltage value output by the lower plate of C1. For the first part:

[0082]

[0083] In the numerator, C represents the capacitance value of C1; in the denominator, represents the equivalent capacitance of C3, C4, C5, C6, C7, C8, C9, C10, and C11 at the lower plate of C1, C represents the capacitance of C1, and 2C represents the capacitance of C2. Therefore, the first part represents the voltage output from the lower plate of capacitor C1 when the upper plate potential of capacitor C1 is the analog value VIN, i.e., the input to the left plate of C9.

[0084] Then, this is equivalent to inputting to the left plate of C9:

[0085]

[0086] The output voltage of the right plate of C9 is equal to the voltage divided by the capacitance of C9 relative to the total capacitance at the point of the right plate of C9. In the numerator, C represents the capacitance of C9; in the denominator, 15C / 64 represents the equivalent capacitance of C5, C6, C7, C8, C10, and C11 at the point on C9's right plate. 2C represents the capacitance of C4, and the two Cs represent the capacitances of C3 and C9, respectively. Therefore, the product of the first and second parts represents the voltage output of C9's right plate, which is the input to C11's left plate.

[0087] Finally, this is equivalent to inputting to the left plate of C11:

[0088]

[0089] The value of VOUT is equal to the voltage divided by the capacitance of C11 relative to the total capacitance at the VOUT output point. In the numerator, C / 4 represents the capacitance value of C11; in the denominator, 15C / 4 represents the equivalent capacitance value of C5, C6, C7, C8, and C10 at the VOUT output point, and C / 4 represents the capacitance value of C11.

[0090] The above illustrates the output potential corresponding to each single-bit weight being 1. It can be seen that the weight ratio of each bit of data in the eight-bit weight is 128:64:32:16:8:4:2:1, that is, the single-bit weight stored in the storage unit connected to the eighth capacitor C8 constitutes the highest bit of the eight-bit weight, and so on. The single-bit weight stored in the storage unit connected to the first capacitor C1 constitutes the lowest bit of the eight-bit weight. Therefore, the multiplication operation of the analog quantity VIN and the eight-bit weight can be realized. The multiplication result is the sum of the output potentials corresponding to the single-bit weights of 1 in the eight-bit weight. For example, when the eight-bit weight is 11000000, the weight stored in the storage unit corresponding to the eighth capacitor C8 and the seventh capacitor C7 is 1, and the weight stored in the other storage units is 0, then at this time:

[0091]

[0092] The output VOUT of the SRAM's in-memory multiplication circuit is a weighted multiplication result of the analog quantity.

[0093] The calculation accuracy of the in-memory multiplication circuit of the SRAM in the above embodiment is verified by some experimental data as follows.

[0094] Reference Figure 4 , which is a simulation diagram of the input and output signals of the SRAM's in-memory multiplication circuit in the first example performing multiplication calculations on an analog signal and an eight-bit digital signal. The input analog signal is 900mV, and the eight-bit weight changes with a 2ns period. The circuit is over-discharged before the analog signal is input or when the stored weight data is changed to reduce errors.

[0095] When 0~2ns, the 8-bit digital weight is 11111111, the in-memory calculation result is 878.8mv, the ideal result is 900mv, and the difference is 21.2mv.

[0096] When the time is 2~4ns, the 8-bit digital weight is 10101010, the in-memory calculation result is 582.3mV, the ideal result is 597.6mV, and the difference is 15.3mV.

[0097] When the time is 4~6ns, the 8-bit digital weight is 10000000, the in-memory calculation result is 438.1mV, the ideal result is 450mV, and the difference is 11.9mV.

[0098] Reference Figure 5 This is a simulation diagram of the input and output signals of the SRAM's in-memory multiplication circuit in the second example performing multiplication of an analog signal and an eight-bit digital signal. The input analog signal is 500mV, and the eight-bit weight changes with a 2ns period. The circuit is over-discharged before the analog signal is input or when the stored weight data is changed to reduce errors.

[0099] When 0~2ns, the 8-bit digital weight is 11111111, the in-memory calculation result is 482.7mv, the ideal result is 500mv, and the difference is 17.3mv.

[0100] When the time is 2~4ns, the 8-bit digital weight is 10101010, the in-memory calculation result is 318.5mV, the ideal result is 332.1mV, and the difference is 13.6mV.

[0101] When the time is 4~6ns, the 8-bit digital weight is 10000000, the in-memory calculation result is 239.4mv, the ideal result is 250mv, and the difference is 10.6mv.

[0102] From the above experimental results, it can be seen that the error between the in-memory calculation result and the ideal result is within the allowable range.

[0103] Therefore, the in-memory multiplication circuit of the SRAM provided by the present invention can realize the multiplication calculation of analog quantity and eight-bit weight. More importantly, the structure of the weighted part in the circuit is relatively simple, and only 11 capacitors are used for implementation. Compared with the existing in-memory multiplication circuit, the number of capacitors used is smaller. In addition, the total capacitance value is 14.25 unit capacitances. When the unit capacitance values ​​are the same, the total capacitance value used is smaller. Fewer capacitors and less total capacitance value both reduce the circuit area overhead, solving the problem of large area overhead of the current in-memory multiplication circuit of the charge domain-based SRAM.

[0104] An embodiment of the present invention further provides an in-memory computing circuit comprising a multiplication circuit and an accumulation circuit. The multiplication circuit is the in-memory multiplication circuit of the SRAM provided by the present invention; the accumulation circuit is configured to accumulate the weighted multiplication results of multiple analog quantities calculated by the multiplication circuit, thereby comprehensively implementing weighted accumulation calculations.

[0105] Reference Figure 3 In an embodiment of the present invention, an SRAM in-memory multiplication operation module is further provided, which encapsulates the SRAM in-memory multiplication operation circuit provided by the present invention and has:

[0106] The first pin VIN connected to the analog input line is used to receive the analog quantity to be weighted multiplied; the second pin VOUT connected to the output node of the in-memory multiplication circuit of the SRAM is used to output the weighted multiplication result of the analog quantity; the third pin WL connected to the word line is used to receive the word line signal; the fourth pin VSS connected to the source of the second NMOS tube is used to connect to the external ground terminal; the eight fifth pins BL connected to the eight first bit lines respectively are used to transmit the first bit line signal; the eight sixth pins BLB connected to the eight second bit lines respectively are used to transmit the second bit line signal; the eight seventh pins Q connected to the eight first storage nodes respectively are used to observe the first storage signal; the eight eighth pins QB connected to the eight second storage nodes respectively are used to observe the second storage signal.

[0107] Preferably, the in-memory multiplication module may further include a discharge tube for discharging the in-memory multiplication circuit. The in-memory multiplication module may further include a ninth pin, discharge, connected to the discharge tube. Discharging the discharge tube enhances the accuracy of the calculations performed by the in-memory multiplication circuit. Accordingly, a tenth pin, VDD, may also be configured to connect to an external power supply.

[0108] In an embodiment of the present invention, a static random access memory (SRAM) is also provided, which has a built-in SRAM in-memory multiplication operation circuit provided by the present invention, and the weighted in-memory multiplication calculation of analog quantities is realized through the SRAM in-memory multiplication operation circuit provided by the present invention.

[0109] An embodiment of the present invention further provides an electronic device, including a memory and a processor, wherein the memory is the static random access memory provided by the present invention.

[0110] It should be understood that the specific embodiments described herein are only used to explain this application and are not used to limit it. Based on the embodiments provided in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0111] Obviously, the accompanying drawings are merely examples or embodiments of the present application. A person skilled in the art can also apply the present application to other similar situations based on these drawings without inventive effort. Furthermore, it is understandable that, although the work involved in this development process may be complex and lengthy, certain design, manufacturing, or production changes based on the technical content disclosed in this application are merely routine technical means for a person skilled in the art and should not be considered to constitute a deficiency in the disclosure of the present application.

Claims

1. An in-memory multiplication circuit of an SRAM, characterized in that: include: A storage part, comprising eight storage units, each storage unit having an analog input terminal and an analog output terminal and being used to store a single-bit weight, each storage unit turning on the analog input terminal and the analog output terminal when the single-bit weight stored in the storage unit is 1 and turning off the analog input terminal and the analog output terminal when the single-bit weight stored in the storage unit is 0, and the analog input terminals of the eight storage units are connected to the same analog input line; a weighted portion, comprising a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor and an eleventh capacitor; Among them, the analog output ends of the eight storage units are respectively connected to the first plates of the first capacitor to the eighth capacitor, the second plates of the first capacitor and the second capacitor are connected to the first plate of the ninth capacitor, the second plates of the third capacitor and the fourth capacitor are connected to the second plate of the ninth capacitor, the second plates of the fifth capacitor and the sixth capacitor are connected to the first plate of the tenth capacitor, the second plates of the seventh capacitor and the eighth capacitor are connected to the second plate of the tenth capacitor, the second plate of the ninth capacitor is also connected to the first plate of the eleventh capacitor, and the second plate of the tenth capacitor is also connected to the second plate of the eleventh capacitor and constitutes the output node of the in-memory multiplication circuit of the SRAM.

2. The in-memory multiplication circuit of the SRAM according to claim 1, characterized in that: The single-bit weights stored in the eight storage units constitute eight-bit weights in reverse order; The capacitance of the first capacitor, the third capacitor, the fifth capacitor, the seventh capacitor, the ninth capacitor and the tenth capacitor are the same, the capacitance of the second capacitor, the fourth capacitor, the sixth capacitor and the eighth capacitor are twice that of the first capacitor, and the capacitance of the eleventh capacitor is one quarter of that of the first capacitor.

3. The in-memory multiplication circuit of the SRAM according to claim 1, characterized in that: Each storage unit includes a storage subunit and a transmission unit, the storage subunit has a first storage node and a second storage node, the transmission unit includes a first NMOS tube, a second NMOS tube and a first PMOS tube, the drain of the first NMOS tube and the source of the first PMOS tube are connected to form an analog input terminal, the source of the first NMOS tube, the drain of the first PMOS tube and the drain of the second NMOS tube are connected to form an analog output terminal, the gate of the first NMOS tube is connected to the first storage node, the gate of the first PMOS tube is connected to the second storage node, the gate of the second NMOS tube is connected to the second storage node, and the source of the second NMOS tube is grounded.

4. The in-memory multiplication circuit of the SRAM according to claim 3, characterized in that: In the storage subunit, the first storage node being high and the second storage node being low indicates that the stored single-bit weight is 1, and the first storage node being low and the second storage node being high indicates that the stored single-bit weight is 0.

5. The in-memory multiplication circuit of the SRAM according to claim 3, characterized in that: The storage subunit includes a third NMOS tube, a fourth NMOS tube, a first inverter and a second inverter. The first inverter and the second inverter are cross-coupled to form a first storage node and a second storage node. The source and the drain of the third NMOS tube are respectively connected to the first storage node and the first bit line. The source and the drain of the fourth NMOS tube are respectively connected to the second storage node and the second bit line. The gates of the third NMOS tube and the fourth NMOS tube are both connected to the word line.

6. An in-memory computing circuit, characterized in that: include; A multiplication circuit, which is an in-memory multiplication circuit of the SRAM according to any one of claims 1 to 5; The accumulation circuit is used to accumulate the weighted multiplication calculation results of multiple analog quantities respectively performed by the multiplication circuit.

7. An in-memory multiplication operation module of SRAM, characterized in that: An in-memory multiplication circuit encapsulated with the SRAM according to any one of claims 1 to 5 and having: A first pin connected to the analog quantity input line, used for receiving the analog quantity to be calculated by weighted multiplication; The second pin connected to the output node of the in-memory multiplication circuit of the SRAM is used to output the weighted multiplication calculation result of the analog quantity.

8. The in-memory multiplication operation module of the SRAM according to claim 7, characterized in that: When the packaged device is the SRAM in-memory multiplication circuit of claim 5, it also has: A third pin connected to the word line, used to receive a word line signal; A fourth pin connected to the source of the second NMOS tube and used to connect to an external ground terminal; Eight fifth pins connected to the eight first bit lines respectively, for transmitting first bit line signals; Eight sixth pins respectively connected to the eight second bit lines and used for transmitting second bit line signals; Eight seventh pins connected to the eight first storage nodes respectively, and used for observing the first storage signal; Eight eighth pins respectively connected to the eight second storage nodes are used to observe the second storage signal.

9. A SRAM, characterized in that: The weighted in-memory multiplication calculation of analog quantities is realized by the in-memory multiplication operation circuit of the SRAM described in any one of claims 1-5.

10. An electronic device comprising a memory and a processor, characterized in that: The memory is the SRAM according to claim 9.

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