A method and system for detecting polysilicon gates in a layout

Abstract

The present invention discloses a method and system for detecting polysilicon gates in a layout, including establishing the electrical connection relationship of metal layers and vias that generate all mask layers, excluding system auxiliary layers, and defining it as a bidirectional connection relationship; when performing layout detection, defining inspection rules, screening out areas with a zero edge distance and no established electrical connection, and then locating areas where both ends of the polysilicon gate are wired; the present invention ensures the effective transmission of signals by establishing a bidirectional electrical connection between the metal layer and the via and excluding non-electrical layers, combines DRC and signal integrity analysis to verify and optimize the connection design, the unidirectional connection rule prevents reverse current and noise interference, and the Flood-fill algorithm quickly identifies unconnected gate areas, thereby improving the circuit performance and reliability.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and specifically to a method and system for detecting polysilicon gates in a layout. Background Art

[0002] Complementary Metal-Oxide-Semiconductor (CMOS) technology is one of the core technologies for the design and manufacture of integrated circuits. CMOS technology can fabricate N-type and P-type MOSFETs on a silicon wafer template. These two types of transistors form the basic units of integrated circuits. In CMOS logic circuits, NMOS and PMOS transistors usually appear in pairs to form a CMOS inverter or more complex logic gate circuits. By changing the level state of the gate terminal connection, the inversion or combination of logic signals can be achieved, and various logic operations can be performed. Polysilicon for the gate is usually selected as the gate material due to its good electrical conductivity, lattice structure similar to the silicon matrix material, and the characteristic of being resistant to high-temperature annealing.

[0003] In a CMOS layout, the wiring quality of the polysilicon gate has a significant impact on the performance and reliability of the circuit. The resistance of the polysilicon gate is relatively large. If the wiring is too long or the design is improper, it will increase the signal transmission delay and affect the operating speed of the circuit. Especially in high-frequency circuits, this impact is more obvious. In addition, parasitic capacitance will be formed between the polysilicon gate and the surrounding metal layers or diffusion regions. If the wiring is dense or the layout is unreasonable, the parasitic capacitance will increase, further affecting signal transmission and circuit stability.

[0004] During the layout design process, in order to meet different design requirements, process requirements, and performance indicators, designers will adopt different drawing methods and techniques. However, in this process, some drawing errors often occur. Especially in analog circuits, where the sensitivity to signals is higher, the situation of punching holes at both ends of the polysilicon gate will increase the resistance and capacitance, affecting the circuit performance. Therefore, a method is needed to check and correct the wiring problems of the polysilicon gate. Summary of the Invention

[0005] The purpose of the present invention is to provide a method and system for detecting polysilicon gates in a layout, which is used to check the situation where both ends of the polysilicon gate in the layout data are connected to signal lines, and position and display it for engineers to correct.

[0006] The purpose of the present invention can be achieved through the following technical solutions:

[0007] The present application provides a method for detecting polysilicon gates in a layout, including the following steps:

[0008] Establish the electrical connection relationship of all metal layers and vias that generate mask layers, excluding system auxiliary layers, and define it as a bidirectional connection relationship;

[0009] Based on the electrical connection relationship between the metal layer and the via, establish the electrical connection relationship between the first metal layer and the gate polysilicon, and define the unidirectional connection rule between the two objects of the first metal layer and the gate polysilicon;

[0010] When performing layout detection, define the inspection rules, define the gate polysilicon as shape1, and define the position where the gate polysilicon overlaps with the first metal layer and there is a via as shape2. By measuring the edge distance between shape1 and shape2, filter out the areas where the edge distance is zero and no electrical connection is established, and then locate the areas where both ends of the polysilicon gate are wired.

[0011] Furthermore, establish the electrical connection relationship between all metal layers and vias that generate mask layers, specifically including:

[0012] Identify the positions of metal layers and vias in the chip, and then define the bidirectional connection rule between the positions of metal layers and vias, so that the signal can be transmitted from one layer to another through the via and can return, and then verify the bidirectional connection through design rule checking and signal integrity analysis.

[0013] Furthermore, verify the bidirectional connection through design rule checking and signal integrity analysis, specifically including:

[0014] Import the design rules of the layout into the DRC tool to check the via pitch, size and connection with the metal layer of the layout;

[0015] Extract the interconnect paths of metal layers and vias from the design layout, generate a physical network model based on the extracted interconnect paths, and output the physical characteristics of the interconnect paths;

[0016] Combined with the physical characteristics of the interconnect paths, set the conditions for signal integrity analysis and use them as the input of the physical network model to perform signal integrity analysis;

[0017] Optimize the via and metal layer design according to the signal integrity analysis results.

[0018] Furthermore, after defining the unidirectional connection rule between the two objects of the first metal layer and the gate polysilicon, use the Flood-fill algorithm to detect and identify the interconnect areas in the layout, specifically including:

[0019] Identify and mark all known connection points in the layout and use them as the starting points of the Flood-fill algorithm;

[0020] Starting from the known connection points, apply the Flood-fill algorithm to recursively fill all connected areas and mark all areas that are electrically connected to the starting point;

[0021] By means of neighborhood search, the connected regions are recursively expanded, and each gate is checked to see if it is connected to a known connection point, so as to quickly identify those gate regions that are not electrically connected to the first metal layer through vias.

[0022] Furthermore, regions with zero edge distance and no electrical connection established are screened out, including identifying specific visual feature edges, and the visual feature edges indicate potential wiring problems.

[0023] Further, according to the measured edge distance between shape1 and shape2, image processing and pattern recognition technologies are used to automatically identify shape1 and shape2 in the figure, as well as the edge distance between shape1 and shape2. The specific content includes:

[0024] Image data is obtained from the layout design software, and the recognition of edges and features in the image is improved through preprocessing operations. An edge detection algorithm is applied to identify the edges of gate polysilicon and the first metal layer;

[0025] Then the Hough transform is used to detect the linear features of the polysilicon gate to identify its position and morphology.

[0026] Further, the edge intensity and direction are detected by the Sobel operator, and the gradient method is applied to process the edges in the image to highlight the contours of gate polysilicon and the first metal layer;

[0027] The calculation of the edge intensity is expressed as: ;

[0028] where E represents the edge intensity, represents the Sobel operator in the horizontal direction, represents the Sobel operator in the vertical direction, represents the convolution operation, and I is the input image;

[0029] The calculation of the edge direction is expressed as: .

[0030] Further, the Hough transform is expressed as: ; where, represents the accumulator space, and h and α respectively represent the vertical distance and angle of the straight line.

[0031] Further, the edge distance between shape1 and shape2 is expressed as:

[0032] ; where D represents the edge distance, is the edge point of shape1, is the edge point of shape2.

[0033] A detection system for polysilicon gates in a layout, comprising a connection relationship establishment module, a unidirectional connection rule definition module, a rule check and signal integrity analysis module, and an image processing and pattern recognition module;

[0034] The connection relationship establishment module is used to establish a two-way electrical connection relationship between the metal layer and the via, and exclude system auxiliary layers that do not participate in electrical connections;

[0035] The unidirectional connection rule definition module defines the unidirectional connection rule between the first metal layer and the polysilicon gate to enable unidirectional current flow;

[0036] The rule check and signal integrity analysis module uses a DRC tool to check whether the layout complies with design specifications, including via pitch, size, and metal layer connection conditions; then performs signal integrity analysis to simulate signal transmission;

[0037] The image processing and pattern recognition module obtains image data from the layout, identifies the edges of the gate polysilicon and the first metal layer through image processing techniques, automatically identifies shape1 and shape2 using pattern recognition techniques, measures the edge distance between shape1 and shape2, and filters out areas where the edge distance is zero and no electrical connection is established.

[0038] The beneficial effects of the present invention are as follows:

[0039] The present invention ensures the effective transmission of signals by establishing a two-way electrical connection relationship between the metal layer and the via and excluding system auxiliary layers that do not participate in electricity. Then, using design rule check (DRC) and signal integrity analysis, it verifies whether the connection between the metal layer and the via complies with design specifications and optimizes the design of the via and the first metal layer. In addition, through the unidirectional connection rule, it ensures that the connection from the first metal layer to the gate polysilicon is unidirectional, preventing potential reverse current or noise interference; it detects the interconnection area through the Flood-fill algorithm, quickly identifies the gate area that has not established an electrical connection with the first metal layer. Finally, combining image processing and pattern recognition techniques, it automatically identifies and measures the edge distance between the polysilicon gate and the first metal layer, accurately locates the wiring problem area, especially potential problems indicated by visual feature edges, solves the polysilicon gate wiring problem in complementary metal-oxide-semiconductor (CMOS) technology, thereby realizing the automatic detection and correction of polysilicon gate wiring problems, and significantly improving the accuracy of layout design and the electrical performance of the circuit. Description of the Drawings

[0040] For better understanding and implementation, the technical solutions of the present application will be described in detail below with reference to the drawings.

[0041] Figure 1 Schematic flow chart of a method for detecting polysilicon gates in a layout provided in Embodiment 1 of this application;

[0042] Figure 2 Schematic flow chart of a method for detecting polysilicon gates in a layout provided in Embodiment 1 of this application to verify two-way connections through design rule checking and signal integrity analysis;

[0043] Figure 3 Schematic flow chart of a method for detecting polysilicon gates in a layout provided in Embodiment 1 of this application to detect and identify the interconnect area in the layout through the Flood-fill algorithm;

[0044] Figure 4 Schematic flow chart of a method for detecting polysilicon gates in a layout provided in Embodiment 1 of this application to automatically identify the edge distance using image processing and pattern recognition technologies;

[0045] Figure 5 Schematic diagram of the metal layer and vias for establishing connections in a method for detecting polysilicon gates in a layout provided in Embodiment 1 of this application;

[0046] Figure 6 Schematic diagram of a unidirectional connection between the first metal layer and the gate polysilicon in a method for detecting polysilicon gates in a layout provided in Embodiment 1 of this application. Detailed implementation manners

[0047] To further elaborate on the technical means and effects adopted by the present invention to achieve the predetermined invention purpose, exemplary embodiments will be described in detail herein, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with this application. On the contrary, they are only examples of methods and systems consistent with some aspects of this application as detailed in the appended claims.

[0048] The terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The singular forms "a", "the", and "said" used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0049] The following, in conjunction with the drawings and preferred embodiments, details the specific implementation manners, features, and their effects according to the present invention.

[0050] Embodiment 1

[0051] Please refer to Figures 1-6 , this embodiment provides a method and system for detecting polysilicon gates in a layout, which is used to check the situation where both ends of the polysilicon gates in the layout data are connected to signal lines, and locate and display them for engineers to correct.

[0052] The present invention provides a method for detecting polysilicon gates in a layout, including the following steps:

[0053] S1. Establish the electrical connection relationship between all metal layers and vias that generate mask layers, excluding system auxiliary layers, and define it as a bidirectional connection relationship. It can penetrate from the first metal layer M1 to the fourth metal layer M4, and the fourth metal layer M4 can also penetrate to the first metal layer M1. Specifically, the first metal layer M1 to the fourth metal layer M4 refer to different metal layers (Metal Layers) in the polysilicon gate, which are used to achieve electrical connection and signal transmission. The first metal layer is the bottom metal layer, responsible for making electrical connection with the underlying semiconductor material (such as a silicon substrate), and can be directly connected to the power supply or reference voltage;

[0054] The second metal layer is used to connect circuit components with different functions, form electrical connections with other metal layers or vias, and can transfer signals from the first metal layer to higher layers;

[0055] The third metal layer is used for more complex circuit layouts, enabling signals to cross multiple regions;

[0056] The fourth metal layer is the highest metal layer, responsible for connecting to external pins or other external circuits to complete the final signal output or reception. By establishing the electrical connection relationship of these metal layers, the electrical behavior of the polysilicon gate can be effectively detected and analyzed to ensure its function and reliability in the integrated circuit. Specifically as Figure 5 shown;

[0057] Specific system auxiliary layers include annotation layers, marking layers, etc., which do not participate in actual electrical connections and need to be excluded when establishing connection relationships.

[0058] Furthermore, establishing the electrical connection relationship between all metal layers and vias that generate mask layers specifically includes:

[0059] Identify the metal layers (such as the first metal layer, the second metal layer, the third metal layer, etc.) and via positions in the chip, then define the bidirectional connection rules between the metal layer and via positions, enabling signals to be transmitted from one layer to another through vias and return, and then verify the bidirectional connection through design rule checking and signal integrity analysis to ensure that the electrical performance meets the requirements.

[0060] Specifically, by precisely defining the two-way connection rules between metal layers (such as the first metal layer to the fourth metal layer), it is ensured that signals can be effectively transmitted between different metal layers. At the same time, system auxiliary layers that do not participate in electrical functions, such as annotation layers and marking layers, are excluded, enabling design rule checking (DRC) and signal integrity analysis to verify whether these connections meet the design specifications, thereby ensuring that the electrical performance of the layout design meets the expected requirements and improving the reliability and performance of the circuit.

[0061] Furthermore, verifying the two-way connection through design rule checking and signal integrity analysis specifically includes:

[0062] S11. Import the design rules of the layout into the DRC tool to check the via pitch, size, and connection with the metal layer of the layout;

[0063] S12. Extract the interconnect paths of the metal layer and vias from the design layout, generate a physical network model based on the extracted interconnect paths, and output the physical characteristics of the interconnect paths, including parameters such as the frequency, load, and transmission path of the signal;

[0064] S13. Combine the physical characteristics of the interconnect paths, set the conditions for signal integrity analysis, including parameters such as the frequency, load capacitance, and transmission path of the signal, and use them as the input of the physical network model to perform signal integrity analysis; the analysis includes signal transmission delay, reflection, impedance matching, and signal attenuation, etc.

[0065] S14. Optimize the via and metal layer designs according to the signal integrity analysis results.

[0066] Use the DRC tool to check whether the layout of the metal layer and vias conforms to the preset design specifications, such as via pitch, size, and correct connection with the metal layer, to ensure that there are no rule-violating errors. Then, through signal integrity analysis, simulate the transmission of signals on the two-way path, focusing on analyzing signal delay, reflection, impedance matching, etc., to ensure that there is no obvious signal attenuation, interference, or parasitic effect during the two-way transmission process, and finally verify that the electrical performance meets the design requirements.

[0067] S2. According to the electrical connection relationship between the metal layer and the via, establish the electrical connection relationship between the first metal layer and the gate polysilicon, define the one-way connection rule between the two objects of the first metal layer and the gate polysilicon, that is, from the first metal layer, it can only reach the gate polysilicon layer through the gate polysilicon via, and cannot go from the gate polysilicon layer to the first metal layer, as Figure 6 shown in the box.

[0068] Specifically, in an integrated circuit, the metal layer is used to form interconnecting lines to provide electrical connections; the gate polysilicon layer, also known as the gate layer (POLY silicon Layer), is used to form the gates of transistors; the gate polysilicon via PC refers to the via that connects the gate polysilicon layer to other layers (such as the metal layer), also known as the gate polysilicon via, which is a conductive layer specifically used to connect the gate polysilicon layer to other levels to form vertical electrical connections.

[0069] Among them, when establishing the electrical connection between the first metal layer M1 and the gate polysilicon, it is stipulated that this connection is unidirectional, that is, only allowing the connection from the first metal layer M1 to the gate polysilicon layer upward through the gate polysilicon via PC, and reverse connection is not allowed. Such a design realizes precise control of the current flow direction, ensures the stability and predictability of the circuit, and at the same time helps to prevent potential reverse current or noise interference, thus optimizing the performance and reliability of the integrated circuit.

[0070] Furthermore, after defining the unidirectional connection rule between the two objects of the first metal layer M1 and the gate polysilicon, the Flood-fill algorithm is used to detect and identify the interconnect regions in the layout, specifically including:

[0071] S21. Identify and mark all known connection points in the layout, which will serve as the starting points for the Flood-fill algorithm;

[0072] S22. Starting from the known connection points, apply the Flood-fill algorithm to recursively fill all connected regions and mark all regions electrically connected to the starting points;

[0073] S23. Through neighborhood search, recursively expand the connection region, check whether each gate is connected to the known connection points, and quickly identify those gate regions that are not electrically connected to the first metal layer M1 through vias.

[0074] Specifically, combining the detection results of the Flood-fill algorithm with the unidirectional connection rule can ensure that all connections from the first metal layer M1 to the gate polysilicon are established according to the predetermined unidirectional rule. At the same time, the unconnected gate regions identified by the Flood-fill algorithm can ensure that the connection between the first metal layer M1 and the gate polysilicon in the layout fully complies with the predetermined unidirectional connection rule, and can quickly identify any unconnected gate regions, thus optimizing the layout design of the entire integrated circuit.

[0075] S3. When performing layout detection, define inspection rules. Define the gate polysilicon as shape1, and define the position where the gate polysilicon overlaps with the first metal layer M1 and there are vias as shape2. By measuring the edge distance between shape1 and shape2, filter out the areas where the edge distance is zero and no electrical connection is established, and then locate the areas where both ends of the polysilicon gate are wired.

[0076] Specifically, filter out the areas where the edge distance is zero and no electrical connection is established, including identifying specific visual feature edges. The visual feature edges indicate potential wiring problems. Through this method, it is possible to accurately locate the areas where both ends of the polysilicon gate are wired, achieve precise positioning and problem identification of the wired areas at both ends of the polysilicon gate, and improve the accuracy and efficiency of layout detection.

[0077] Furthermore, according to the measured edge distance between shape1 and shape2, use image processing and pattern recognition techniques to automatically identify shape1 and shape2 in the figure, as well as the edge distance between shape1 and shape2. The specific content includes:

[0078] S31. Obtain image data from the layout design software, improve the recognition of edges and features in the image through preprocessing operations, and apply an edge detection algorithm to identify the edges of the gate polysilicon (polysilicon gate) and the first metal layer M1;

[0079] Specifically, detect the edge strength and direction through the Sobel operator, and apply the gradient method to process the edges in the image to highlight the contours of the gate polysilicon and the first metal layer M1;

[0080] The calculation of the edge strength is expressed as: ;

[0081] where E represents the edge strength, represents the Sobel operator in the horizontal direction, represents the Sobel operator in the vertical direction, represents the convolution operation, and I is the input image;

[0082] The calculation of the edge direction is expressed as: ; where θ represents the edge direction.

[0083] S32. Then use the Hough transform to detect the linear features of the polysilicon gate and identify its position and morphology;

[0084] The Hough transform is expressed as: ; where represents the accumulator space, and h and α respectively represent the vertical distance and angle of the straight line.

[0085] Furthermore, the edge distance between shape1 and shape2 is expressed as:

[0086] ; where D represents the edge distance, is an edge point of shape1, is an edge point of shape2.

[0087] Specifically, by combining image processing techniques and pattern recognition methods, this process can automatically identify the edges of gate polysilicon (polysilicon gate) and the first metal layer M1 (shape1 and shape2 respectively) from an integrated circuit layout, and accurately measure the edge distance between them. The Sobel operator is used to calculate the edge strength and direction, and the Hough transform is used to identify the linear features of the gate, thus precisely locating potential wiring problem areas, especially those with a zero edge distance, ensuring the accuracy of the layout design and the reliability of the circuit performance.

[0088] Specifically, the present invention provides an automated method for detecting polysilicon gates in an integrated circuit layout. First, in step S1, a two-way electrical connection relationship is established between the metal layers (such as the first metal layer M1 to the fourth metal layer M4) and the vias, while excluding system auxiliary layers that do not participate in the electrical connection, such as the annotation layer and the marking layer. Then, through design rule checking (DRC) tools and signal integrity analysis, it is verified whether the connection between the metal layer and the via complies with the design specifications and ensures the signal transmission performance. In step S2, a one-way connection rule between the first metal layer M1 and the polysilicon gate (gate polysilicon) is specifically defined, allowing only the connection from the first metal layer M1 to the gate polysilicon through the gate polysilicon via (PC), ensuring the unidirectional flow of current, thereby improving the stability and reliability of the circuit. In step S3, using image processing techniques such as the Sobel operator and the Hough transform, the edges of the overlapping region of the gate polysilicon (shape1) and the first metal layer M1 (shape2) are automatically identified, and the regions where no electrical connection is established are screened out by measuring the distance between these edges, especially those with a zero edge distance. These regions may indicate potential wiring problems, especially by identifying the visual feature edges to indicate these problems. The wiring problems at both ends of the polysilicon gate can be accurately located, thereby improving the detection efficiency and accuracy of the entire integrated circuit.

[0089] By changing the original two-way connection between the first metal layer M1 and the gate polysilicon into a one-way connection from the first metal layer M1 to the gate polysilicon when establishing the electrical connection relationship, and then by additional rule limitations, the target area can be located; the user can directly locate the positions of the wire connections at both ends of the polysilicon gate, without the need for manual inspection to prevent missed inspections. Additionally, engineers can choose whether to modify according to the actual situation. This method improves the accuracy and efficiency of positioning and reduces the need for manual inspection. Through the present invention, the target area, that is, the positions of the wire connections at both ends of the polysilicon gate, can be accurately located, thereby improving the performance and reliability of the circuit. This method can automatically detect and correct the wiring problems of the polysilicon gate, reduce the need for manual inspection, and improve efficiency and accuracy.

[0090] Embodiment 2

[0091] This embodiment provides a detection system for polysilicon gates in a layout, including a connection relationship establishment module, a one-way connection rule definition module, a rule check and signal integrity analysis module, and an image processing and pattern recognition module;

[0092] The connection relationship establishment module is used to establish a two-way electrical connection relationship between metal layers (such as the first metal layer M1 to the fourth metal layer M4) and vias, and exclude system auxiliary layers that do not participate in electrical connections, such as annotation layers and marking layers;

[0093] The one-way connection rule definition module defines the one-way connection rule between the first metal layer M1 and the polysilicon gate to make the current flow unidirectionally, improving the stability and reliability of the circuit;

[0094] The rule check and signal integrity analysis module uses DRC tools to check whether the layout complies with the design specifications, including via spacing, size, and metal layer connection conditions; then performs signal integrity analysis, simulates signal transmission, and analyzes signal delay, reflection, impedance matching, and signal attenuation, etc., to ensure that the electrical performance meets the design requirements;

[0095] The image processing and pattern recognition module obtains image data from the layout, and uses image processing techniques to identify the edges of the gate polysilicon (gate polysilicon) and the first metal layer M4, automatically identifies shape1 and shape2 using pattern recognition techniques, measures the edge distance between shape1 and shape2, filters out areas with a zero edge distance and no established electrical connection, and accurately locates potential wiring problems.

[0096] Embodiment 3

[0097] This embodiment is different from Embodiment 1 and further includes an integrated machine learning enhancement model for training the model to recognize complex layout patterns and potential defects. Specifically, it uses historical data and known layout defect cases to train a classifier to automatically identify and classify different layout problems.

[0098] The specific content includes:

[0099] Collect a large amount of historical layout design data and known layout defect cases, and preprocess the collected data, including image enhancement, denoising, and normalization, to improve the training effect of subsequent machine learning models;

[0100] Extract key features from the preprocessed image data, use techniques such as Sobel operators and Hough transforms to accurately identify the edges of polysilicon gates and the first metal layer M1, and then select a convolutional neural network CNN to train a classifier based on the extracted key features;

[0101] Use the collected historical data and feature information to train the machine learning model. During the training process, use a large number of labeled layout images as inputs to let the CNN learn how to identify the edges of polysilicon gates and the first metal layer M1 and the connection relationship between them from complex image data. At the same time, use a part of the reserved data as a validation set to continuously adjust the network parameters to optimize the performance and prevent overfitting;

[0102] Apply the trained machine learning model to new integrated circuit layout designs, automatically detect and classify potential layout problems, combine previously defined unidirectional connection rules and image processing techniques to accurately locate wiring problems at both ends of polysilicon gates and other possible design defects. Finally, based on the results output by the model, engineers can quickly identify problems and make necessary corrections to improve the quality and reliability of circuit designs.

[0103] As described above, it is only a preferred embodiment of the present invention and does not impose any form of limitation on the present invention. Although the present invention has been disclosed above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some changes or modifications to the above-disclosed technical content to form an equivalent embodiment with equivalent changes within the scope of the technical solution of the present invention. However, as long as it does not depart from the content of the technical solution of the present invention, any brief modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A method for detecting polysilicon gates in a layout, characterized in that: It includes the following steps: Establish the electrical connection relationship of all metal layers and vias that generate the mask layer, excluding the system auxiliary layer, and define it as a bidirectional connection relationship, where the bidirectional connection relationship means that the first metal layer and the fourth metal layer are interconnected; According to the electrical connection relationship of the metal layer and the via, establish the electrical connection relationship between the first metal layer and the gate polysilicon, and define the unidirectional connection rule between the two objects of the first metal layer and the gate polysilicon; When performing layout detection, define the inspection rules, define the gate polysilicon as shape1, and define the position where the gate polysilicon overlaps with the first metal layer and there is a via as shape2. By measuring the edge distance between shape1 and shape2, filter out the area where the edge distance is zero and no electrical connection is established, and then locate the area where both ends of the gate polysilicon are wired; Among them, after defining the unidirectional connection rule between the two objects of the first metal layer and the gate polysilicon, use the Flood-fill algorithm to detect and identify the interconnected areas in the layout, specifically including: Identify and mark all known connection points in the layout and use them as the starting points of the Flood-fill algorithm; Starting from the known connection points, apply the Flood-fill algorithm to recursively fill all connected areas and mark all areas that are electrically connected to the starting point; Through neighborhood search, recursively expand the connection area, check whether each gate is connected to the known connection points, and quickly identify the gate areas that are not electrically connected to the first metal layer through vias.

2. The detection method of polysilicon gates in a layout according to claim 1, characterized in that: Establish the electrical connection relationship of all metal layers and vias that generate the mask layer, specifically including: Identify the positions of metal layers and vias in the chip, then define the bidirectional connection rule between the positions of metal layers and vias, so that the signal can be transmitted from one layer to another through the via and can return, and then verify the bidirectional connection through design rule check and signal integrity analysis.

3. A method for detecting polysilicon gates in a layout according to claim 2, characterized in that: Verify the bidirectional connection through design rule check and signal integrity analysis, specifically including: Import the design rules of the layout into the DRC tool to check the via pitch, size and connection with the metal layer of the layout; Extract the interconnect paths of the metal layer and the via from the design layout, generate a physical network model based on the extracted interconnect paths, and output the physical characteristics of the interconnect paths; Combined with the physical characteristics of the interconnect paths, set the conditions for signal integrity analysis and use them as the input of the physical network model to perform signal integrity analysis; Optimize the via and metal layer design according to the signal integrity analysis results.

4. The detection method of polysilicon gates in a layout according to claim 1, characterized in that: Filter out the area where the edge distance is zero and no electrical connection is established, including identifying specific visual feature edges, and the visual feature edges indicate potential wiring problems.

5. A method for detecting polysilicon gates in a layout according to claim 1, characterized in that: According to the measured edge distance between shape1 and shape2, use image processing and pattern recognition technologies to automatically identify shape1 and shape2 in the figure, and the edge distance between shape1 and shape2. The specific content includes: Obtain image data from the layout design software, improve the recognition of edges and features in the image through preprocessing operations, and apply edge detection algorithms to identify the edges of the gate polysilicon and the first metal layer; Then use the Hough transform to detect the linear features of the polysilicon gate to identify its position and morphology.

6. The detection method of polysilicon gates in a layout according to claim 5, characterized in that: The edge detection algorithm detects the edge intensity and direction through the Sobel operator, and applies the gradient method to process the edges in the image to highlight the contours of the polysilicon gate and the first metal layer; The edge strength calculation is expressed as: ; Among them, E represents the edge strength, represents the Sobel operator in the horizontal direction, represents the Sobel operator in the vertical direction, represents the convolution operation, and I is the input image; The edge direction calculation is expressed as: .

7. A method for detecting polysilicon gates in a layout according to claim 5, characterized in that: The Hough transform is expressed as: ; where represents the accumulator space, and h and α represent the perpendicular distance and angle of the straight line, respectively.

8. A method for detecting a polysilicon gate in a layout according to claim 5, wherein: Calculate the edge distance between shape1 and shape2, expressed as: ; where D represents the edge distance, is an edge point of shape1, is an edge point of shape2.

9. A polysilicon gate detection system in a layout, applying a polysilicon gate detection method in a layout according to any one of claims 1-8, characterized in that: Including a connection relationship establishment module, a unidirectional connection rule definition module, a rule check and signal integrity analysis module, and an image processing and pattern recognition module; The connection relationship establishment module is used to establish a two-way electrical connection relationship between the metal layer and the via, and exclude the system auxiliary layer that does not participate in the electrical connection; The unidirectional connection rule definition module defines the unidirectional connection rule between the first metal layer and the polysilicon gate to enable the unidirectional flow of current; The rule check and signal integrity analysis module uses the DRC tool to check whether the layout meets the design specifications, including the via pitch, size, and metal layer connection conditions; then perform signal integrity analysis to simulate signal transmission; The image processing and pattern recognition module obtains image data from the layout, identifies the edges of the polysilicon gate and the first metal layer through image processing techniques, automatically identifies shape1 and shape2 using pattern recognition techniques, measures the edge distance between shape1 and shape2, and filters out the areas where the edge distance is zero and no electrical connection is established.

Images