Data retention method, device, storage control chip and storage medium

Abstract

The application discloses a data keeping method, device, storage control chip and storage medium. The method comprises the following steps: performing scanning on a Flash, and reading error bit numbers of each page in the Flash; screening unstable pages according to the error bit numbers; adjusting threshold voltages of the unstable pages according to a preset adjustment method, so that the error bit numbers of the unstable pages change, generating a re-reading voltage table according to a change result, and storing the re-reading voltage table. The unstable pages are screened in advance, the threshold voltages of the unstable pages are adjusted, the threshold voltage adjustment causes the error bit numbers of the unstable pages to change, the re-reading voltage table is generated according to the change result, and the data accuracy of the Flash can be kept since the re-reading voltage table records the threshold voltages for adjusting the unstable pages into stable pages.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of flash memory, in particular to a data keeping method, device, storage control chip and storage medium. BACKGROUND

[0002] NAND Flash (hereinafter referred to as Flash) is widely used in the storage industry due to its capacity and stability, and is currently the preferred storage medium for manufacturing storage products.

[0003] Due to the unique physical properties of Flash, such as SLC type Flash, if the voltage of a storage unit is above the threshold voltage, it is determined that the charge state of the storage unit is "1"; if the voltage of the storage unit is below the threshold voltage, it is determined that the charge state of the storage unit is "0". Flash is based on the above working principle to realize data reading.

[0004] Flash will become unstable over time, and the electrons stored in the storage unit will be lost, causing the threshold voltage distribution to move. If the original factory configured threshold voltage is still used to read data from Flash at this time, it will cause misjudgment of data, i.e. read error. SUMMARY

[0005] The purpose of the present application is to overcome the shortcomings of the prior art, and to provide a data keeping method, device, storage control chip and storage medium, which can keep the accuracy of Flash data.

[0006] The first aspect of the present application provides a data keeping method, comprising:

[0007] performing scanning on Flash to read the number of error bits of each page in Flash;

[0008] screening unstable pages according to the number of error bits;

[0009] adjusting the threshold voltage of the unstable pages according to a preset adjustment method, so that the number of error bits of the unstable pages changes, and generating a re-reading voltage table according to the change result;

[0010] storing the re-reading voltage table.

[0011] Further, in one of the preferred embodiments, the reading of the number of error bits of each page in Flash comprises:

[0012] reading the number of error bits of each Frame in the current page;

[0013] The number of error bits in each of the frames is compared, and the highest number of error bits is taken as the number of error bits of the current page.

[0014] Further, in one of the preferred embodiments, the filtering out of the unstable page according to the number of error bits comprises:

[0015] The number of error bits of the page in each block is counted, and the number of error bits exceeding a first preset threshold is counted.

[0016] The unstable page is filtered out based on the result of the number of times of exceeding.

[0017] If the Flash is a single-bit type, the unstable page includes the current page; if the Flash is a multi-bit type, the unstable page includes the current page and a shared page corresponding to the current page.

[0018] Further, in one of the preferred embodiments, the unstable page is changed according to the preset adjustment method, and a re-reading voltage table is generated according to the change result, comprising:

[0019] The threshold voltage value of the register is configured according to the preset adjustment step, and the number of error bits of the unstable page after adjustment is read.

[0020] According to the change result of the number of error bits, the matching relationship between the register and the unstable page is confirmed.

[0021] The threshold voltage value of the register matched with the unstable page is configured according to the preset adjustment step, and a re-reading voltage table is generated, wherein the re-reading voltage table includes a plurality of re-reading voltage sequences, and each re-reading voltage sequence records the threshold voltage value of the register corresponding to the unstable page.

[0022] Further, in one of the preferred embodiments, after the threshold voltage value of the register matched with the unstable page is configured according to the preset adjustment step, and a re-reading voltage table is generated, it further comprises:

[0023] The re-reading voltage sequence in which the number of error bits drops to a second preset threshold is filtered out as a target re-reading voltage sequence.

[0024] The target re-reading voltage sequence is composed into a target re-reading voltage table.

[0025] The re-reading voltage table is stored, comprising:

[0026] The target re-reading voltage table is stored.

[0027] The second aspect of the present application provides a data retention device, comprising:

[0028] a scanning module, configured to perform scanning on the Flash, and read error bit numbers of each page in the Flash;

[0029] a screening module, configured to screen unstable pages according to the error bit numbers;

[0030] an adjusting module, configured to adjust threshold voltages of the unstable pages according to a preset adjusting method, so that the error bit numbers of the unstable pages change, and generate a re-reading voltage table according to a change result;

[0031] a storage module, configured to store the re-reading voltage table.

[0032] Further, in one of the preferred embodiments, the scanning module comprises:

[0033] a reading unit, configured to read error bit numbers of each Frame in the current page;

[0034] a confirming unit, configured to take the highest error bit number in each Frame as the error bit number of the current page.

[0035] Further, in one of the preferred embodiments, the screening module comprises:

[0036] a counting unit, configured to count the pages whose error bit numbers exceed a first preset threshold in each block;

[0037] a locking unit, configured to screen unstable pages based on a result of the exceeding times;

[0038] If the Flash is a single-bit type, the unstable pages include the current page; if the Flash is a multi-bit type, the unstable pages include the current page and a shared page corresponding to the current page.

[0039] Further, in one of the preferred embodiments, the adjusting module comprises:

[0040] a voltage configuring unit, configured to configure threshold voltage values of registers one by one, and read the error bit numbers of the unstable pages after the adjustment;

[0041] a matching unit, configured to confirm a matching relationship between the registers and the unstable pages according to a change result of the error bit numbers;

[0042] a generating unit, configured to configure threshold voltage values of the registers matched with the unstable pages according to a preset adjusting step, and generate a re-reading voltage table, wherein the re-reading voltage table comprises a plurality of re-reading voltage sequences, and each re-reading voltage sequence records the threshold voltage values of the registers corresponding to the unstable pages.

[0043] Further, in one of the preferred embodiments, the adjusting module further comprises:

[0044] a target screening unit configured to screen a re-reading voltage sequence in which the error bit number drops to a second preset threshold value as a target re-reading voltage sequence;

[0045] a sequence forming unit configured to form the target re-reading voltage sequence into a target re-reading voltage table;

[0046] The storage module for storing the re-reading voltage table comprises:

[0047] storing the target re-reading voltage table.

[0048] The technical solution of the present application comprises: performing scanning on a Flash, reading the error bit number of each page in the Flash; screening unstable pages according to the error bit number; adjusting the threshold voltage of the unstable pages according to a preset adjustment method, so as to change the error bit number of the unstable pages, and generating a re-reading voltage table according to the change result; and storing the re-reading voltage table. By screening unstable pages in advance, the threshold voltage of these unstable pages is adjusted, the threshold voltage adjustment will change the error bit number of the unstable pages, and a re-reading voltage table is generated according to the change result. Since the re-reading voltage table records the threshold voltage for adjusting the unstable pages into stable pages, the data accuracy of the Flash can be maintained. BRIEF DESCRIPTION OF DRAWINGS

[0049] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced as follows. It should be understood that the following drawings only show some of the embodiments of the present application, and therefore should not be considered as a limitation on the scope. For those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0050] Figure 1 is a flowchart of a data retention method according to an embodiment of the present application;

[0051] Figure 2 is a flowchart of a data retention method according to another embodiment of the present application;

[0052] Figure 3 is a structural diagram of a data retention device according to an embodiment of the present application;

[0053] Figure 4 is a structural diagram of a data retention device according to another embodiment of the present application;

[0054] Figure 5Fig. 1 shows a structural schematic diagram of a storage control chip according to an embodiment of the present application.

[0055] Figure 6 Fig. 2 shows a structural schematic diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0056] In order to make the application more comprehensively understood, the related drawings will be used in the following detailed description of the application. The preferred embodiments of the application are shown in the drawings. However, the application can be realized in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided for the purpose of making the disclosure of the application more thorough and comprehensive.

[0057] It should be noted that when an element is referred to as being "fixed" to another element, it can be directly on the other element or there can be an intervening element. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements can be present. The terms "vertical", "horizontal", "left", "right", and the like as used herein are for purposes of illustration and description only and are not intended to be limiting.

[0058] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0059] In the related art, as the use time of the Flash increases, the electronic stored in the storage unit will be lost, causing the threshold voltage distribution to move. If the original factory configured threshold voltage is still used to read data from the Flash at this time, it will cause misjudgment of the data, i.e., read error occurs.

[0060] Therefore, in order to solve the above technical problems, the present application provides a data retention method, which can keep the accuracy of the data of the Flash.

[0061] The technical solutions of the present application will be described in detail below with reference to the drawings.

[0062] Before formally describing the technical solutions of the present application, the professional terms involved in the present application will be described.

[0063] Read Retry: is a mechanism to manage the read and write operation of Flash. Due to the physical characteristics of Flash, the threshold voltage of Flash will shift as a whole due to the increase of quality, usage times and located in extreme environment. If the original configured threshold voltage is still used to read data at this time, the read data will be misjudged. After using the read retry mechanism, the threshold voltage can be changed constantly to try to find the voltage point that can read out the correct data until the correct data is read out.

[0064] Retry Table: if the Flash constantly changes the threshold voltage until it matches the voltage point that can read out the correct data. The adjustment range of the threshold voltage is recorded in the retry table, and the Flash can implement the read retry of the data based on the retry table.

[0065] The key of the read retry mechanism lies in the establishment of the retry table. Due to the storage capacity of the Flash and the requirements of the related storage protocol (such as the SD standard protocol, the USB standard protocol), the Flash cannot read without cost, therefore, the "good and bad" of the establishment of the retry table is particularly important. The table not only needs to consider how to reduce the occupied capacity of the Flash as much as possible, but also needs to consider how to use the least read times to make the Flash read out the correct data. It needs to be emphasized that the "correct data" mentioned above does not require the data read out by the Flash to be exactly the same as the original data, and a part of the bit error of the data can be allowed, as long as the bit error can be corrected by the ECC error correction mechanism.

[0066] Figure 1 Fig. 1 shows a flowchart of a data retention method according to an embodiment of the present application.

[0067] Referring to Fig. 1, a data retention method includes the following steps: Figure 1

[0068] Step S110, performing scanning on the Flash to read the number of error bits of each page in the Flash.

[0069] ​The flash is divided into Die (LUN), Plane, Block and Page according to the architecture hierarchy. The full scan of the flash is performed to read each Plane, each Block and each Page in the flash. The purpose of the full scan is to read the basic information of each Page in the flash. In the embodiment, the number of error bits of each Page is read. In the firmware design, the Page is the smallest unit capable of data storage composed of several Frames. For most models of flash, the size of the Page is 16Kbyte, and the size of the Frame is 1Kbyte, that is, each Page includes 16 Frames, and each Frame corresponds to the number of error bits.

[0070] It should be noted that in the embodiment, the number of error bits of each Page is determined by the following method: the number of error bits of each Frame in the current Page is read; the highest number of error bits in each Frame is taken as the number of error bits of the current Page. For example, in the current Page, the number of error bits of 16 Frames is read, in which the number of error bits of 52 Bit is the highest bit of all Frames, and thus the number of error bits is taken as the number of error bits of the current Page, that is, in the current Page, 52 Bit of error data will occur in each 1Kbyte of data.

[0071] Step S120: screening out unstable Pages according to the number of error bits.

[0072] It should be noted that due to the characteristics of the physical structure of the flash, the properties of the Pages with the same page offset in different Blocks are almost the same, which is due to the management architecture of WordLine in the flash. For example, there are totally 10 Blocks in the flash, each Block includes 10 Pages, if the number of error bits of the first Page of the 0th Block to the 6th Block is all beyond the ECC error correction performance, then these Pages are unstable Pages, due to the management architecture characteristics of WordLine, the first Page of the 7th Block to the 9th Block will also become extremely unstable, which is equivalent to the WordLine1 managing the first Page of the 10 Blocks, when the unstable Pages of this WordLine exceed a certain proportion, the Pages on this WordLine need to be determined as unstable Pages.

[0073] In addition, the Flash can be classified into SLC, MLC, TLC and QLC types according to the number of stored bits. For the SLC Flash, one WordLine corresponds to one page; for the MLC Flash, two pages, i.e., a pair (LowPage and Upper Page); for the TLC Flash, three pages (Lower Page, Upper Page and Extra Page); and for the QLC Flash, four pages (Lower Page, Upper Page, Extra Page and Top Page, which are called differently by different Flash manufacturers). The above pages are shared pages (Shared Page), and according to the data manual of the Flash, the shared pages have an obvious characteristic point, i.e., the shared pages are associated with each other. For example, when the TLC Flash is operated to write data, if the 0th-2nd pages in the current block are shared pages, when the 0th page (Low Page) is operated to write data, the 1st page (Upper Page) and the 2nd page (Extra Page) must be operated to write data at the same time.

[0074] In addition, for most types of Flash, the order of the shared pages in different blocks is fixed. Taking the TLC Flash as an example, assuming that each block has 9 pages, regardless of the 0th block, the 1st block or the 8th block, the order of the pages is Low Page, Upper Page and Extra Page, i.e., the 0th-2nd pages are Low Page, Upper Page and Extra Page; the 3rd-5th pages are Low Page, Upper Page and Extra Page; and the 6th-8th pages are Low Page, Upper Page and Extra Page.

[0075] Therefore, in the embodiment, the following method can be used to screen the unstable pages in the Flash: counting the pages in each block whose number of error bits exceeds the first preset threshold; and screening the unstable pages based on the result of the number of times of exceeding; wherein, if the Flash is a single-bit type, the unstable pages include the current page; and if the Flash is a multi-bit type, the unstable pages include the current page and the shared pages corresponding to the current page.

[0076] For example, assuming that there are 10 blocks in the current TLC type of Flash, and each block has 9 pages, after reading the error bit number of each page, the table 1 is obtained, wherein "0" represents that the error bit number of the page is greater than a first preset threshold (the first preset threshold is configured to 42 Bit / 1K in this case, and the first preset threshold can be flexibly set according to actual conditions, and is not specifically limited in this embodiment), that is, the page is an unstable page; "1" represents that the error bit number of the page is less than or equal to the first preset threshold. LP is the abbreviation of Low Page; UP is the abbreviation of Upper Page; and XP is the abbreviation of Extra Page. The row of table 1 represents the page number; and the column of table 1 represents the block number.

[0077]

[0078]

[0079] Table 1

[0080] According to table 1, the probability that the error bit number of the 0th page, the 1st page, the 2nd page, the 6th page and the 7th page is greater than the first preset threshold is all more than 50% (that is, the number of exceeding times is 5), so these pages are unstable pages. However, since the Flash is of the TLC type, the 0th-2nd pages are shared pages; the 3rd-5th pages are shared pages; and the 6th-8th pages are shared pages. When the 0th page, the 1st page, the 2nd page, the 6th page and the 7th page are screened out as unstable, the corresponding shared pages of the unstable pages also need to be screened out, that is, the 0th-2nd pages and the 6th-8th pages are all screened out.

[0081] It should be noted that the above case is an example of the TLC type of Flash, and for the SLC and QLC types of Flash, the principle can refer to the example of table 1. For the SLC type of Flash, since there is no distinction of shared pages, only the unstable pages need to be located, and the shared pages do not need to be located.

[0082] Step S130, adjusting the threshold voltage of the unstable page according to a preset adjustment method, so that the error bit number of the unstable page changes, and generating a re-reading voltage table according to the change result.

[0083] It should be noted that after the unstable pages are screened out, the threshold voltage of the unstable page is adjusted by using the preset adjustment method, so that the error bit number of the unstable page changes. According to the data sheet of each type of Flash, the threshold voltage value is related to the register value, that is, the register value can be configured to adjust the threshold voltage value, so as to change the error bit number of the page.

[0084] For example, for the TLC type of Flash, the total number of registers is 8, and the size of each register is 1 byte. As shown in Table 2, "Reg" is the abbreviation of register, the following number "x" represents the number of the register, and "-" represents the register value. Table 2 does not set the register value (but the register value is pre-set when the Flash is manufactured, and the embodiment is only described and thus not set).

[0085] Reg0 Reg1 Reg2 Reg3 Reg4 Reg5 Reg6 Reg7 - - - - - - - -

[0086] Table 2

[0087] As mentioned above, for the multi-bit type of Flash, there are shared pages in the Flash, and the shared pages are associated with each other in the architecture management of the Flash. When adjusting the threshold voltage of the unstable page, it is necessary to clearly determine which register values will affect which shared pages. In the case of Table 1, when adjusting the threshold voltage of the shared pages 0-2, the following method can be used: configuring the threshold voltage value of the register matched with the unstable page according to the preset adjustment step, and generating a re-reading voltage table, wherein the re-reading voltage table includes a plurality of re-reading voltage sequences, and each re-reading voltage sequence records the threshold voltage value of the register corresponding to the unstable page.

[0088] First, the value of the register Reg0 is adjusted to "0x0a", that is, increased by 10 mV, and the other registers Reg1-7 remain unchanged, that is, the initial value, and the number of error bits of the 0th page (Low Page) is read at this time to determine whether the number of error bits of the 0th page (Low Page) has changed. If so, it is determined that the register Reg0 will affect the number of error bits of the 0th page (Low Page). After the determination is completed, the register Reg1 is adjusted to "0x0a" (which can be set to other values), that is, increased by 10 mV, and the other registers Reg0, Reg2-7 remain unchanged, and the number of error bits of the 0th page (Low Page) is read at this time to determine whether the number of error bits of the 0th page (Low Page) has changed. If so, it is determined that the register Reg1 will affect the number of error bits of the 0th page (Low Page). The register value is adjusted in the above manner one by one until the matching relationship between the register and the unstable page is determined. It should be emphasized that if it is determined that the register has a matching relationship with the page of the LP type, the register will not have a matching relationship with other types (UP, XP, or TP).

[0089] Thus, the matching relationship between the registers and the unstable pages is confirmed, and it is confirmed that registers Reg0-1 have a matching relationship with the 0th page (Low Page), i.e., adjusting the value of the registers Reg0-1 (any one of the two registers) will affect the number of error bits of the 0th page (Low Page); registers Reg2-4 have a matching relationship with the 1st page (Upper Page), i.e., adjusting the value of the registers Reg2-4 (any one of the three registers) will affect the number of error bits of the 1st page (Upper Page); and registers Reg5-6 have a matching relationship with the 2nd page (Extra Page), i.e., adjusting the value of the registers Reg5-6 (any one of the two registers) will affect the number of error bits of the 2nd page (Extra Page).

[0090] It should be noted that for most Flash, the register Reg7 basically does not affect any type of page, and the default value is set to "0x00". If there is an impact, the traversal determination method described above can be used.

[0091] It should be further noted that for most types of Flash, the order of the different block shared pages is fixed. That is, after the matching relationship between the registers and the unstable pages is confirmed, the matching relationship between the registers and the unstable pages is applicable to all blocks. For example, the registers Reg0-1 affect the Low Page of the 1st block, and also affect the Low Page of the 2nd block; the registers Reg2-4 affect the Upper Page of the 1st block, and also affect the Upper Page of the 2nd block; and the registers Reg5-6 affect the Extra Page of the 1st block, and also affect the Extra Page of the 2nd block.

[0092] According to the preset adjustment step, the threshold voltage value of the register matched with the unstable page is configured, and a read voltage table is generated, wherein the read voltage table includes a plurality of read voltage sequences, and each read voltage sequence records the threshold voltage value of the register matched with the unstable page. According to the above case, Table 3 can be obtained.

[0093]

[0094]

[0095] Table 3

[0096] It should be noted that since LP is affected by registers Reg0~1, and each register is 1 byte in size, when two registers combine to affect LP, it is equivalent to 65536 (256*256) register values affecting the number of error bits of LP. However, the Flash has a service life and cannot be read repeatedly indefinitely, so a preset adjustment step is configured to adjust the register value matched by LP. In this embodiment, the preset adjustment step is configured as "0x04", and register Reg1 is calculated as the low bit and register Reg0 is calculated as the high bit.

[0097] In the first adjustment, register Reg1 is "0x04"; register Reg0 is "0x00";

[0098] In the second adjustment, register Reg1 is "0x08"; register Reg0 is "0x00";

[0099] In the third adjustment, register Reg1 is "0x0c"; register Reg0 is "0x00";

[0100] In the fourth adjustment, register Reg1 is "0x10"; register Reg0 is "0x00".

[0101] It should be particularly emphasized that the maximum value of a single register is "0xFF", and when the register exceeds this value, it will overflow and need to be carried forward. The carry value is related to the preset adjustment step. When carrying forward.

[0102] In the 65th adjustment, register Reg1 is "0x00"; register Reg0 is "0x04";

[0103] In the 66th adjustment, register Reg1 is "0x04"; register Reg0 is "0x04";

[0104] In the 67th adjustment, register Reg1 is "0x08"; register Reg0 is "0x04";

[0105] ...

[0106] This cycle continues until the 16384th adjustment, register Reg1 is "0xFF"; register Reg0 is "0xFF", completing the traversal and obtaining a complete read voltage table related to the number of error bits affecting LP. The read voltage table of Table 3 includes multiple read voltage sequences, and each read voltage sequence records the register value (i.e., the threshold voltage value) corresponding to the unstable page.

[0107] Similarly, corresponding read voltage tables can be generated for other matching relationships, such as Tables 4 and 5.

[0108]

[0109] Table 4

[0110] The read-voltage table generation principle of Table 4 can refer to Table 3, which will not be described here again. It needs to be particularly pointed out that, since the number of error bits of UP is affected by 3 register values, which is equivalent to 16777216 (256*256*256) register values affecting the number of error bits of LP, the preset adjustment step needs to be configured as large as possible, otherwise it will lead to too many read times.

[0111]

[0112] Table 5

[0113] The read-voltage table generation principle of Table 5 can refer to Table 3, which will not be described here again.

[0114] It also needs to be particularly emphasized that, according to a large amount of debugging experience in the prior art, for most Flash, the register value interval [0x96, 0xD0] is easy to cause Flash damage, therefore, when adjusting the register value according to the preset adjustment step, the interval [0x96, 0xD0] can be directly skipped.

[0115] After generating the read-voltage tables of Table 3, Table 4 and Table 5, Table 3, Table 4 and Table 5 can be combined, and the combination is to combine the read-voltage sequences of the same group sequence of different tables. For example, the read-voltage sequence groups of the first group in Table 3, the first group in Table 4 and the first group in Table 5 are combined; the read-voltage sequence groups of the second group in Table 3, the second group in Table 4 and the second group in Table 5 are combined; the read-voltage sequence groups of the third group in Table 3, the third group in Table 4 and the third group in Table 5 are combined, and so on, to obtain the complete read-voltage table of the Flash. However, the number of error bits corresponding to the read-voltage sequences of the same group sequence of different tables may be different, and in the embodiment, the following two ways are provided for selection;

[0116] 1) The mean value of the number of error bits is calculated. For example, when the read-voltage sequence groups of the first group in Table 3, the first group in Table 4 and the first group in Table 5 are combined, the number of error bits of the first group LP in Table 3 is 8, the number of error bits of the first group UP in Table 4 is 8, and the number of error bits of the first group XP in Table 5 is 12, and the number of error bits obtained after mean value calculation is about 9 (if the decimal point is greater than or equal to 0.5, it is incremented).

[0117] 2) Select the minimum number of error bits. For example, when the read voltage sequence combination of the 2nd group in Table 3, the 2nd group in Table 4 and the 2nd group in Table 5 are read, the number of error bits of the 2nd group LP in Table 3 is 8, the number of error bits of the 2nd group UP in Table 4 is 9, and the number of error bits of the 1st group XP in Table 5 is 15, then the minimum number of error bits is 8.

[0118] Step S140, store the read voltage table.

[0119] The complete read voltage table is obtained and stored. Since the read voltage table is generated for the unstable pages of the Flash, the number of error bits of the unstable pages can be reduced when the unstable pages are read using the read voltage, and therefore the same effect can be achieved on the stable pages of the Flash using the read voltage. In this embodiment, the unstable pages are pre-selected, and the threshold voltage of the unstable pages is adjusted. The adjustment of the threshold voltage changes the number of error bits of the unstable pages, and the read voltage table is generated according to the change result. Since the read voltage table records the threshold voltage of the unstable pages adjusted to stable pages, the data accuracy of the Flash can be maintained.

[0120] Figure 2 A flowchart of a data retention method in another embodiment of the application is shown.

[0121] Referring to Figure 2 A data retention method includes the following steps:

[0122] Step S210, perform scanning on the Flash to read the number of error bits of each page in the Flash.

[0123] This step is described in relation to step S110, and will not be repeated here.

[0124] Step S220, select the unstable pages according to the number of error bits.

[0125] This step is described in relation to step S120, and will not be repeated here.

[0126] Step S230, configure the threshold voltage value of the register one by one, and read the number of error bits of the adjusted unstable pages.

[0127] This step is described in relation to the part of "configure the threshold voltage value of the register" in step S130, and will not be repeated here.

[0128] Step S240, confirm the matching relationship between the register and the unstable pages according to the change result of the number of error bits.

[0129] The step S130 is described in the part of "the matching relationship between the register and the unstable page", and will not be repeated here.

[0130] The step S250 is described in the part of "generating the read voltage table", and will not be repeated here.

[0131] The step S130 is described in the part of "generating the read voltage table", and will not be repeated here.

[0132] The step S260 is described in the part of "generating the read voltage table", and will not be repeated here.

[0133] It should be noted that even if the read voltage table excludes the register value [0x96, 0xD0] which is easy to damage the flash read interval value, the read voltage sequence included in the read voltage table is still very large relative to the flash. As mentioned above, the flash cannot perform unlimited read without cost, and the number of read times is limited. The flash needs to read accurate data as much as possible within the minimum number of read times (again, accurate data does not mean that it needs to be the same as the original data, only the number of error bits of the read data is not more than the ECC error correction performance of the flash, and it is considered to be accurate data). Therefore, when the flash performs the read operation, the most appropriate read voltage must be selected as much as possible to perform the read operation.

[0134] The step S270 is described in the part of "generating the read voltage table", and will not be repeated here.

[0135] Each read voltage sequence corresponds to an error bit number, and only needs to sort the multiple read voltage sequences in the read voltage table according to the corresponding error bit number. For example, if the read voltage table includes 100 read voltage sequences, and each read voltage sequence corresponds to an error bit number, the read voltage sequence whose error bit number is less than or equal to the second preset threshold (for example, less than or equal to 20 bits, and the second preset threshold can be flexibly set according to the actual situation, and is not specifically limited) is selected as the target read voltage sequence, and these target read voltage sequences are combined to form the target read voltage table.

[0136] The step S280 is described in the part of "generating the read voltage table", and will not be repeated here.

[0137] It should be noted that, since the target re-reading voltage sequence can make the corresponding re-reading voltage thereof drop below the second preset threshold under the error bit number of the page, the target re-reading voltage sequence has better re-reading accuracy, and thus the target re-reading voltage table is stored in the Flash, and the storage control chip for controlling the Flash is used to read and call, so that the re-reading of the Flash is realized, and the accuracy of the data is maintained.

[0138] Corresponding to the foregoing method embodiments, the present application provides a data retention device and corresponding embodiments.

[0139] Figure 3 A structural schematic diagram of a data retention device in an embodiment of the present application is shown.

[0140] Referring to Figure 3 A data retention device 300 includes a scanning module 310, a screening module 320, an adjusting module 330, and a storage module 340.

[0141] The scanning module 310 is configured to perform scanning on the Flash and read the error bit number of each page in the Flash.

[0142] Further, in the embodiment, the scanning module 310 includes a reading unit 311 and a confirming unit 312. The reading unit 311 is configured to read the error bit number of each Frame in the current page. The confirming unit 312 is configured to take the highest error bit number in each Frame as the error bit number of the current page.

[0143] The screening module 320 is configured to screen out unstable pages according to the error bit number.

[0144] Further, in the embodiment, the screening module 320 includes a counting unit 321 and a locking unit 322. The counting unit 321 is configured to count the pages with error bit numbers exceeding the first preset threshold in each block. The locking unit 322 is configured to screen out unstable pages based on the result of the exceeding number. Wherein, if the Flash is a single-bit type, the unstable pages include the current page; if the Flash is a multi-bit type, the unstable pages include the current page and the shared page corresponding to the current page.

[0145] The adjusting module 330 is configured to adjust the threshold voltage of the unstable pages according to a preset adjustment method, so that the error bit number of the unstable pages changes, and a re-reading voltage table is generated according to the change result.

[0146] Further, in the embodiment, the adjusting module 330 comprises a voltage configuring unit 331, a matching unit 332 and a generating unit 333. The voltage configuring unit 331 is configured to configure the threshold voltage value of the register one by one, and read the error bit number of the unstable page after adjustment. The matching unit 332 is configured to confirm the matching relationship between the register and the unstable page according to the change result of the error bit number. The generating unit 333 is configured to configure the threshold voltage value of the register matched with the unstable page according to the preset adjustment step, and generate a re-reading voltage table, wherein the re-reading voltage table comprises a plurality of re-reading voltage sequences, and each re-reading voltage sequence records the threshold voltage value of the register corresponding to the unstable page.

[0147] The storage module 340 is configured to store the re-reading voltage table.

[0148] It should be noted that the data retention method implemented by the data retention device disclosed in the embodiment is the same as the above-mentioned embodiment, and therefore will not be described in detail here. Alternatively, each module in the embodiment and the above-mentioned other operations or functions are respectively used to implement the method in the foregoing embodiment.

[0149] Figure 4 A structural schematic diagram of a data retention device in another embodiment of the present application is shown.

[0150] Please refer to Figure 4 A data retention device comprises a scanning module 310, a screening module 320, an adjusting module 330 and a storage module 340. The functions of the scanning module 310, the screening module 320 and the adjusting module 330 are described in the foregoing embodiment, and therefore will not be described here. Figure 3 Here, no further description is given.

[0151] Further, in the embodiment, the scanning module 310 comprises a reading unit 311 and a confirming unit 312. The functions of the reading unit 311 and the confirming unit 312 are described in the foregoing embodiment, and therefore will not be described here. Figure 3 Here, no further description is given.

[0152] Further, in the embodiment, the screening module 320 comprises a statistical unit 321 and a locking unit 322. The functions of the statistical unit 321 and the locking unit 322 are described in the foregoing embodiment, and therefore will not be described here. Figure 3 Here, no further description is given.

[0153] Further, in the embodiment, the adjusting module 330 comprises a voltage configuring unit 331, a matching unit 332 and a generating unit 333. The functions of the voltage configuring unit 331, the matching unit 332 and the generating unit 333 are described in the foregoing embodiment, and therefore will not be described here. Figure 3 Here, no further description is given.

[0154] Still further, in the embodiment, the adjusting module 330 further comprises a target screening unit 334 and a sequence forming unit 335.

[0155] The target screening unit 334 is configured to screen the re-reading voltage sequence with the error bit number falling to the second preset threshold as a target re-reading voltage sequence.

[0156] The sequence forming unit 335 is configured to form the target re-reading voltage sequence into a target re-reading voltage table.

[0157] Further, in the embodiment, the storage module 340 is configured to store the target re-reading voltage table.

[0158] As shown in Figure 5 Fig. 5 is a structural schematic diagram of a storage control chip according to an embodiment of the present application.

[0159] Referring to Fig. 5, a storage control chip 500 includes the data retention device 300.

[0160] It should be noted that the storage control chip according to the embodiment can pre-screen unstable pages, adjust the threshold voltage of the unstable pages, change the error bit number of the unstable pages due to the threshold voltage adjustment, and generate a re-reading voltage table according to the change result. Since the re-reading voltage table records the threshold voltage of the unstable pages adjusted to stable pages, the data accuracy of the Flash can be maintained.

[0161] Referring to Figure 6 , another embodiment of the present application shows a computing electronic device 600 including a processor 610 and a memory 620.

[0162] The processor 610 can be a central processing unit (CPU), and can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.

[0163] The general-purpose processor can be a microprocessor or any conventional processor. The memory 610 can include various types of storage units, such as system memory, read-only memory (ROM) and permanent storage device.

[0164] The ROM can store static data and instructions that are needed by the processor 620 or other modules of the computer. The permanent storage device can be a read-only memory, a flash memory or a hard disk. In some embodiments, the permanent storage device can be a non-volatile memory, which can retain stored instructions and data even when the computer is powered off.

[0165] In some other embodiments, the permanent storage device can be a removable storage device (e.g., a floppy disk, a compact disk, etc.). The system memory can be a read-and-write memory device or a volatile read-and-write memory device, such as a dynamic random access memory. The system memory can store some or all of the instructions and data that the processor needs at runtime.

[0166] In addition, the memory 620 can include a combination of any or all of the above, including various types of semiconductor memory chips, such as DRAM, SRAM, SDRAM, flash, programmable read-only memory, magnetic disks and / or optical disks, etc.

[0167] In some embodiments, the memory 620 can include a removable storage device, such as a compact disk (CD), a read-only digital versatile disk (e.g., DVD-ROM, dual-layer DVD-ROM), a read-only Blu-ray disk, an ultra-density disk, a flash memory card (e.g., SD card, min SD card, and Micro-SD card, etc.), a magnetic floppy disk, etc. The computer readable storage media does not include carrier waves and transitory electronic signals propagating through a wire or cable, or wireless transmissions. The memory 620 stores executable code that, when executed by the processor 610, can cause the processor 610 to perform some or all of the steps described above.

[0168] In addition, the method according to the present application can also be implemented as a computer program or a computer program product, which includes computer program code instructions for performing some or all of the steps of the above-mentioned method according to the present application.

[0169] Alternatively, the present application can also be implemented as a computer readable storage medium (or non-transitory machine readable storage medium or machine readable storage medium) having stored thereon executable code (or computer program or computer instruction code), which, when executed by a processor of an electronic device (or a server, etc.), can cause the processor to perform some or all of the steps of the above-mentioned method according to the present application.

[0170] Having described various embodiments of the application, it is to be understood that the above description is meant not to limit and not to encompass all of the possible embodiments. Many modifications and variations of this application can be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. It is intended that the scope of the application be defined by the scope of the patent and by the claims as allowed by the patent office, which can include adaptations based on the description, equivalents, and / or substitutions of elements individually or collectively to the entire disclosure.

Claims

1. A data retention method, characterized by, The method comprises the following steps: performing scanning on the Flash, and reading error bit numbers of each page in the Flash; counting the pages in each block whose error bit numbers exceed a first preset threshold value; screening unstable pages based on the result of the exceeding times; wherein, if the Flash is a single-bit type, the unstable pages include the current page; if the Flash is a multi-bit type, the unstable pages include the current page and a shared page corresponding to the current page; configuring threshold voltage values of registers one by one, and reading the error bit numbers of the unstable pages after adjustment; confirming the matching relationship between the registers and the unstable pages according to the change result of the error bit numbers; configuring the threshold voltage values of the registers matched with the unstable pages according to a preset adjustment step, and generating a re-reading voltage table, wherein the re-reading voltage table includes a plurality of re-reading voltage sequences, and each re-reading voltage sequence records the threshold voltage values of the registers corresponding to the unstable pages; storing the re-reading voltage table.

2. The data retention method of claim 1, wherein, The reading of the error bit numbers of each page in the Flash comprises the following steps: reading error bit numbers of each Frame in the current page; taking the highest error bit number in each Frame as the error bit number of the current page.

3. The data retention method of claim 1, wherein, After the configuration of the threshold voltage values of the registers matched with the unstable pages according to the preset adjustment step and the generation of the re-reading voltage table, the method further comprises the following steps: screening a re-reading voltage sequence whose error bit number drops to a second preset threshold value as a target re-reading voltage sequence; forming a target re-reading voltage table by using the target re-reading voltage sequence; the storage of the re-reading voltage table comprises the following step: storing the target re-reading voltage table.

4. A data retention device, characterized by The method comprises the following steps: a scanning module for performing scanning on the Flash, and reading error bit numbers of each page in the Flash; a screening module for screening unstable pages according to the error bit numbers; an adjustment module for adjusting the threshold voltage of the unstable pages according to a preset adjustment method, so that the error bit numbers of the unstable pages change, and a re-reading voltage table is generated according to the change result; a storage module for storing the re-reading voltage table; the screening module comprises the following steps: a counting unit for counting the pages in each block whose error bit numbers exceed a first preset threshold value; a locking unit for screening unstable pages based on the result of the exceeding times; wherein, if the Flash is a single-bit type, the unstable pages include the current page; if the Flash is a multi-bit type, the unstable pages include the current page and a shared page corresponding to the current page; the adjustment module comprises the following steps: a voltage configuration unit for configuring threshold voltage values of registers one by one, and reading the error bit numbers of the unstable pages after adjustment; a matching unit for confirming the matching relationship between the registers and the unstable pages according to the change result of the error bit numbers; The generating unit is configured to generate a re-reading voltage table by configuring the threshold voltage value of the register matched with the unstable page according to a preset adjustment step, wherein the re-reading voltage table comprises a plurality of groups of re-reading voltage sequences, and each group of the re-reading voltage sequences records the threshold voltage value of the register corresponding to the unstable page.

5. The data retention device of claim 4, wherein, The scanning module comprises: The reading unit is configured to read the error bit number of each frame in the current page; The confirming unit is configured to take the highest error bit number in each frame as the error bit number of the current page.

6. The data retention device of claim 4, wherein, The adjusting module further comprises: The target screening unit is configured to screen a re-reading voltage sequence with the error bit number falling to a second preset threshold as a target re-reading voltage sequence; The sequence forming unit is configured to form a target re-reading voltage table from the target re-reading voltage sequence; The storage module for storing the re-reading voltage table comprises: The target re-reading voltage table is stored.

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