Semiconductor device and forming method thereof

Abstract

The invention discloses a semiconductor device and a forming method thereof. The forming method of the semiconductor device comprises the following steps: forming a first mask on a substrate; forming a plurality of first openings and second openings in the first mask; forming a first well in a first region of the substrate exposed by the plurality of first openings, and forming an alignment cloth plant in a second region of the substrate exposed by the second openings; forming an alignment mark by recessing the alignment cloth; and patterning the multilayer semiconductor lattice under the alignment of the alignment mark. The process is repeated for each layer of the integrated circuit device, and the precise alignment improves the accuracy of stacking the different layers together.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices and methods of forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous generation. During the IC evolution process, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be produced using a manufacturing process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. This scaling down also increases the complexity of processing and manufacturing ICs. Summary of the invention

[0003] In some embodiments of the present disclosure, a method for forming a semiconductor device includes the following steps: forming a first mask above a substrate; forming a plurality of first openings and a second opening in the first mask; forming a plurality of first wells in a plurality of first regions of the substrate exposed by the plurality of first openings, and forming an alignment plant in a second region of the substrate exposed by the second opening; recessing the alignment plant to form an alignment mark; and patterning a multilayer semiconductor lattice under the alignment of the alignment mark.

[0004] In some embodiments of the present disclosure, a semiconductor device includes: a substrate; a first well of a first doping type located in the substrate; an alignment mark located on the substrate, the alignment mark including the first doping type; a stack of multiple semiconductor nanostructures located above the first well; a source / drain region contacting the stack; and a gate structure surrounding the multiple semiconductor nanostructures.

[0005] In some embodiments of the present disclosure, a method for forming a semiconductor device includes the following steps: in the same implantation operation, forming a plurality of first wells in a plurality of first regions of a substrate, and forming an alignment implant in a second region of the substrate offset from the plurality of first regions; forming an alignment mark by recessing the alignment implant and simultaneously covering the plurality of first wells in a self-alignment process; and patterning a multilayer semiconductor lattice under the alignment of the alignment mark. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure can be best understood from the following detailed description in conjunction with the accompanying drawings. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for the sake of clarity of discussion, the size of various features may be arbitrarily increased or reduced.

[0007] Figures 1 to 9 is a diagrammatic cross-sectional side view of a portion of an IC device at various stages of fabrication according to an embodiment of the present disclosure;

[0008] Fig.10 is a flow chart of a method of forming an IC device according to various embodiments;

[0009] Fig.11 is a diagrammatic cross-sectional side view of a portion of an IC according to various embodiments.

[0010]

Explanation of symbols

[0011] 10: Installation

[0012] 21: First semiconductor layer

[0013] 22: The First Nanostructure

[0014] 23: Second semiconductor layer

[0015] 24: Second Nanostructure

[0016] 25: Multi-layer stacking

[0017] 26: Vertical Stacking

[0018] 27A: First opening

[0019] 27B: Second opening

[0020] 32: Fins

[0021] 57, 67: Opening

[0022] 110:Substrate

[0023] 112: Upper surface

[0024] 120: The First Curtain

[0025] 121: Bottom mask layer

[0026] 123: Intermediate cover layer

[0027] 125: Photosensitive layer

[0028] 130: First Opening

[0029] 131: Etching stop layer

[0030] 132: Second opening

[0031] 133: Interlayer dielectric

[0032] 270: First Well

[0033] 272: Second Well

[0034] 300: Second curtain

[0035] 472, 472A, 472B: Well alignment marks

[0036] 511, 521: bottom mask layer

[0037] 523: Second intermediate mask layer

[0038] 525: Photosensitive layer

[0039] 670: Second Well

[0040] 800: Area

[0041] 810: Layer

[0042] 811: Oxide layer

[0043] 812, 814: mask layer

[0044] 1000:Method

[0045] 1010, 1020, 1030, 1040, 1050, 1060: Action

[0046] BB, CC: line

[0047] D1~D4: Distance

[0048] L1~L3: Length

[0049] X: Direction

[0050] Y: direction

[0051] Z: Direction DETAILED DESCRIPTION

[0052] The following disclosure is used to implement many different embodiments or examples of different features of the subject matter. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are directly contacted, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the disclosure may repeat element symbols or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself specify the relationship between the various embodiments or configurations discussed.

[0053] Additionally, for ease of description, spatially relative terms, such as "below," "beneath," "below," "above," and "above," may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0054] Terms indicating relative degrees, such as "about", "substantially", etc., should be interpreted as what one of ordinary skill would do under the current technical specifications.

[0055] The terms "first", "second", "third", etc. may be used herein to describe a sequence of events or an order of elements, but may be interchanged or changed in certain contexts. For example, the second layer may be formed on the first layer (e.g., formed sequentially thereafter), but in certain contexts, the first layer may be referred to as the "second layer", "third layer", "fourth layer", etc., and the second layer may be referred to as the "first layer", "third layer", "fourth layer", etc.

[0056] The term "enclose" may be used herein to describe a structure that fully or partially encloses another element or structure, such as in three dimensions. For example, a first structure may "enclose" a second structure on four sides (e.g., left, right, front, and back) without enclosing the second structure on two perpendicular sides (e.g., top and bottom). In other examples, a first structure may partially surround a second structure, such as by surrounding three sides (e.g., top, front, and back) while leaving other sides (e.g., left, right, and bottom) exposed.

[0057] The present disclosure generally relates to semiconductor devices, and more specifically to field-effect transistors (FETs), such as planar FETs, three-dimensional fin FETs (FinFETs), or nanostructured FETs, such as nanosheet FETs (NSFETs), nanowire FETs (NWFETs), gate-all-around FETs (GAAFETs), and the like.

[0058] A semiconductor device may be formed by performing a series of operations. For example, a deposition or epitaxial growth operation may form a material layer on a wafer surface. A lithography operation may form a mask that protects certain areas and exposes other areas of the material layer according to a pattern. An etching operation may form an opening by removing some or all of the material of the material layer in the exposed area. Then, another deposition or epitaxial growth operation may be performed to form another material layer in the opening.

[0059] In the lithography exposure process, the material layers of the semiconductor device may be exposed to different patterns on the mask in different operations. The substrate or wafer may include many areas, each area being exposed using the same or different masks. To correctly stack the patterns at each exposure, alignment marks and overlay marks may be used in conjunction with other methods. Overlay margins may be built into the design to allow for small errors in alignment. For example, overlay margins ensure that even if errors occur during alignment, the resulting features do not overlap each other, which could result in defects in the final device. The impact of using overlay margins is cumulative, as alignment errors in different areas of the semiconductor substrate may be additive. As feature size decreases, the impact of the cumulative overlay margin may reduce the gain that smaller features gain from the total device area.

[0060] A zero mark, also known as a "reference mark" or "baseline mark," is an alignment mark used as a reference point during the alignment process. The zero mark serves as a fixed reference point whose position is precisely known relative to the coordinates of the wafer. The "zero mark" may refer to a mark formed in the base silicon wafer or its "zero layer." Wafers may be coated with various materials to create different layers of IC devices as described above. In lithography operations, a light-sensitive layer such as photoresist is applied to the surface of the wafer. The photoresist is then exposed to light through a mask that contains the pattern of the layer to be created. To accurately stack multiple layers, one or more alignment marks, which may include the zero mark, are present on the wafer. A sensor or camera in the lithography equipment may detect the alignment marks. The lithography equipment uses the zero mark as a reference point to precisely align the pattern on the mask relative to the existing features on the wafer. The equipment adjusts the position and orientation of the mask or wafer to ensure proper alignment. After alignment, the lithography process continues and the pattern on the mask is transferred to the photoresist on the wafer. Once the pattern is formed on the wafer by lithography, other steps such as etching or deposition are performed to etch or add selected materials, respectively, to create the features of the IC device. This process can be repeated for each layer of the IC device, and precise alignment improves the accuracy of stacking different layers together. By using the zero mark as a reference point, beneficial accuracy can be achieved in the IC manufacturing process, resulting in high-performance and reliable electronic devices.

[0061] In many IC devices, an operation shortly after forming the zero mark in the base silicon is to form an implanted well or well region, where an oxide diffusion or oxide definition (OD) region or active region of the device can be subsequently formed. Before forming the well, the wafer can be cleaned and prepared for further processing. Then, a layer of photoresist is coated on the surface of the wafer, and the photoresist is exposed under the alignment of the zero mark formed before applying the photoresist using a mask with the desired pattern. The pattern selects the location where the well will be formed. The wafer can then be exposed to high-energy ions of the selected dopant type via ion implantation. The ions penetrate the wafer surface and come to rest at a selected depth, thereby forming a well region. The type of dopant used may depend on the type of well to be formed (e.g., n-type or p-type). After ion implantation, the wafer can undergo an annealing process to activate the dopant atoms and repair any damage caused by the implantation. In many IC devices, the well regions are isolated from each other by shallow trench isolation (STI) or other isolation techniques. The use of a zero mark to align the lithographic exposure of the photoresist can be considered a form of "indirect alignment," which introduces errors in the positioning of the well region.

[0062] In an embodiment of the present disclosure, a "direct" or "self-aligned" method for aligning the patterning of implanted well regions improves the accuracy of locating well regions and locating subsequently formed OD regions. Self-aligned alignment marks or "p-well" (PWL) alignment marks are formed during the formation of a first well region (such as a p-well region). The self-aligned alignment marks can then be used during the formation of a second well region (such as an n-well region). The self-aligned alignment marks can then be used during OD patterning. "OD patterning" can refer to patterning that forms fins, and nanosheet channels can be located in these fins. Since the first and second well regions and subsequent fins are directly aligned via self-aligned alignment marks, rather than indirectly aligned via zero marks, the fins can be precisely positioned in the first and second well regions. This can help improve the reliability and performance of the device.

[0063] The nanostructured transistor structure can be patterned by any suitable method. For example, one or more lithography processes can be used to pattern the structure, including a double patterning process or a multiple patterning process. Typically, the double patterning process or the multiple patterning process can combine lithography with a self-aligned process, thereby allowing the creation of patterns having a pitch that is, for example, smaller than that obtained using a single direct lithography process. For example, in one embodiment, a sacrificial layer formed above a substrate is patterned using a lithography process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the nanostructure.

[0064] Figures 1 to 8are diagrammatic cross-sectional side views of an IC device at various stages of fabrication according to an embodiment of the present disclosure. Fig.10 A flow chart illustrating method 1000 of forming an IC device or a portion thereof from a workpiece according to one or more aspects of the present disclosure. Method 1000 is merely an example and is not intended to limit the present disclosure to that expressly described in method 1000. Additional actions may be provided before, during, and after method 1000, and some of the actions described may be replaced, eliminated, or moved for additional embodiments of the method. For simplicity, not all actions are described in detail herein. Method 1000 is described below in conjunction with fragmentary perspective views and / or cross-sectional views of a workpiece at different stages of manufacture according to an embodiment of method 1000, such as Figures 1 to 8 For the avoidance of doubt, in the drawings, the X direction is perpendicular to the Y direction, and the Z direction is perpendicular to the X direction and the Y direction. It should be noted that since the workpiece can be manufactured into a semiconductor device, the workpiece may be referred to as a semiconductor device depending on the context.

[0065] exist Figure 1 , a substrate 110 is provided. The substrate 110 may be a semiconductor substrate, such as a bulk semiconductor, and may be doped (e.g., with a p-type or n-type dopant) or undoped. The semiconductor material of the substrate 110 may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium arsenide, gallium indium phosphide, and / or indium gallium phosphide; or a combination thereof. Other substrates may be used, such as a single-layer substrate, a multi-layer substrate, or a gradient substrate.

[0066] A first mask 120 may be formed on the substrate 110, corresponding to Fig.10 The first mask 120 may include a bottom mask layer 121 located on the substrate 110 and in direct contact with the substrate 110 , one or more intermediate mask layers 123 located on the bottom mask layer 121 , and a photosensitive layer 125 located on the intermediate mask layer 123 .

[0067] The mask layer 121 is formed on the upper surface 112 of the substrate 110. The bottom mask layer 121 may be a spin-on carbon (SOC) layer 121. Spin-on carbon materials are used as anti-reflective layers to flatten uneven morphologies, or as the bottom layer of a three-layer photoresist in a semiconductor manufacturing method. In some embodiments, the SOC material is coated on the substrate and then subjected to a cross-linking operation between a polymer and a cross-linking agent. The cross-linking operation may be a thermal cross-linking operation. The SOC layer is heated to initiate the thermal cross-linking operation. In some embodiments, the SOC layer 121 is deposited as a liquid mixture and the substrate 110 is rotated while the SOC layer is deposited above the substrate 110. In some embodiments, the SOC layer 121 includes a SOC composition including a carbon backbone polymer, a first cross-linking agent, and a second cross-linking agent. In some embodiments, the spin-on carbon composition includes a solvent. In some embodiments, the solvent is selected so that the polymer and the cross-linking agent can be uniformly dissolved in the solvent and distributed onto the substrate.

[0068] In some embodiments, the non-connected SOC layer is formed to have a thickness ranging from about 200 nm to about 2,000 nm. In some embodiments, the non-connected SOC layer has a thickness ranging from about 400 nm to about 1,500 nm, and in other embodiments, the non-connected SOC layer has a thickness ranging from about 500 nm to about 1,200 nm, depending on the underlying structure (topology), design requirements, and / or process requirements.

[0069] The SOC layer 121 may be first heated at a temperature range of about 100°C to about 170°C to form a partially cross-linked SOC layer. In some embodiments, the temperature range of the first heating is about 100°C to about 150°C. After the first heating, the partially cross-linked SOC layer may be allowed to cool. The partially cross-linked SOC layer is then subsequently subjected to a second heating at a second temperature higher than the first temperature to form a further or fully cross-linked SOC layer, which may be the SOC layer 121. In some embodiments, the second temperature range is about 170°C to about 300°C.

[0070] After forming the SOC layer 121, one or more intermediate mask layers 123 are formed. The intermediate layer 123 of the three-layer photoresist structure 120 may have a composition that provides anti-reflective properties and / or hard mask properties for lithography operations. In some embodiments, the intermediate layer 123 includes a silicon-containing layer (e.g., a silicon hard mask material). In some embodiments, the intermediate layer 123 is a silicon-containing anti-reflective coating (SiARC). The intermediate layer 123 may include a silicon-containing inorganic polymer. In other embodiments, the intermediate layer 123 includes a siloxane polymer. In other embodiments, the intermediate layer 123 includes silicon oxide (e.g., spin-on glass (SOG)), silicon nitride, silicon oxynitride, polysilicon, metal-containing organic polymer materials, containing metals such as titanium, titanium nitride, aluminum and / or tantalum, and / or other suitable materials. The intermediate layer 123 may be bonded to adjacent layers, such as by covalent bonding, hydrogen bonding, or hydrophilic-hydrophilic forces.

[0071] The photoresist layer 125 is a photosensitive layer patterned by exposure to actinic radiation and development. Typically, the chemical properties of the photoresist area hit by the incident radiation will change, depending on the type of photoresist used. Whether the photoresist is positive or negative tone may depend on the type of developer used to develop the photoresist. For example, when the developer is a water-based developer (such as, tetramethylammonium hydroxide (TMAH) solution), some positive tone photoresists provide positive patterns (that is, the exposed areas are removed by the developer). On the other hand, when the developer is an organic solvent, the same photoresist provides a negative pattern (that is, the unexposed areas are removed by the developer). In addition, in some negative tone photoresists developed with TMAH solution, the unexposed areas of the photoresist are removed by TMAH, and the exposed areas of the photoresist that are cross-linked when exposed to actinic radiation remain on the substrate after development.

[0072] Figure 1The structure is then processed to form a first opening 130 and a second opening 132. Forming the openings may include developing the photoresist layer 125 according to the pattern of the mask. For example, a portion of the photoresist layer 125 is selectively exposed to actinic radiation. In some embodiments, the mask is used to form an exposed portion and an unexposed portion of the photoresist layer 125. In some embodiments, the radiation exposure is performed by placing the photoresist-coated substrate in a lithography tool. The lithography tool includes a mask, an optical device, an exposure radiation source that provides exposure radiation, and a movable stage for supporting and moving the substrate under the exposure radiation. In some embodiments, the photoresist layer 125 is selectively exposed using deep ultraviolet (DUV) lithography to form exposed areas and unexposed areas. For example, the selective exposure can be performed by an ArF excimer laser with a wavelength of about 193nm. Subsequently, a solvent is used to develop to form openings in the photoresist layers 130, 132.

[0073] exist Figure 2 In the embodiment, after forming the first opening 130 and the second opening 132 in the photoresist 125, the first opening 27A and the second opening 27B are formed by etching the intermediate layer 123 and the bottom layer 121, and the patterned photoresist 125 is used as an etching mask to etch the intermediate layer 123 and the bottom layer 121 to extend the openings 130 and 132, corresponding to Fig.10 The middle layer 123 and the bottom layer 121 may be etched by wet or dry etching. In some embodiments, the openings 27A and 27B expose the substrate 110. The remaining portion of the photoresist 125 may then be removed by one or more stripping or etching operations, such as Figure 2 As displayed.

[0074] Further in Figure 2 In the embodiment, the first well 270 and the second well 272 are formed by the first opening 27A and the second opening 27B, respectively, corresponding to Fig.10 The first well 270 may be a well for forming active regions (e.g., fins, channels, and source / drains), and the second well 272 may be a well for use as an alignment mark in subsequent processes, such as forming fins from a multi-layer semiconductor lattice. The first well 270 may be referred to as an active well 270, and the second well 272 may be referred to as an alignment well 272.

[0075] The first well 270 and the second well 272 may be formed by an implantation process, such as an ion implantation process, or "IMP". Ion implantation forms a region (in a device or structure) doped with selected ions to change the chemical, physical and / or electrical properties of the region. In an IMP process, accelerated ions are struck against a region of a substrate so that these ions may be implanted as dopants into the substrate at selected locations to selected depths. These dopants may impart selected properties to a device or structure, which may be beneficial for a variety of applications.

[0076] The ion beam may be generated by an ion source or accelerator (not shown) and contains high energy accelerated ions (e.g., primary ions) for bombarding a target on a target surface. For example, the target may be an exposed area of ​​a substrate 110, and the target surface may be an upper surface 112 of the exposed area. The target may represent any suitable solid material (e.g., undoped silicon of a wafer) and include a plurality of atoms. The ions of the ion beam may move among the atoms of the target after implanting the target. For example, some ions may collide with atoms, other ions may be ejected after colliding with atoms, but other ions may be implanted in atoms, while further ions may be guiding ions that penetrate the target atoms. The ion beam may strike the target surface from various directions, and ions (e.g., primary ions) may be implanted or ejected, depending on the tilt angle of the ion beam. The ion beam may be incident on the target surface (e.g., surface 112) at a tilt angle of about 0 degrees to about 15 degrees. The ejected ions may be referred to as "secondary ions."

[0077] In some embodiments, the first well 270 and the second well 272 are p-type wells or "p-wells" doped with dopant ions suitable for forming a p-type doped semiconductor. For example, the dopant ions may be ions of boron, aluminum, gallium, etc. The dimensions (e.g., width, length, and depth) of the first well 270 and the second well 272 may be approximately the same or different. For example, the width of the second well 272 in the X-axis direction may exceed the width of each first well 270. The first well 270 and the second well 272 may have the same depth because they are formed in the same implantation operation. That is, the energy of the ion beam that implants the dopant ions into the first well 270 and the second well 272 is the same, so the depth of each well may be approximately the same. The dopant type and concentration of the first well 270 and the second well 272 are also substantially the same because they are formed in the same implantation operation. The first well 270 and the second well 272 may have similar profiles due to similar tilt angle characteristics. In some embodiments, such as Figure 2 As shown, the first well 270 and the second well 272 may each extend below the bottom mask layer 121 along the X-axis direction.

[0078] exist Figure 3 and Figure 4 In the embodiment, after the first well 270 and the second well 272 are formed, a well alignment mark (or "plant alignment mark") 472 is formed by removing a portion (or "recess") to align with the well 272, corresponding to Fig.10 Action 1040. A second mask 300 may be formed covering the active well 270 and exposing the alignment well 272, as shown. The second mask 300 may be a photosensitive layer or multiple layers, and may be similar to the reference Figure 1The second mask 300 may be a "globby" mask that substantially covers the entire wafer except for the alignment well or wells 272. For example, the second mask 300 may fill the opening 27A, leaving the opening 27B exposed. It should be understood that the well alignment mark 472 is formed using the same bottom mask layer 121 used to form the first well 270, so that the well alignment mark 472 is self-aligned with the first well 270. That is, the bottom mask layer 121 is not removed by ashing before forming the well alignment mark 472, but serves as a hard mask for forming the well alignment mark 472.

[0079] In some embodiments, the patterning of the second mask 300 may be performed by exposure using a low frequency wavelength used to pattern the first mask 120. For example, the first mask 120 may be patterned using an ArF excimer laser having a first deep ultraviolet (DUV) wavelength of about 193 nm, and the second mask 300 may be patterned using a KrF excimer laser having a second DUV wavelength of about 248 nm. In another example, the first mask 120 may be patterned by EUV light (e.g., about 13.5 nm), and the second mask 300 may be patterned by deep ultraviolet (DUV) light (e.g., about 248 nm). This is different from the zero mark, which is patterned using an ArF excimer laser having a first DUV wavelength of about 193 nm. That is, the operation of recessing the alignment well 272 to form the well alignment mark 472 may be simpler than the operation of recessing the substrate to form the zero mark.

[0080] Figure 4 Depicts recessing the alignment well 272 through the opening 27B to form a well alignment mark 472. In some embodiments, the opening 27B extends partially into the alignment well 272 by an appropriate etching operation. For example, etching the p-well may use a selective process with KOH as an etchant that preferentially etches p-type silicon while leaving other areas (such as n-type silicon or undoped silicon of the substrate 110 and the material of the bottom mask layer 121) relatively unaffected. The process may be performed at an elevated temperature to increase the etching rate and maintain control over the etching parameters. The etching process may be anisotropic. Selected etching conditions, such as temperature, concentration, and etching time, may be selected to achieve a selected etching depth and sidewall profile. The choice of etchant may vary. Other etchants, such as tetramethylammonium hydroxide (TMAH), may also be used to etch into p-type wells, such as the alignment well 272.

[0081] The well alignment mark 472 may extend to a first depth D1 of the substrate 110. The first depth D1 may be measured from the upper surface 112 of the substrate 110 to the lowest level of the well alignment mark 472. The recess in the well alignment mark 472 may extend to a second depth D2 that is shallower than the first depth D1. That is, the recess does not extend through the well alignment mark 472, but stops at the lowest level of the well alignment mark 472. In some embodiments, the ratio of the second depth D2 to the first depth D1 is in the range of about 0.1 to about 0.9. In some embodiments, the ratio of the second depth D2 to the first depth D1 is in the range of about 0.5 to about 0.8.

[0082] exist FIG. 5A to FIG. 5C , after the well alignment mark 472 is recessed, the bottom mask layer 121 may be removed and another bottom mask layer 521 may be formed to fill and cover the opening 27B on the well alignment mark 472. In some embodiments, the bottom mask layer 521 is formed by backfilling the opening 27B instead of replacing the entire bottom mask layer 121. After the bottom mask layer 521 is formed, a second intermediate mask layer 523 is formed on the bottom mask layer 521. Then, a photosensitive layer 525 or a photoresist layer 525 is formed on the second intermediate mask layer 523. The formation and composition of the bottom mask layer 521, the second intermediate mask layer 523, and the photosensitive layer 525 may be the same as in reference 1. Figure 1 The formation and composition of the bottom mask layer 121 , the middle mask layer 123 , and the photosensitive layer 125 are similar or identical.

[0083] The photosensitive layer 525 may be patterned to form an opening 57 through which an n-type well or n-well will be formed in a subsequent operation. The patterned photosensitive layer 525 may be similar to the Figure 1 The opening 57 overlaps the area between the first wells 270 along the X-axis direction, as shown. In some embodiments, the edge of the opening 57 may partially overlap the edge of the first well 270. The opening 57 may be formed by patterning using DUV light generated by an ArF excimer laser having a wavelength of about 193 nm. The opening 57 is formed using a well alignment mark 472 for alignment. This facilitates obtaining precise alignment relative to the first well 270.

[0084] Figure 5B and Figure 5C For along Figure 5A A diagrammatic cross-sectional view of section line BB. Figure 5B In the embodiment, the first wells 270 are spaced apart from each other by a distance D3, and the well alignment mark 472 is spaced apart from the first well 270 by a distance D4. In some embodiments, the distance D4 exceeds the distance D3. The length of the first well 270 in the Y-axis direction is L1, and the length of the well alignment mark 472 in the Y-axis direction is L2. In some embodiments, the first wells 270 have different lengths from each other. In some embodiments, the first wells 270 have different lengths from each other. Figure 5B . For example, the first well 270 may be L-shaped or C-shaped rather than linear. In some embodiments, the length L1 is substantially the same as the length L2. In some embodiments, the length L1 is different from the length L2. For example, the length L1 may exceed the length L2. That is, the first well 270 may be an elongated feature, while the well alignment mark 472 is not elongated (e.g., may be square or round).

[0085] The well alignment mark 472 laterally surrounds the bottom mask layer 511 in the groove. That is, the bottom mask layer 511 is located in the groove of the well alignment mark 472, and the well alignment mark 472 has a wall that surrounds the groove in the XY plane. In some embodiments, the area ratio of the groove to the total area of ​​the well alignment mark 472 is in the range of about 20% to about 90%. Above about 90%, the risk of breaking through the surrounding area of ​​the well alignment mark 472 around the groove may increase, which may reduce the optical recognizability of the well alignment mark 472 during lithography operations. Below about 20%, the well alignment mark 472 may not be clear or distinguishable enough as a basis for alignment during lithography operations.

[0086] Figure 5C Depicted are two well alignment marks 472A, 472B adjacent to the first well 270. The first well alignment mark 472A has a length L2 in the Y-axis direction, and the second well alignment mark 472B has a length L3 in the Y-axis direction. The lengths L2, L3 are shorter than the length L1 of the first well 270. In some embodiments, the lengths L2, L3 are substantially the same. In some embodiments, the lengths L2, L3 are different. That is, one of the well alignment marks 472A, 472B may be elongated, while the other is shorter in the Y-axis direction. Typically, the well alignment marks 472A, 472B may be fully aligned with each other along the Y-axis direction. However, in some embodiments, the well alignment marks 472A, 472B may be partially aligned with each other, such that one of the well alignment marks 472A, 472B is closer to the first well 270 than the other.

[0087] exist Figure 6 In the embodiment of the present invention, the opening 57 is extended to form an opening 67 that exposes the upper surface 112 of the substrate 110. Then, a second well 670 is formed in the region between and / or adjacent to the first wells 270. The formation of the second well 670 is similar to the reference well 270 in most cases. Figure 2The formation of the first well 270 described above. Instead of a p-type dopant, the second well 670 may be formed by ion implantation of n-type dopant ions, such as phosphorus, arsenic, antimony, etc. In some embodiments, the second well 670 has an edge region merged with an edge region of the first well 270. The second well 670 may be formed to the same or different depth as the first well 270. The second well 670 may be narrower than the first well 270 in the X-axis direction. In some embodiments, the formation of the second well 670 is omitted and the second well 670 does not exist.

[0088] Forming the second well 670 under the alignment of the well alignment mark 472 facilitates improving the alignment accuracy of the second well 670 to the first well 270. Compared to zero mark alignment, the alignment accuracy is improved by up to 40%.

[0089] Figures 7 to 9 To illustrate a cross-sectional side view, the formation of the active region or OD (or fin 32 and stack 26) is depicted via alignment well alignment marks 472. Figure 7 , well alignment mark 472 is located at Figure 8 Prior to forming the OD, a number of operations may be performed, as described below to provide context.

[0090] See also Figure 8 , forming a multilayer stack 25 or "lattice" above the substrate 110 of alternating layers of first semiconductor layers 21 and second semiconductor layers 23, corresponding to Fig.10 Action 1060. Figure 8 , but other numbers of layers 21 (e.g., 2, 4, or more) may be formed. In some embodiments, the first semiconductor layer 21 may be formed of a first semiconductor material suitable for n-type nanoFETs, such as silicon, silicon carbide, etc., and the second semiconductor layer 23 may be formed of a second semiconductor material suitable for p-type nanoFETs, such as silicon germanium, etc. Each layer 21, 23 of the multilayer stack 25 may be epitaxially grown using methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), etc.

[0091] Due to the high etching selectivity between the first semiconductor material and the second semiconductor material, the second semiconductor layer 23 of the second semiconductor material can be removed without significantly removing the first semiconductor layer 21 of the first semiconductor material, thereby allowing the first semiconductor layer 21 to be patterned to form the channel region of the nanoFET. In some embodiments, the first semiconductor layer 21 is removed and the second semiconductor layer 23 is patterned to form the channel region. The high etching selectivity allows the first semiconductor layer 21 of the first semiconductor material to be removed without significantly removing the second semiconductor layer 23 of the second semiconductor material, thereby allowing the second semiconductor layer 23 to be patterned to form the channel region of the nanoFET.

[0092] exist Figure 8 In the embodiment of the present invention, before forming the lattice 25, a layer 810 may be formed to (partially or completely) fill the recess of the well alignment mark 472. In some embodiments, the layer 810 may be undoped silicon. The layer 810 may have an upper surface that inherits the contour of the recess. That is, the upper surface of the layer 810 may be tilted downward and have a lower height above the recess and a higher height on both sides of the recess.

[0093] After forming the layer 810 , the lattice 25 may be formed by alternately growing the second semiconductor layer 23 and the first semiconductor layer 21 as described above.

[0094] exist Fig. 9 In the embodiment of the present invention, the fin 32 is formed in the layer 810 and the optional substrate 110, and the nanostructures 22, 24 are formed in the multilayer stack 25 to form a vertical stack 26 of the channel 22. In some embodiments, the nanostructures 22, 24 and the fin 32 can be formed by etching grooves in the multilayer stack 25, the layer 810 and the optional substrate 110. The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc. or a combination thereof. The etching can be anisotropic. For example, a third mask including an oxide layer 811 and one or more hard mask layers or other suitable mask layers 812, 814 can be formed on the multilayer stack 25. The mask layers 812, 814 and the oxide layer 811 may be patterned so that the area of ​​the multilayer stack 25 for forming the active region or OD is covered by the mask layers 812, 814 and the oxide layer 811, and other areas outside the active region or OD are exposed by the mask layers 812, 814 and the oxide layer 811. Then, etching may be performed to recess other areas to form the vertical stack 26 of the fins 32 and nanostructures 22, 24, and the resulting structure is as shown. Fig. 9 Depicted.

[0095] The first nanostructure 22 (hereinafter also referred to as "channel 22") is formed by the first semiconductor layer 21, and the second nanostructure 24 is formed by the second semiconductor layer 23. The distance between adjacent fins 32 and the nanostructures 22 and 24 may be about 18 nm to about 100 nm. Fig. 9 As illustrated, a single fin 32 including both sides of the well alignment mark 472 is included to facilitate simplicity of illustration.

[0096] The use of well alignment marks 472 to align the formation of fins 32 facilitates improved alignment accuracy during lithography operations that expose areas outside of fins 32 for removal in the anisotropic etching process described above.

[0097] Fig.11 A portion of the IC device 10 is provided along Fig. 9 . A diagrammatic cross-sectional side view of line CC depicted in FIG. After forming the fins 32, further processing may be performed to form active devices 20A, 20B of the IC device 10. For example, shallow trench isolation (STI) may be formed between adjacent fins 32. A sacrificial gate may be formed across the fins 32, and the area of ​​the fins 32 exposed by the sacrificial gate may be recessed to form a nanosheet channel 22 of a single transistor 20A, 20B. The source / drain region 82 may be epitaxially grown between adjacent stacks 26 of the nanosheet channel 22. The sacrificial gate may be replaced by an active gate 200. The active gate 200 or gate structure 200 may surround the nanosheet channel 22. Contacts may then be formed to provide electrical connections to the source / drain regions and the active gate. The source / drain contacts may be formed by an interlayer dielectric (ILD) 133 and an etch stop layer 131. The source / drain contacts may be separated from the active gate 200 by sidewall spacers 41. The source / drain regions 82 may be separated from the active gate 200 by internal spacers 74 present between the nanosheet channels 22. Further interconnect structures including metal layers embedded in an interlayer dielectric (ILD) may be established over the contacts to provide electrical interconnection between devices (e.g., transistors, capacitors, etc.) of the IC device 10.

[0098] Embodiments may provide advantages. By forming the well alignment mark 472 in the same process as the first well 270 , the alignment between the first well 270 and the second well 670 and between the first well 270 and the fin 32 is improved.

[0099] According to at least one embodiment, a method includes the following steps: forming a first mask on a substrate; forming a first opening and a second opening in the first mask; forming a first well in a first region of the substrate exposed by the first opening, and forming an alignment plant in a second region of the substrate exposed by the second opening; forming an alignment mark by recessing the alignment plant; and patterning a multilayer semiconductor lattice under the alignment of the alignment mark. In some embodiments of the present disclosure, the method further includes: forming a second mask above a substrate; forming a plurality of third openings in the second mask; and forming a plurality of second wells in a plurality of third regions of the substrate exposed by the plurality of third openings, the type of the plurality of second wells being different from the type of the plurality of first wells. In some embodiments of the present disclosure, the step of forming the plurality of first wells includes: forming a plurality of P-type wells. In some embodiments of the present disclosure, the step of forming the second mask includes: forming a first mask layer above the substrate, the first mask layer extending into a groove above the alignment mark; and forming a second mask layer above the first mask layer. In some embodiments of the present disclosure, the method further includes: depositing a semiconductor material layer in a third opening above the alignment mark; and forming the multilayer semiconductor lattice by alternately depositing a plurality of first semiconductor layers and a plurality of second semiconductor layers on the semiconductor material layer and the substrate. In some embodiments of the present disclosure, the step of recessing the alignment plant is partially etching the alignment plant without penetrating the alignment plant. In some embodiments of the present disclosure, the step of recessing the alignment plant is partially etching the alignment plant so that a plurality of vertical sidewalls of the alignment plant remain in the alignment mark.

[0100] According to at least one embodiment, a device includes: a substrate; a first well of a first doping type located in the substrate; an alignment mark located on the substrate, the alignment mark including the first doping type; a semiconductor nanostructure stack located above the first well; a source / drain region in contact with the stack; and a gate structure surrounding the semiconductor nanostructure. In some embodiments of the present disclosure, the alignment mark extends to the same depth in the substrate as the first well. In some embodiments of the present disclosure, the first well and the alignment mark include a plurality of P-type dopants. In some embodiments of the present disclosure, a semiconductor layer is located on the alignment mark, the semiconductor layer contacts a plurality of vertical sidewalls of the alignment mark and extends to a level coplanar with a plurality of upper surfaces of the plurality of vertical sidewalls. In some embodiments of the present disclosure, the device further includes an opening located in the alignment mark, the opening extending to a depth shallower than a lower surface of the alignment mark. In some embodiments of the present disclosure, the device further includes a second well adjacent to the first well, the doping type of the second well being different from the doping type of the first well.

[0101] According to at least one embodiment, the method includes the following steps: forming a first well in a first region of a substrate and forming an alignment implant in a second region of the substrate offset from the first region in the same implantation operation; forming an alignment mark by recessing the alignment implant while covering the first well in a self-aligned process; and patterning the multilayer semiconductor lattice under the alignment of the alignment mark. In some embodiments of the present disclosure, the method further includes: forming a bottom mask layer on the substrate; forming an intermediate mask layer on the bottom mask layer; and forming a photosensitive layer on the intermediate mask layer; wherein the steps of forming the alignment implant and recessing the alignment implant are performed through the same opening in the bottom mask layer. In some embodiments of the present disclosure, the method further includes: removing the bottom mask layer; forming a second bottom mask layer, the second bottom mask layer covering the alignment mark; and forming a plurality of second wells of a different dopant type than the plurality of first wells, the step of forming the plurality of second wells being by passing through a plurality of openings in the second bottom mask layer. In some embodiments of the present disclosure, the method further includes: after the step of forming a pair of alignment plants: forming a second photosensitive layer covering the plurality of first wells and exposing the same opening recessed with the alignment plants. In some embodiments of the present disclosure, the step of forming the plurality of first wells includes: forming the plurality of first wells whose width in a first direction does not exceed the width of the alignment plants in the first direction. In some embodiments of the present disclosure, the step of forming the alignment plants includes: forming the alignment plants whose length in a second direction does not exceed the length of the plurality of first wells in the second direction, the second direction being transverse to the first direction. In some embodiments of the present disclosure, the method further includes: during the step of forming the plurality of first wells, forming a plurality of alignment plants, the plurality of alignment plants being arranged along the second direction, and a total length of the plurality of alignment plants not exceeding the length of the plurality of first wells.

[0102] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that the present disclosure can be easily used by those skilled in the art as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and these equivalent constructions can be variously changed, substituted, and altered without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming a semiconductor device, characterized in that: The following steps are involved: forming a first mask above a substrate; forming a plurality of first openings and a second opening in the first mask; forming a plurality of first wells in a plurality of first regions of the substrate exposed by the plurality of first openings, and forming an alignment plant in a second region of the substrate exposed by the second opening; Depressing the alignment fabric to form an alignment mark; and A multi-layer semiconductor lattice is patterned under the alignment of the alignment mark.

2. The method according to claim 1, characterized in that Further comprising the following steps: forming a second mask above a substrate; forming a plurality of third openings in the second mask; and A plurality of second wells are formed in a plurality of third regions of the substrate exposed by the plurality of third openings, and a type of the plurality of second wells is different from a type of the plurality of first wells.

3. The method according to claim 2, characterized in that The step of forming the plurality of first wells includes the following steps: forming a plurality of P-type wells.

4. The method according to claim 2, characterized in that The step of forming the second mask comprises the following steps: forming a first mask layer above the substrate, wherein the first mask layer extends into a groove above the alignment mark; and A second mask layer is formed above the first mask layer.

5. The method according to claim 1, characterized in that Further comprising the following steps: depositing a semiconductor material layer in a third opening above the alignment mark; and The multi-layer semiconductor lattice is formed by alternately depositing a plurality of first semiconductor layers and a plurality of second semiconductor layers on the semiconductor material layer and the substrate.

6. The method according to claim 1, characterized in that The step of recessing the alignment fabric is to partially etch the alignment fabric without penetrating the alignment fabric.

7. The method according to claim 1, characterized in that The step of recessing the alignment plant is to partially etch the alignment plant so that multiple vertical sidewalls of the alignment plant remain in the alignment mark.

8. A semiconductor device, characterized in that: Include: a substrate; A first well of a first doping type is located in the substrate; an alignment mark located on the substrate, the alignment mark comprising the first doping type; a stack of multiple semiconductor nanostructures located above the first well; a source / drain region contacting the stack; and A gate structure surrounds the plurality of semiconductor nanostructures.

9. The device according to claim 8, characterized in that The alignment mark extends in the substrate to the same depth as the first well.

10. A method for forming a semiconductor device, characterized in that: The following steps are involved: In a same implantation operation, a plurality of first wells are formed in a plurality of first regions of a substrate, and an alignment implant is formed in a second region of the substrate offset from the plurality of first regions; forming an alignment mark by recessing the alignment pattern while covering the plurality of first wells in a self-alignment process; and A multi-layer semiconductor lattice is patterned under the alignment of the alignment mark.

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