Semiconductor device process method

Abstract

The invention relates to the technical field of semiconductors, and discloses a semiconductor device process method, which comprises the steps of providing a semiconductor substrate in a process cavity, and forming a target through hole or a target groove and a barrier layer covering the target through hole or the target groove on the semiconductor substrate; depositing and forming a tungsten nucleating layer on the barrier layer; depositing a first metal tungsten layer on the tungsten nucleating layer, wherein the first metal tungsten layer covers the surface of the semiconductor substrate and the side wall of the target through hole or the target groove; etching to remove the convex-angle blocking part, and forming the convex-angle blocking part as a part of the first metal tungsten layer at the joint of the surface of the semiconductor substrate and the side wall of the target through hole or the target groove so as to prevent the target through hole or the target groove from being sealed in advance; and depositing a second metal tungsten layer on the semiconductor substrate, wherein the second metal tungsten layer is connected to the first metal tungsten layer and seamlessly fills the target through hole or the target groove. According to the invention, the electrical property and the product yield of the semiconductor device are ensured.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device process method. Background Art

[0002] In the semiconductor manufacturing process, metal tungsten is widely used in the metallization process of integrated circuit through holes and interconnect layers due to its excellent anti-electromigration performance and excellent conformality during tungsten chemical vapor deposition. With the continuous miniaturization of integrated circuit size and the increase in the aspect ratio of through holes and trenches, traditional tungsten chemical vapor deposition will produce obvious gaps during tungsten deposition, especially when facing "convex corner" morphology, which will seriously affect the electrical properties of the device and the yield of the product. Summary of the invention

[0003] In view of this, the present application provides a semiconductor device process method to solve the above-mentioned technical problems.

[0004] To achieve the above objectives, according to the first aspect, the technical solution adopted is: A semiconductor device process method, comprising: Providing a semiconductor substrate in a process chamber, wherein a target through hole or a target trench is formed on the semiconductor substrate, and a barrier layer covering the target through hole or the target trench; Depositing a tungsten nucleation layer on the barrier layer; Depositing a first metal tungsten layer on the tungsten nucleation layer, wherein the first metal tungsten layer covers the surface of the semiconductor substrate and the sidewalls of the target through hole or the target trench; Etching and removing the convex corner blocking portion, the convex corner blocking portion being a portion of the first metal tungsten layer formed at the connection between the surface of the semiconductor substrate and the sidewall of the target through hole or the target trench; A second metal tungsten layer is deposited on the semiconductor substrate, wherein the second metal tungsten layer is connected to the first metal tungsten layer and fills the target through hole or the target trench without any gap.

[0005] The present application is further configured as follows: depositing the tungsten nucleation layer, depositing the first metal tungsten layer, etching away the convex corner blocking portion, and depositing the second metal tungsten layer are all completed in the same process chamber and at the same set temperature.

[0006] The present application is further configured as follows: the set temperature includes 400-450°C.

[0007] The present application is further configured as follows: the deposition of a tungsten nucleation layer on the barrier layer comprises: Under the set temperature and the first chamber pressure, the process chamber is introduced with a precursor gas, a reducing gas and an inert carrier gas, wherein the precursor gas comprises WF6, the reducing gas comprises SiH4 and H2, and the inert carrier gas comprises Ar; The precursor gas is reduced by the reducing gas and reacts on the surface of the barrier layer to form the tungsten nucleation layer having a target thickness, wherein the target thickness is comprised between 20 nm and 60 nm.

[0008] The present application is further configured as follows: depositing a first metal tungsten layer on the tungsten nucleation layer comprises: Under the set temperature and the second chamber pressure, a precursor gas, a reducing gas and an inert carrier gas are introduced into the process chamber, wherein the precursor gas comprises WF6, the reducing gas comprises H2, and the inert carrier gas comprises Ar; The precursor gas is reduced by the reducing gas to form a first metal tungsten layer on the tungsten nucleation layer.

[0009] The present application is further configured as follows: the etching to remove the convex corner blocking portion includes: At the set temperature and the third chamber pressure, the process chamber in capacitively coupled plasma mode is introduced with an etching gas and a dilution gas at a set power, wherein the etching gas includes NF3 and the dilution gas includes Ar or H2; The etching gas removes the convex corner stopper.

[0010] The present application is further configured as follows: the first chamber pressure includes 5-30T, the second chamber pressure includes 70-90T, the third chamber pressure includes 300-800mT, and the set power includes 100-400W.

[0011] The present application is further configured as follows: the target groove has a set aspect ratio, and the range of the set aspect ratio includes 7:1 to 4:1.

[0012] The present application is further configured as follows: an epitaxial layer is formed on the semiconductor substrate, and the target through hole or the target trench is formed on the epitaxial layer.

[0013] The present application is further configured as follows: before forming a barrier layer on the semiconductor substrate, the present application further includes: The semiconductor substrate is cleaned by chemical cleaning or plasma cleaning.

[0014] In summary, compared with the prior art, the present application discloses a semiconductor device process method, including forming a barrier layer on a semiconductor substrate in a process chamber, depositing a tungsten nucleation layer on the barrier layer, depositing a first metal tungsten layer covering the surface of the semiconductor substrate and the side walls of a target through hole or a target groove on the tungsten nucleation layer, and after etching away part of the first metal tungsten layer to form a convex corner barrier portion at the connection between the surface of the semiconductor substrate and the side walls of the target through hole or the target groove, depositing a second metal tungsten layer on the semiconductor substrate, wherein the second metal tungsten layer is connected to the first metal tungsten layer and fills the target through hole or the target groove without gaps, that is, through the above-mentioned arrangement, a uniform and dense metal tungsten layer is formed by a deposition-etching-deposition process in the process chamber, avoiding the disadvantage of obvious gaps in the traditional tungsten deposition process, thereby ensuring the electrical properties and product yield of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0016] Figure 1 is a process flow chart of the semiconductor device process method of this embodiment; Figure 2 is a schematic structural diagram of a first semiconductor device of this embodiment; Figure 3 is a schematic structural diagram of a second semiconductor device of this embodiment; Figure 4 is a schematic structural diagram of a third semiconductor device of this embodiment; Figure 5 It is a schematic structural diagram of the fourth semiconductor device of this embodiment. DETAILED DESCRIPTION

[0017] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0018] It should be noted that, in this article, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element. In addition, components, features, and elements with the same name in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined by their explanation in the specific embodiment or further combined with the context of the specific embodiment.

[0019] It should be further understood that the terms "comprising" and "including" indicate the presence of the described features, steps, operations, elements, components, items, kinds, and / or groups, but do not exclude the presence, occurrence or addition of one or more other features, steps, operations, elements, components, items, kinds, and / or groups. The terms "or", "and / or", "including at least one of the following", etc. used in this application may be interpreted as inclusive, or mean any one or any combination. For example, "including at least one of the following: A, B, C" means "any one of the following: A; B; C; A and B; A and C; B and C; A and B and C", and for another example, "A, B or C" or "A, B and / or C" means "any one of the following: A; B; C; A and B; A and C; B and C; A and B and C". Exceptions to this definition will only occur when the combination of elements, functions, steps or operations is inherently mutually exclusive in some way.

[0020] It should be understood that although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of this document, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, as used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless otherwise indicated in the context.

[0021] It should be understood that the orientations or positional relationships indicated by terms such as "top", "bottom", "up", "down", "vertical", and "horizontal" are based on the orientations or positional relationships shown in the accompanying drawings and are only for the convenience of describing the present application and simplifying the description. They do not indicate or imply that the device referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0022] For ease of description, in the following embodiments, the orthogonal space formed by the horizontal plane and the vertical direction is used as an example for explanation, and this premise should not be understood as a limitation to the present application.

[0023] Please refer to Figure 1 , Figure 1 : is a process flow chart of a semiconductor device process method of this embodiment, and the semiconductor device process method includes: S101 , providing a semiconductor substrate 1 in a process chamber, on which a target through hole 2 or a target trench 3 and a barrier layer 4 covering the target through hole 2 or the target trench 3 are formed.

[0024] In this step, refer to Figure 2 According to environmental requirements, a plurality of target through holes 2, or a plurality of target grooves 3, or a combination of target through holes 2 and target grooves 3 can be formed on the semiconductor substrate 1, wherein the target through holes 2 or target grooves 3 can also be arranged according to preset rules for subsequent metallization preparation of semiconductor integrated circuit through holes and interconnection layers.

[0025] Among them, the forming material of the semiconductor substrate 1 of this embodiment can be single crystal silicon, polycrystalline silicon, amorphous silicon or doped silicon and the like. The material of the semiconductor substrate 1 can also be a SiGe substrate, a III-V group element compound substrate, a silicon carbide substrate or its stacked structure, or a silicon-on-insulator structure, or a diamond substrate or other semiconductor material substrates known to those skilled in the art. For example, P atoms can be implanted into single crystal silicon to form an N-type conductive semiconductor substrate, and B atoms can be implanted into single crystal silicon to form a P-type conductive semiconductor substrate, so as to improve the selectivity of the material and its adaptability to the actual production environment.

[0026] S102 , a tungsten nucleation layer 5 is deposited on the barrier layer 4 .

[0027] It should be noted that the barrier layer 4 can be formed of titanium (Ti) and titanium nitride (TiN), wherein Ti plays the role of an adhesion layer to prevent TiN from directly contacting the semiconductor substrate 1 and causing large stress to cause the barrier layer 4 to fall off, and TiN plays the role of a barrier layer to prevent subsequent oxidation reactions such as WF6 process gas and Ti from causing "tungsten volcano" defects, that is, Ti and TiN cooperate to provide an ideal surface for the growth of tungsten, so Ti and TiN can be selected as the bottom layer of the tungsten nucleation layer.

[0028] Among them, before forming the barrier layer 4 on the semiconductor substrate 1, it also includes: cleaning the semiconductor substrate 1, and the cleaning treatment includes chemical cleaning or plasma cleaning. For example, chemical cleaning uses chemical reagents to clean the semiconductor substrate 1 to remove the natural oxide layer, surface particles, metal ions, etc. on the surface of the semiconductor substrate 1, wherein the chemical reagent may include a combination of one or more of sulfuric acid, hydrochloric acid, nitric acid, and hydrofluoric acid. That is to say, the acidic solution may include any one of the above-mentioned various solutions, or may also include a combination of any two or more of the above-mentioned various solutions. This embodiment does not limit it here, thereby ensuring that the semiconductor substrate 1 is clean before the barrier layer 4 is formed.

[0029] In an optional embodiment, an epitaxial layer 9 is formed on the semiconductor substrate 1, and the target through hole 2 or the target groove 3 is formed on the epitaxial layer 9 for subsequent interconnection, filling or other processes. Specifically, a buried layer and an epitaxial layer 9 stacked in sequence can be formed on the semiconductor substrate 1. At this time, the functional layers of the semiconductor device can all be formed on the epitaxial layer. It can be understood that the epitaxial layer 9 is formed by epitaxially growing a layer of dielectric material on the semiconductor substrate 1, which can be stacked with a multi-layer structure. Then, the target through hole 2 or the target groove 3 can be formed on the epitaxial layer 9 by photolithography and etching processes.

[0030] S103 , depositing a first metal tungsten layer 6 on the tungsten nucleation layer 5 , wherein the first metal tungsten layer 6 covers the surface of the semiconductor substrate 1 and the sidewalls of the target through hole 2 or the target trench 3 .

[0031] In this step, the first metal tungsten layer 6 is formed on the tungsten nucleation layer 5, and covers the surface of the semiconductor substrate 1, and the side walls of the target through hole 2 or the target groove 3. It should be noted that the first metal tungsten layer 6 does not completely fill the target through hole 2 or the target groove 3, that is, the first metal tungsten layer 6 of this embodiment is formed on the side walls of the target through hole 2 or the target groove 3 and still maintains a cavity in the target through hole 2 or the target groove 3 that conforms to the side wall contour of the target through hole 2 or the target groove 3, so as to facilitate the subsequent process of this embodiment.

[0032] In the specific implementation process, a tungsten nucleation layer 5 is deposited on the barrier layer 4, which may specifically include: at a set temperature and a first chamber pressure, a precursor gas, a reducing gas and an inert carrier gas are introduced into the process chamber; the precursor gas is reduced by the reducing gas and reacts on the surface of the barrier layer 4 to form a tungsten nucleation layer 5 with a target thickness.

[0033] The precursor gas may include WF6, the reducing gas may include SiH4 and H2, and the inert carrier gas may include Ar.

[0034] The main reaction process is as follows: WF6+3SiH4→W+3SiF4+3H2 Based on this, the precursor gas is reduced by the reducing gas, that is, WF6 is reduced by SiH4 and H2, so that WF6 is decomposed and a tungsten nucleation layer 5 with a target thickness is formed on the surface of the barrier layer 4. Of course, SiF4 can be discharged from the process chamber as a by-product in the subsequent process.

[0035] It should be noted that in the above reaction process, the inert gas Ar is introduced as a carrier gas to promote gas flow and maintain the uniformity of the reaction in the process chamber to avoid uneven nucleation, while H2 acts as an auxiliary reducing agent in this process and reduces the required metal tungsten nucleation layer by cooperating with SiH4.

[0036] The set temperature is 400-450°C, and the first chamber pressure is 5-30T.

[0037] The target thickness of the tungsten nucleation layer 5 is in the range of 20-60 nm.

[0038] In an optional embodiment, the temperature is set to 420°C, the first chamber pressure is 25T, and the target thickness of the tungsten nucleation layer is 40nm, then a tungsten nucleation layer 5 is deposited on the barrier layer 4, specifically including: under environmental parameters of 420°C and 25T, WF6 gas, SiH4 and H2 gas and Ar carrier gas are introduced into the process chamber; WF6 is reduced by SiH4 and H2, and reacts on the surface of the barrier layer 4 to form a tungsten nucleation layer 5 with a thickness of 40nm.

[0039] Furthermore, a first metal tungsten layer 6 is deposited on the tungsten nucleation layer 5 , which may specifically include: under a set temperature and a second chamber pressure, a precursor gas, a reducing gas and an inert carrier gas are introduced into the process chamber, the precursor gas is reduced by the reducing gas, and the first metal tungsten layer 6 is formed on the tungsten nucleation layer 5 .

[0040] Wherein, the precursor gas includes WF6, the reducing gas includes H2, and the inert carrier gas includes Ar.

[0041] The main reaction process is as follows: WF6+3H2→W+6HF Based on this, WF6 is reduced by H2 to form a first metal tungsten layer 6 on the tungsten nucleation layer 5. Of course, HF as a by-product can be discharged from the process chamber in the subsequent process.

[0042] The set temperature is 400-450°C, and the second chamber pressure is 70-90T.

[0043] Similarly, in the above reaction process, inert gas Ar is introduced as a carrier gas.

[0044] In an optional embodiment, the temperature is set to 420°C and the pressure of the second chamber is 80T, then a first metal tungsten layer 6 is deposited on the tungsten nucleation layer 5, specifically including: under environmental parameters of 420°C and 80T, WF6, H2 and Ar are introduced into the process chamber, WF6 is reduced by H2, and the first metal tungsten layer 6 is formed on the tungsten nucleation layer 5.

[0045] It should be noted that the deposition to form the tungsten nucleation layer 5 and the deposition to form the first metal tungsten layer 6 on the tungsten nucleation layer 5 are both completed in the same process chamber by chemical vapor deposition.

[0046] S104 , etching and removing the convex corner blocking portion 8 , which is a portion of the first metal tungsten layer 6 formed at the connection between the surface of the semiconductor substrate 1 and the sidewall of the target through hole 2 or the target trench 3 .

[0047] In this step, refer to Figure 2 and Figure 3 , etching away the convex corner blocking portion 8, that is, etching partially the first metal tungsten layer 6, thereby avoiding the uneven internal space of the target through hole 2 or the target groove 3 caused by the uneven deposition of the first metal tungsten layer 6. Therefore, the disadvantage of obvious gaps in the traditional tungsten deposition process can be avoided, that is, the uneven first metal tungsten layer 6 blocks or blocks the internal space of the target through hole 2 or the target groove 3, resulting in insufficient deposition of metal tungsten. That is to say, this step etches part of the first metal tungsten layer 6, thereby providing the necessary conditions for the subsequent complete deposition of metal tungsten into the target through hole 2 or the target groove 3.

[0048] In the specific implementation process, the first metal tungsten layer 6 at the connection between the surface of the semiconductor substrate 1 and the side wall of the target through hole 2 or the target groove 3 has a convex corner blocking portion 8, that is, at the opening of the target through hole 2 or the target groove 3 (the top edge area of ​​the target through hole 2 or the target groove 3), the first metal tungsten layer 6 has a convex corner blocking portion 8. It can be understood that for the convex corner morphology of the target through hole 2 or the target groove 3 formed on the semiconductor substrate 1, due to the uneven distribution of gas (precursor gas and reducing gas) concentration during the chemical vapor deposition process, especially in the target through hole 2 or the target groove 3 with a large aspect ratio, it is difficult for the gas to diffuse evenly to the bottom of the hole or the bottom of the groove, so the deposition speed of metal tungsten at the opening is relatively fast, that is, a convex corner blocking portion 8 is formed at the opening of the target through hole 2 or the target groove 3.

[0049] In the semiconductor device process method of the present embodiment, in a process chamber, a barrier layer 4 is formed on a semiconductor substrate 1 to cover a target through hole 2 or a target groove 3 of the semiconductor substrate 1, a tungsten nucleation layer 5 is deposited on the barrier layer 4, and a first metal tungsten layer 6 is deposited on the tungsten nucleation layer 5 to cover the surface of the semiconductor substrate 1 and the side walls of the target through hole 2 or the target groove 3, wherein the first metal tungsten layer 6 has a convex corner barrier 8 at the connection between the surface of the semiconductor substrate 1 and the side walls of the target through hole 2 or the target groove 3, and after the convex corner barrier 8 is etched away, a subsequent metal tungsten deposition step is performed, thereby forming a uniform and dense metal tungsten layer, avoiding the disadvantage of obvious gaps in the traditional tungsten deposition process, and ensuring the electrical properties and product yield of the semiconductor device.

[0050] In the specific implementation process, etching to remove the convex corner blocking portion 8 includes: at a set temperature and a third chamber pressure, introducing etching gas and dilution gas into a process chamber in a capacitively coupled plasma mode at a set power; and removing the convex corner blocking portion 8 with the etching gas.

[0051] The etching gas includes NF3, and the dilution gas includes Ar or H 2。

[0052] Among them, the set temperature includes 400-450°C, the third chamber pressure includes 300-800mT, and the set power includes 100-400W.

[0053] That is, in the process of etching away the convex corner blocking portion 8, the temperature of the process chamber is maintained at 400-450°C during the etching process, which is consistent with the temperature of the deposition process of depositing the tungsten nucleation layer 5 on the blocking layer 4 and depositing the first metal tungsten layer 7 on the tungsten nucleation layer 5 in the aforementioned embodiment. Then, NF3 is used as the main etching gas. NF3 will decompose under the action of plasma to produce active fluorine atoms, which will then react with the convex corner blocking portion 8 to generate volatile by-products, such as WF6, thereby achieving the removal of the convex corner blocking portion 8. Among them, the dilution gas is used to adjust the etching atmosphere and reaction rate of the etching gas.

[0054] It should be noted that the process chamber adopts a capacitively coupled plasma mode to form a uniform plasma in the chamber, ensure that the etching gas is fully ionized, and improve the accuracy and control of etching.

[0055] In an optional embodiment, the temperature is set to 420°C, the pressure of the third chamber is 800mT, and the power is set to 250W, then the convex corner blocking portion 8 is etched away, specifically comprising: under the environmental parameters of 420°C and 800mT, NF3 and Ar or H2 are introduced into the process chamber in capacitively coupled plasma mode at a power of 250W; the convex corner blocking portion 8 is removed by etching gas.

[0056] It should be noted that in order to avoid the disadvantage of obvious gaps in the traditional tungsten deposition process, that is, the uneven first metal tungsten layer 6 blocks or seals the internal space of the target through hole 2 or the target groove 3, resulting in insufficient metal tungsten deposition, and to ensure that the subsequent second metal tungsten layer 7 is seamlessly filled in the target through hole 2 or the target groove 3, this embodiment uses a capacitively coupled plasma mode process chamber at a set temperature and a third chamber pressure. After the etching gas and the dilution gas are introduced at a set power to remove the convex corner blocking portion 8, the first metal tungsten layer 7 has a gradually expanding opening in the target through hole 2 or the target groove 3 from the bottom of the semiconductor substrate 1 toward the top of the semiconductor substrate 1.

[0057] S105 , depositing a second metal tungsten layer 7 on the semiconductor substrate 1 , wherein the second metal tungsten layer 7 is connected to the first metal tungsten layer 6 and fills the target through hole 2 or the target trench 3 without any gap.

[0058] In this step, refer to Figure 4 and Figure 5 After the convex corner blocking portion 8 is etched away, that is, after the first metal tungsten layer 6 is partially etched, the second metal tungsten layer 7 is deposited, and the second metal tungsten layer 7 is seamlessly filled in the target through hole 2 or the target groove 3, thereby forming a uniform and dense metal tungsten layer on the target through hole 2 or the target groove 3 of the semiconductor substrate 1.

[0059] It should be noted that, in the present application, the deposition of the tungsten nucleation layer 5, the deposition of the first metal tungsten layer 6, the etching to remove the convex corner blocking portion 8, and the deposition of the second metal tungsten layer 7 are all completed in the same process chamber, thereby ensuring the consistency of the chamber temperature environment of the semiconductor device process and the production efficiency.

[0060] That is, the ambient reaction temperature of the process chamber can be kept consistent, so that the deposition of the tungsten nucleation layer 5, the deposition of the first metal tungsten layer 6, the etching removal of the convex corner blocking portion 8, and the deposition of the second metal tungsten layer 7 are all completed in the same process chamber and at the same set temperature, which may be 400-450°C.

[0061] Preferably, the set temperature is 420°C.

[0062] In an optional embodiment, after the second metal tungsten layer 7 is deposited on the semiconductor substrate 1 , chemical mechanical polishing or dry etching may be performed to ensure that the second metal tungsten layer 7 is smooth and flat on the semiconductor substrate 1 .

[0063] That is, the first metal tungsten layer 6 and the second metal tungsten layer 7 are successively deposited in the target through hole 2 or the target groove 3 to form a target metal tungsten layer 10. Of course, the target metal tungsten layer 10 is evenly and densely filled in the target through hole 2 or the target groove 3, thereby avoiding the disadvantage of obvious gaps in the traditional tungsten deposition process, thereby ensuring the electrical properties of the semiconductor device and the product yield.

[0064] In an optional embodiment, the target groove 3 has a set aspect ratio, and the range of the set aspect ratio includes 7:1 to 4:1, that is, the semiconductor device process method of the present application acts on the target groove 3 with a high aspect ratio to form a uniform and dense metal tungsten layer in the target groove 3 with a high aspect ratio.

[0065] Of course, the aspect ratio set in the present application is not limited to this, and it can also be other aspect ratio ranges required by actual environment.

[0066] In the semiconductor device process method of the present embodiment, in a process chamber, a barrier layer 4 is formed on a semiconductor substrate 1, the barrier layer 4 covers a target through hole 2 or a target groove 3 of the semiconductor substrate 1, a tungsten nucleation layer 5 is formed on the barrier layer 4, and a first metal tungsten layer 6 covering the surface of the semiconductor substrate 1 and the sidewalls of the target through hole 2 or the target groove 3 is deposited on the tungsten nucleation layer 5, wherein the first metal tungsten layer 6 has a convex corner barrier portion 8 at the connection between the surface of the semiconductor substrate 1 and the sidewalls of the target through hole 2 or the target groove 3, after the convex corner barrier portion 8 is removed by etching, a second metal tungsten layer 7 is deposited on the semiconductor substrate 1, and the second metal tungsten layer 7 is connected to the first metal tungsten layer 4 and is seamlessly filled in the target through hole 2 or the target groove 3. Therefore, under the reaction conditions of the same process chamber, a deposition-etching-deposition process is used to form a uniform and dense metal tungsten layer on the target through hole 2 or the target groove 3 for the first metal tungsten layer 6 and the second metal tungsten layer 7, thereby avoiding the disadvantage of obvious gaps in the traditional tungsten deposition process, and ensuring the electrical properties and product yield of the semiconductor device.

[0067] The semiconductor device process method provided by the present application is described in detail above, and the principle and implementation method of the present application are described in detail using specific examples. It should be noted that in the present application, the description of each embodiment has its own emphasis, and for the part that is not described or recorded in detail in a certain embodiment, please refer to the relevant description of other embodiments.

[0068] The above are only preferred embodiments of the present application, and the patent scope of the present application is not limited thereto. The various technical features of the technical solution of the present application can be arbitrarily combined. In order to make the description concise, not all possible combinations of the various technical features in the above embodiments are described. Any equivalent structure or equivalent process transformation made using the contents of the specification and drawings of this application, or directly or indirectly used in other related technical fields, as long as there is no contradiction in the combination of these technical features, are equally included in the patent protection scope of the present application.

Claims

1. A semiconductor device process method, characterized in that: include: Providing a semiconductor substrate in a process chamber, wherein a target through hole or a target trench is formed on the semiconductor substrate, and a barrier layer covering the target through hole or the target trench; Depositing a tungsten nucleation layer on the barrier layer; Depositing a first metal tungsten layer on the tungsten nucleation layer, wherein the first metal tungsten layer covers the surface of the semiconductor substrate and the sidewalls of the target through hole or the target trench; Etching and removing the convex corner blocking portion, the convex corner blocking portion being a portion of the first metal tungsten layer formed at the connection between the surface of the semiconductor substrate and the sidewall of the target through hole or the target trench; A second metal tungsten layer is deposited on the semiconductor substrate, wherein the second metal tungsten layer is connected to the first metal tungsten layer and fills the target through hole or the target trench without any gap.

2. The semiconductor device process according to claim 1, wherein: Depositing the tungsten nucleation layer, depositing the first metal tungsten layer, etching away the convex corner blocking portion, and depositing the second metal tungsten layer are all completed in the same process chamber and at the same set temperature.

3. The semiconductor device process according to claim 2, wherein: The set temperature includes 400-450°C.

4. The semiconductor device process according to claim 1, wherein: The step of depositing a tungsten nucleation layer on the barrier layer comprises: Under the set temperature and the first chamber pressure, the process chamber is introduced with a precursor gas, a reducing gas and an inert carrier gas, wherein the precursor gas comprises WF6, the reducing gas comprises SiH4 and H2, and the inert carrier gas comprises Ar; The precursor gas is reduced by the reducing gas and reacts on the surface of the barrier layer to form the tungsten nucleation layer having a target thickness, wherein the target thickness is comprised between 20 nm and 60 nm.

5. The semiconductor device process according to claim 4, characterized in that: The step of depositing a first metal tungsten layer on the tungsten nucleation layer comprises: Under the set temperature and the second chamber pressure, a precursor gas, a reducing gas and an inert carrier gas are introduced into the process chamber, wherein the precursor gas comprises WF6, the reducing gas comprises H2, and the inert carrier gas comprises Ar; The precursor gas is reduced by the reducing gas to form a first metal tungsten layer on the tungsten nucleation layer.

6. The semiconductor device process according to claim 5, characterized in that: The etching and removing of the convex corner blocking portion comprises: At the set temperature and the third chamber pressure, the process chamber in capacitively coupled plasma mode is fed with an etching gas and a dilution gas at a set power, wherein the etching gas includes NF3 and the dilution gas includes Ar or H2; The etching gas removes the convex corner stopper.

7. The semiconductor device process according to claim 6, wherein: The first chamber pressure includes 5-30T, the second chamber pressure includes 70-90T, the third chamber pressure includes 300-800mT, and the set power includes 100-400W.

8. The semiconductor device process according to claim 1, wherein: The target trench has a set aspect ratio, and the range of the set aspect ratio includes 7:1 to 4:

1.

9. The semiconductor device process according to claim 1, wherein: An epitaxial layer is formed on the semiconductor substrate, and the target through hole or the target trench is formed on the epitaxial layer.

10. The semiconductor device process according to claim 1, wherein: Before forming the barrier layer on the semiconductor substrate, the method further comprises: The semiconductor substrate is cleaned by chemical cleaning or plasma cleaning.

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