Pre-doping process testing structure, manufacturing method thereof and pre-doping process testing method

Abstract

The invention provides a pre-doping process testing structure, a manufacturing method thereof and a pre-doping process testing method. The pre-doping process test structure comprises a substrate, an active region is defined in the substrate, and the active region comprises a first region and a second region; the pre-doped grid electrode is formed on the surface of the active region of the first region, extends in the first direction and has a first key size in the second direction; wherein an included angle is formed between the first direction and the second direction; the non-pre-doped grid electrode is formed on the surface of the active region of the second region, extends along the first direction and has a second key size along the second direction; wherein the critical dimension deviation caused by the pre-doping process can be obtained by testing the first critical dimension and the second critical dimension. According to the technical scheme, the two areas are arranged in the pre-doping process test structure to measure the first key size and the second key size respectively, and the key size deviation caused by the doping process is obtained to monitor the etching deviation.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a pre-doping process test structure and a manufacturing method thereof, and a pre-doping process test method. Background Art

[0002] Polysilicon depletion refers to the gate voltage that attracts minority carriers to the dielectric and channel interface, causing carriers to accumulate at the polysilicon (Poly) and dielectric interface, resulting in the depletion of semiconductor charges in the nearby area. Figure 1 As shown, the depletion of charge is equivalent to forming a depletion layer 13 at the interface between the polysilicon 11 and the dielectric layer 12, which increases the electrical thickness of the dielectric layer 11 and reduces the driving current capability. Therefore, when Poly is used as the gate, the depletion region capacitance is increased through NMOS Poly pre-doping to increase the gate control capability. At the 90nm to 40nm process nodes, most of them only use Pre-doping for NMOS, and PMOS does not use Pre-doping. However, there is only one Pre-doping design for the general critical dimension bar (CD Bar) and NMOS test unit (Testkey), such as Figure 2 As shown, the traditional CD Bar design can only monitor the CD of the complete Pre-doping or non-Pre-doping Poly Etch (ET) process.

[0003] Therefore, how to optimize the test structure to simultaneously monitor the critical dimensions of pre-doped and non-pre-doped is a problem that needs to be solved. Summary of the invention

[0004] The technical problem to be solved by the present invention is how to optimize the test structure to simultaneously monitor the critical dimensions of pre-doping and non-pre-doping, and to provide a pre-doping process test structure and a manufacturing method thereof, and a pre-doping process test method.

[0005] In order to solve the above problems, the present invention provides a pre-doping process test structure, including: a substrate, an active area is defined in the substrate, and the active area includes a first area and a second area; a pre-doped gate formed on the surface of the active area in the first area, the pre-doped gate extends along a first direction and has a first critical dimension along a second direction; wherein the first direction forms an angle with the second direction; a non-pre-doped gate formed on the surface of the active area in the second area, the non-pre-doped gate extends along the first direction and has a second critical dimension along the second direction; wherein, by testing the first critical dimension and the second critical dimension, the critical dimension deviation caused by the pre-doping process can be obtained.

[0006] In order to solve the above problems, the present invention provides a method for manufacturing a pre-doping process test structure, the method comprising the following steps: providing a substrate, wherein an active area is defined in the substrate, and the active area comprises a first area and a second area; forming a dielectric layer on the surface of the active area and depositing a polysilicon layer on the surface of the dielectric layer; performing a pre-doping process on the polysilicon layer in the first area; patterning the polysilicon layer to form a pre-doped gate on the surface of the active area in the first area and a non-pre-doped gate on the surface of the active area in the second area, wherein the pre-doped gate extends along a first direction and has a first critical dimension along a second direction, the non-pre-doped gate extends along the first direction and has a second critical dimension along the second direction, and the first direction forms an angle with the second direction.

[0007] In order to solve the above problems, the present invention provides a pre-doping process testing method, comprising the following steps: providing a first test unit, the first test unit adopting the first test unit described in the present invention; measuring a first critical dimension of a pre-doped gate and a second critical dimension of a non-pre-doped gate; obtaining a difference between the first critical dimension of the pre-doped gate and the second critical dimension of the non-pre-doped gate to obtain a critical dimension deviation caused by the pre-doping process.

[0008] The above technical solution sets two areas in a pre-doping process test structure to measure the first critical dimension and the second critical dimension respectively, obtains the difference between the first critical dimension and the second critical dimension to obtain the critical dimension deviation caused by the doping process, and then sets the deviation value in advance in the etching process to obtain pre-doped gates and non-pre-doped gates with consistent critical dimensions.

[0009] It should be understood that the above general description and the detailed description below are exemplary and explanatory only and cannot limit the present invention. The techniques, methods and devices known to ordinary technicians in the relevant field may not be discussed in detail, but where appropriate, the techniques, methods and devices should be considered as part of the authorization specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the following is a brief introduction to the drawings required for the description of the specific embodiments. Obviously, the drawings described below are only some specific embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0011] Figure 1 Schematic diagram of transistor polysilicon depletion in the prior art.

[0012] Figure 2It is a structural schematic diagram of a critical dimension test unit in the prior art.

[0013] Figure 3 It is a structural schematic diagram of the first embodiment of the pre-doping process test structure of the present invention.

[0014] Figure 4 The present invention is a flowchart of the steps of an embodiment of a method for manufacturing a pre-doping process test structure according to the present invention.

[0015] Figure 5A A schematic structural diagram of a substrate is provided for one embodiment of a method for manufacturing a pre-doping process test structure according to the present invention.

[0016] Figure 5B This is a structural schematic diagram of depositing a polysilicon layer on the surface of the substrate in an embodiment of the method for manufacturing the pre-doping process test structure of the present invention.

[0017] Figure 5C This is a structural schematic diagram of performing a pre-doping process on the polysilicon layer in the first region according to an embodiment of the method for manufacturing the pre-doping process test structure of the present invention.

[0018] Figure 5D The schematic diagram of the structure of the patterned polysilicon layer is an embodiment of the method for manufacturing the pre-doping process test structure of the present invention.

[0019] Figure 6 It is a structural schematic diagram of the second embodiment of the pre-doping process test structure of the present invention.

[0020] Figure 7 It is a structural schematic diagram of the third embodiment of the pre-doping process test structure of the present invention.

[0021] Figure 8 It is a schematic diagram of edge shadow of the pre-doping process in the prior art.

[0022] Fig. 9 It is a structural schematic diagram of a fourth embodiment of the pre-doping process test structure of the present invention.

[0023] Fig.10 This is a flowchart of the steps of the first embodiment of the pre-doping process testing method of the present invention.

[0024] Fig.11 This is a flow chart of the steps of the second embodiment of the pre-doping process testing method of the present invention.

[0025] Fig.12 This is a flow chart of the steps of the third embodiment of the pre-doping process testing method of the present invention.

[0026] Fig.13A flowchart of the fourth embodiment of the pre-doping process testing method of the present invention DETAILED DESCRIPTION

[0027] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0028] See also Figure 3 , which is a schematic diagram of the structure of the first embodiment of the pre-doping process test structure of the present invention. Figure 3 As shown, the pre-doping process test structure includes: a substrate 30, an active area AA, a pre-doped gate 31, and a non-pre-doped gate 32. An active area AA is defined in the substrate 30, and the active area AA includes a first area 301 and a second area 302. The pre-doped gate 31 is formed on the surface of the active area AA in the first area 301, and the pre-doped gate 31 extends along a first direction D1 and has a first critical dimension CD1 along a second direction D2; wherein the first direction D1 forms an angle with the second direction D2. The non-pre-doped gate 32 is formed on the surface of the active area AA in the second area 302, and the non-pre-doped gate 32 extends along the first direction D1 and has a second critical dimension CD2 along the second direction D2. wherein, by testing the first critical dimension CD1 and the second critical dimension CD2, the critical dimension deviation caused by the pre-doping process can be obtained.

[0029] In this embodiment, the first critical dimension CD1 is the critical dimension of any of the pre-doped gates 31 (i.e., the width of the pre-doped gate 31 along the second direction D2), and the second critical dimension CD2 is the critical dimension of any of the non-pre-doped gates 32 (i.e., the width of the non-pre-doped gate 32 along the second direction D2). In other embodiments, the first critical dimension is the average value of the critical dimensions of all the pre-doped gates 31; the second critical dimension is the average value of the critical dimensions of all the non-pre-doped gates 32.

[0030] In this embodiment, two regions are set in a pre-doping process test structure to form a pre-doped gate 31 and a non-pre-doped gate 32 respectively, and a first critical dimension CD1 of the pre-doped gate 31 and a second critical dimension CD2 of the non-pre-doped gate 32 are measured to obtain the difference between the first critical dimension CD1 and the second critical dimension CD2 to obtain the critical dimension deviation caused by the doping process, and then the deviation value is set in advance in the etching process to obtain the pre-doped gate and the non-pre-doped gate with the same critical dimension.

[0031] See also Figure 4 , which is a flow chart of steps of an embodiment of the method for manufacturing the pre-doping process test structure of the present invention. Figure 4 As shown, the method for manufacturing the pre-doping process test structure includes the following steps: step S41, providing a substrate, in which an active area is defined, and the active area includes a first area and a second area; step S42, forming a dielectric layer on the surface of the active area and depositing a polysilicon layer on the surface of the dielectric layer; step S43, performing a pre-doping process on the polysilicon layer in the first area; step S44, graphing the polysilicon layer to form a pre-doped gate on the surface of the active area in the first area and a non-pre-doped gate on the surface of the active area in the second area, wherein the pre-doped gate extends along a first direction and has a first critical dimension along a second direction, the non-pre-doped gate extends along the first direction and has a second critical dimension along the second direction, and the first direction forms an angle with the second direction.

[0032] Please refer to Figure 5A And step S41, providing a substrate 50, wherein an active area AA is defined in the substrate 50, and the active area AA includes a first region 501 and a second region 502. In this embodiment, the substrate 50 is a single crystal silicon layer.

[0033] Please refer to Figure 5B And step S42, forming a dielectric layer 508 on the surface of the active area AA and depositing a polysilicon layer 510 on the surface of the dielectric layer 508. In this embodiment, the dielectric layer 508 is a silicon oxide layer. The dielectric layer 508 is formed on the surface of the active area AA along the third direction D3.

[0034] Please refer to Figure 5C And step S43 , performing a pre-doping process on the polysilicon layer 510 in the first region 501 .

[0035] Please refer to Figure 3 and Figure 5D And step S44, patterning the polysilicon layer 510 to form a pre-doped gate 51 on the surface of the active area AA of the first region 501, and forming a non-pre-doped gate 52 on the surface of the active area AA of the second region 502, wherein the pre-doped gate 51 extends along the first direction D1 and has a first critical dimension CD1 along the second direction D2, and the non-pre-doped gate 52 extends along the first direction D1 and has a second critical dimension CD2 along the second direction D2, and the first direction D1 forms an angle with the second direction D2. The plane formed by the first direction D1 and the second direction D2 forms an angle with the third direction D3.

[0036] Please continue reading Figure 3 In some embodiments, the pre-doping process test structure includes a first test unit 100, and the first test unit 100 includes a first region 301 and a second region 302 arranged in parallel along the second direction D2. The first region 301 is formed with a plurality of pre-doped gates 31, and the plurality of pre-doped gates 31 extend along the first direction D1 and are arranged along the second direction D2. The second region 302 is formed with a plurality of non-pre-doped gates 32, and the plurality of non-pre-doped gates 32 extend along the first direction D1 and are arranged along the second direction D2.

[0037] See also Figure 6 , which is a schematic diagram of the structure of the second embodiment of the pre-doping process test structure of the present invention. Figure 3 The embodiment shown is different in that the pre-doping process test structure includes a second test unit 200, and the second test unit 200 includes a plurality of first regions 601 and a plurality of second regions 602 alternately arranged along the second direction D2; a pre-doped gate 61 is formed in each of the first regions 601; and a non-pre-doped gate 62 is formed in each of the second regions 602. The pre-doped gate 61 extends along the first direction D1 and has a first critical dimension CD1 along the second direction D2; the non-pre-doped gate 32 extends along the first direction D1 and has a second critical dimension CD2 along the second direction D2. Figure 6 The second test unit 200 shown can also obtain the critical dimension deviation caused by the pre-doping process by testing the first critical dimension and the second critical dimension.

[0038] See also Figure 7 , which is a schematic diagram of the structure of the third embodiment of the pre-doping process test structure of the present invention. Figure 4 The embodiment shown is different in that Figure 7 In the second test unit 200 shown: a plurality of the pre-doped gates 71 are connected in parallel to a first pad 731, and a plurality of the non-pre-doped gates 72 are connected in parallel to a second pad 732; by applying a test voltage at the first pad 731 and the second pad 732, it is possible to determine whether the pre-doping process has an electrical impact based on the measured electrical parameters. Specifically, if the electrical parameters of the pre-doped gate 71 and the non-pre-doped gate 72 are the same, it is determined that the pre-doping process has no electrical impact; if the electrical parameters of the pre-doped gate 71 are different from the electrical parameters of the non-pre-doped gate 72, it is determined that the pre-doping process has an electrical impact. In this embodiment, a plurality of the pre-doped gates 71 are connected in parallel to form the interdigitated gates of a multi-finger gate transistor, and a plurality of the non-pre-doped gates 72 are connected in parallel to form the interdigitated gates of a multi-finger gate transistor.

[0039] In some embodiments, in the second test unit 200: a virtual gate 74 is formed in at least one second region 702 located at the edge of the active area AA, and the virtual gate 74 is electrically connected to a third pad 733; by applying a test voltage at the second pad 732 and the third pad 733, it is possible to determine whether the test result is valid based on the measured electrical parameters. If the difference between the electrical parameters of the virtual gate 74 and the electrical parameters of the non-pre-doped gate 72 is less than a preset threshold, the test result is determined to be valid, and the determination of whether the pre-doping process has an electrical impact can be continued. In this embodiment, the virtual gate 74 is a single transistor, which can be used as a control group for the electrical test of multi-finger gate transistors. In other embodiments, the virtual gate 74 may not be set.

[0040] In some embodiments, the second test unit 200 further includes: a contact structure row, located between the pre-doped gate 71 and the non-pre-doped gate 72, each contact structure row including a plurality of contact structures 75 arranged along the first direction. The contact structure 75 is a conventional electrical structure, and the spacing between each contact structure 75 and the adjacent pre-doped gate 71 or the non-pre-doped gate 72 is fixed and equal. In this embodiment, the contact structure 75 is located in the second region 702. In other embodiments, the contact structure 75 may also be located in the first region 701.

[0041] like Figure 8 As shown, in step S43 of the method for manufacturing the pre-doping process test structure, when the pre-doping process is performed on the polysilicon layer 89 of the first region 801, due to the existence of the photoresist layer 88, the proximity effect of the edge of the pre-doping region may affect the ion implantation amount, such as Figure 8 As shown in the middle label 87, the electrical optimization effect is not obvious. Therefore, the pre-doping process test structure of the present invention also provides a fourth embodiment to test whether the pre-doping process edge shadow has an electrical effect.

[0042] See also Fig. 9 , which is a schematic diagram of the structure of the fourth embodiment of the pre-doping process test structure of the present invention. Fig. 9As shown, the pre-doping process test structure includes a third test unit 300, and the third test unit 300 includes a plurality of first regions 901 arranged at intervals along the second direction D2; a pre-doped gate 91 is formed in each of the first regions 901, and in the second direction D2, there is a first distance from the edge of the pre-doped gate 91 to the edge of the first region 901, and the first distances in the plurality of first regions 901 gradually increase, and the value of the first distance in one of the first regions 901 is a standard value X1, and the values ​​of the first distances in the other first regions 901 are scaled values ​​of the standard value X1 (such as 0.8*X1, 0.9*X1, 1.05*X1, etc.); by testing the electrical parameters of each of the pre-doped gates 91 of the third test unit 300 respectively, it is determined whether there is an electrical influence on the edge shadow of the pre-doping process.

[0043] If the first distance of the third test unit 300 with the best electrical parameters is the standard value X1, it is determined that the edge shadow of the pre-doping process has no effect on the electrical properties of the semiconductor structure; if the first distance of the third test unit with the best electrical parameters is a scaled value of the standard value X1 (such as 0.9*X1), it is determined that the edge shadow of the pre-doping process has an effect on the electrical properties of the semiconductor structure, and the value of the first distance is modified to the scaled value (i.e. 0.9*X1).

[0044] Among them, the standard value X1 is the first distance obtained by the existing technology. The above technical solution sets the scaling values ​​of multiple standard values ​​and measures the electrical properties of multiple test structures to verify whether the edge shadow of the pre-doping process has an electrical impact, and obtains the optimal value of the first distance through testing.

[0045] Based on the same inventive concept, some embodiments of the present invention further provide a pre-doping process testing method.

[0046] See also Fig.10 , which is a flow chart of the steps of the first embodiment of the pre-doping process testing method of the present invention. Fig.10 As shown, the pre-doping process testing method includes the following steps: step S101, providing a first test unit, the first test unit adopts the first test unit described in the present invention; step S102, measuring the first critical dimension of the pre-doped gate and the second critical dimension of the non-pre-doped gate; step S103, obtaining the difference between the first critical dimension of the pre-doped gate and the second critical dimension of the non-pre-doped gate to obtain the critical dimension deviation caused by the pre-doping process.

[0047] Please refer to Figure 3 And step S101, providing a first test unit 100, wherein the first test unit 100 adopts the present invention Figure 3The first test unit 100 shown in FIG. In other embodiments, Figure 6 The second test unit 200 shown executes steps S102 to S103.

[0048] Please refer to Figure 3 And step S102 , measuring a first critical dimension CD1 of the pre-doped gate 31 and a second critical dimension CD2 of the non-pre-doped gate 32 .

[0049] Please refer to Figure 3 And step S103, obtaining the difference between the first critical dimension of the pre-doped gate 31 and the second critical dimension CD2 of the non-pre-doped gate 32, so as to obtain the critical dimension deviation caused by the pre-doping process. In a pre-doping process test structure, two regions are set to form the pre-doped gate 31 and the non-pre-doped gate 32 respectively, and the difference between the first critical dimension CD1 and the second critical dimension CD2 is obtained by measuring the first critical dimension CD1 of the pre-doped gate 31 and the second critical dimension CD2 of the non-pre-doped gate 32 to obtain the critical dimension deviation caused by the doping process, and then the deviation value is set in advance in the etching process to obtain the pre-doped gate and the non-pre-doped gate with the same critical dimensions.

[0050] See also Fig.11 , which is a flow chart of the steps of the second embodiment of the pre-doping process testing method of the present invention. Fig.11 As shown, the pre-doping process testing method also includes the following steps: step S111, providing a second test unit, the second test unit adopts the second test unit described in the present invention; step S112, applying a test voltage at the first pad and the second pad to measure the electrical parameters of the pre-doped gate and the non-pre-doped gate; step S113, judging whether the pre-doping process has an electrical impact based on the electrical parameters of the pre-doped gate and the non-pre-doped gate.

[0051] Please refer to Figure 7 And step S111, providing a second test unit 200, the second test unit 200 adopts the present invention Figure 7 The second test unit 200 is shown.

[0052] Please refer to Figure 7 And step S112, applying a test voltage to the first pad 731 and the second pad 732 to measure the electrical parameters of the pre-doped gate 71 and the non-pre-doped gate 72. In some embodiments, the electrical parameters are capacitance, breakdown voltage or saturation current.

[0053] Please refer to Figure 7And step S113, judging whether the pre-doping process has an electrical impact according to the electrical parameters of the pre-doped gate 71 and the non-pre-doped gate 72. In some embodiments, if the electrical parameters of the pre-doped gate 71 and the non-pre-doped gate 72 are the same, it is determined that the pre-doping process has no electrical impact; if the electrical parameters of the pre-doped gate 71 are different from the electrical parameters of the non-pre-doped gate 72, it is determined that the pre-doping process has an electrical impact. In this embodiment, a plurality of the pre-doped gates 71 are connected in parallel to form the interdigitated gates of the multi-finger gate transistor, and a plurality of the non-pre-doped gates 72 are connected in parallel to form the interdigitated gates of the multi-finger gate transistor.

[0054] In some embodiments, in the second test unit 200: a virtual gate 74 is formed in at least one second region 702 located at the edge of the active area AA, and the virtual gate 74 is electrically connected to a third pad 733; before step S112, the following steps are also included: applying a test voltage at the second pad 732 and the third pad 733 to measure electrical parameters; if the difference between the electrical parameters of the virtual gate 74 and the electrical parameters of the non-pre-doped gate 72 is less than a preset threshold, the test result is determined to be valid; and then step S112 is executed. In this embodiment, the virtual gate 74 is a single transistor, which can be used as a control group for the electrical test of the multi-finger gate transistor.

[0055] See also Fig.12 , which is a flow chart of the steps of the third embodiment of the pre-doping process testing method of the present invention. Fig.12 As shown, the pre-doping process testing method also includes the following steps: step S121, providing a plurality of the second test units, and the pre-doped gates of the plurality of the second test units have different doping amounts; step S122, respectively testing the electrical parameters of the pre-doped gates of the plurality of the second test units; step S123, counting the doping amounts of the second test units corresponding to the electrical parameters that meet the process requirements, so as to obtain the process window of the doping amount.

[0056] Please refer to Figure 7 In step S121, a plurality of second test units 200 are provided, wherein the pre-doped gate electrodes 71 of the plurality of second test units 200 have different doping amounts. Figure 7 The second test unit 200 is shown.

[0057] Please refer to Figure 7 And step S122, respectively testing the electrical parameters of the pre-doped gates 71 of the plurality of second test units 200. In some embodiments, the electrical parameters of the pre-doped gates 71 are measured by applying a test voltage to the first pad 731. The electrical parameters are capacitance, breakdown voltage or saturation current.

[0058] Please refer to Figure 7 And step S123, counting the doping amount of the second test unit 200 corresponding to the electrical parameters that meet the process requirements to obtain the process window of the doping amount.

[0059] See also Fig.13 , which is a flow chart of the steps of the fourth embodiment of the pre-doping process testing method of the present invention. Fig.13 As shown, the pre-doping process testing method also includes the following steps: step S131, providing a third test unit, and the third test unit adopts the third test unit described in the present invention; step S132, testing the electrical parameters of each pre-doped gate of the third test unit respectively to determine whether there is an electrical impact on the edge shadow of the pre-doping process.

[0060] Please refer to Fig. 9 And step S131, providing a third test unit 300, the third test unit 300 adopts the present invention Fig. 9 The third test unit 300 is shown. The edge of the pre-doped gate 91 of the third test unit 300 has a first distance to the edge of the first region 901, and the first distances in the first regions 901 gradually increase. The value of the first distance in one of the first regions 901 is the standard value X1, and the values ​​of the first distances in the other first regions 901 are scaled values ​​of the standard value X1 (such as 0.8*X1, 0.9*X1, 1.05*X1, etc.)

[0061] Please refer to Fig. 9 Step S132, respectively test the electrical parameters of each of the pre-doped gate electrodes 91 of the third test unit 300 to determine whether the edge shadow of the pre-doping process has an electrical impact. In some embodiments, if the first distance of the third test unit 300 with the best electrical parameters is the standard value X1, it is determined that the edge shadow of the pre-doping process has no electrical impact; if the first distance of the third test unit 300 with the best electrical parameters is a scaled value of the standard value X1 (such as 1.05*X1), it is determined that the edge shadow of the pre-doping process has an electrical impact, and the value of the first distance is modified to the scaled value (i.e., 1.05*X1).

[0062] Among them, the standard value X1 is the first distance obtained by the existing technology. The above technical solution sets the scaling values ​​of multiple standard values ​​and measures the electrical properties of multiple test structures to verify whether the edge shadow of the pre-doping process has an electrical impact, and obtains the optimal value of the first distance through testing.

[0063] The above technical solution can also be extended to the influence of static random access memory bit cell (SRAM Bit cell), well region (Well), lightly doped drain (LDD), heavily doped (Plus), and pre-doping mask boundary check (Pre-doping Mask Boundary Check) on electrical properties.

[0064] It should be noted that references in the specification to "an embodiment", "an embodiment", "an exemplary embodiment", "some embodiments", etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. In addition, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, whether or not explicitly described, it is within the knowledge of a technician in the relevant art to implement such feature, structure, or characteristic in conjunction with other embodiments.

[0065] Typically, a term can be understood at least in part from usage in context. For example, the term "one or more" as used herein depends at least in part on the context and can be used to describe any feature, structure or characteristic in a singular sense, or can be used to describe a combination of features, structures or features in a plural sense. Similarly, terms such as "one", "a" or "the" can also be understood to express singular usage or to express plural usage, depending at least in part on the context. In addition, the term "based on" can be understood to not necessarily be intended to express a set of exclusive factors, but can alternatively, also at least in part depending on the context, allow for the presence of other factors that are not necessarily explicitly described. It should also be noted in this specification that "connected / coupled" refers not only to the direct coupling of one component to another component, but also to the indirect coupling of one component to another component through an intermediate component.

[0066] It should be noted that the terms "including" and "having" and their variations involved in the documents of the present invention are intended to cover non-exclusive inclusions. The terms "first", "second", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. Unless the context clearly indicates otherwise, it should be understood that the data used in this way can be interchanged under appropriate circumstances. In addition, the embodiments of the present invention and the features in the embodiments can be combined with each other unless there is a conflict. In addition, in the above description, the description of well-known components and technologies is omitted to avoid unnecessary confusion of the concepts of the present invention. In the above embodiments, each embodiment focuses on the differences from other embodiments, and the same / similar parts between the embodiments can be referred to each other.

[0067] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A pre-doping process test structure, characterized in that: include: A substrate, wherein an active region is defined in the substrate, and the active region includes a first region and a second region; A pre-doped gate is formed on the surface of the active area of ​​the first region, the pre-doped gate extends along a first direction and has a first critical dimension along a second direction; wherein the first direction forms an angle with the second direction; a non-pre-doped gate formed on a surface of the active area of ​​the second region, the non-pre-doped gate extending along the first direction and having a second critical dimension along the second direction; By testing the first critical dimension and the second critical dimension, the critical dimension deviation caused by the pre-doping process can be obtained.

2. The pre-doping process test structure according to claim 1, characterized in that: comprising a first test unit, wherein the first test unit comprises a first area and a second area arranged in parallel along the second direction; A plurality of pre-doped gates are formed in the first region, and the plurality of pre-doped gates extend along the first direction and are arranged along the second direction; A plurality of the non-pre-doped gates are formed in the second region, and the plurality of the non-pre-doped gates extend along the first direction and are arranged along the second direction.

3. The pre-doping process test structure according to claim 1, characterized in that: comprising a second test unit, wherein the second test unit comprises a plurality of the first areas and a plurality of the second areas alternately arranged along the second direction; A pre-doped gate is formed in each of the first regions; A non-pre-doped gate is formed in each of the second regions.

4. The pre-doping process test structure according to claim 2 or 3, characterized in that: The first critical dimension is a critical dimension of any of the pre-doped gates, or the first critical dimension is an average value of critical dimensions of all the pre-doped gates; The second critical dimension is a critical dimension of any one of the non-pre-doped gates, or the second critical dimension is an average value of critical dimensions of all the non-pre-doped gates.

5. The pre-doping process test structure according to claim 3, characterized in that: In the second test unit: a plurality of the pre-doped gates are connected in parallel to a first pad, and a plurality of the non-pre-doped gates are connected in parallel to a second pad; By applying a test voltage to the first pad and the second pad, it can be determined whether the pre-doping process has an electrical impact based on the measured electrical parameters.

6. The pre-doping process test structure according to claim 5, characterized in that: In the second test unit: a dummy gate is formed in at least one second region located at the edge of the active region, and the dummy gate is electrically connected to a third pad; By applying a test voltage to the second pad and the third pad, it is possible to determine whether the test result is valid based on the measured electrical parameters.

7. The pre-doping process test structure according to claim 3, characterized in that: The second test unit further includes: a contact structure row located between the pre-doped gate and the non-pre-doped gate, each contact structure row including a plurality of contact structures arranged along a first direction.

8. The pre-doping process test structure according to claim 1, characterized in that: The method comprises a third test unit, wherein the third test unit comprises a plurality of first regions arranged at intervals along the second direction; a pre-doped gate is formed in each of the first regions, and in the second direction, a first distance is provided between an edge of the pre-doped gate and an edge of the first region, and the first distances in the plurality of first regions gradually increase, a value of the first distance in one of the first regions is a standard value, and values ​​of the first distances in the other first regions are scaled values ​​of the standard value; By testing the electrical parameters of the pre-doped gate of each of the third test units respectively, it is determined whether the edge shadow of the pre-doping process has an electrical impact.

9. A method for manufacturing a pre-doping process test structure, characterized in that: The method comprises the following steps: Providing a substrate, wherein an active region is defined in the substrate, and the active region includes a first region and a second region; Forming a dielectric layer on the surface of the active area and depositing a polysilicon layer on the surface of the dielectric layer; performing a pre-doping process on the polysilicon layer in the first region; The polysilicon layer is patterned to form a pre-doped gate on the surface of the active area in the first region and a non-pre-doped gate on the surface of the active area in the second region, wherein the pre-doped gate extends along a first direction and has a first critical dimension along a second direction, and the non-pre-doped gate extends along the first direction and has a second critical dimension along the second direction, and the first direction forms an angle with the second direction.

10. A pre-doping process testing method, characterized in that: The steps include: Providing a first test unit, wherein the first test unit is the first test unit as claimed in claim 2; Measuring a first critical dimension of a pre-doped gate and a second critical dimension of a non-pre-doped gate; A difference between a first critical dimension of the pre-doped gate and a second critical dimension of the non-pre-doped gate is obtained to obtain a critical dimension deviation caused by a pre-doping process.

11. The method according to claim 10, characterized in that The following steps are also included: Providing a second test unit, wherein the second test unit is the second test unit as claimed in claim 5; Applying a test voltage to the first pad and the second pad to measure electrical parameters of the pre-doped gate and the non-pre-doped gate; Whether the pre-doping process has an electrical impact is determined based on the electrical parameters of the pre-doped gate and the non-pre-doped gate.

12. The method according to claim 11, characterized in that If the electrical parameters of the pre-doped gate and the non-pre-doped gate are the same, it is determined that the pre-doping process has no electrical impact; If the electrical parameters of the pre-doped gate are different from the electrical parameters of the non-pre-doped gate, it is determined that the pre-doping process has an electrical impact.

13. The method according to claim 11, characterized in that In the second test unit: a virtual gate is formed in at least one second area located at the edge of the active area, and the virtual gate is electrically connected to a third pad; before the step of applying a test voltage at the first pad and the second pad to measure the electrical parameters of the pre-doped gate and the non-pre-doped gate, the following steps are also included: applying a test voltage at the second pad and the third pad to measure the electrical parameters; if the difference between the electrical parameters of the virtual gate and the electrical parameters of the non-pre-doped gate is less than a preset threshold value, the test result is determined to be valid, and the step of applying a test voltage at the first pad and the second pad to measure the electrical parameters of the pre-doped gate and the non-pre-doped gate is executed.

14. The method according to claim 11, characterized in that The following steps are also included: Providing a plurality of the second test units, wherein the pre-doped gates of the plurality of the second test units have different doping amounts; Testing the electrical parameters of the pre-doped gates of the plurality of second test units respectively; The doping amount of the second test unit corresponding to the electrical parameter meeting the process requirement is counted to obtain a process window of the doping amount.

15. The method according to claim 11, characterized in that The electrical parameter is capacitance, breakdown voltage or saturation current.

16. The method according to claim 10, characterized in that The following steps are also included: Providing a third test unit, wherein the third test unit is the third test unit as claimed in claim 8; The electrical parameters of each pre-doped gate of the third test unit are tested respectively to determine whether the edge shadow of the pre-doping process has an electrical impact.

17. The method according to claim 16, characterized in that If the first distance of the third test unit with the best electrical parameter is the standard value, it is determined that the edge shadow of the pre-doping process has no electrical impact; If the first distance of the third test unit with the best electrical parameter is a scaled value of the standard value, it is determined that the edge shadow of the pre-doping process has an electrical impact, and the value of the first distance is modified to the scaled value.

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