Antenna device

Abstract

An antenna device comprises a transparent substrate, an antenna electrode layer, an active component layer, a redistribution structure and a wafer. The antenna electrode layer is located on the first face of the transparent substrate and comprises an antenna electrode located in the circuit layout area of the transparent antenna device. The active element layer is located on the second face of the transparent substrate and comprises active elements located in the circuit layout area. The redistribution structure is located on the active component layer and comprises a signal line and a connecting pad which are located in the line layout area. The wafer is bonded to the pad of the redistribution structure and located in the circuit layout area. The transparent antenna device is provided with a light-transmitting area located beside the circuit layout area.

Description

Technical Field

[0001] The invention relates to an antenna device. Background Art

[0002] Wireless communication technology is ubiquitous in modern life. For example, smartphones are usually equipped with wireless communication technology systems such as wireless wide area network systems (Wireless Wide Area Network, WWAN), digital television broadcasting systems (Digital Television Broadcasting System, DTV), satellite positioning navigation systems (Global Positioning System, GPS), wireless local area network systems (Wireless Local Area Network, WLAN), near field communication transmission systems (Near Field Communication, NFC), long-term evolution systems (Long Term Evolution, LTE) and wireless personal network systems (Wireless Personal Network, WLPN). In addition, in important cities or public spaces, providing a wireless local area network environment has become a necessary facility, and many people even set up their own wireless local area network at home.

[0003] Wireless communication devices use their built-in antennas to transmit or receive wireless signals. With the advancement of wireless communication technology, many manufacturers are committed to developing more efficient antenna devices. Summary of the invention

[0004] The present invention provides an antenna device having a light-transmitting area, so that a user can see the landscape behind the antenna device through the antenna device.

[0005] At least one embodiment of the present invention provides a transparent antenna device, which includes a transparent substrate, an antenna electrode layer, an active component layer, a redistribution structure and a chip. The transparent substrate has a first surface and a second surface opposite to the first surface. The antenna electrode layer is located on the first surface of the transparent substrate and includes an antenna electrode located in a circuit layout area of ​​the transparent antenna device. The active component layer is located on the second surface of the transparent substrate and includes an active component located in the circuit layout area. The redistribution structure is located on the active component layer and includes a signal line and a pad located in the circuit layout area. The chip is bonded to the pad of the redistribution structure and is located in the circuit layout area. The transparent antenna device has a light-transmitting area located next to the circuit layout area, and the transmittance of the light-transmitting area is 35% to 85%. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a cross-sectional schematic diagram of an antenna device according to an embodiment of the present invention.

[0007] Figures 2A to 2L It is a cross-sectional schematic diagram of various stages of a manufacturing process of an antenna unit according to an embodiment of the present invention.

[0008] Figure 3A is a partial cross-sectional schematic diagram of an antenna device according to an embodiment of the present invention.

[0009] Figure 3B is a partial cross-sectional schematic diagram of an antenna device according to an embodiment of the present invention.

[0010] Figure 4 is a cross-sectional schematic diagram of an antenna device according to an embodiment of the present invention.

[0011] FIG. 5A to FIG. 5H It is a cross-sectional schematic diagram of various stages of a manufacturing process of an antenna unit according to an embodiment of the present invention.

[0012] Fig. 6A is a partial cross-sectional schematic diagram of an antenna device according to an embodiment of the present invention.

[0013] Figure 6B is a partial cross-sectional schematic diagram of an antenna device according to an embodiment of the present invention.

[0014] Figure 6C is a partial cross-sectional schematic diagram of an antenna device according to an embodiment of the present invention.

[0015] Fig.6D is a partial cross-sectional schematic diagram of an antenna device according to an embodiment of the present invention.

[0016] Figure 7 is a cross-sectional schematic diagram of an antenna device according to an embodiment of the present invention.

[0017] FIG. 8A to FIG. 8C It is a cross-sectional schematic diagram of various stages of a manufacturing process of an antenna unit according to an embodiment of the present invention.

[0018] Fig. 9 is a schematic top view of an antenna device according to an embodiment of the present invention.

[0019] Fig.10 is a cross-sectional schematic diagram of an antenna device according to an embodiment of the present invention.

[0020] Fig.11 is a cross-sectional schematic diagram of an antenna unit according to an embodiment of the present invention.

[0021] Fig.12 is a cross-sectional schematic diagram of an antenna unit according to an embodiment of the present invention.

[0022] Fig.13 is a cross-sectional schematic diagram of an antenna unit according to an embodiment of the present invention.

[0023] Fig.14 is a schematic top view of an antenna unit according to an embodiment of the present invention.

[0024] The reference numerals are as follows:

[0025] 1A,1B,1C,1D,1E,1F,1G: Antenna device

[0026] 10A, 10B, 10C, 10D, 10E, 10F, 10G: Antenna unit

[0027] 100:Transparent substrate

[0028] 110: Antenna electrode layer

[0029] 110', 120', 240': Conductive material layer

[0030] 112,122,132A,132B,222,242: Seed layer

[0031] 112', 122', 242': seed material layer

[0032] 114,124,134A,134B,224,244:Metal layer

[0033] 114', 124', 244': metal material layer

[0034] 120: Conductive layer

[0035] 130A, 130B: Conductive vias

[0036] 140B: Protective layer

[0037] 150: buffer layer

[0038] 160: Conductor layer

[0039] 170: first dielectric layer

[0040] 180: First circuit layer

[0041] 190: Second dielectric layer

[0042] 200: Second circuit layer

[0043] 210: first organic insulating layer

[0044] 220: First redistribution layer

[0045] 230: second organic insulating layer

[0046] 240: Second redistribution layer

[0047] 250: Chip

[0048] 252: Conductive connection structure

[0049] 260: Bottom filling material

[0050] AP: Antenna electrode

[0051] CE: Connecting electrodes

[0052] CH: Semiconductor channel structure

[0053] DP: driving electrode

[0054] GND: Ground electrode

[0055] LR: Circuit layout area

[0056] MM1: First Metal Mesh

[0057] MM2: Second Metal Mesh

[0058] O1: Opening

[0059] P: Pad

[0060] PR1, PR2, PR3, PR4, PR5: Photoresist pattern layer

[0061] RL: Rewiring Structure

[0062] S1: Side 1

[0063] S2: Side 2

[0064] SD: Source / Drain

[0065] SE: Shielding Electrode

[0066] SL1,SL2:Signal line

[0067] ST: Break

[0068] T: Active Components

[0069] TF: Temporary membrane

[0070] TH:Through Hole

[0071] TL: Active Component Layer

[0072] TR: Translucent Zone

[0073] WA,WG:width

[0074] X1, Y1: Line width

[0075] X2, Y2: Line distance DETAILED DESCRIPTION

[0076] Figure 1 is a cross-sectional diagram of an antenna device 1A according to an embodiment of the present invention. Figure 1 , the antenna device 1A includes a transparent substrate 100, an antenna electrode layer 110, an active component layer TL, a redistribution structure RL and a chip 250. In the present embodiment, the antenna device 1A also includes a conductive layer 120, a protective layer 140B, a buffer layer 150 and a bottom filling material 260. The antenna device 1A has a circuit layout area LR and a light-transmitting area TR. The circuit layout area LR includes a chip and various circuits, which makes it difficult for light to pass through the circuit layout area LR. In the present embodiment, the light-transmitting area TR does not contain any metal or other opaque materials, and the transmittance is 70% to 85%, but the present invention is not limited thereto. In other embodiments, a metal mesh is provided in the light-transmitting area TR for light to penetrate. In the present embodiment, the visual transmittance of the circuit layout area LR and the light-transmitting area TR as a whole is 25% to 55%.

[0077] The transparent substrate 100 is made of glass, organic polymer or other applicable materials. Glass is, for example, Pyrex glass. Quartz (such as fused silica glass), soda-lime glass, aluminosilicate glass, borosilicate glass, aluminoborosilicate glass, or other suitable materials or combinations thereof.

[0078] The transparent substrate 100 has a first surface S1 and a second surface S2 opposite to the first surface S1. In some embodiments, the thickness of the transparent substrate 100 is greater than or equal to 0.3 mm, preferably less than or equal to 0.7 mm.

[0079] The conductive via 130A is disposed in the transparent substrate 100 and extends from the first surface S1 of the transparent substrate 100 to the second surface S2. The conductive via 130A is located in the circuit layout region LR. In some embodiments, the material of the conductive via 130A includes copper (Cu), aluminum (Al), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), tungsten (W), conductive oxides (such as indium tin oxide, indium zinc oxide, etc.) or other suitable materials or combinations of the above materials. In the present embodiment, the conductive via 130A includes a seed layer 132A formed on the surface of the substrate through hole of the transparent substrate 100 and a metal layer 134A formed on the seed layer 132A, but the present invention is not limited thereto. In other embodiments, the seed layer 132A may be omitted.

[0080] The antenna electrode layer 110 and the protective layer 140B are located on the first surface S1 of the transparent substrate 100. The material of the antenna electrode layer 110 includes copper (Cu), aluminum (Al), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), tungsten (W), conductive oxides (such as indium tin oxide, indium zinc oxide, etc.) or other suitable materials or combinations of the above materials. In the present embodiment, the antenna electrode layer 110 includes a seed layer 112 formed on the surface of the transparent substrate 100 and a metal layer 114 formed on the seed layer 112, but the present invention is not limited thereto. In other embodiments, the seed layer 112 can be omitted. The antenna electrode layer 110 includes an antenna electrode AP located in the line layout region LR.

[0081] The protective layer 140B covers the antenna electrode layer 110. The protective layer 140B can be used to protect the antenna electrode layer 110 to prevent the antenna electrode layer 110 from being oxidized or damaged during the process. In some embodiments, the protective layer 140B includes an organic material (e.g., polyimide, epoxy resin, etc.) or an inorganic material (e.g., silicon nitride, silicon oxide, etc.) or other suitable materials or a combination of the above materials.

[0082] The conductive layer 120 , the buffer layer 150 , the active device layer TL, the redistribution structure RL, the bottom filling material 260 and the chip 250 are located on the second surface S2 of the transparent substrate 100 .

[0083] The conductive layer 120 and the buffer layer 150 are located between the second surface S2 of the transparent substrate 100 and the active device layer TL. The material of the conductive layer 120 includes copper (Cu), aluminum (Al), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), tungsten (W), conductive oxides (such as indium tin oxide, indium zinc oxide, etc.) or other suitable materials or combinations of the above materials. In the present embodiment, the conductive layer 120 includes a seed layer 122 formed on the surface of the transparent substrate 100 and a metal layer 124 formed on the seed layer 122, but the present invention is not limited thereto. In other embodiments, the seed layer 122 can be omitted.

[0084] The conductive layer 120 includes a ground electrode GND and a connection electrode CE located in the circuit layout region LR. The ground electrode GND at least partially overlaps the antenna electrode AP, and the ground electrode GND surrounds the connection electrode CE. In some embodiments, the connection electrode CE is electrically connected to the antenna electrode AP through a conductive via 130A. In some embodiments, the width W of the ground electrode GND is G Greater than the width W of the antenna electrode AP A .

[0085] The buffer layer 150 covers the conductive layer 120. In some embodiments, the buffer layer 150 includes an organic material (eg, polyimide, etc.) or an inorganic material (eg, silicon nitride, silicon oxide, etc.) or a combination of the above materials.

[0086] The active device layer TL is located on the buffer layer 150 and includes active devices T located in the circuit layout region LR. In this embodiment, the active device layer TL includes a semiconductor layer 160 , a first dielectric layer 170 , a first circuit layer 180 , a second dielectric layer 190 and a second circuit layer 200 .

[0087] The semiconductor layer 160 is located on the buffer layer 150. The semiconductor layer 160 has a single-layer structure or a multi-layer structure, and includes amorphous silicon, polycrystalline silicon, microcrystalline silicon, single crystal silicon, organic semiconductor materials, oxide semiconductor materials (e.g., indium zinc oxide, indium gallium zinc oxide or other suitable materials, or a combination of the above materials) or other suitable materials or a combination of the above materials. In the present embodiment, the semiconductor layer 160 includes a plurality of semiconductor channel structures CH.

[0088] The first dielectric layer 170 is located on the semiconductor layer 160 .

[0089] The first circuit layer 180 is located on the first dielectric layer 170 and includes a plurality of gates G overlapping the semiconductor channel structure CH. Figure 1, the gate G in the first circuit layer 180 is shown, but the present invention is not limited to the first circuit layer 180 only including the gate G. In some embodiments, the first circuit layer 180 includes other conductive structures in addition to the gate G.

[0090] The second dielectric layer 190 is located on the first circuit layer 180 and the first dielectric layer 170 , and covers the gate G.

[0091] The second circuit layer 200 is located on the second dielectric layer 190 and includes a plurality of source / drain electrodes SD and a plurality of signal lines SL1. The source / drain electrodes SD pass through the first dielectric layer 170 and the second dielectric layer 190 and are electrically connected to the corresponding semiconductor channel structure CH. Each active device T includes a corresponding semiconductor channel structure CH, a corresponding gate G, and a corresponding source / drain electrode SD. In some embodiments, the digital signal required by the chip 250 is transmitted through the signal line SL1.

[0092] In some embodiments, the active device layer TL includes various active devices T, which cooperate with each other to form a circuit. By providing a circuit in the active device layer TL, the circuits required to be provided in the chip can be reduced, thereby reducing the size and cost of the chip.

[0093] In some embodiments, the materials of the first dielectric layer 170 and the second dielectric layer 190 include organic polymers (such as polyimide, etc.) or inorganic materials (such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, zirconium oxide, hafnium oxide or other suitable materials or combinations of the above materials). In some embodiments, the materials of the first circuit layer 180 and the second circuit layer 200 include copper (Cu), aluminum (Al), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), tungsten (W), conductive oxides (such as indium tin oxide, indium zinc oxide, etc.) or other suitable materials or combinations of the above materials.

[0094] The redistribution structure RL is located on the active device layer TL. In this embodiment, the redistribution structure RL includes a first organic insulating layer 210 , a first redistribution layer 220 , a second organic insulating layer 230 and a second redistribution layer 240 .

[0095] The first organic insulating layer 210 is located on the second dielectric layer 190 of the active device layer TL.

[0096] The first redistribution layer 220 is located on the first organic insulating layer 210. In some embodiments, part of the first redistribution layer 220 passes through the first organic insulating layer 210 and is electrically connected to the second circuit layer 200 of the active device layer TL, and another part of the first redistribution layer 220 passes through the first organic insulating layer 210, the active device layer TL and the buffer layer 150, and is electrically connected to the ground electrode GND and the connection electrode CE of the conductive layer 120. In some embodiments, the first redistribution layer 220 further includes a shielding electrode SE overlapping the active device T. In some embodiments, a ground signal is applied to the shielding electrode SE to reduce the interference of external signals on the active device T.

[0097] The material of the first redistribution layer 220 includes copper (Cu), aluminum (Al), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), tungsten (W), conductive oxides (such as indium tin oxide, indium zinc oxide, etc.) or other suitable materials or combinations of the above materials. In the present embodiment, the first redistribution layer 220 includes a seed layer 222 and a metal layer 224 formed on the seed layer 222, but the present invention is not limited thereto.

[0098] The second organic insulating layer 230 is located on the first organic insulating layer 210 and the first redistribution layer 220 .

[0099] The second redistribution layer 240 is located on the second organic insulating layer 230 and includes a signal line SL2 and a pad P located in the circuit layout region LR. In some embodiments, a portion of the second redistribution layer 240 passes through the second organic insulating layer 230 and is electrically connected to the first redistribution layer 220. In some embodiments, the signal line SL2 includes, for example, a DC voltage line, a radio frequency (RF) signal input line, an RF signal output line, and the like.

[0100] The material of the second redistribution layer 240 includes copper (Cu), aluminum (Al), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), tungsten (W), conductive oxides (such as indium tin oxide, indium zinc oxide, etc.) or other suitable materials or combinations of the above materials. In the present embodiment, the second redistribution layer 240 includes a seed layer 242 and a metal layer 244 formed on the seed layer 242, but the present invention is not limited thereto.

[0101] In some embodiments, the material of the second organic insulating layer 230 includes polyimide or other suitable materials, and has high transmittance and low dielectric loss (dissipation factor, Df). For example, the transmittance of the second organic insulating layer 230 for light with a wavelength of 400nm to 800nm ​​is greater than 90%. In some embodiments, the dielectric constant (dielectric constant, Dk) of the second organic insulating layer 230 is less than 4, and the dielectric loss is less than 0.004. In some embodiments, the first redistribution layer 220 and / or the second redistribution layer 240 include signal lines for transmitting high-frequency RF signals. The use of a second organic insulating layer 230 with a larger thickness and low dielectric loss is beneficial to reduce the loss of the transmission signal during high-frequency operation. In some embodiments, the thickness of the second organic insulating layer 230 is greater than the thickness of the first dielectric layer 170 and the thickness of the second dielectric layer 190 in the active device layer TL. For example, the thickness of the second organic insulating layer 230 is 50 microns to 100 microns, and the thickness of the first dielectric layer 170 and the thickness of the second dielectric layer 190 are 30 nanometers to 500 nanometers. In some embodiments, the first organic insulating layer 210 is formed by coating, and its thickness ranges from 3 microns or less, and can be used as a flat layer of the second wiring layer 200. In some embodiments, the thickness of the first redistribution layer 220 and the thickness of the second redistribution layer 240 in the redistribution structure RL are greater than the thickness of the first wiring layer 180 and the thickness of the second wiring layer 200 in the active device layer TL.

[0102] The chip 250 is located in the circuit layout region LR and is bonded to the pads P of the redistribution structure RL by surface-mount technology (SMT). In some embodiments, the ground electrode GND, the connection electrode CE, and the active device T are electrically connected to the chip 250 .

[0103] In some embodiments, the chip 250 is bonded to the pad P through the conductive connection structure 252. The conductive connection structure 252 is, for example, solder, conductive glue or other suitable structures. In some embodiments, the bottom filling material 260 is located between the chip 250 and the redistribution structure RL, and surrounds the connection point between the chip 250 and the redistribution structure RL (i.e., the conductive connection structure 252). In some embodiments, the bottom filling material 260 may include a thermal interface material (TIM) to facilitate heat dissipation of the chip 250. For example, the thermal conductivity of the bottom filling material 260 is greater than 0.3W / Mk.

[0104] In some embodiments, the chip 250 includes a beamformer integrated circuit (BFIC) or other active / passive components.

[0105] The antenna device 1A includes a plurality of antenna units 10A in an array, which will be described below in conjunction with Figures 2A to 2L A method for manufacturing the antenna unit 10A in the antenna device 1A will be described.

[0106] Please refer to Figure 2A , providing a transparent substrate 100. The transparent substrate 100 is drilled to have a through hole TH extending from the first surface S1 to the second surface S2. In some embodiments, the method of forming the through hole TH includes laser ablation, wet etching, dry etching, excimer laser ablation or other suitable methods or a combination of the above methods. In the present embodiment, the through hole TH includes a side wall perpendicular to the first surface S1 and the second surface S2, but the present invention is not limited thereto. In other embodiments, the through hole TH includes an inclined side wall. For example, the shape of the through hole TH may be a regular trapezoid or an inverted trapezoid.

[0107] Please refer to Figure 2B , a conductive material is deposited on the transparent substrate 100. The conductive material layer 110' and the conductive material layer 120' are formed on the first surface S1 and the second surface S2 respectively, and the conductive through hole 130A is formed in the through hole TH.

[0108] For example, seed material layers 112' and 122' are formed on the first surface S1 and the second surface S2 of the transparent substrate 100 respectively by sputtering, chemical plating or other suitable processes, and a seed layer 132A is formed in the through hole TH. Then, metal material layers 114' and 124' and a metal layer 134A are formed on the seed material layers 112' and 122' and the seed layer 132A respectively by electroplating. In other embodiments, the seed material layers 112', 122' and the seed layer 132A can be omitted, and the conductive material layer 110', the conductive material layer 120' and the conductive through hole 130A can be formed by chemical plating, physical vapor deposition (such as sputtering, thermal evaporation, electron beam evaporation, etc.), chemical vapor deposition, atomic layer deposition or other suitable methods or combinations of the above methods. In other embodiments, the conductive material layer 110', the conductive material layer 120' and the conductive via 130A may include a cured conductive adhesive, wherein the conductive material layer 110' and the conductive material layer 120' may be formed by coating, printing and other processes, and the conductive via 130A may be formed by a hole filling process. In some embodiments, the material of the conductive material layer 110' and the conductive material layer 120' may be different from the material of the conductive via 130A. When the conductive material layer 110' and the conductive material layer 120' are formed by a printing process, the subsequent patterning process of the conductive material layer 110' and the conductive material layer 120' may be omitted.

[0109] Please refer to Figure 2C , a temporary film TF is attached to the conductive material layer 120', and a photoresist pattern layer PR1 is formed on the conductive material layer 110'.

[0110] Please refer to Figure 2D The conductive material layer 110' is etched using the photoresist pattern layer PR1 as a mask to form an antenna electrode layer 110 including the antenna electrode AP. After the etching process is performed, the photoresist pattern layer PR1 is removed by an ashing process, a stripping process or other suitable processes.

[0111] Please refer to Figure 2E , a protective layer 140B is formed on the antenna electrode layer 110 .

[0112] Please refer to Figure 2F , remove the temporary film TF, and pattern the conductive material layer 120' to obtain the ground electrode GND and the connecting electrode CE. For example, a photoresist pattern layer (not shown) is formed on the conductive material layer 120', and the conductive material layer 120' is etched using the photoresist pattern layer as a mask. Then, the photoresist pattern layer is removed by an ashing process, a stripping process or other suitable processes.

[0113] Please refer to Figure 2G, a buffer layer 150 is formed on the ground electrode GND and the connecting electrode CE.

[0114] Please refer to Figure 2H , forming a semiconductor layer 160, a first dielectric layer 170 and a first wiring layer 180 on the buffer layer 150. In some embodiments, the semiconductor layer 160, the first dielectric layer 170 and the first wiring layer 180 are formed by physical vapor deposition, chemical vapor deposition, atomic layer deposition or other suitable processes. In some embodiments, the semiconductor layer 160 is optionally doped by an ion implantation process or other suitable process.

[0115] Please refer to Fig.2I , forming the second dielectric layer 190 and the second circuit layer 200 on the first dielectric layer 170. In some embodiments, the second dielectric layer 190 and the second circuit layer 200 are formed by physical vapor deposition, chemical vapor deposition, atomic layer deposition or other suitable processes.

[0116] Please refer to Figure 2J , forming a first organic insulating layer 210 on the second dielectric layer 190 and the second wiring layer 200. Next, a plurality of openings are formed in the first organic insulating layer 210 by laser drilling or other suitable processes, and some of the openings also extend through the second dielectric layer 190, the first dielectric layer 170 and the buffer layer 150. Then, a first redistribution layer 220 is formed on the surface of the first organic insulating layer 210 and in the aforementioned openings.

[0117] For example, a blanket seed material layer (not shown) is first formed on the surface of the first organic insulating layer 210 and in the aforementioned opening. Then, a photoresist pattern layer (not shown) is formed on the seed material layer. A metal layer 224 is formed on the portion of the seed material layer exposed by the photoresist pattern layer by an electroplating process. Then, the photoresist pattern layer and the seed material layer located thereunder are removed. The remaining seed material layer is the seed layer 222.

[0118] Please refer to Figure 2K , forming the second organic insulating layer 230 on the first organic insulating layer 210. In some embodiments, the method of forming the second organic insulating layer 230 includes attaching a dry film to the first organic insulating layer 210 or coating a liquid organic material (such as a liquid polyimide (PI) material) on the first organic insulating layer 210.

[0119] Next, a plurality of openings are formed in the second organic insulating layer 230 by laser drilling or other suitable processes. Then, a second redistribution layer 240 is formed on the surface of the second organic insulating layer 230 and in the aforementioned openings.

[0120] For example, a blanket seed material layer (not shown) is first formed on the surface of the second organic insulating layer 230 and in the opening of the second organic insulating layer 230. Then, a photoresist pattern layer (not shown) is formed on the seed material layer. A metal layer 244 is formed on the portion of the seed material layer exposed by the photoresist pattern layer by an electroplating process. Then, the photoresist pattern layer and the seed material layer located thereunder are removed. The remaining seed material layer is the seed layer 242.

[0121] Finally, please refer to Figure 2L , the chip 250 is bonded to the second redistribution layer 240, and a bottom filling material 260 is formed between the chip 250 and the second redistribution layer 240. In some embodiments, the surface of the pad P may be treated with electroless nickel immersion gold (ENIG), immersion silver plating, etc. to improve the yield of the chip bonding process. In some embodiments, before the chip bonding process, an organic material such as an organic solderability preservative (OSP) may be formed on the pad P, which can protect the metal pad from rusting (such as sulfurization or oxidation) due to contact with air, so as to improve the yield of the chip bonding process.

[0122] Figure 3A is a partial cross-sectional schematic diagram of an antenna device according to an embodiment of the present invention. Figure 3A The antenna arrangement is similar to Figure 1 The antenna device 1A is different in that: Figure 3A In the embodiment of FIG. 5 , the width of the conductive via 130A at the side close to the antenna electrode AP is different from the width of the conductive via 130A at the side close to the connection electrode CE. Figure 3A In the embodiment of the present invention, the width of the conductive via 130A on the side close to the antenna electrode AP is greater than the width of the conductive via 130A on the side close to the connection electrode CE, but the present invention is not limited thereto. In other embodiments, the width of the conductive via 130A on the side close to the antenna electrode AP is less than the width of the conductive via 130A on the side close to the connection electrode CE, such as Figure 3B shown.

[0123] Figure 4 is a cross-sectional schematic diagram of an antenna device 1B according to an embodiment of the present invention. It must be noted here that: Figure 4 The implementation examples are used Figure 1 The component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0124] Figure 4 The antenna device 1B and Figure 1 The difference between the antenna device 1A and the antenna device 1B is that in the antenna device 1B, the conductive via 130B and the antenna electrode layer 110 are formed after the second organic insulating layer 230 is formed. The conductive via 130B passes through the second organic insulating layer 230, the first organic insulating layer 210, the second dielectric layer 190, the first dielectric layer 170, the buffer layer 150 and the transparent substrate 100, and extends from the pad P of the redistribution structure RL to the first surface S1 of the transparent substrate 100 to electrically connect the pad P and the antenna electrode AP.

[0125] The antenna device 1B includes a plurality of antenna units 10B in an array, which will be described below in conjunction with FIG. 5A to FIG. 5H A method for manufacturing the antenna unit 10B in the antenna device 1B will be described.

[0126] Please refer to Figure 5A First, a blanket seed material layer 122' is formed on the second surface S2 of the transparent substrate 100 by sputtering, chemical plating or other suitable processes. Then, a photoresist pattern layer PR2 is formed on the seed material layer 122'. A metal layer 124 is formed on the portion of the seed material layer 122' exposed by the photoresist pattern layer by electroplating.

[0127] Please refer to Figure 5B , remove the photoresist pattern layer PR2 and the seed material layer thereunder. The remaining seed material layer is the seed layer 122. In other embodiments, the step of forming the seed material layer 112' can be omitted, and the conductive layer 120 can be formed by chemical plating, physical vapor deposition (e.g., sputtering, thermal evaporation, electron beam evaporation, etc.), chemical vapor deposition, atomic layer deposition, or a combination thereof.

[0128] Please refer to Figure 5C , forming a buffer layer 150, a semiconductor layer 160, a first dielectric layer 170, a first circuit layer 180, a second dielectric layer 190, a second circuit layer 200, a first organic insulating layer 210, a first redistribution layer 220 and a second organic insulating layer 230, the formation methods of the above layers are the same as Figure 2G to Figure 2K The embodiments are similar and will not be described again here.

[0129] Please refer to Figure 5DAfter forming the second organic insulating layer 230, a drilling process is performed to form a plurality of openings O1 in the second organic insulating layer 230 that expose the first redistribution layer 220. In addition, through holes TH are formed that pass through the second organic insulating layer 230, the first organic insulating layer 210, the second dielectric layer 190, the first dielectric layer 170, the buffer layer 150, and the transparent substrate 100. The drilling process includes, for example, laser ablation, wet etching, dry etching, excimer laser ablation, or other suitable methods or a combination of the above methods.

[0130] Please refer to Figure 5E , a conductive material is deposited on the second organic insulating layer 230 and the transparent substrate 100. The conductive material layer 110' and the conductive material layer 240' are formed on the first surface S1 of the transparent substrate 100 and the second organic insulating layer 230, respectively, and the conductive through hole 130B is formed in the through hole TH. The conductive through hole 130B passes through the redistribution structure RL, the active device layer TL, the buffer layer 150 and the transparent substrate 100.

[0131] For example, seed material layers 112', 242' are formed on the first surface S1 of the transparent substrate 100 and the second organic insulating layer 230 respectively by sputtering, chemical plating or other suitable processes, and a seed layer 132B is formed in the through hole TH. Then, metal material layers 114', 244' and metal layer 134B are formed on the seed material layers 112', 242' and the seed layer 132B respectively by electroplating. In other embodiments, the seed material layers 112', 242' and the seed layer 132B can be omitted, and the conductive material layer 110', the conductive material layer 240' and the conductive through hole 130B can be formed by chemical plating, physical vapor deposition (such as sputtering, thermal evaporation, electron beam evaporation (e-beam evaporation)), chemical vapor deposition, atomic layer deposition or a combination thereof. In other embodiments, the conductive material layer 110', the conductive material layer 240' and the conductive via 130B may include a cured conductive adhesive, wherein the conductive material layer 110' and the conductive material layer 240' may be formed by coating, printing and other processes, and the conductive via 130B may be formed by a hole filling process. In some embodiments, the material of the conductive material layer 110' and the conductive material layer 240' may be different from the material of the conductive via 130B. When the conductive material layer 110' and the conductive material layer 240' are formed by a printing process, the subsequent patterning process of the conductive material layer 110' and the conductive material layer 240' may be omitted.

[0132] A photoresist pattern layer PR3 is formed on the conductive material layer 240 ′, and a photoresist pattern layer PR4 is formed on the conductive material layer 110 ′.

[0133] Please refer to Fig. 5F, using the photoresist pattern layer PR3 and the photoresist pattern layer PR4 as masks, an etching process is performed on the conductive material layer 240 ′ and the conductive material layer 110 ′ to form the antenna electrode layer 110 and the second redistribution layer 240 .

[0134] Please refer to Figure 5G , a protective layer 140B is formed on the antenna electrode layer 110 .

[0135] Please refer to Figure 5H , bonding the chip 250 to the second redistribution layer 240 , and forming a bottom filling material 260 between the chip 250 and the second redistribution layer 240 .

[0136] Fig. 6A is a partial cross-sectional schematic diagram of an antenna device according to an embodiment of the present invention. Fig. 6A The antenna arrangement is similar to Figure 4 The antenna device 1B has the following differences: Fig. 6A In the embodiment of FIG. 1 , the width of the conductive via 130B on the side close to the pad P is different from the width of the conductive via 130A on the side close to the antenna electrode AP. Fig. 6A In some embodiments, the width of the conductive via 130B on the side close to the pad P is greater than the width of the conductive via 130B on the side close to the antenna electrode AP. In some embodiments, the conductive via 130B has a step ST near the junction between the transparent substrate 100 and the buffer layer 150, so that part of the conductive via 130B contacts the second surface S2 of the transparent substrate 100. For example, when performing the drilling process (please refer to Figure 5D ), due to the different laser absorption rates of different materials, when the buffer layer 150 (for example, polyimide) and the transparent substrate 100 (for example, glass) are dug through at one time, a step will be formed at the junction of the two, thereby making the width of the conductive via 130B at the buffer layer 150 larger than the width of the conductive via 130B at the transparent substrate 100. Such a step has the additional advantage of reducing the problems caused by thermal stress in subsequent processes.

[0137] Figure 6B is a partial cross-sectional schematic diagram of an antenna device according to an embodiment of the present invention. Figure 6B The antenna arrangement is similar to Figure 4 The antenna device 1B has the following differences: Figure 6B In the embodiment of FIG. 1 , the conductive via 130B has a structure that is wide at the top and bottom sides and narrow in the middle. For example, the conductive via 130B has the smallest width near the junction between the transparent substrate 100 and the buffer layer 150 .

[0138] In some embodiments, during the drilling process (see Figure 5D), laser drilling is first performed from the first side S1 of the transparent substrate 100, and the laser drilling at this time stops at the junction of the transparent substrate 100 and the buffer layer 150. Next, laser drilling is performed from the second organic insulating layer 230, and the resulting drilling hole is connected to the drilling hole previously formed from the first side S1 to obtain a through hole that is wide at the upper and lower sides and narrow in the middle. Finally, a conductive material is filled into the through hole to obtain a conductive through hole 130B that is wide at the upper and lower sides and narrow in the middle. Figure 6B In the embodiment of the present invention, the conductive via 130B has no step difference at the junction of the transparent substrate 100 and the buffer layer 150, but the present invention is not limited thereto. In other embodiments, the conductive via 130B has a step difference ST at the junction of the transparent substrate 100 and the buffer layer 150, such as Figure 6C and Fig.6D shown.

[0139] Figure 7 is a cross-sectional schematic diagram of an antenna device 1C according to an embodiment of the present invention. It must be noted here that: Figure 7 The implementation examples are used Figure 1 The component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0140] Figure 7 The antenna device 1C and Figure 1 The difference between the antenna device 1A and the antenna device 1C is that in the antenna device 1C, the antenna electrode AP is driven by signal coupling.

[0141] In this embodiment, the ground electrode GND has an opening overlapping the antenna electrode AP. The first redistribution layer 220 of the redistribution structure RL includes a driving electrode DP, wherein the driving electrode DP overlaps the opening of the ground electrode GND and the antenna electrode AP.

[0142] The antenna device 1C includes a plurality of antenna units 10C in an array, which will be described below in conjunction with FIG. 8A to FIG. 8C A method for manufacturing the antenna unit 10C in the antenna device 1C will be described.

[0143] Please refer to Fig. 8A , forming a conductive layer 120, a buffer layer 150, a semiconductor layer 160, a first dielectric layer 170, a first wiring layer 180, a second dielectric layer 190, a second wiring layer 200, a first organic insulating layer 210, a first redistribution layer 220 and a second organic insulating layer 230, the formation methods of the above layers are the same as FIG. 5A to FIG. 5C The embodiment is similar to the embodiment of FIG. 1 , and the only difference is that the first redistribution layer 220 of the embodiment includes the driving electrode DP.

[0144] Please refer to Figure 8B A plurality of openings are formed in the second organic insulating layer 230 by laser drilling or other suitable processes. Then, a second redistribution layer is formed on the surface of the second organic insulating layer 230 and in the aforementioned openings.

[0145] For example, a blanket seed material layer 242' is first formed on the surface of the second organic insulating layer 230 and in the opening of the second organic insulating layer 230. Then, a photoresist pattern layer PR5 is formed on the seed material layer 242'. A metal layer 244 is formed on the portion of the seed material layer 242' exposed by the photoresist pattern layer PR5 by an electroplating process.

[0146] Please refer to Figure 8C , remove the photoresist pattern layer PR5 and the seed material layer 242 ′ thereunder. The remaining seed material layer is the seed layer 242 .

[0147] Finally, the chip 250 is bonded to the second redistribution layer 240 , and an underfill material 260 is formed between the chip 250 and the second redistribution layer 240 .

[0148] Fig. 9 is a schematic top view of an antenna device according to an embodiment of the present invention. Fig. 9 The conductive layer 120 of the antenna device, the first circuit layer 180 and the second circuit layer 200 in the active component layer, and the antenna electrode AP are shown, and other components are omitted. The description of other components can refer to any of the above embodiments, and will not be repeated here.

[0149] Please refer to Fig. 9 In this embodiment, the antenna device includes a light-transmitting region TR in which no metal structure is disposed. In this embodiment, the active device layer TL includes a circuit CR, wherein the circuit CR includes a plurality of active devices (not shown). In this embodiment, the active device does not overlap the antenna electrode AP.

[0150] Fig.10 FIG. 1 is a cross-sectional schematic diagram of an antenna unit 10D of an antenna device 1D according to an embodiment of the present invention. It must be noted that: Fig.10 The implementation examples are used Figure 1 The component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0151] Fig.10 The antenna device 1D and Figure 1The difference between the antenna device 1A and the antenna device 1D is that in the antenna device 1D, the antenna electrode AP and / or the conductive layer 120 are embedded in the transparent substrate 100. For example, a groove that can accommodate the antenna electrode AP and / or the conductive layer 120 is first formed on the transparent substrate 100, and then the antenna electrode AP and / or the conductive layer 120 are formed in the groove. With such a design, the antenna device 1D can have a flatter surface.

[0152] Fig.11 1 is a cross-sectional schematic diagram of an antenna unit 10E of an antenna device 1E according to an embodiment of the present invention. It must be noted here that: Fig.11 The implementation examples are used Figures 2A to 2L The component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0153] In the present embodiment, the antenna electrode layer 110 of the antenna device 1E includes an antenna electrode AP and a first metal mesh MM1. The first metal mesh MM1 is connected to the antenna electrode AP. In the present embodiment, the antenna electrode AP is disposed in the circuit layout region LR, and the first metal mesh MM1 extends from the circuit layout region LR to the light-transmitting region TR, so that a first portion of the first metal mesh MM1 is located in the circuit layout region LR, and a second portion of the first metal mesh MM1 is located in the light-transmitting region TR. In some embodiments, the first metal mesh MM1 is only disposed in the light-transmitting region TR, and is not disposed in the circuit layout region LR. In some embodiments, when a metal mesh is included in the light-transmitting region TR, the transmittance of the light-transmitting region TR is between 35% and 83%.

[0154] In some embodiments, the area of ​​the antenna electrode AP is substantially the same as the area of ​​the wafer 250. For example, the area of ​​the antenna electrode AP is 0.8 to 1.2 times the area of ​​the wafer 250 to prevent precision inaccuracy problems in the process.

[0155] In some embodiments, the ratio of the line width Y1 of the first metal mesh MM1 to the line distance Y2 is 1:1 to 1:50, for example, 1:1, 1:10, 1:20, 1:30, 1:40 or 1:50.

[0156] The conductive layer 120 includes a ground electrode GND, a connecting electrode CE, and a second metal mesh MM2. The second metal mesh MM2 is connected to the ground electrode GND. In the present embodiment, the ground electrode GND is disposed in the circuit layout region LR, and the second metal mesh MM2 extends from the circuit layout region LR to the light transmission region TR, so that the first portion of the second metal mesh MM2 is located in the circuit layout region LR, and the second portion of the second metal mesh MM2 is located in the light transmission region TR. In some embodiments, the second metal mesh MM2 is only disposed in the light transmission region TR, and is not disposed in the circuit layout region LR.

[0157] The area of ​​the ground electrode GND is substantially the same as the area of ​​the chip 250. For example, the area of ​​the ground electrode GND is 0.8 to 1.2 times the area of ​​the chip 250 to prevent precision misalignment during the process.

[0158] In some embodiments, the line width X1 of the second metal mesh MM2 is 1:1 to 1:50 compared to the line spacing X2, for example, 1:1, 1:10, 1:20, 1:30, 1:40 or 1:50. In some embodiments, the metal lines in the first metal mesh MM1 are parallel to and overlap the metal lines in the second metal mesh MM2, but the present invention is not limited thereto. In other embodiments, the extension direction of the metal lines in the first metal mesh MM1 is staggered with the extension direction of the metal lines in the second metal mesh MM2.

[0159] In this embodiment, by arranging the first metal mesh MM1 and the second metal mesh MM2 in the light-transmitting region TR, the transmittance of the antenna device 1E can be made more uniform, preventing the user from easily noticing the existence of the circuit layout region LR. In addition, the aperture ratio of the antenna device 1E can be increased, and the warping problem of the antenna device 1E can be reduced.

[0160] In some embodiments, the line width and line spacing of the metal lines in the first metal mesh MM1 and the second metal mesh MM2 will affect the transmittance of the light-transmitting region TR. The transmittance of the light-transmitting region TR without any metal components and the transmittance when the light-transmitting region TR includes one of the first metal mesh MM1 and the second metal mesh MM2 are shown in Table 1.

[0161] Table 1

[0162]

[0163] Fig.12 FIG. 1 is a cross-sectional schematic diagram of an antenna unit 10F of an antenna device 1F according to an embodiment of the present invention. It must be noted that: Fig.12 The implementation examples are used FIG. 5A to FIG. 5H Embodiments and Fig.11The component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0164] Please refer to Fig.12 , the antenna electrode layer 110 of the antenna device 1F includes an antenna electrode AP and a first metal mesh MM1. The first metal mesh MM1 is connected to the antenna electrode AP. In this embodiment, the antenna electrode AP is disposed in the circuit layout region LR, and the first metal mesh MM1 extends from the circuit layout region LR to the light transmission region TR, so that the first part of the first metal mesh MM1 is located in the circuit layout region LR, and the second part of the first metal mesh MM1 is located in the light transmission region TR. In some embodiments, the first metal mesh MM1 is only disposed in the light transmission region TR, and is not disposed in the circuit layout region LR.

[0165] The conductive layer 120 includes a ground electrode GND and a second metal mesh MM2. The second metal mesh MM2 is connected to the ground electrode GND. In the present embodiment, the ground electrode GND is disposed in the circuit layout region LR, and the second metal mesh MM2 extends from the circuit layout region LR to the light-transmitting region TR, so that the first portion of the second metal mesh MM2 is located in the circuit layout region LR, and the second portion of the second metal mesh MM2 is located in the light-transmitting region TR. In some embodiments, the second metal mesh MM2 is only disposed in the light-transmitting region TR, and is not disposed in the circuit layout region LR.

[0166] In this embodiment, by arranging the first metal mesh MM1 and the second metal mesh MM2 in the light-transmitting region TR, the transmittance of the antenna device 1F can be made more uniform, preventing the user from easily noticing the existence of the circuit layout region LR. In addition, the aperture ratio of the antenna device 1F can be increased, and the warping problem of the antenna device 1F can be reduced.

[0167] Fig.13 FIG. 1 is a cross-sectional schematic diagram of an antenna unit 10G of an antenna device 1G according to an embodiment of the present invention. It must be noted that: Fig.13 The implementation examples are used FIG. 8A to FIG. 8C Embodiments and Fig.11 The component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0168] Please refer to Fig.13, the antenna electrode layer 110 of the antenna device 1G includes an antenna electrode AP and a first metal mesh MM1. The first metal mesh MM1 is connected to the antenna electrode AP. In this embodiment, the antenna electrode AP is disposed in the circuit layout region LR, and the first metal mesh MM1 extends from the circuit layout region LR to the light transmission region TR, so that the first part of the first metal mesh MM1 is located in the circuit layout region LR, and the second part of the first metal mesh MM1 is located in the light transmission region TR. In some embodiments, the first metal mesh MM1 is only disposed in the light transmission region TR, and is not disposed in the circuit layout region LR.

[0169] The conductive layer 120 includes a ground electrode GND and a second metal mesh MM2. The second metal mesh MM2 is connected to the ground electrode GND. In the present embodiment, the ground electrode GND is disposed in the circuit layout region LR, and the second metal mesh MM2 extends from the circuit layout region LR to the light-transmitting region TR, so that the first portion of the second metal mesh MM2 is located in the circuit layout region LR, and the second portion of the second metal mesh MM2 is located in the light-transmitting region TR. In some embodiments, the second metal mesh MM2 is only disposed in the light-transmitting region TR, and is not disposed in the circuit layout region LR.

[0170] In this embodiment, by arranging the first metal mesh MM1 and the second metal mesh MM2 in the light-transmitting region TR, the transmittance of the antenna device 1G can be made more uniform, preventing the user from easily noticing the existence of the circuit layout region LR. In addition, the aperture ratio of the antenna device 1G can be increased, and the warping problem of the antenna device 1G can be reduced.

[0171] Fig.14 is a schematic top view of an antenna unit according to an embodiment of the present invention. Fig.14 The antenna device shows an antenna electrode layer (including antenna electrode AP and first metal mesh MM1), a conductive layer (including ground electrode GND and second metal mesh MM2) and a chip 250, and other elements are omitted. The description of other elements can refer to any of the above embodiments, and will not be repeated here.

[0172] Please refer to Fig.14 In this embodiment, the antenna electrode AP in the antenna electrode layer 110 and the ground electrode GND in the conductive layer 120 are arranged in the circuit layout area LR and overlap the chip 250. The first metal mesh MM1 in the antenna electrode layer 110 and the second metal mesh MM2 in the conductive layer 120 overlap each other and are arranged in the light-transmitting area TR. By setting the first metal mesh MM1 and the second metal mesh MM2, the difference in transmittance between the circuit layout area LR and the light-transmitting area TR can be reduced, so as to prevent the user from easily perceiving the existence of the circuit layout area LR.

Claims

1. An antenna device, comprising: A transparent substrate having a first surface and a second surface opposite to the first surface; An antenna electrode layer is located on the first surface of the transparent substrate and includes: An antenna electrode is located in a circuit layout area of ​​the transparent antenna device; An active device layer is located on the second surface of the transparent substrate and includes: an active component located in the circuit layout area; A redistribution structure is located on the active device layer and includes: A signal line and a pad are located in the circuit layout area; and A chip is bonded to the pad of the redistribution structure and is located in the circuit layout area, wherein the transparent antenna device has a light-transmitting area located next to the circuit layout area, and the transmittance of the light-transmitting area is 35% to 85%.

2. The antenna device according to claim 1, further comprising: A conductive layer is located between the second surface of the transparent substrate and the active device layer, and includes: a ground electrode at least partially overlapping the antenna electrode and electrically connected to the chip; and a connection electrode electrically connected to the chip, wherein the ground electrode surrounds the connection electrode; and A conductive through hole extends from the first surface of the transparent substrate to the second surface and connects the antenna electrode and the connecting electrode. 3 . The antenna device as claimed in claim 2 , wherein a width of the conductive via at a side close to the antenna electrode is different from a width of the conductive via at a side close to the connection electrode.

4. The antenna device according to claim 1, further comprising: A conductive via extends from the pad of the redistribution structure to the first surface of the transparent substrate, wherein the conductive via passes through the active component layer and the transparent substrate and electrically connects the antenna electrode and the pad.

5. The antenna device according to claim 1, further comprising: A conductive layer is located between the second surface of the transparent substrate and the active device layer, and includes: A ground electrode at least partially overlaps the antenna electrode and is electrically connected to the chip, wherein the ground electrode includes an opening overlapping the antenna electrode; wherein the rewiring structure also includes a driving electrode, which overlaps the opening and the antenna electrode.

6. The antenna device according to claim 1, further comprising: A bottom filling material is located between the chip and the redistribution structure and surrounds the contact between the chip and the redistribution structure.

7. The antenna device as claimed in claim 1, wherein the antenna electrode layer further comprises: A first metal mesh is electrically connected to the antenna electrode, wherein the line width ratio of the first metal mesh is 1:1 to 1:50, wherein the first portion of the first metal mesh is located in the circuit layout area, and the second portion of the first metal mesh is located in the light-transmitting area.

8. The antenna device according to claim 1, further comprising: A conductive layer is located between the second surface of the transparent substrate and the active device layer, and includes: a ground electrode at least partially overlapping the antenna electrode and electrically connected to the chip; and A second metal mesh is connected to the ground electrode, wherein the line width ratio of the second metal mesh is 1:1 to 1:50, and wherein the second metal mesh is at least partially located in the light-transmitting area.

9. The antenna device according to claim 1, further comprising: A conductive layer is located between the second surface of the transparent substrate and the active device layer, and includes: A ground electrode at least partially overlaps the antenna electrode and is electrically connected to the chip, wherein the width of the ground electrode is greater than the width of the antenna electrode.

10. The antenna device as claimed in claim 1, wherein the active component layer comprises: a semiconductor channel structure; a first dielectric layer located on the semiconductor channel structure; a gate overlapping the semiconductor channel structure; A plurality of source / drain electrodes electrically connected to the semiconductor channel structure, wherein the active device comprises the semiconductor channel structure, the gate and the plurality of source / drain electrodes; The rewiring structure includes: a first organic insulating layer, located on the active device layer; a first redistribution layer, located on the first organic insulating layer; a second organic insulating layer, located on the first organic insulating layer, wherein the thickness of the second organic insulating layer is greater than the thickness of the first dielectric layer; and A second redistribution layer is located on the second organic insulating layer and includes the pad and the signal line.

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