Signal processing circuit

Abstract

The present disclosure relates to a signal processing circuit, comprising: a channel sampling unit (20), including a first terminal (IN1+) and a second terminal (IN1−) connected to a sensor (10) and a sampling circuit (22), the sampling circuit (22) being configured to allow a positive current and a negative current from the sensor (10) to flow between the first terminal (IN1+) and the second terminal (IN1−) and including a sampling end (P1) provided on a current path between the first terminal (IN1+) and the second terminal (IN1−), wherein the current direction of the positive current is opposite to the current direction of the negative current; a signal modulation unit (30), configured to obtain a sampling voltage at the sampling end (P1) and process the sampling voltage to generate a first processed signal; and a processor (40), configured to receive the first processed signal and generate an output signal based on the first processed signal.

Description

Technical Field

[0001] The present disclosure relates to the field of signal acquisition, and more particularly to a signal processing circuit for processing sensor signals. Background Art

[0002] In the field of signal acquisition, the state of the equipment can be effectively detected by acquiring the signal from the sensor. As an application example, the engine is usually equipped with a cylinder pressure signal acquisition system and is configured to collect the in-cylinder pressure signal at high speed. The in-cylinder pressure signal is usually a current signal, generally in the range of -20mA~20mA. Through the acquisition of the in-cylinder pressure signal and comprehensive calculation and analysis, on the one hand, thermodynamic parameters such as explosion pressure, mean effective pressure, and heat release rate can be obtained; on the other hand, the combustion state of the engine can be judged in real time, and abnormal combustion phenomena can be identified and warned. The traditional signal processing circuit used to process signals from sensors is not satisfactory in terms of performance, and there is a need to further improve the signal processing circuit. Summary of the invention

[0003] An object of the present disclosure is to provide a signal processing circuit that aims to solve one or more of the above problems and other potential problems.

[0004] One aspect of the present disclosure provides a signal processing circuit. The signal processing circuit includes: a channel sampling unit, including a first terminal and a second terminal respectively connected to a first end and a second end of a sensor and a sampling circuit arranged between the first terminal and the second terminal, the sampling circuit is configured to allow a positive current and a negative current from the sensor to flow between the first terminal and the second terminal and includes a sampling terminal arranged on a current path between the first terminal and the second terminal, wherein the current direction of the positive current is opposite to the current direction of the negative current; a signal modulation unit, configured to obtain a sampling voltage at the sampling terminal and process the sampling voltage to generate a first processed signal; and a processor, configured to receive the first processed signal and generate an output signal based on the first processed signal.

[0005] In some embodiments, the sampling circuit includes: a first MOS tube; a sampling resistor; a current limiting resistor connected in series with the sampling resistor; and a second MOS tube; wherein the first end of the first MOS tube is connected to the sampling resistor, the second end of the first MOS tube is connected to the first terminal, the sampling end is arranged at a first node where the first end of the first MOS tube and the sampling resistor are connected to each other, the first end of the second MOS tube is connected to the current limiting resistor, the second end of the second MOS tube is connected to the second terminal, and the second node where the sampling resistor and the current limiting resistor are connected to each other is grounded.

[0006] In some embodiments, the first MOS transistor and the second MOS transistor are packaged in the same chip and share a heat sink.

[0007] In some embodiments, the signal processing circuit also includes a voltage limiting unit, which is configured to limit the voltage at the first node to a predetermined voltage range, wherein the voltage limiting unit includes a forward current limiting branch and a negative current branch connected in parallel with the forward current limiting branch, and each of the current branches includes one or more diodes connected in series with each other.

[0008] In some embodiments, the processor includes a signal type identification module configured to: identify the output signal as an analog quantity in response to the first processed signal being within a first range.

[0009] In some embodiments, the signal identification module is further configured to: identify the output signal as a switch quantity in response to the first processed signal being in a second range, wherein the second range includes a high logic level range and a low logic level range, the minimum value of the high logic level range is greater than the maximum value of the first range, and the maximum value of the low logic level range is less than the minimum value of the first range.

[0010] In some embodiments, the signal type identification module is configured to: determine that the first processed signal belongs to an analog quantity in response to determining that the first processed signal is in the first range during multiple consecutive sampling periods; and / or determine that the first processed signal belongs to a switch quantity in response to determining that the first processed signal is in the second range during multiple consecutive sampling periods.

[0011] In some embodiments, the signal processing circuit further includes a channel switch control unit configured to activate or deactivate a channel sampling unit based on a channel switch signal from the processor; wherein the gate of the first MOS tube and the gate of the second MOS tube are connected to the same third node, and the third node is a voltage node in the channel switch control unit.

[0012] In some embodiments, the channel switch control unit includes: a first voltage-dividing resistor; a second voltage-dividing resistor connected in series with the first voltage-dividing resistor; and a third MOS tube, the second end of the third MOS tube is connected to the third node, the first voltage-dividing resistor is connected to the second voltage-dividing resistor at the third node, and the first end of the third MOS tube is connected to the other end of the second voltage-dividing resistor; wherein the voltage node is the third node; wherein the third MOS tube is configured to be turned off based on a channel turn-on signal from the processor, so that the first MOS tube and the second MOS tube can be turned on based on the voltage at the third node; the third MOS tube is configured to be turned on based on a channel turn-off signal from the processor, so that the first MOS tube and the second MOS tube are turned off.

[0013] In some embodiments, the channel switch control unit also includes a delay unit, which is configured to: turn off the third MOS tube without delay in response to a channel turn-on signal from the processor; and turn on the third MOS tube after a predetermined time delay in response to the channel turn-off signal from the processor.

[0014] In some embodiments, the delay unit includes: a resistor, one end of which is connected to the channel-on end of the processor and is configured to receive the channel-on signal from the processor, and the other end of the resistor is connected to the gate of the third MOS tube; a capacitor, one end of which is grounded and the other end is connected to the connection node between the resistor and the third MOS tube; and a diode, which is connected in parallel with the resistor and is configured to discharge the amount stored in the capacitor through the diode in response to the channel-off signal from the processor.

[0015] In some embodiments, the processor is configured such that: the first processed signal sampled in an initial predetermined number of sampling cycles after the channel sampling unit is activated is not used to generate the output signal, and the first processed signal sampled after the initial predetermined number of sampling cycles after the channel sampling unit is activated is used to generate the output signal.

[0016] In some embodiments, the signal processing circuit further includes: a redundant channel sampling unit, the redundant channel sampling unit including a third terminal and a fourth terminal respectively connected to the first end and the second end of the sensor and a second sampling circuit arranged between the third terminal and the fourth terminal, the second sampling circuit being configured to allow positive current and negative current from the sensor to flow between the third terminal and the fourth terminal and including a second sampling terminal arranged on a current path between the third terminal and the fourth terminal; a second signal modulation unit configured to acquire a sampling voltage at the second sampling terminal and process the sampling voltage to generate a second processed signal; and the processor being configured to receive the second processed signal and generate the output signal based on the second processed signal.

[0017] In some embodiments, the redundant channel sampling unit is configured as a redundant signal acquisition channel of the channel sampling unit, and the processor also includes redundant control logic, which is configured to activate the channel sampling unit and one of the redundant channel sampling units based on predetermined rules, and make the redundant channel sampling unit disabled when the channel sampling unit is enabled; and the channel sampling unit disabled when the redundant channel sampling unit is enabled.

[0018] The signal processing circuit according to the present disclosure can achieve one or more of the following technical effects:

[0019] Positive and negative bidirectional current collection can be realized;

[0020] It has protection capabilities such as channel short circuit, overcurrent, and misconnection;

[0021] Supports multiple signal acquisitions, for example, it can not only realize the acquisition of analog current signals (such as pressure sensors), but also the acquisition of switch voltage signals (such as Hall sensors, magnetoelectric sensors);

[0022] Possessing adaptive sampling mode function for various signal acquisitions;

[0023] Support multi-channel redundant configuration;

[0024] It has the function of preventing the device from powering off and restarting during multi-channel switching. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The above and other objects, features and advantages of the embodiments of the present disclosure will become readily understood by reading the following detailed description with reference to the accompanying drawings. In the accompanying drawings, several embodiments of the present disclosure are shown by way of example and not limitation.

[0026] Figure 1 An overall schematic diagram of a signal processing system according to an embodiment of the present disclosure is shown.

[0027] Figure 2 A schematic diagram of implementing a channel sampling unit of a signal processing circuit according to an embodiment of the present disclosure is shown.

[0028] Figure 3 A structural schematic diagram of a signal processing system according to another embodiment of the present disclosure is shown.

[0029] Figure 4 A schematic diagram of implementing a channel switch control unit of a signal processing circuit according to the present disclosure is shown.

[0030] Figure 5 An overall schematic diagram of a signal processing circuit including a redundant channel sampling unit according to the present disclosure is shown. DETAILED DESCRIPTION

[0031] Unless otherwise indicated, corresponding numbers and symbols in different figures generally refer to corresponding regions. The accompanying drawings are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale. The edges of features drawn in the drawings do not necessarily represent the end of the feature range.

[0032] References to "one embodiment" or "an implementation" in the framework of this specification are intended to indicate that a particular configuration, structure, or characteristic described with respect to the embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment," "in one embodiment," etc., which may appear in various aspects of this specification, do not necessarily refer to exactly the same embodiment. Furthermore, particular configurations, structures, or characteristics may be combined in any appropriate manner in one or more embodiments.

[0033] Figure 1 FIG. 1 shows an overall schematic diagram of a signal processing system 1 according to an embodiment of the present disclosure. Figure 1 As shown, the signal processing system 1 may include one or more sensors 10 and a signal processing circuit suitable for processing the signal from the sensor 10. The signal processing circuit may include a channel sampling unit 20, a signal modulation unit 30 and a processor 40. The channel sampling unit 20 is connected to the sensor 10. The channel sampling unit 20 may include a connection terminal suitable for connecting to the corresponding terminal of the sensor, and the voltage sampled by the channel sampling unit 20 may be output to the signal modulation unit 30, and the signal modulation unit 30 is configured to receive the sampled voltage from the channel sampling unit 20 and convert it into a suitable voltage signal suitable for processing by the processor 40. The processor 40 receives the signal from the signal modulation unit 30 and processes and / or identifies the signal, and outputs the processing and / or identification result to the output unit 50. In some embodiments, the output unit 50 may be, for example, an upper-level processing unit that communicates with the processor 40.

[0034] Figure 2 FIG. 2 shows a schematic diagram of implementing a channel sampling unit 20 of a signal processing circuit according to an embodiment of the present disclosure. Figure 2 As shown, the channel sampling unit 20 includes a first terminal IN1+ and a second terminal IN1 − respectively connected to the first end and the second end of the sensor 10 , and a sampling circuit 22 disposed between the first terminal IN1+ and the second terminal IN1 −.

[0035] The sampling circuit 22 includes a sampling terminal P arranged on a current path between a first terminal IN1+ and a second terminal IN1-. 1 (also referred to as the first node). According to the present disclosure, the first sampling circuit 22 is configured to allow positive current and negative current from the sensor 10 to flow between the first terminal IN1+ and the second terminal IN1-. The current direction of the positive current is opposite to the current direction of the negative current. Thus, the first sampling circuit 22 can realize the collection of positive and negative current signals from the sensor 10.

[0036] like Figure 2 As shown, the sampling circuit 22 may include: a first MOS transistor Q1, a sampling resistor R1, a current limiting resistor R2, and a second MOS transistor Q2. The source of the first MOS transistor Q1 is connected to one end of the sampling resistor R1, and the drain of the first MOS transistor Q1 is connected to the first terminal IN1+. The source of the second MOS transistor Q2 is connected to the current limiting resistor R2, and the drain of the second MOS transistor Q2 is connected to the second terminal IN1-. The sampling terminal P 1 A first node P is set at which the current input terminal of the first MOS tube Q1 and the sampling resistor R1 are connected to each other. 1 The second node P where the sampling resistor R1 and the current limiting resistor R2 are connected to each other 2 The gate of the first MOS transistor Q1 and the gate of the second MOS transistor Q2 may be controlled synchronously. In some embodiments, as shown in the figure, the gate of the first MOS transistor Q1 and the gate of the second MOS transistor Q2 may be connected together.

[0037] In the illustrated embodiment, the first MOS transistor Q1 and the second MOS transistor Q2 are both NMOS transistors, the source of the NMOS transistor corresponds to the first end; the drain of the NMOS transistor corresponds to the second end. It should be understood that the illustrated embodiment is only exemplary, and the MOS transistor may also be a PMOS transistor.

[0038] When the current from the sensor 10 is a positive current, the current flows in the direction of IN1+—Q1—R1—R2—Q2—IN1-. When the current from the sensor 10 is a negative current, the current flows in the direction of IN1—Q2—R2—R1—Q1—IN1+.

[0039] According to the present disclosure, the sampling circuit 22 also has a circuit protection function. When the current from the sensor 10 is a forward current, Q1, R1, and the source-drain voltage V applied to the MOS tube Q1 MOS Together they form a forward current limiting unit to limit excessive forward current. 2 grounded, so the current applied to R1 is (V MOS -V GS ) / R1,V GS is the source-gate voltage of Q1. Similarly, when the current from the sensor 10 is negative, Q2, R2, and the source-drain voltage V applied to the MOS tube Q2 are MOS Together they form a negative current limiting unit to limit excessive negative current. 2 The point is grounded, so the current applied to R1 is (V MOS -V GS ) / R1,V GS is the source-gate voltage of Q2. Thus, the above circuit structure of the sampling circuit can provide a protection function for the entire sampling circuit. This is particularly beneficial when the signal processing circuit samples multiple types of circuits.

[0040] In some embodiments, due to the positive current limit and negative current limit voltage V MOS The two NMOS can be packaged in the same chip. On the one hand, the same package makes it easier to make the turn-on voltage of the two NMOS consistent. On the other hand, the positive current limiting and negative current limiting only work in one direction at a time, so they only need to share the heat dissipation part. Therefore, using one package for two chips saves cost and space.

[0041] In some embodiments, the sampling circuit 22 may further include a voltage limiting unit 24, which is configured to limit the voltage of the first node P 1 The voltage at the first node P 1 The voltage at the voltage limiting unit 24 is too large. In some embodiments, the voltage limiting unit 24 includes a forward current limiting branch and a negative current branch connected in parallel with the forward current limiting branch. The forward current limiting branch may include one or more diodes D1, D2 connected in series with each other; the negative current limiting branch may include one or more diodes D3, D4 connected in series with each other. In the illustrated embodiment, two diodes are used, but it should be understood that other numbers of diodes, such as one or more, may also be used. The resistance value of R1 can be appropriately selected in combination with the voltage to prevent the influence of the leakage current of the MOS tube on the sampling error when collecting small currents.

[0042] In some embodiments, the signal processing circuit supports the acquisition of multiple types of sensor signals. This is particularly beneficial in some application scenarios. For example, in engine applications, in addition to collecting the in-cylinder pressure signal (usually a current signal), it is also necessary to collect a key phase digital signal representing the speed (such as a magnetoelectric sensor or a Hall sensor, such as a voltage signal of tens of volts). In this case, the signal processing circuit needs to be able to support the acquisition of signals for the pressure sensor and the magnetoelectric sensor or the Hall sensor at the same time.

[0043] According to the present disclosure, the processor 40 may include a signal type identification module, which is configured to: identify the output signal as an analog quantity in response to the first processed signal being in the first range. This corresponds to, for example, a scenario in which the signal applied between the first terminal IN1+ and the second terminal IN1- of the sampling circuit 22 is a current signal from a pressure sensor. The pressure sensor is used, for example, to collect the pressure in the cylinder of the engine, and the pressure signal is in the form of a current signal. After the current signal from the pressure sensor is applied between the first terminal IN1+ and the second terminal IN1- of the sampling circuit 22, the sampling terminal P is obtained. 1 The processor 40 determines that the first processed signal is an analog quantity from the pressure sensor according to the magnitude of the first processed signal.

[0044] In some embodiments, the signal identification module of the processor 40 is further configured to: identify the output signal as a switch quantity in response to the first processed signal being in a second range, wherein the second range includes a high logic level range and a low logic level range, the minimum value of the high logic level range is greater than the maximum value of the first range, and the maximum value of the low logic level range is less than the minimum value of the first range. This corresponds to, for example, a scenario in which the signal applied between the first terminal IN1+ and the second terminal IN1- of the sampling circuit 22 is a voltage signal from a magnetoelectric sensor or a Hall sensor. The magnetoelectric sensor or the Hall sensor is used, for example, to collect a key phase digital signal representing the speed of the engine, and the speed signal is, for example, in the form of a voltage signal indicating high and low logic levels. After the voltage signal from the magnetoelectric sensor or the Hall sensor is applied between the first terminal IN1+ and the second terminal IN1- of the sampling circuit 22, the sampling terminal P is obtained. 1 The processor 40 determines that the first processed signal is a switch quantity from a magnetoelectric sensor or a Hall sensor according to the magnitude of the first processed signal.

[0045] In some embodiments, the signal type identification module is configured to: determine that the first processed signal belongs to an analog quantity in response to determining that the first processed signal is in the first range in a plurality of consecutive sampling periods; and / or determine that the first processed signal belongs to a switch quantity in response to determining that the first processed signal is in the second range in a plurality of consecutive sampling periods. Thus, erroneous identification can be prevented.

[0046] According to the signal processing circuit disclosed in the present invention, it is possible to collect signals of multiple types of sensors, including analog and switch signals. As an application example of engine scenarios, it not only supports the signal collection of pressure sensors, but also supports the signal collection of speed sensors such as Hall sensors and magnetoelectric sensors.

[0047] Figure 3 A structural schematic diagram of a signal processing circuit according to another embodiment of the present disclosure is shown. Figure 3 The embodiment shown is Figure 1 The embodiment shown is similar except that Figure 3 The signal processing circuit of the illustrated embodiment further includes a channel switch control unit 60 for controlling whether the channel sampling unit 20 is working. The channel switch control unit 60 can selectively enable or disable the channel sampling unit 20 based on a signal from the processor 40. By selectively enabling or disabling (e.g., by means of the signal CH1) the channel sampling unit 20, the signal processing circuit can be allowed to select a desired signal acquisition channel. This arrangement is particularly useful when the signal processing circuit has multiple signal acquisition channels.

[0048] Figure 4 FIG. 4 shows a schematic diagram of implementing a channel switch control unit 60 of a signal processing circuit according to the present disclosure. Figure 4 As shown, the channel switch control unit 60 is configured to activate or deactivate the channel sampling unit 20 based on the channel switch signal CH1 from the processor 40. The channel switch signal CH1 can be a high level or low level switch signal. 3 It can be connected to the gate of the first MOS transistor Q1 and the gate of the second MOS transistor Q2. 3 The voltage is used to control the on / off of the first MOS tube Q1 and the second MOS tube Q2.

[0049] In some embodiments, Figure 4 As shown, the channel switch control unit 60 includes: a first voltage-dividing resistor R3, one end of which is connected to a power supply; a second voltage-dividing resistor R4 connected in series with the first voltage-dividing resistor R3, the first voltage-dividing resistor R3 at a third node P 3The drain of the third MOS tube Q3 is connected to the third node P 3 The source of the third MOS transistor Q3 is connected to the other end of the second voltage-dividing resistor R4 and is grounded. In the illustrated embodiment, the MOS transistor Q3 is illustrated as an NMOS transistor, but it should be understood that this is merely exemplary, and the MOS transistor Q3 may also be a PMOS transistor.

[0050] In some embodiments, the third MOS transistor Q3 is configured to be turned off based on the channel turn-on signal CH1 from the processor 40, so that the first MOS transistor Q1 and the second MOS transistor Q2 can be turned on based on the voltage at the third node; the third MOS transistor Q3 is configured to be turned on based on the channel turn-off signal from the processor 40, so that the first MOS transistor Q1 and the second MOS transistor Q2 are turned off.

[0051] As an example, Figure 4 As shown, when CH1 is at a high level, Q3 is turned on. Since the source of Q3 is grounded, the third node P 3 is low level; accordingly, the first MOS transistor Q1 and the second MOS transistor Q2 are turned off. Similarly, when CH1 is low level, Q3 is turned off. Since the source of Q3 is grounded, the third node P 3 is high level; accordingly, the first MOS tube Q1 and the second MOS tube Q2 are turned on.

[0052] In some embodiments, Figure 4 As shown, the channel switch control unit 60 also includes a delay unit 62, which is configured to: turn off the third MOS tube Q3 without delay in response to the channel turn-on signal from the processor 40; and turn on the third MOS tube Q3 after a predetermined time delay in response to the channel turn-off signal from the processor 40.

[0053] Through such an arrangement, when the channel sampling unit 20 is enabled, the channel sampling unit 20 can be enabled without delay; and when the channel sampling unit 20 is disabled, the channel sampling unit 20 can be disabled with a delay for a period of time. This can effectively prevent the electrical circuit where the channel sampling unit 20 is located from being immediately powered off after the channel sampling unit 20 is disabled. In some application scenarios, for example, when the sensor needs to be powered by the electrical circuit where the channel sampling unit 20 is located, once the electrical circuit where the channel sampling unit 20 is located is immediately powered off, the sensor will be powered off and cannot work normally. Even if the electrical circuit where the sensor is located is powered on again, the sensor needs to be restarted to work normally, which will take a long time. As an example, when the sensor is a two-wire sensor, the power supply line and signal line of the sensor are shared. When the enabled state and the disabled state are switched, it is possible that two channels are temporarily disabled at the same time, which will cause the sensor to lose power. The sensor power failure usually has a long restart process, which seriously affects the signal acquisition.

[0054] In some embodiments, Figure 4 As shown, the delay unit 62 includes: a resistor R5, one end of which is connected to the channel-on end of the processor 40 and is configured to receive a channel-on signal CH1 from the processor 40, and the other end of the resistor is connected to the gate of the third MOS tube Q3; a capacitor C1, one end of which is grounded, and the other end of which is connected to a connection node P4 between the resistor R5 and the third MOS tube Q3; and a diode D5, which is connected in parallel with the resistor R5 and is configured to discharge the amount stored in the capacitor C1 through the diode D5 in response to a channel-off signal from the processor 40.

[0055] When the channel sampling unit 20 is converted from the enabled state to the disabled state, CH1 will change from a low level (e.g., 0) to a high level (e.g., 1) to turn on the third MOS tube Q3. After CH1 changes from 0 to 1, due to the charging process of R5 and C1, it takes a certain charging time for the gate voltage at Q3 to change from low to high. As a result, it will take a certain delay time for the enabled state to be converted to the disabled state. On the other hand, when CH1 changes from 1 to 0, the charge of C1 is quickly discharged through the diode D5, thereby quickly converting from the disabled state to the enabled state.

[0056] In some embodiments, the processor 40 is configured such that: the first processed signal sampled in the first predetermined number of sampling cycles after the channel sampling unit 20 is activated is not used to generate the output signal, and the first processed signal sampled after the first predetermined number of sampling cycles after the channel sampling unit 20 is activated is used to generate the output signal. In this case, the error that may be caused by the first few samplings between the deactivation and activation switching of the channel sampling unit 20 can be avoided. According to the present disclosure, by adopting the delay unit, the power-off problem of the sensor can be effectively avoided, thereby affecting the acquisition of the signal.

[0057] Figure 5 An overall schematic diagram of a signal processing circuit including a redundant channel sampling unit according to the present disclosure is shown. Figure 5 The embodiment shown is Figure 3 The embodiment shown is similar to the embodiment shown in FIG. 1 , except that the signal processing circuit may include a second channel sampling unit 20b as a redundant channel sampling unit. Figure 5 As shown, the signal processing circuit may include a plurality of sampling channels, namely a first channel sampling unit 20a and a second channel sampling unit 20b as a redundant channel sampling unit. Each channel sampling unit 20a, 20b is similar to the aforementioned reference Figure 2 The channel sampling unit 20 is similar to the above-mentioned channel sampling unit 20, and its detailed description is omitted. Each channel sampling unit 20a, 20b may include a respective channel switch control unit 60a, 60b. Each channel switch control unit 60a, 60b is similar to the above-mentioned reference Figure 4 The channel switch control unit 60 is similar, and its detailed description is omitted.

[0058] In some embodiments, Figure 5 As shown, the processor 40 may also include a redundant control logic, which is configured to activate one of the channel sampling unit 20a and the redundant channel sampling unit 20b based on a predetermined rule, and when the channel sampling unit 20a is enabled, the redundant channel sampling unit 20b is disabled; when the redundant channel sampling unit 20b is enabled, the channel sampling unit 20a is disabled. The predetermined rule may correspond to an abnormality or failure of the channel sampling unit, for example. For example, when the channel sampling unit 20a is in a normal operating state, if no signal from the channel sampling unit 20a is detected within a predetermined period, the processor 40 considers that the channel sampling unit 20a is operating abnormally. In this case, the redundant control logic instruction of the processor 40 disables the channel sampling unit 20a and enables the channel sampling unit 20b.

[0059] like Figure 5As shown, the processor 40 can send channel switch signals CH1 and CH2 to the channel switch control units 60a and 60b, respectively, and the channel sampling units 20a and 20b can enter an enabled state or a disabled state based on the channel switch signals CH1 and CH2. CH1 and CH2 can be inverse to each other, for example, if CH1 is 0, then CH2 is 1; or, if CH1 is 1, then CH2 is 0.

[0060] According to the present disclosure, the signal processing circuit supports redundant configuration of the channel sampling units, thereby further improving the reliability of the system.

[0061] Through the teachings given in the above description and the related drawings, many modifications and other embodiments of the present disclosure given here will be recognized by those skilled in the art of the present disclosure. Therefore, it is to be understood that the embodiments of the present disclosure are not limited to the specific embodiments disclosed, and modifications and other embodiments are intended to be included in the scope of the present disclosure. In addition, although the above description and the related drawings describe the example embodiments in the context of some example combinations of parts and / or functions, it should be appreciated that different combinations of parts and / or functions can be provided by alternative embodiments without departing from the scope of the present disclosure. In this regard, for example, other combinations of parts and / or functions that are different from those clearly described above are also expected to be within the scope of the present disclosure. Although specific terms are used here, they are only used in a general and descriptive sense and are not intended to be limited.

Claims

1. A signal processing circuit, comprising: A channel sampling unit (20), comprising a first terminal (IN1+) and a second terminal (IN1-) respectively connected to a first end and a second end of a sensor (10), and a sampling circuit (22) arranged between the first terminal (IN1+) and the second terminal (IN1-), wherein the sampling circuit (22) is configured to allow a positive current and a negative current from the sensor (10) to flow between the first terminal (IN1+) and the second terminal (IN1-) and comprises a sampling terminal (P1) arranged on a current path between the first terminal (IN1+) and the second terminal (IN1-), wherein a current direction of the positive current is opposite to a current direction of the negative current; A signal modulation unit (30) configured to obtain a sampled voltage at the sampling terminal (P1) and process the sampled voltage to generate a first processed signal; as well as a processor (40) configured to receive the first processed signal and generate an output signal based on the first processed signal; The sampling circuit (22) comprises: The first MOS tube (Q1); Sampling resistor (R1); a current limiting resistor (R2) connected in series with the sampling resistor (R1); and The second MOS tube (Q2); The first end of the first MOS tube (Q1) is connected to the sampling resistor (R1), the second end of the first MOS tube (Q1) is connected to the first terminal (IN1+), the sampling end (P1) is arranged at a first node where the first end of the first MOS tube (Q1) and the sampling resistor (R1) are connected to each other, the first end of the second MOS tube (Q2) is connected to the current limiting resistor (R2), the second end of the second MOS tube (Q2) is connected to the second terminal (IN1-), and the second node (P2) where the sampling resistor (R1) and the current limiting resistor (R2) are connected to each other is grounded.

2. The signal processing circuit according to claim 1, wherein the first MOS transistor (Q1) and the second MOS transistor (Q2) are packaged in the same chip and share a heat sink.

3. The signal processing circuit according to claim 1, further comprising a voltage limiting unit (24), wherein the voltage limiting unit (24) is configured to limit the voltage at the first node to a predetermined voltage range, wherein the voltage limiting unit (24) comprises a forward current limiting branch and a negative current branch connected in parallel with the forward current limiting branch, and each of the current branches comprises one or more diodes (D1, D2; D3, D4) connected in series with each other.

4. The signal processing circuit according to claim 1, wherein the processor (40) comprises a signal type identification module, the signal type identification module being configured to: identify the output signal as an analog quantity in response to the first processed signal being within a first range.

5. The signal processing circuit according to claim 4, wherein the signal type identification module is further configured to: identify the output signal as a switch value in response to the first processed signal being in a second range, The second range includes a high logic level range and a low logic level range, the minimum value of the high logic level range is greater than the maximum value of the first range, and the maximum value of the low logic level range is less than the minimum value of the first range.

6. The signal processing circuit according to claim 5, wherein the signal type identification module is configured to: determine that the first processed signal belongs to an analog quantity in response to determining that the first processed signal is in the first range during multiple consecutive sampling cycles; and / or determine that the first processed signal belongs to a switch quantity in response to determining that the first processed signal is in the second range during multiple consecutive sampling cycles.

7. The signal processing circuit according to any one of claims 1 to 6, further comprising a channel switch control unit (60) configured to activate a channel sampling unit (20) or deactivate the channel sampling unit (20) based on a channel switch signal (CH1) from the processor (40); The gate of the first MOS tube (Q1) and the gate of the second MOS tube (Q2) are connected to the same third node (P3), and the third node (P3) is a voltage node in the channel switch control unit (60).

8. The signal processing circuit according to claim 7, wherein the channel switch control unit (60) comprises: The first voltage divider resistor (R3); A second voltage-dividing resistor (R4) connected in series with the first voltage-dividing resistor (R3); a third MOS transistor (Q3), wherein a second end of the third MOS transistor (Q3) is connected to the third node (P3), the first voltage-dividing resistor (R3) is connected to the second voltage-dividing resistor (R4) at the third node (P3), and the first end of the third MOS transistor (Q3) is connected to the other end of the second voltage-dividing resistor (R4); wherein the voltage node is the third node (P3); The third MOS transistor (Q3) is configured to be turned off based on a channel turn-on signal from the processor (40), so that the first MOS transistor (Q1) and the second MOS transistor (Q2) can be turned on based on the voltage at the third node; the third MOS transistor (Q3) is configured to be turned on based on a channel turn-off signal from the processor (40), so that the first MOS transistor (Q1) and the second MOS transistor (Q2) are turned off.

9. The signal processing circuit according to claim 8, wherein the channel switch control unit (60) further comprises a delay unit, wherein the delay unit is configured to: turn off the third MOS tube (Q3) without delay in response to a channel turn-on signal from the processor (40); and turn on the third MOS tube (Q3) after a predetermined time delay in response to the channel turn-off signal from the processor (40).

10. The signal processing circuit according to claim 9, wherein the delay unit comprises: a resistor (R5), one end of the resistor (R5) being connected to the channel conduction end of the processor (40) and being configured to receive the channel conduction signal from the processor (40), and the other end of the resistor being connected to the gate of the third MOS tube (Q3); A capacitor (C1), one end of the capacitor (C1) is grounded, and the other end is connected to a connection node (P4) between the resistor (R5) and the third MOS tube (Q3); and A diode (D5) is connected in parallel with the resistor (R5) and is configured to discharge the electricity stored in the capacitor (C1) through the diode (D5) in response to the channel shut-off signal from the processor (40).

11. The signal processing circuit according to claim 9, wherein the processor (40) is configured such that: the first processed signal sampled in an initial predetermined number of sampling cycles after the channel sampling unit (20) is activated is not used to generate the output signal, and the first processed signal sampled after the initial predetermined number of sampling cycles after the channel sampling unit (20) is activated is used to generate the output signal.

12. The signal processing circuit according to any one of claims 1 to 6 and 8 to 11, further comprising: A redundant channel sampling unit, the redundant channel sampling unit comprising a third terminal and a fourth terminal respectively connected to the first terminal and the second terminal of the sensor (10) and a second sampling circuit arranged between the third terminal and the fourth terminal, the second sampling circuit being configured to allow a positive current and a negative current from the sensor (10) to flow between the third terminal and the fourth terminal and comprising a second sampling terminal arranged on a current path between the third terminal and the fourth terminal; a second signal modulation unit configured to obtain a sampled voltage at the second sampling end and process the sampled voltage to generate a second processed signal; as well as The processor (40) is configured to receive the second processed signal and to generate the output signal based on the second processed signal.

13. The signal processing circuit according to claim 12, wherein the redundant channel sampling unit is configured as a redundant signal acquisition channel of the channel sampling unit, The processor (40) further comprises a redundancy control logic, wherein the redundancy control logic is configured to activate one of the channel sampling unit and the redundant channel sampling unit based on a predetermined rule, and to enable the redundant channel sampling unit to be disabled when the channel sampling unit is enabled, and to enable the channel sampling unit to be disabled when the redundant channel sampling unit is enabled.

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