Driving circuit and control method thereof

Abstract

The embodiment of the invention provides a driving circuit and a control method thereof. The driving circuit comprises a first driving module and a coupling elimination module. The first driving module comprises a first control end, a first output end, a first input end and a second input end connected to the coupling elimination module; the first driving module is configured to output a target voltage in a first stage and a second stage, and the first stage is earlier than the second stage; the first driving module is configured to synchronize the input voltage of the first input end to the first output end in response to the switching of the first control end from the first voltage to the second voltage in a first stage; the first driving module is configured to synchronize the input voltage of the second input end to the first output end in response to switching of the first control end from the second voltage to the first voltage in a second stage; the target voltage is between the first voltage and the second voltage.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuits, and in particular to a driving circuit and a control method thereof. Background Art

[0002] In the field of integrated circuits, the influence of coupling capacitance on circuit reliability is increasing day by day. How to eliminate the adverse influence of coupling capacitance without affecting circuit performance is a problem that technicians in this field want to solve. Summary of the invention

[0003] In view of this, an embodiment of the present disclosure provides a driving circuit and a control method thereof.

[0004] To achieve the above purpose, the technical solution of the present disclosure is implemented as follows:

[0005] In a first aspect, an embodiment of the present disclosure provides a driving circuit, comprising: a first driving module and a coupling elimination module; the first driving module comprises a first control terminal, a first output terminal, a first input terminal and a second input terminal connected to the coupling elimination module; the first driving module is configured to output a target voltage in a first stage and a second stage, the first stage being earlier than the second stage; the first driving module is configured to synchronize the input voltage of the first input terminal to the first output terminal in response to the first control terminal switching from the first voltage to the second voltage in the first stage; the first driving module is configured to synchronize the input voltage of the second input terminal to the first output terminal in response to the first control terminal switching from the second voltage to the first voltage in the second stage; the target voltage is between the first voltage and the second voltage.

[0006] In some embodiments, the first driving module includes a first transistor and a second transistor, the first transistor and the second transistor have different doping types; the gate of the first transistor and the gate of the second transistor are connected to the first control terminal, and the drain of the first transistor and the drain of the second transistor are connected to the first output terminal; the source of the first transistor is the first input terminal, and the source of the second transistor is the second input terminal; the first driving module is configured to turn on the first transistor in the first stage and turn on the second transistor in the second stage.

[0007] In some embodiments, the coupling elimination module includes a second control terminal, a third input terminal, and a fourth input terminal connected to the second voltage, and the first input terminal and the third input terminal are connected to a target voltage source; the coupling elimination module is configured to synchronize the input voltage of the third input terminal to the second input terminal in response to the first voltage input by the second control terminal in the first stage; the coupling elimination module is configured to synchronize the input voltage of the fourth input terminal to the second input terminal in response to the second control terminal switching from the first voltage to the second voltage in the second stage.

[0008] In some embodiments, the first output terminal is connected to a storage unit; wherein the storage unit includes a storage transistor and a storage capacitor, the drain of the storage transistor is connected to the storage capacitor, and the gate of the storage transistor is connected to the first output terminal; the storage transistor is configured to be turned on in the first stage and the second stage.

[0009] In some embodiments, the storage transistor and the second transistor are N-type transistors, the first transistor is a P-type transistor; and the first voltage is greater than the second voltage.

[0010] In some embodiments, the storage transistor and the second transistor are P-type transistors, the first transistor is an N-type transistor; and the first voltage is less than the second voltage.

[0011] In some embodiments, the coupling elimination module includes a third transistor and a fourth transistor, the third transistor has the same doping type as the first transistor, and the fourth transistor has the same doping type as the second transistor; the gate of the third transistor and the gate of the fourth transistor are connected to the second control terminal, and the drain of the third transistor and the drain of the fourth transistor are connected to the second input terminal; the source of the third transistor is the third input terminal, and the source of the fourth transistor is the fourth input terminal; the coupling elimination module is configured to turn on the fourth transistor in the first stage; and the coupling elimination module is configured to turn on the third transistor in the second stage.

[0012] In some embodiments, a source of the storage transistor is connected to a sense amplifier module; and the sense amplifier module is configured to sense storage data in the storage cell after the second stage.

[0013] In a second aspect, an embodiment of the present disclosure provides a control method for a driving circuit, wherein the driving circuit includes a first driving module and a coupling elimination module, wherein the first driving module includes a first control terminal, a first output terminal, a first input terminal, and a second input terminal connected to the coupling elimination module; the control method includes: in a first stage and a second stage, applying a first signal to the first control terminal to make the first driving module output a target voltage, the first stage being earlier than the second stage; in the first stage, the first signal is switched from the first voltage to the second voltage, so that the first driving module synchronizes the input voltage of the first input terminal to the first output terminal; the target voltage is between the first voltage and the second voltage; in the second stage, the first signal is switched from the second voltage to the first voltage, so that the first driving module synchronizes the input voltage of the second input terminal to the first output terminal.

[0014] In some embodiments, the first driving module includes a first transistor and a second transistor, the first transistor and the second transistor have different doping types; the gate of the first transistor and the gate of the second transistor are connected to the first control terminal, and the drain of the first transistor and the drain of the second transistor are connected to the first output terminal; the source of the first transistor is the first input terminal, and the source of the second transistor is the second input terminal; the control method also includes: in the first stage, the first signal is switched from the first voltage to the second voltage to turn on the first transistor; in the second stage, the first signal is switched from the second voltage to the first voltage to turn on the second transistor.

[0015] In some embodiments, the coupling elimination module includes a second control terminal, a third input terminal, and a fourth input terminal connected to the second voltage, and the first input terminal and the third input terminal are connected to a target voltage source; the control method also includes: applying a second signal to the second control terminal; wherein, in the first stage, the second signal is maintained at the first voltage so that the coupling elimination module synchronizes the voltage of the fourth input terminal to the second input terminal; in the second stage, the second signal is switched from the first voltage to the second voltage so that the coupling elimination module synchronizes the voltage of the third input terminal to the second input terminal.

[0016] In some embodiments, the first output terminal is connected to a storage unit; wherein the storage unit includes a storage transistor and a storage capacitor, the drain of the storage transistor is connected to the storage capacitor, and the gate of the storage transistor is connected to the first output terminal; the control method further includes: in the first stage and the second stage, the storage transistor is turned on.

[0017] In some embodiments, the storage transistor and the second transistor are N-type transistors, and the first transistor is a P-type transistor; the control method further includes: the first voltage is greater than the second voltage.

[0018] In some embodiments, the storage transistor and the second transistor are P-type transistors, and the first transistor is an N-type transistor; the control method further includes: the first voltage is less than the second voltage.

[0019] In some embodiments, the coupling elimination module includes a third transistor and a fourth transistor, the third transistor has the same doping type as the first transistor, and the fourth transistor has the same doping type as the second transistor; the gate of the third transistor and the gate of the fourth transistor are connected to the second control terminal, and the drain of the third transistor and the drain of the fourth transistor are connected to the second input terminal; the source of the third transistor is the third input terminal, and the source of the fourth transistor is the fourth input terminal; the control method also includes: in the first stage, the second signal maintains the first voltage, and the fourth transistor is turned on; in the second stage, the second signal switches from the first voltage to the second voltage, and the third transistor is turned on.

[0020] In some embodiments, the source of the storage transistor is connected to a sensing amplifier module; after the second stage, a sensing stage is further included; in the sensing stage, the sensing amplifier module is used to sense the storage data in the storage unit.

[0021] The embodiment of the present disclosure provides a driving circuit and a control method thereof, wherein the driving circuit comprises: a first driving module and a coupling elimination module; the first driving module comprises a first control terminal, a first output terminal, a first input terminal and a second input terminal connected to the coupling elimination module; the first driving module is configured to output a target voltage in a first stage and a second stage, wherein the first stage is earlier than the second stage; the first driving module is configured to synchronize the input voltage of the first input terminal to the first output terminal in response to the first control terminal switching from the first voltage to the second voltage in the first stage; the first driving module is configured to synchronize the input voltage of the second input terminal to the first output terminal in response to the first control terminal switching from the second voltage to the first voltage in the second stage; the target voltage is between the first voltage and the second voltage. The embodiment of the present disclosure utilizes the coupling elimination module to switch the input signal of the first control terminal twice in the first stage and the second stage respectively, so that the coupling capacitor between the first control terminal and other devices undergoes one charge and one discharge, thereby eliminating the influence of the coupling capacitor on the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1A A schematic diagram of the structure of a storage circuit in the related art provided by an embodiment of the present disclosure;

[0023] Figure 1B for Figure 1A A timing diagram of a read operation of the storage circuit shown;

[0024] Figure 2 A structural schematic diagram 1 of a driving circuit provided in an embodiment of the present disclosure;

[0025] Figure 3A A schematic diagram of a driving circuit provided in an embodiment of the present disclosure Figure 2 ;

[0026] Figure 3B for Figure 3A The timing diagram of the driving circuit shown in the first stage and the second stage;

[0027] Figure 4A A third structural diagram of a driving circuit provided in an embodiment of the present disclosure;

[0028] Figure 4B for Figure 4A The timing diagram of the driving circuit shown in the first stage and the second stage;

[0029] Figure 5A A structural schematic diagram 1 of a storage circuit provided in an embodiment of the present disclosure;

[0030] Figure 5B for Figure 5A A timing diagram of a read operation of the storage circuit shown;

[0031] Fig. 6A A schematic diagram of a storage circuit provided in an embodiment of the present disclosure Figure 2 ;

[0032] Figure 6B for Fig. 6A A timing diagram of a read operation of the storage circuit shown;

[0033] Figure 7 A schematic diagram of the steps of a control method for a drive circuit provided in the present invention. DETAILED DESCRIPTION

[0034] The following will be combined with the embodiments of the present disclosure and the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0035] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0036] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0037] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0038] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0039] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0040] In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below, but in addition to these detailed descriptions, the present disclosure may also have other implementations.

[0041] Figure 1A A schematic diagram of the structure of a storage circuit in the related art provided by an embodiment of the present disclosure; Figure 1B for Figure 1A The read operation timing diagram of the storage circuit shown. Figure 1A The storage circuit includes a single transistor single capacitor (1Transistor1Capacitor, 1T1C) storage unit, a word line driving circuit 110 and a sense amplifier (Sense Amplifier, SA) 120.

[0042] The storage unit includes a storage transistor T0 and a storage capacitor C0, the word line driving circuit 110 is connected to the gate of the storage transistor T0 through the word line WL, the drain of the storage transistor T0 is connected to a plate of the storage capacitor C0, the source of the storage transistor T0 is connected to the bit line BL1, and the sensing amplifier 120 is coupled between the bit line BL1 and the reference bit line BL2.

[0043] The word line driving circuit 110 includes a first MOS transistor Tp and a second MOS transistor Tn, wherein the source of the first MOS transistor Tp is connected to a power signal Vdd, the source of the second MOS transistor Tn is connected to a low level (for example, grounded), the gate of the first MOS transistor Tp and the gate of the second MOS transistor Tn are connected to a control signal mwl, and the drain of the first MOS transistor Tp and the drain of the second MOS transistor Tn are connected to the gate of the storage transistor T0.

[0044] See also Figure 1B , Figure 1BTake the storage data in the storage cell as "0" as an example. The read operation on the storage cell includes a preparation stage, a charge sharing (CS) stage and a sensing (Sensing) stage. The preparation stage may include a pre-charge (PC) stage and an offset cancellation (OC) stage.

[0045] In the preparatory stage, the control signal mwl and the power signal Vdd maintain a high level. At this time, the second MOS transistor Tn is turned on to transmit the source voltage of the second MOS transistor Tn to the word line WL, so the word line WL maintains a low level; the bit line BL1 and the reference bit line BL2 are charged to the reference voltage Vcc / 2.

[0046] In the charge sharing stage, the control signal mwl switches from a high level to a low level, and the power signal Vdd switches from a low level to a high level. At this time, the first MOS tube Tp is turned on to transfer the source voltage of the first MOS tube Tp to the word line WL, so the word line WL switches from a low level to a high level to turn on the storage transistor T0. In an ideal state, since the storage data in the storage cell is "0", that is, there is no charge (or a small amount of charge) in the storage capacitor C0, a small amount of charge in the bit line BL1 will be transferred to the storage capacitor C0, causing the voltage on the bit line BL1 to drop and the voltage on the reference bit line BL2 to rise. However, since the control signal mwl switches from a high level to a low level at this stage, the coupling capacitor C between the control signal mwl and the bit line BL1 is p1 The discharge phenomenon occurs, and the coupling capacitance C between the control signal mwl and the bit line BL1 p2 The discharge phenomenon occurs, so that when the control signal mwl switches from a high level to a low level, the voltage on the bit line BL1 and the reference bit line BL2 decreases to a certain extent (ie, Figure 1B The circled part in the middle), that is, the voltage on the bit line BL1 and the reference bit line BL2 is pulled down by the coupling capacitor, which will affect the accuracy of the memory cell reading operation.

[0047] In the sensing stage, the sense amplifier 120 amplifies the small voltage difference between the bit line BL1 and the reference bit line BL2. When the voltage difference between the bit line BL1 and the reference bit line BL2 is a negative value, the storage data in the read storage cell is "0", and the sense amplifier 120 transmits the read storage data to the data bus. In addition, the sensing stage not only includes amplifying the small voltage difference between the bit line BL1 and the reference bit line BL2, but also includes switching the control signal mwl from a low level to a high level and switching the power supply signal Vdd from a high level to a low level when transmitting the storage data to the data bus. At this time, the word line WL is switched to a low level to turn off the storage transistor T0, so as to ensure the stability of the storage data, reduce power consumption and extend the service life of the storage cell.

[0048] Since the sensing amplifier 120 amplifies the small voltage difference between the bit line BL1 and the reference bit line BL2 during the charge sharing phase, the coupling capacitance C cannot be eliminated even though the control signal mwl is switched from a low level to a high level during the sensing phase. p1 and C p2 Impact on read operations. In addition to affecting the reading of data stored in the storage unit, the coupling capacitor also affects the reliability of other small signal rail-to-rail amplifier circuits. Therefore, how to eliminate the negative impact of the coupling capacitor is an urgent problem to be solved. The small signal rail-to-rail amplifier circuit can be, for example: a rail-to-rail operational amplifier, a rail-to-rail comparator, or a current mirror rail-to-rail amplifier.

[0049] In view of this, the present disclosure provides the following embodiments:

[0050] An embodiment of the present disclosure provides a driving circuit, including: a first driving module and a coupling elimination module; the first driving module includes a first control terminal, a first output terminal, a first input terminal and a second input terminal connected to the coupling elimination module; the first driving module is configured to output a target voltage in a first stage and a second stage, and the first stage is earlier than the second stage; the first driving module is configured to synchronize the input voltage of the first input terminal to the first output terminal in response to the first control terminal switching from the first voltage to the second voltage in the first stage; the first driving module is configured to synchronize the input voltage of the second input terminal to the first output terminal in response to the first control terminal switching from the second voltage to the first voltage in the second stage; the target voltage is between the first voltage and the second voltage.

[0051] Figure 2 A schematic diagram of a driving circuit provided by an embodiment of the present disclosure. Figure 2 The driving circuit includes a first driving module 210 and a coupling elimination module 220. The first driving module 210 includes a first control terminal Pctrl1, a first input terminal P1, a second input terminal P2 and a first output terminal Pout.

[0052] The first input terminal P1 is configured to input the target voltage Vt in the first stage, and the coupling elimination module 220 is configured to input the target voltage Vt to the second input terminal P2 in the second stage. The first driving module 210 is configured to, in the first stage, switch from the first voltage V1 to the second voltage V2 in response to the first signal Vctrl1 inputted from the first control terminal Pctrl1, and synchronize the input voltage of the first input terminal P1 to the first output terminal Pout, so that the first driving module 210 outputs the target voltage Vt in the first stage; the first driving module 210 is also configured to, in the second stage, switch from the second voltage V2 to the first voltage V1 in response to the first signal Vctrl1 inputted from the first control terminal Pctrl1, and synchronize the input voltage of the second input terminal P2 to the first output terminal Pout, so that the first driving module 210 outputs the target voltage Vt in the first stage.

[0053] The driving circuit provided in the embodiment of the present disclosure utilizes a coupling elimination module to switch the input signal of the first control terminal twice in the first stage and the second stage respectively, so that the coupling capacitor between the first control terminal and other devices undergoes one charge and one discharge, thereby eliminating the influence of the coupling capacitor on the circuit.

[0054] In some embodiments, the first driving module includes a first transistor and a second transistor, the first transistor and the second transistor have different doping types; the gate of the first transistor and the gate of the second transistor are connected to the first control terminal, and the drain of the first transistor and the drain of the second transistor are connected to the first output terminal; the source of the first transistor is the first input terminal, and the source of the second transistor is the second input terminal; the first driving module is configured to turn on the first transistor in the first stage and turn on the second transistor in the second stage.

[0055] See also Figure 2 The first driving module 210 includes a first transistor T1 and a second transistor T2, wherein the gate of the first transistor T1 and the gate of the second transistor T2 are connected to the first control terminal Pctrl1, the drain of the first transistor T1 and the drain of the second transistor T2 are connected to the first output terminal Pout; the source of the first transistor T1 is the first input terminal P1, and the source of the second transistor T2 is the second input terminal P2; the first driving module 210 is configured to turn on the first transistor T1 in the first stage and turn on the second transistor T2 in the second stage.

[0056] The doping types of the first transistor T1 and the second transistor T2 are different, so that the first transistor T1 is turned on when the gate voltage is the second voltage V2, and the first transistor T1 can synchronize the input voltage of the first input terminal P1 to the first output terminal Pout, so the first driving module 210 can output the target voltage Vt in the first stage; and the second transistor T2 is turned on when the gate voltage is the first voltage V1, and the second transistor T2 can synchronize the input voltage of the second input terminal P2 to the first output terminal Pout, so the first driving module 210 can output the target voltage Vt in the second stage. For example: the first transistor T1 is a P-type transistor, and the second transistor T2 is an N-type transistor; or the first transistor T1 is an N-type transistor, and the second transistor T2 is a P-type transistor.

[0057] In some embodiments, the coupling elimination module includes a second control terminal, a third input terminal, and a fourth input terminal connected to a second voltage, and the first input terminal and the third input terminal are connected to a target voltage source; the coupling elimination module is configured to synchronize the input voltage of the fourth input terminal to the second input terminal in response to the first voltage input to the second control terminal in a first stage; the coupling elimination module is configured to synchronize the input voltage of the third input terminal to the second input terminal in response to the second control terminal switching from the first voltage to the second voltage in a second stage.

[0058] See also Figure 2 The coupling elimination module 220 includes a second control terminal Pctrl2, a third input terminal P3, a fourth input terminal P4, and an output terminal connected to the second input terminal P2. The first input terminal P1 and the third input terminal P3 are connected to a target voltage source Xpp, and the target voltage source Xpp is used to generate a target voltage Vt.

[0059] The fourth input terminal P4 is configured to input the second voltage V2 in the first stage, and the third input terminal P3 is configured to input the target voltage Vt in the second stage. The coupling elimination module 220 is configured to synchronize the input voltage of the fourth input terminal P4 to the second input terminal P2 in the first stage in response to the first signal Vctrl2 inputted from the second control terminal Pctrl2 being the first voltage V1; the coupling elimination module 220 is also configured to synchronize the input voltage of the third input terminal P3 to the second input terminal P2 in the second stage in response to the first signal Vctrl2 inputted from the second control terminal Pctrl2 switching from the first voltage V1 to the second voltage V2.

[0060] In some embodiments, the coupling elimination module includes a third transistor and a fourth transistor, the third transistor has the same doping type as the first transistor, and the fourth transistor has the same doping type as the second transistor; the gate of the third transistor and the gate of the fourth transistor are connected to the second control terminal, and the drain of the third transistor and the drain of the fourth transistor are connected to the second input terminal; the source of the third transistor is the third input terminal, and the source of the fourth transistor is the fourth input terminal; the coupling elimination module is configured to turn on the third transistor in the first stage; the coupling elimination module is configured to turn on the third transistor in the second stage.

[0061] See also Figure 2 The coupling elimination module 220 includes a third transistor T3 and a fourth transistor T4, wherein the gate of the third transistor T3 and the gate of the fourth transistor T4 are connected to the second control terminal Pctrl2, and the drain of the third transistor T3 and the drain of the fourth transistor T4 are connected to the second input terminal P2; the source of the third transistor T3 is the third input terminal P3, and the source of the fourth transistor T4 is the fourth input terminal P4; the coupling elimination module 220 is configured to turn on the fourth transistor T4 in the first stage and turn on the third transistor T3 in the second stage.

[0062] The third transistor T3 and the first transistor T1 have the same doping type, and the fourth transistor T4 and the second transistor T2 have the same doping type, so that the fourth transistor T4 is turned on when the gate voltage is the first voltage V1, and the fourth transistor T4 can synchronize the input voltage of the fourth input terminal P4 to the second input terminal P2, so the coupling elimination module 220 can input the second voltage V2 to the second input terminal P2 in the first stage; and the third transistor T3 is turned on when the gate voltage is the second voltage V2, and the third transistor T3 can synchronize the input voltage of the third input terminal P3 to the second input terminal P2, so the coupling elimination module 220 can input the target voltage Vt to the second input terminal P2 in the second stage. For example: the third transistor T3 and the first transistor T1 are P-type transistors, and the fourth transistor T4 and the second transistor T2 are N-type transistors; or the third transistor T3 and the first transistor T1 are N-type transistors, and the fourth transistor T4 and the second transistor T2 are P-type transistors.

[0063] In some embodiments, the time for switching the rising edge or falling edge of the first signal Vctrl1, the second signal Vctrl2 and the target voltage source Xpp is extremely short. At the same time, since the transistor has high-speed switching characteristics, high input impedance and low output impedance, the time for switching on the first transistor T1 and the second transistor T2 in the first driving module 210 and the time for switching on the third transistor T3 and the fourth transistor T4 in the coupling elimination module 220 when the above signals are switched can be almost ignored.

[0064] Figure 3AA schematic diagram of a driving circuit provided in an embodiment of the present disclosure Figure 2 ; Figure 3B for Figure 3A The timing diagram of the driving circuit shown in the first stage and the second stage. Figure 3A In the description, it is taken as an example that the third transistor T3 and the first transistor T1 are P-type transistors, the fourth transistor T4 and the second transistor T2 are N-type transistors, and the first voltage V1 is greater than the second voltage V2.

[0065] See also Figure 3A and Figure 3B , the input voltage of the fourth input terminal P4 is the second voltage V2. In the preparatory stage (before the first stage), the second signal Vctrl2 is at a high level (the first voltage V1), the target voltage source Xpp is at a low level (the second voltage V2), and at this time the fourth transistor T4 in the coupling elimination module 220 is turned on, so that the coupling elimination module 220 synchronizes the input voltage of the fourth input terminal P4 to the second input terminal P2 before the first stage. The first signal Vctrl1 is at a high level (the first voltage V1), and at this time the second transistor T2 in the first driving module 210 is turned on, so that the first driving module 210 synchronizes the input voltage of the second input terminal P2 to the first output terminal Pout, that is, the output voltage Vout of the first driving module 210 is at a low level (the second voltage V2).

[0066] In the first stage, the second signal Vctrl2 is at a high level (first voltage V1), and the target voltage source Xpp switches from a low level (second voltage V2) to a high level (target voltage Vt). During the process of the target voltage source XPP switching to a high level (rising edge) and after switching to a high level, the fourth transistor T4 in the coupling elimination module 220 is turned on, so that the coupling elimination module 220 synchronizes the input voltage of the fourth input terminal P4 to the second input terminal P2 in the first stage. The first signal Vctrl1 switches from a high level (first voltage V1) to a low level (second voltage V2), and after the first signal Vctrl1 switches to a low level (falling edge), the target voltage source Xpp switches from a low level (second voltage V2) to a high level (target voltage Vt). In the process of the first signal Vctrl1 switching to a low level, the first driving module 210 switches from turning on the second transistor T2 to turning on the first transistor T1, so that the first driving module 210 synchronizes the input voltage of the first input terminal P1 to the first output terminal Pout after the first signal Vctrl1 switches to a low level, that is, the output voltage Vout of the first driving module 210 after the first signal Vctrl1 switches to a low level switches from a low level (second voltage V2) to a high level (target voltage Vt).

[0067] In the second stage, the second signal Vctrl2 switches from a high level (first voltage V1) to a low level (second voltage V2), the target voltage source Xpp is a high level (target voltage Vt), and the coupling elimination module 220 switches from turning on the fourth transistor T4 to turning on the third transistor T3 during the process of the second signal Vctrl2 switching to a low level, so that the coupling elimination module 220 synchronizes the input voltage of the third input terminal P3 to the second input terminal P2 after the third transistor T3 is turned on. After the second signal Vctrl2 switches to a low level, the first signal Vctrl1 switches from a low level (second voltage V2) to a high level (first voltage V1), and the first driving module 210 switches from turning on the first transistor T1 to turning on the second transistor T2 during the process of the first signal Vctrl1 switching to a high level, so that the first driving module 210 synchronizes the input voltage of the second input terminal P2 to the first output terminal Pout after the first signal Vctrl1 switches to a high level, that is, the output voltage Vout of the first driving module 210 is a high level (target voltage Vt).

[0068] It should be noted that the target voltage Vt is at a higher level than the second voltage V2. Figure 3B The high level in Vout is Vt, and the low level is V2.

[0069] In some embodiments, the coupling capacitance generated by the control signal switching from a high level to a low level will affect the small signal rail-to-rail amplifier circuit, which can be used as follows: Figure 3A The coupling elimination module shown enables the control signal (i.e., the first signal) to switch twice in the first stage and the second stage without affecting the output voltage of the first driving module, so that the coupling capacitor can be charged and discharged once, thereby eliminating the influence of the coupling capacitor on small signal amplification.

[0070] Figure 4A A third structural diagram of a driving circuit provided in an embodiment of the present disclosure; Figure 4B for Figure 4A The timing diagram of the driving circuit shown in the first stage and the second stage. Figure 4A In the description, it is taken as an example that the third transistor T3 and the first transistor T1 are N-type transistors, the fourth transistor T4 and the second transistor T2 are P-type transistors, and the first voltage V1 is less than the second voltage V2.

[0071] See also Figure 4A and Figure 4B, the input voltage of the fourth input terminal P4 is the second voltage V2. In the preparatory stage (before the first stage), the second signal Vctrl2 is at a low level (the first voltage V1), the target voltage source Xpp is at a high level (the second voltage V2), and at this time the fourth transistor T4 in the coupling elimination module 220 is turned on, so that the coupling elimination module 220 synchronizes the input voltage of the fourth input terminal P4 to the second input terminal P2 before the first stage. The first signal Vctrl1 is at a low level (the first voltage V1), and at this time the second transistor T2 in the first driving module 210 is turned on, so that the first driving module 210 synchronizes the input voltage of the second input terminal P2 to the first output terminal Pout, that is, the output voltage Vout of the first driving module 210 is at a high level (the second voltage V2).

[0072] In the first stage, the second signal Vctrl2 is at a low level (first voltage V1), and the target voltage source Xpp switches from a high level (second voltage V2) to a low level (target voltage Vt). During the process of the target voltage source XPP switching to a low level (falling edge) and after switching to a low level, the fourth transistor T4 in the coupling elimination module 220 is turned on, so that the coupling elimination module 220 synchronizes the input voltage of the fourth input terminal P4 to the second input terminal P2 in the first stage. The first signal Vctrl1 switches from a low level (first voltage V1) to a high level (second voltage V2), and after the first signal Vctrl1 switches to a high level (rising edge), the target voltage source Xpp switches from a high level (second voltage V2) to a low level (target voltage Vt). In the process of the first signal Vctrl1 switching to a high level, the first driving module 210 switches from turning on the second transistor T2 to turning on the first transistor T1, so that the first driving module 210 synchronizes the input voltage of the first input terminal P1 to the first output terminal Pout after the first signal Vctrl1 switches to a high level, that is, the output voltage Vout of the first driving module 210 after the first signal Vctrl1 switches to a high level switches from a high level (second voltage V2) to a low level (target voltage Vt).

[0073] In the second stage, the second signal Vctrl2 switches from a low level (first voltage V1) to a high level (second voltage V2), the target voltage source Xpp is a low level (target voltage Vt), and the coupling elimination module 220 switches from turning on the fourth transistor T4 to turning on the third transistor T3 during the process of the second signal Vctrl2 switching to a high level, so that the coupling elimination module 220 synchronizes the input voltage of the third input terminal P3 to the second input terminal P2 after the third transistor T3 is turned on. After the second signal Vctrl2 switches to a high level, the first signal Vctrl1 switches from a high level (second voltage V2) to a low level (first voltage V1), and the first driving module 210 switches from turning on the first transistor T1 to turning on the second transistor T2 during the process of the first signal Vctrl1 switching to a low level, so that the first driving module 210 synchronizes the input voltage of the second input terminal P2 to the first output terminal Pout after the first signal Vctrl1 switches to a low level, that is, the output voltage Vout of the first driving module 210 is a low level (target voltage Vt).

[0074] It should be noted that the target voltage Vt is at a lower level than the second voltage V2. Figure 4B The high level in Vout is V2 and the low level is Vt.

[0075] In some embodiments, the coupling capacitance generated by the control signal switching from a low level to a high level will affect the small signal rail-to-rail amplifier circuit, which can be used as follows: Figure 4A The coupling elimination module shown enables the control signal (i.e., the first signal) to switch twice in the first stage and the second stage without affecting the output voltage of the first driving module, so that the coupling capacitor can be charged and discharged once, thereby eliminating the influence of the coupling capacitor on small signal amplification.

[0076] In some embodiments, the first output terminal is connected to a storage unit; wherein the storage unit includes a storage transistor and a storage capacitor, the drain of the storage transistor is connected to the storage capacitor, and the gate of the storage transistor is connected to the first output terminal; the storage transistor is configured to be turned on in the first stage and the second stage.

[0077] In some embodiments, the first output terminal Pout can be connected to the gate of the storage transistor, and the first driving module 210 is configured to output the target voltage Vt in the first stage and the second stage to turn on the storage transistor in the first stage and the second stage. It should be noted that the target voltage Vt can be the threshold voltage of the storage transistor.

[0078] In some embodiments, a source of the storage transistor is connected to a sense amplifier module; and the sense amplifier module is configured to sense the storage data in the storage cell after the second stage.

[0079] In some embodiments, the sense amplifier module includes a bit line, a reference bit line, and a sense amplifier coupled between the bit line and the reference bit line.

[0080] In some embodiments, the memory cell is configured to share charges in the first stage and the second stage, so that the storage capacitor discharges to the bit line or the bit line discharges to the storage capacitor in different storage states of the memory cell, thereby causing a voltage difference between the bit line and the reference bit line. The sensing amplifier amplifies the voltage difference between the bit line and the reference bit line after the second stage to sense the storage data in the memory cell.

[0081] In some embodiments, if the storage transistor is an N-type transistor, when the first signal switches from a high level to a low level in the first stage, the coupling capacitors between the first signal and the bit line and the reference bit line are discharged, causing the voltages on the bit line and the reference bit line to drop to a certain extent, which will affect the accuracy of the read operation. When the first signal switches from a low level to a high level in the second stage, the coupling capacitors between the first signal and the bit line and the reference bit line are charged, causing the voltages on the bit line and the reference bit line to rise to a certain extent. It can be understood that the first signal undergoes a drop and a rise in the first stage and the second stage, respectively, causing the coupling capacitor to discharge and charge once, thereby eliminating the influence of the coupling capacitor on the voltages on the bit line and the reference bit line, and avoiding the influence of the coupling capacitor on the read operation of the storage unit.

[0082] In other embodiments, if the storage transistor is a P-type transistor, when the first signal switches from a low level to a high level in the first stage, the coupling capacitors between the first signal and the bit line and the reference bit line are charged, so that the voltages on the bit line and the reference bit line rise to a certain extent, which will affect the accuracy of the reading operation. When the first signal switches from a high level to a low level in the second stage, the coupling capacitors between the first signal and the bit line and the reference bit line are discharged, so that the voltages on the bit line and the reference bit line drop to a certain extent. It can be understood that the first signal rises and falls once in the first stage and the second stage respectively, so that the coupling capacitor is charged and discharged once, thereby eliminating the influence of the coupling capacitor on the voltages on the bit line and the reference bit line, and avoiding the influence of the coupling capacitor on the reading operation of the storage unit.

[0083] In some embodiments, the storage transistor and the second transistor are N-type transistors, the first transistor is a P-type transistor, and the first voltage is greater than the second voltage.

[0084] Figure 5A A structural schematic diagram 1 of a storage circuit provided in an embodiment of the present disclosure; Figure 5B for Figure 5A The read operation timing diagram of the storage circuit shown. Figure 5A In the description, an example is given in which the third transistor T3 and the first transistor T1 are P-type transistors, and the fourth transistor T4, the second transistor T2 and the storage transistor Ts are N-type transistors. Figure 5B In the description, the storage data in the storage unit is "0" as an example.

[0085] Figure 5A The specific structure and other details of the first driving module 210 and the coupling elimination module 220 are similar to those of Figure 3A Similar to the above, the parts not mentioned can be referred to Figure 3A The description of , will not be repeated here one by one.

[0086] See also Figure 5A The first output terminal Pout is connected to the gate of the storage transistor Ts through the word line WL, the drain of the storage transistor Ts is connected to a plate of the storage capacitor Cs, the source of the storage transistor Ts is connected to the bit line BL, and the sense amplifier SA is coupled between the bit line BL and the reference bit line RBL.

[0087] Figure 5B The specific timing and other details of Vctrl1, Vctrl2, Xpp and Vout in the preparation stage, the first stage and the second stage are the same as those in the Figure 3B Similar to the above, the parts not mentioned can be referred to Figure 3B The description of , will not be repeated here one by one.

[0088] See also Figure 5B In the preparatory stage, the bit line BL and the reference bit line RBL are charged to the reference voltage Vcc / 2. Ideally, in the first and second stages, since the storage data in the memory cell is "0", that is, there is no charge (or a small amount of charge) in the storage capacitor Cs, a small amount of charge in the bit line BL will be transferred to the storage capacitor Cs, causing the voltage on the bit line BL to drop and the voltage on the reference bit line RBL to rise.

[0089] In actual state, in the first stage, when the first signal Vctrl1 switches from a high level (first voltage V1) to a low level (second voltage V2), the coupling capacitor between the first signal Vctrl1 and the bit line BL and the reference bit line RBL discharges, so that when the first signal Vctrl1 switches from a high level to a low level, the voltages on the bit line BL and the reference bit line RBL drop to a certain extent (e.g. Figure 5B501 in FIG); in the second stage, when the first signal Vctrl1 switches from a low level (second voltage V2) to a high level (first voltage V1), the coupling capacitors between the first signal Vctrl1 and the bit line BL and the reference bit line RBL are charged, so that when the first signal Vctrl1 switches from a low level to a high level, the voltages on the bit line BL and the reference bit line RBL rise to a certain extent (as shown in FIG. Figure 5B As shown in 502 in FIG. 1 , it can be understood that the portion of the voltage on the bit line BL and the reference bit line RBL that rises at 502 compensates for the portion of the voltage on the bit line BL and the reference bit line RBL that drops at 501, that is, the two switchings of the first signal Vctrl1 in the first stage and the second stage can calibrate the voltage on the bit line BL and the reference bit line RBL, thereby eliminating the influence of the coupling capacitor on the voltage on the bit line and the reference bit line, and avoiding the influence of the coupling capacitor on the memory cell read operation.

[0090] In the sensing stage, the sense amplifier SA amplifies the small voltage difference between the bit line BL and the reference bit line RBL. When the voltage difference between the bit line BL and the reference bit line RBL is a negative value, the storage data in the read storage cell is "0", and the sense amplifier SA transmits the read storage data to the data bus. In addition, the sensing stage not only includes amplifying the small voltage difference between the bit line BL and the reference bit line RBL, but also includes switching the second signal Vctrl2 from a low level (second voltage V2) to a high level (first voltage V1) when transmitting the storage data to the data bus, and switching the target voltage source Xpp from a high level (target voltage Vt) to a low level (second voltage V2). At this time, Vout (word line WL) is switched to a low level (second voltage V2) to turn off the storage transistor Ts, so as to ensure the stability of the storage data, reduce power consumption and extend the service life of the storage cell.

[0091] It should be noted that, since the first output terminal of the first driving module is directly connected to the word line WL, and the word line, bit line and reference bit line in the storage unit are close to each other, coupling capacitance is inevitably generated between the first driving module and the bit line and the reference bit line. However, the coupling elimination module is not directly connected to the word line WL, so the coupling elimination module and the bit line and the reference bit line can be located in different wiring layers or the distance between the coupling elimination module and the bit line and the reference bit line is large enough to generate coupling capacitance, so as to avoid the second control signal affecting the voltage on the bit line and the reference bit line.

[0092] In some embodiments, the storage transistor and the second transistor are P-type transistors, the first transistor is an N-type transistor, and the first voltage is less than the second voltage.

[0093] Fig. 6A A schematic diagram of a storage circuit provided in an embodiment of the present disclosure Figure 2; Figure 6B for Fig. 6A The read operation timing diagram of the storage circuit shown. Fig. 6A In the description, an example is given in which the third transistor T3 and the first transistor T1 are N-type transistors, and the fourth transistor T4, the second transistor T2 and the storage transistor Ts are P-type transistors. Figure 6B In the description, the storage data in the storage unit is "0" as an example.

[0094] Fig. 6A The specific structure and other details of the first driving module 210 and the coupling elimination module 220 are similar to those of Figure 4A Similar to the above, the parts not mentioned can be referred to Figure 4A The description of , will not be repeated here one by one.

[0095] See also Fig. 6A The first output terminal Pout is connected to the gate of the storage transistor Ts through the word line WL, the drain of the storage transistor Ts is connected to a plate of the storage capacitor Cs, the source of the storage transistor Ts is connected to the bit line BL, and the sense amplifier SA is coupled between the bit line BL and the reference bit line RBL.

[0096] Figure 6B The specific timing and other details of Vctrl1, Vctrl2, Xpp and Vout in the preparation stage, the first stage and the second stage are the same as those in the Figure 4B Similar to the above, the parts not mentioned can be referred to Figure 4B The description of , will not be repeated here one by one.

[0097] See also Figure 6B In the preparatory stage, the bit line BL and the reference bit line RBL are charged to the reference voltage Vcc / 2. Ideally, in the first and second stages, since the storage data in the memory cell is "0", that is, there is no charge (or a small amount of charge) in the storage capacitor Cs, a small amount of charge in the bit line BL will be transferred to the storage capacitor Cs, causing the voltage on the bit line BL to drop and the voltage on the reference bit line RBL to rise.

[0098] In actual state, in the first stage, when the first signal Vctrl1 switches from a low level (first voltage V1) to a high level (second voltage V2), the coupling capacitors between the first signal Vctrl1 and the bit line BL and the reference bit line RBL are charged, so that when the first signal Vctrl1 switches from a low level to a high level, the voltages on the bit line BL and the reference bit line RBL rise to a certain extent (e.g. Figure 6B601 in FIG. 6 ); in the second stage, when the first signal Vctrl1 switches from a high level (second voltage V2) to a low level (first voltage V1), the coupling capacitor between the first signal Vctrl1 and the bit line BL and the reference bit line RBL discharges, so that when the first signal Vctrl1 switches from a high level to a low level, the voltages on the bit line BL and the reference bit line RBL decrease to a certain extent (as shown in FIG. 6 ). Figure 6B As shown in 602 in FIG. 1 , it can be understood that the portion of the voltage on the bit line BL and the reference bit line RBL that decreases at 602 compensates for the portion of the voltage on the bit line BL and the reference bit line RBL that increases at 601, that is, the two switchings of the first signal Vctrl1 in the first stage and the second stage can calibrate the voltage on the bit line BL and the reference bit line RBL, thereby eliminating the influence of the coupling capacitor on the voltage on the bit line and the reference bit line, and avoiding the influence of the coupling capacitor on the memory cell read operation.

[0099] In the sensing stage, the sense amplifier SA amplifies the small voltage difference between the bit line BL and the reference bit line RBL. When the voltage difference between the bit line BL and the reference bit line RBL is a negative value, the storage data in the read storage cell is "0", and the sense amplifier SA transmits the read storage data to the data bus. In addition, the sensing stage not only includes amplifying the small voltage difference between the bit line BL and the reference bit line RBL, but also includes switching the second signal Vctrl2 from a high level (second voltage V2) to a low level (first voltage V1) when transmitting the storage data to the data bus, and switching the target voltage source Xpp from a low level (target voltage Vt) to a high level (second voltage V2). At this time, Vout (word line WL) is switched to a high level (second voltage V2) to turn off the storage transistor Ts to ensure the stability of the storage data, reduce power consumption and extend the service life of the storage cell.

[0100] The embodiment of the present disclosure also provides a control method for a driving circuit, wherein the driving circuit includes a first driving module and a coupling elimination module, wherein the first driving module includes a first control terminal, a first output terminal, a first input terminal, and a second input terminal connected to the coupling elimination module; the control method includes: in a first stage and a second stage, applying a first signal to the first control terminal to enable the first driving module to output a target voltage, the first stage being earlier than the second stage; in the first stage, the first signal is switched from the first voltage to the second voltage to enable the first driving module to synchronize the input voltage of the first input terminal to the first output terminal; the target voltage is between the first voltage and the second voltage; in the second stage, the first signal is switched from the second voltage to the first voltage to enable the first driving module to synchronize the input voltage of the second input terminal to the first output terminal.

[0101] Figure 7 A schematic diagram of the steps of a control method of a driving circuit provided by the present disclosure. Figure 7 , the control method comprises the following steps:

[0102] Step 710: In the first phase and the second phase, applying a first signal to the first control terminal to enable the first driving module to output a target voltage.

[0103] Step 720: In the first stage, the first signal is switched from the first voltage to the second voltage, so that the first driving module synchronizes the input voltage of the first input terminal to the first output terminal.

[0104] Step 730: In the second stage, the first signal is switched from the second voltage to the first voltage, so that the first driving module synchronizes the input voltage of the second input terminal to the first output terminal.

[0105] The control method of the driving circuit provided in the embodiment of the present disclosure utilizes a coupling elimination module to switch the first signal twice in the first stage and the second stage respectively, so that the coupling capacitor between the first control terminal and other devices undergoes one charge and one discharge, thereby eliminating the influence of the coupling capacitor on the circuit.

[0106] In some embodiments, the first driving module includes a first transistor and a second transistor, and the first transistor and the second transistor have different doping types; the gate of the first transistor and the gate of the second transistor are connected to the first control terminal, and the drain of the first transistor and the drain of the second transistor are connected to the first output terminal; the source of the first transistor is the first input terminal, and the source of the second transistor is the second input terminal; the control method also includes: in the first stage, the first signal is switched from the first voltage to the second voltage to turn on the first transistor; in the second stage, the first signal is switched from the second voltage to the first voltage to turn on the second transistor.

[0107] In some embodiments, the coupling elimination module includes a second control terminal, a third input terminal, and a fourth input terminal connected to a second voltage, and the first input terminal and the third input terminal are connected to a target voltage source; the control method also includes: applying a second signal to the second control terminal; wherein, in a first stage, the second signal is maintained at a first voltage so that the coupling elimination module synchronizes the voltage of the fourth input terminal to the second input terminal; in a second stage, the second signal is switched from the first voltage to the second voltage so that the coupling elimination module synchronizes the voltage of the third input terminal to the second input terminal.

[0108] In some embodiments, the coupling elimination module includes a third transistor and a fourth transistor, the third transistor has the same doping type as the first transistor, and the fourth transistor has the same doping type as the second transistor; the gate of the third transistor and the gate of the fourth transistor are connected to the second control terminal, and the drain of the third transistor and the drain of the fourth transistor are connected to the second input terminal; the source of the third transistor is the third input terminal, and the source of the fourth transistor is the fourth input terminal; the control method also includes: in the first stage, the second signal maintains the first voltage and the fourth transistor is turned on; in the second stage, the second signal switches from the first voltage to the second voltage, and the third transistor is turned on.

[0109] In some embodiments, the coupling capacitance generated by the control signal switching from a high level to a low level will affect the small signal rail-to-rail amplifier circuit. Through the control method provided in the embodiment of the present disclosure, the control signal (i.e., the first signal) is switched twice in the first stage and the second stage, so that the coupling capacitance can be charged and discharged once, thereby eliminating the influence of the coupling capacitance on the small signal amplification.

[0110] In some embodiments, the first output terminal is connected to a storage unit; wherein the storage unit includes a storage transistor and a storage capacitor, the drain of the storage transistor is connected to the storage capacitor, and the gate of the storage transistor is connected to the first output terminal; the control method also includes: in the first stage and the second stage, the storage transistor is turned on.

[0111] In some embodiments, the source of the storage transistor is connected to the sensing amplifier module; after the second stage, a sensing stage is further included; in the sensing stage, the sensing amplifier module is used to sense the storage data in the storage unit.

[0112] In some embodiments, the sense amplifier module includes a bit line, a reference bit line, and a sense amplifier coupled between the bit line and the reference bit line.

[0113] The first signal undergoes a drop and a rise in the first stage and the second stage respectively, so that the coupling capacitor is discharged and charged once, thereby eliminating the influence of the coupling capacitor on the voltages on the bit line and the reference bit line, and avoiding the influence of the coupling capacitor on the storage unit read operation.

[0114] In some embodiments, the storage transistor and the second transistor are N-type transistors, and the first transistor is a P-type transistor; the control method further includes: the first voltage is greater than the second voltage.

[0115] In some embodiments, the storage transistor and the second transistor are P-type transistors, and the first transistor is an N-type transistor; the control method further includes: the first voltage is less than the second voltage.

[0116] It should be noted here that the description of the control method of the drive circuit above is similar to the description of the drive circuit embodiment above, and has similar beneficial effects as the drive circuit embodiment. For technical details not disclosed in the control method embodiment of the drive circuit disclosed in the present invention, please refer to the description of the drive circuit embodiment disclosed in the present invention for understanding.

[0117] The embodiment of the present disclosure provides a driving circuit and a control method thereof, wherein the driving circuit comprises: a first driving module and a coupling elimination module; the first driving module comprises a first control terminal, a first output terminal, a first input terminal and a second input terminal connected to the coupling elimination module; the first driving module is configured to output a target voltage in a first stage and a second stage, wherein the first stage is earlier than the second stage; the first driving module is configured to synchronize the input voltage of the first input terminal to the first output terminal in response to the first control terminal switching from the first voltage to the second voltage in the first stage; the first driving module is configured to synchronize the input voltage of the second input terminal to the first output terminal in response to the first control terminal switching from the second voltage to the first voltage in the second stage; the target voltage is between the first voltage and the second voltage. The embodiment of the present disclosure utilizes the coupling elimination module to switch the input signal of the first control terminal twice in the first stage and the second stage respectively, so that the coupling capacitor between the first control terminal and other devices undergoes one charge and one discharge, thereby eliminating the influence of the coupling capacitor on the circuit.

[0118] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0119] The above description is only a preferred embodiment of the present disclosure, and does not limit the patent scope of the present disclosure. All equivalent structural changes made by using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present disclosure.

Claims

1. A driving circuit, characterized in that: include: A first driving module and a coupling elimination module; the first driving module comprises a first control terminal, a first output terminal, a first input terminal and a second input terminal connected to the coupling elimination module; The first driving module is configured to output a target voltage in a first stage and a second stage, the first stage being earlier than the second stage; The first driving module is configured to synchronize the input voltage of the first input terminal to the first output terminal in response to the first control terminal switching from the first voltage to the second voltage during the first stage; The first driving module is configured to synchronize the input voltage of the second input terminal to the first output terminal in response to the first control terminal switching from the second voltage to the first voltage during the second stage; The target voltage is between the first voltage and the second voltage.

2. The driving circuit according to claim 1, characterized in that: The first driving module includes a first transistor and a second transistor, and the first transistor and the second transistor have different doping types; The gate of the first transistor and the gate of the second transistor are connected to the first control terminal, the drain of the first transistor and the drain of the second transistor are connected to the first output terminal; the source of the first transistor is the first input terminal, and the source of the second transistor is the second input terminal; The first driving module is configured to turn on the first transistor in the first phase, and turn on the second transistor in the second phase.

3. The driving circuit according to claim 2, characterized in that: The coupling elimination module comprises a second control terminal, a third input terminal and a fourth input terminal connected to the second voltage, the first input terminal and the third input terminal are connected to a target voltage source; The coupling elimination module is configured to synchronize the input voltage of the fourth input terminal to the second input terminal in response to the first voltage inputted from the second control terminal during the first stage; The coupling elimination module is configured to synchronize the input voltage of the third input terminal to the second input terminal in response to the second control terminal switching from the first voltage to the second voltage during the second stage.

4. The driving circuit according to claim 3, characterized in that: The first output terminal is connected to a storage unit; wherein the storage unit comprises a storage transistor and a storage capacitor, the drain of the storage transistor is connected to the storage capacitor, and the gate of the storage transistor is connected to the first output terminal; The storage transistor is configured to be turned on in the first phase and the second phase.

5. The driving circuit according to claim 4, characterized in that: The storage transistor and the second transistor are N-type transistors, the first transistor is a P-type transistor; the first voltage is greater than the second voltage.

6. The driving circuit according to claim 4, characterized in that: The storage transistor and the second transistor are P-type transistors, the first transistor is an N-type transistor; the first voltage is less than the second voltage.

7. The driving circuit according to claim 3, characterized in that: The coupling elimination module includes a third transistor and a fourth transistor, the third transistor has the same doping type as the first transistor, and the fourth transistor has the same doping type as the second transistor; The gate of the third transistor and the gate of the fourth transistor are connected to the second control terminal, the drain of the third transistor and the drain of the fourth transistor are connected to the second input terminal; the source of the third transistor is the third input terminal, and the source of the fourth transistor is the fourth input terminal; The coupling elimination module is configured to turn on the fourth transistor in the first stage; The coupling elimination module is configured to turn on the third transistor in the second stage.

8. The driving circuit according to claim 4, characterized in that: The source of the storage transistor is connected to the sensing amplifier module; The sense amplification module is configured to sense storage data in the storage unit after the second stage.

9. A control method for a driving circuit, characterized in that: The driving circuit includes a first driving module and a coupling elimination module, wherein the first driving module includes a first control terminal, a first output terminal, a first input terminal, and a second input terminal connected to the coupling elimination module; the control method includes: In a first stage and a second stage, a first signal is applied to the first control terminal to make the first driving module output a target voltage, the first stage being earlier than the second stage; In the first stage, the first signal is switched from a first voltage to a second voltage, so that the first driving module synchronizes the input voltage of the first input terminal to the first output terminal; the target voltage is between the first voltage and the second voltage; In the second stage, the first signal is switched from the second voltage to the first voltage, so that the first driving module synchronizes the input voltage of the second input terminal to the first output terminal.

10. The control method according to claim 9, characterized in that: The first driving module includes a first transistor and a second transistor, and the first transistor and the second transistor have different doping types; The gate of the first transistor and the gate of the second transistor are connected to the first control terminal, and the drain of the first transistor and the drain of the second transistor are connected to the first output terminal; The source of the first transistor is the first input terminal, and the source of the second transistor is the second input terminal; The control method further comprises: In the first stage, the first signal is switched from a first voltage to a second voltage to turn on the first transistor; In the second phase, the first signal is switched from the second voltage to the first voltage to turn on the second transistor.

11. The control method according to claim 10, characterized in that: The coupling elimination module comprises a second control terminal, a third input terminal and a fourth input terminal connected to the second voltage, the first input terminal and the third input terminal are connected to a target voltage source; The control method further comprises: Applying a second signal to the second control terminal; wherein, in the first stage, the second signal is maintained at the first voltage, so that the coupling elimination module synchronizes the voltage of the fourth input terminal to the second input terminal; In the second stage, the second signal is switched from the first voltage to the second voltage, so that the coupling elimination module synchronizes the voltage of the third input terminal to the second input terminal.

12. The control method according to claim 11, characterized in that: The first output terminal is connected to a storage unit; wherein the storage unit includes a storage transistor and a storage capacitor, the drain of the storage transistor is connected to the storage capacitor, and the gate of the storage transistor is connected to the first output terminal; the control method further includes: In the first phase and the second phase, the storage transistor is turned on.

13. The control method according to claim 12, characterized in that: The storage transistor and the second transistor are N-type transistors, and the first transistor is a P-type transistor; The control method further includes: the first voltage is greater than the second voltage.

14. The control method according to claim 12, characterized in that: The storage transistor and the second transistor are P-type transistors, and the first transistor is an N-type transistor; The control method further includes: the first voltage is less than the second voltage.

15. The control method according to claim 11, characterized in that: The coupling elimination module includes a third transistor and a fourth transistor, the third transistor has the same doping type as the first transistor, and the fourth transistor has the same doping type as the second transistor; The gate of the third transistor and the gate of the fourth transistor are connected to the second control terminal, the drain of the third transistor and the drain of the fourth transistor are connected to the second input terminal; the source of the third transistor is the third input terminal, and the source of the fourth transistor is the fourth input terminal; the control method further includes: In the first stage, the second signal maintains the first voltage, and the fourth transistor is turned on; In the second stage, the second signal is switched from the first voltage to the second voltage, and the third transistor is turned on.

16. The control method according to claim 12, characterized in that: The source of the storage transistor is connected to the sensing amplifier module; After the second stage, a sensing stage is further included; in the sensing stage, the sensing amplification module is used to sense the storage data in the storage unit.

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