Clock gating circuit, chip and electronic equipment
By designing a clock gate circuit, using the cooperation of the comparison unit and the control unit to determine whether the clock of the register is turned off, the problem of excessive power consumption in the integrated circuit is solved, and higher performance and longer battery life are achieved.
Patent Information
- Application Number
- CN202411553861.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-01
- Publication Date
- 2025-02-11
AI Technical Summary
In integrated circuit designs, excessive power consumption can cause chip overheating, performance degradation and even damage, especially in mobile devices, low-power designs can significantly extend battery life and improve user experience.
A clock gate circuit is designed, including an inverter, a comparison unit and a control unit. By comparing the comparison unit to compare whether the first data input signal is consistent with its delay signal, the control unit decides whether to turn off the clock of the register based on the comparison result, thereby saving dynamic power consumption.
By turning off unnecessary clock signals, dynamic power consumption of the register is reduced, circuit performance is improved, and battery life is extended. At the same time, by placing the control unit in advance, the clock power consumption of the buffer unit on the clock tree is optimized, reducing power consumption waste.
Smart Images
Figure CN119420347A_ABST
Abstract
Description
Technical Field
[0001] The present application belongs to the field of integrated circuits, and specifically relates to a clock gating circuit, a chip and an electronic device. Background Art
[0002] In integrated circuit design, power consumption is a particularly important indicator. If the chip consumes too much power, a lot of heat will be generated. If there is no effective heat dissipation measure, it may cause the chip to overheat, performance degradation or even damage. By reducing power consumption, heat generation can be reduced, allowing the chip to run at a higher frequency and higher performance. Especially in mobile devices such as smartphones, tablets and laptops, low-power design can significantly extend battery life and improve user experience. Summary of the invention
[0003] In view of this, the purpose of the present application is to provide a clock gating circuit, a chip and an electronic device to reduce the power consumption of the circuit, thereby improving the performance of the circuit.
[0004] The embodiment of the present application is implemented as follows:
[0005] In a first aspect, an embodiment of the present application provides a clock gating circuit, comprising: an inverter, a comparison unit and a control unit; the input end of the inverter is used to connect to the data output end of a register, and the output end of the inverter is used to connect to the data input end of the register; the comparison unit is used to compare a first data input signal with a second data input signal for consistency, and output a comparison result, wherein the second data input signal is obtained by delaying the first data input signal, and the delay difference between the first data input signal and the second data input signal is greater than or equal to one times the clock period of the register, and less than two times the clock period of the register; the input end of the control unit is used to receive the comparison result and the clock input to the register, and the output end of the control unit is connected to the clock input end of the register; the control unit is used to determine whether to turn off the clock of the register according to the comparison result.
[0006] In the above embodiment, the comparison unit compares whether the first data input signal and the delayed signal of the first data input signal (i.e., the second data input signal) are consistent, so that the control unit decides whether to turn off the clock of the register according to the comparison result. For example, when the comparison result indicates that the first data input signal is consistent with the second data input signal, the control unit turns off the clock of the register. Since when the first data input signal is consistent with the second data input signal, it means that the input of the register in the current cycle has not changed compared with the input of the register in the previous cycle, the register does not need to collect the current value to output the correct value, because the register will save the value of the previous cycle by default; when the register does not need to collect the current value, by turning off the clock of the register, the register will not sample the current value, thereby saving dynamic power consumption on the clock. At the same time, by inserting an inverter between the output terminal Q and the input terminal D of the register, the register and the comparison unit can be decoupled, so that the comparison unit can compare the first data input signal and the second data input signal, thereby allowing the control unit to be advanced, that is, the control unit can be placed at the front of the clock tree, further optimizing the clock power consumption of the buffer unit on the clock tree, and further improving the power consumption problem of the buffer unit on the clock tree. At the same time, the delay of the second data input signal relative to the first data input signal is greater than one times the clock cycle of the register so that the previous cycle value of the second data input signal arrives in the next clock cycle; and less than the clock cycles of two registers so as to ensure that the second data input signal is also switched cycle by cycle to ensure timing correctness, and at the same time, an additional timing margin can be added to ensure the correctness of the comparison logic.
[0007] In combination with a possible implementation manner of the embodiment of the first aspect, the clock gating circuit further includes: a delay unit connected to the comparison unit, and the delay unit is used to delay the received first data input signal to obtain the second data input signal.
[0008] In the above embodiment, by setting a delay unit, only the first data input signal is required, and there is no need to input the first data input signal and the second data input signal at the same time. The second data input signal can be obtained by delaying the first data input signal using the delay unit, thereby simplifying the signal control process.
[0009] In combination with a possible implementation manner of the embodiment of the first aspect, the clock gating circuit further includes: a buffer unit, and the output end of the control unit is connected to the clock input end of the register through the buffer unit.
[0010] In the above embodiment, since the control unit is moved forward to the front of the clock tree, the distance between the output end of the control unit and the clock input end of the register is lengthened. Therefore, the attenuation of the clock signal is reduced by setting a buffer unit between the output end of the control unit and the clock input end of the register. At the same time, since the control unit is moved forward to the front of the clock tree, the control unit can control more devices, further optimizing the clock power consumption of the buffer unit on the clock tree.
[0011] In combination with a possible implementation manner of the first aspect, if the time required for the first data input signal to reach a stable state is k times the clock period of the register, k is greater than or equal to (xy) and less than or equal to x; the maximum delay of the buffer unit is (x-1) times the clock period of the register, and the minimum delay of the buffer unit is (xy) times the clock period of the register; wherein x and y are both integers greater than or equal to 1, and (xy) is an integer greater than or equal to 0.
[0012] In the above embodiment, in order to prevent the control unit from being too advanced to meet the timing requirement, the above constraints are set to ensure that the control unit in advance will not change the value of the register, but will only affect the time when the correct value arrives.
[0013] In combination with a possible implementation manner of the first aspect, the comparison unit includes: a first logic gate, a first input end of the first logic gate is used to receive the first data input signal, a second input end of the first logic gate is used to receive the second data input signal, and an output end of the first logic gate is connected to the control unit, wherein the first logic gate is an XOR gate or an XOR gate.
[0014] In the above embodiment, an XOR gate or an XNOR gate is used to compare the changes of the first data input signal and the second data input signal. For example, when the comparison result of the XOR gate is 1, it indicates that the first data input signal is inconsistent with the second data input signal. In this way, it can be quickly determined whether the first data input signal and the second data input signal are consistent. At the same time, since the XOR gate or the XNOR gate has a lower area and cost than the comparator, it is beneficial to reduce costs and circuit area.
[0015] In combination with a possible implementation manner of the first aspect, the comparison unit includes: an XOR gate, a first input end of the XOR gate is used to receive the first data input signal, a second input end of the XOR gate is used to receive the second data input signal, and an output end of the XOR gate is connected to the control unit.
[0016] In the above embodiment, an XOR gate is used to compare the changes of the first data input signal and the second data input signal. For example, when the comparison result is 1, it indicates that the first data input signal is inconsistent with the second data input signal. In this way, it can be quickly determined whether the first data input signal and the second data input signal are consistent. At the same time, since the XOR gate has a lower area and cost than the comparator, it is beneficial to reduce costs and circuit area.
[0017] In combination with a possible implementation manner of the first aspect, the comparison unit includes: an XENO gate, wherein the first input end of the XENO gate is used to receive the first data input signal, the second input end of the XENO gate is used to receive the second data input signal, and the output end of the XENO gate is connected to the control unit.
[0018] In the above embodiment, an XEN-NOR gate is used to compare the changes of the first data input signal and the second data input signal. For example, when the comparison result is 0, it indicates that the first data input signal is inconsistent with the second data input signal. In this way, it can be quickly determined whether the first data input signal and the second data input signal are consistent. At the same time, since the XEN-NOR gate has a lower area and cost than the comparator, it is beneficial to reduce the overall cost of the circuit and reduce the circuit area.
[0019] In combination with a possible implementation manner of the first aspect embodiment, the control unit includes: a second logic gate, a first input end of the second logic gate is used to receive the comparison result, a second input end of the second logic gate is used to receive the clock of the register, and an output end of the second logic gate is connected to the clock input end of the register, wherein the second logic gate is one of an AND gate, a NAND gate, an OR gate, and a NOR gate.
[0020] In the above embodiment, a logic gate (one of an AND gate, a NAND gate, an OR gate, and a NOR gate) is used as a control device to control whether to turn off the clock of the register. Since the logic gate has a small area and low cost, it is beneficial to reduce the overall cost of the circuit and reduce the circuit area.
[0021] In combination with a possible implementation manner of the embodiment of the first aspect, if the comparison unit includes an XOR gate, the control unit includes: an AND gate or a NAND gate.
[0022] In the above embodiment, if the comparison unit is implemented by an XOR gate, the control unit can use an AND gate or a NAND gate as a control device to control whether to turn off the clock of the register. By combining an XOR gate + an AND gate or a NAND gate, the clock of the register can be turned off. While achieving its purpose, it is beneficial to reduce the overall cost of the circuit and reduce the circuit area.
[0023] In combination with a possible implementation manner of the embodiment of the first aspect, if the comparison unit includes an XNOR gate, the control unit includes: an OR gate or a NOR gate.
[0024] In the above embodiment, if the comparison unit is implemented by an XNOR gate, the control unit can use an OR gate or a NOR gate as a control device to control whether to turn off the clock of the register. The clock of the register can be turned off by combining an XNOR gate + an OR gate or a NOR gate. While achieving its purpose, it is beneficial to reduce the overall cost of the circuit and reduce the circuit area.
[0025] In combination with a possible implementation manner of the first aspect, the clock gating circuit also includes: an isolation unit, which is used to be connected to the data output end of the register, and the isolation unit is used to isolate the reverse influence of the subsequent circuit on the register, wherein the subsequent circuit is a circuit connected to the output end of the isolation unit.
[0026] In the above embodiment, an isolation unit is provided at the data output end of the register. The isolation unit is used to facilitate adding related constraints without affecting the reverse circuit between the Q end and the D end of the register, thereby reducing the reverse impact of subsequent related constraints on the register.
[0027] In a second aspect, an embodiment of the present application further provides a chip, comprising a clock gating circuit provided in the embodiment of the first aspect described above and / or in any possible implementation manner in combination with the embodiment of the first aspect.
[0028] In a third aspect, an embodiment of the present application further provides an electronic device, comprising a chip provided in the embodiment of the second aspect described above.
[0029] Other features and advantages of the present application will be described in the following description. The purpose and other advantages of the present application can be realized and obtained through the structures specifically pointed out in the written description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings. The above and other purposes, features and advantages of the present application will be more clearly shown in the drawings.
[0031] Figure 1 A schematic diagram showing the connection between a first clock gating circuit and a register provided in an embodiment of the present application is shown.
[0032] Figure 2A schematic diagram showing the connection between a second clock gating circuit and a register provided in an embodiment of the present application is shown.
[0033] Figure 3 A schematic diagram showing the connection between a third clock gating circuit and a register provided in an embodiment of the present application is shown.
[0034] Figure 4 A schematic diagram showing the connection between a fourth clock gating circuit and a register provided in an embodiment of the present application is shown.
[0035] Figure 5 A circuit schematic diagram of a clock gating circuit provided in an embodiment of the present application is shown.
[0036] Figure 6 A waveform timing diagram of a clock gating circuit provided in an embodiment of the present application is shown.
[0037] Figure 7 A schematic structural diagram of an electronic device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION
[0038] The technical solutions in the embodiments of the present application will be described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The following embodiments can be used as examples to more clearly illustrate the technical solutions of the present application, and cannot be used to limit the scope of protection of the present application. It will be appreciated by those skilled in the art that, in the absence of conflict, the features in the following embodiments and embodiments can be combined with each other.
[0039] It should be noted that similar numbers and letters represent similar items in the following figures, so once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. At the same time, in the description of this application, relational terms such as "first", "second", etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.
[0040] Furthermore, the term "and / or" in this application is merely a term used to describe the association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B may represent three situations: A exists alone, A and B exist at the same time, and B exists alone.
[0041] In the description of the embodiments of the present application, unless otherwise clearly specified or limited, the technical term "connection" may refer to a direct connection or an indirect connection through an intermediate medium.
[0042] When designing low-power circuits, power consumption can be reduced from two directions: "static power consumption" and "dynamic power consumption". Among them, static power consumption consists of two parts. One part is gate leakage power consumption (Gate Leakage Power), which is the conduction power consumption from the source to the drain of the device, which is related to the thickness of the gate oxide layer and the power supply voltage; the other part is intrinsic leakage power consumption (Intrinsic Leakage Power), which is caused by the low threshold voltage of the device. Dynamic power consumption mainly consists of two parts, one part is the switching power consumption (Net Switching Power) on the chip connection; the other part is the internal power consumption (Internal Power) of the transistor unit, both of which are related to the charging and discharging of the equivalent capacitance when the chip is working.
[0043] In specific implementation, different low-power technologies can be divided into coarse-grained and fine-grained according to the degree of implementation. For example, shutting down the entire module is to save power from a relatively large range, which is called coarse-grained, while clock gating is accurate to specific registers, which can be called fine-grained control.
[0044] In low-power technology, there is a method for reducing dynamic power consumption in a fine-grained manner called self-gating technology. An embodiment of the present application provides a clock gating circuit for reducing dynamic power consumption in a fine-grained manner. The clock gating circuit is used to save the dynamic power consumption of registers.
[0045] The clock gating circuit provided in the embodiment of the present application can be used as a test circuit for power consumption verification analysis; it can also be used as a part of the physical circuit in the actual chip design to dynamically turn off and on the clock signal during operation, thereby reducing power consumption while maintaining performance.
[0046] In chip design or circuit design, there is a class of static signals and quasi-static signals (slowly changing signals), such as control signals or TDR (Test Design Register, where TDR is used to read or write test stimulus) signals in DFT (Design for Test) design. These signals do not need to change every cycle. They usually stop changing or change slowly after a certain period of time. Their own flip rate is low. At the same time, these signals may be used to control other logics. Therefore, in the prior art, clock gating design is not used to control their power consumption. Therefore, self-gating design can be inserted to optimize the dynamic power consumption of these signals on the clock network.
[0047] The clock gating circuit provided in the embodiment of the present application can be applied to static signals and quasi-static signals that complete flipping within a certain period. The clock gating circuit proposed in the present application can place the control unit at a more forward position in the clock tree according to the characteristics of static signals and quasi-static signals (such as no change or slow change within a certain period of time), thereby further optimizing the clock power consumption without affecting the function of the circuit.
[0048] Combine the following Figure 1 The clock gating circuit provided in the embodiment of the present application is described. Figure 1 As shown, the clock gating circuit provided in the embodiment of the present application includes: an inverter (INV), a comparison unit and a control unit, and the comparison unit is connected to the control unit.
[0049] The input end of the inverter is used to connect to the data output end (Q end) of the register (Register), and the output end of the inverter is used to connect to the data input end (D end) of the register. The comparison unit is used to compare the first data input signal (such as represented by D1) with the second data input signal (such as represented by D0) for consistency, output the comparison result, and output the comparison result to the control unit. The input end of the control unit is used to receive the comparison result and the clock clk of the input register, and the output end of the control unit is connected to the clock input end (such as the CLK end) of the register. The control unit is used to determine whether to turn off the clock of the register according to the comparison result.
[0050] The second data input signal D0 is obtained by delaying the first data input signal D1, and the second data input signal is a delayed signal of the first data input signal, which can represent the first data input signal of the previous cycle. The comparison unit is used to compare the consistency of the first data input signal and the second data input signal, which is equivalent to comparing whether the first data input signal of the current cycle is consistent with the first data input signal of the previous cycle, or comparing whether the first data input signal of the current cycle has changed with the first data input signal of the previous cycle, so that the control unit decides whether to turn off the clock of the register according to the comparison result.
[0051] The first data input signal is a data output signal of the previous stage circuit of the clock gating circuit. It can be understood that the clock gating circuit can be used as a part of the chip design, and the input end of the clock gating circuit can also be connected to the output end of its previous stage circuit, and can receive the data output signal of the previous stage circuit of the clock gating circuit. Similarly, the output end of the clock gating circuit can also be connected to the input end of its next stage circuit, and is used to output the data input signal to the next stage circuit.
[0052] In the embodiment of the present application, an inverter is inserted between the output terminal Q and the input terminal D of the register. When the clock of the register is not turned off, the output terminal value of the register changes from 0 (indicating a low level) to 1 (indicating a high level) in the first cycle by default, and changes to 0 again in the next cycle, and so on. If the clock of the register is turned off, the register maintains the state of the previous cycle. Therefore, by controlling when the clock of the register is turned off, the output value of the register can be controlled.
[0053] By inserting an inverter between the output terminal Q and the input terminal D of the register, the register and the comparison unit can be decoupled so that the first data input signal is no longer input into the data input terminal of the register. The comparison unit can compare the first data input signal of the register with the first data input signal of the previous cycle, so that during the power consumption verification analysis, the comparison unit and the control unit can be advanced (advanced to a position far away from the register, rather than close to the register) to save dynamic power consumption on the clock tree, because the advanced control unit will not change the value of the register when it meets the static timing, and will only affect the time when the correct value of the register arrives.
[0054] During power consumption verification analysis, the clock gating circuit provided in the embodiment of the present application can place the control unit at the front of the clock tree, thereby further optimizing the clock power consumption of the buffer unit on the clock tree, thereby improving the power consumption waste problem of the buffer unit on the clock tree.
[0055] Since the clock gating circuit provided in the embodiment of the present application can be used as a test circuit, and can also be used as a part of a physical circuit in an actual chip design, in one possible implementation, when the clock gating circuit is used as a part of a physical circuit, the clock gating circuit provided in the embodiment of the present application can also include a register. When the clock gating circuit is used as a test circuit, the above-mentioned register may not be included.
[0056] In order to ensure the correctness of the comparison logic, the delay difference between the first data input signal D1 and the second data input signal D0 must be greater than or equal to one time of the register clock cycle (clk), and less than twice the register clock cycle. For example, TDleay1 is used to represent the delay difference between the first data input signal and the second data input signal, then 1*clk≤TDleay1<2*clk. For example, in a possible implementation, TDleay1=1.5*clk, and by adding an additional timing margin (Margin), the correctness of the comparison logic can be ensured.
[0057] Since the comparison unit compares the first data input signal with the delayed signal of the first data input signal (ie, the second data input signal), therefore, in a possible implementation manner, Figure 2As shown, the clock gating circuit further includes: a delay cell (Delay Cell), the delay cell is connected to the comparison unit, and the delay cell is used to delay the received first data input signal to obtain a second data input signal.
[0058] In one embodiment, the number of delay units is at least one, and the received first data input signal is delayed by at least one delay unit so that the delay difference between the first data input signal D1 and the second data input signal D0 satisfies the timing constraint of 1*clk≤TDleay1<2*clk.
[0059] Since the clock gating circuit provided in the embodiment of the present application can place the control unit at the front of the clock tree, thereby further optimizing the clock power consumption of the buffer unit on the clock tree, therefore, in a possible implementation manner, Figure 3 As shown, the clock gating circuit may further include: a buffer unit, the output end of the control unit is connected to the clock input end of the register through the buffer unit. In the embodiment of the present application, the number of the buffer unit is at least one, and multiple buffer units may be designed under the premise of meeting the timing requirements.
[0060] After chip layout and routing, the clock tree may be very long. In order to solve the DRC (Design Rule Check) problem, many buffer units will be inserted into the clock tree. These buffer units will increase dynamic power consumption as the clock flips. The control unit can be moved forward as much as possible to control more buffer units, thereby saving more dynamic power consumption. However, if the control unit is too far forward, the timing requirements will not be met. In order to avoid the control unit being too far forward and unable to meet the timing requirements, the timing requirements can be met by the following constraints. If the time required for the first data input signal to reach a stable state is k times the clock cycle of the register, that is, k*clk, k is greater than or equal to (xy) and less than or equal to x; then the maximum delay of the buffer unit is (x-1) times the clock cycle of the register, and the minimum delay of the buffer unit is (xy) times the clock cycle of the register; wherein x and y are both integers greater than or equal to 1, and (xy) is an integer greater than or equal to 0. When the signal reaches a stable state, its frequency, amplitude, phase, etc. will tend to be stable, and the frequency, amplitude, and phase can be allowed to fluctuate within an acceptable range (i.e., an error range).
[0061] For example, when constraining the first data input signal in the circuit in the timing SDC (Synopsys DesignConstraints, design constraint file), you can add a set_multicycle_path constraint. Assume that the following constraints are added: set_multicycle_path x-setup-to REG / D; set_multicycle_path y-hold-toREG / D, where REG / D represents the data input terminal of the register. This constraint means that the first data input signal needs to reach a stable state between xy and x clock cycles to ensure the change at the next moment.
[0062] The clock gating circuit provided in the embodiment of the present application needs to satisfy that the first data input signal reaches a stable state within a certain period, so as to meet the changes at the next moment. From the output end of the control unit to the clock input end (REG / CLK) of the register, the following constraints can also be added to meet the timing requirements, so as to ensure that the first data input signal reaches a stable state between the xy to x periods. Assuming that the control unit includes an AND gate (AND), the output end (AND / OUT) of the control unit to the clock input end (REG / CLK) of the register needs to satisfy the following constraints: set_max_delay(x-1)*clk_period-from AND / OUT-to REG / CLK; set_min_delay(xy)*clk_period-from AND / OUT-to REG / CLK. That is, the maximum delay of the buffer unit is (x-1) times the clock period of the register, and the minimum delay of the buffer unit is (xy) times the clock period of the register.
[0063] The first data input signal can be a static signal or a quasi-static signal. When performing power consumption verification analysis, the SDC constraint set_max_delay / set_min_delay can be used to allow the EDA (Electronic Design Automation) tool to automatically perform timing checks to ensure that the quasi-static signal reaches a stable state between the xy and x cycles. Designers can add the above timing constraints to the clock gating circuit of this application according to design requirements to ensure the correctness of the designed function.
[0064] When performing power verification analysis, in one implementation, if you need to add timing constraints to the register output after inserting the self-gating logic, you can add an isolation unit after the register output. The purpose of adding the isolation unit is to facilitate the subsequent addition of related constraints without affecting the change relationship between the Q end and the D end of the register. In this implementation, if Figure 4As shown, the clock gating circuit also includes: an isolation unit, the isolation unit is used to be connected to the data output end of the register, and the isolation unit is used to isolate the reverse influence of the subsequent circuit on the register. The subsequent circuit is a circuit connected to the output end of the isolation unit. The isolation unit can be a buffer unit.
[0065] It should be noted that, in some implementations, Figure 1 to Figure 4 The register in the schematic diagram shown can be used as part of the clock gating circuit. Accordingly, at this time, Figure 1 to Figure 4 Schematic diagram of a clock gating circuit provided for different embodiments of the present application.
[0066] In one implementation, the above-mentioned comparison unit may include: a first logic gate, the first input end of the first logic gate is used to receive a first data input signal, the second input end of the first logic gate is used to receive a second data input signal, and the output end of the first logic gate is connected to the control unit, wherein the first logic gate is an XOR gate or an XOR gate.
[0067] In one implementation, when the first logic gate is an XOR gate, the comparison unit may include: an XOR gate, wherein the first input end of the XOR gate is used to receive the first data input signal, the second input end of the XOR gate is used to receive the second data input signal, and the output end of the XOR gate is connected to the control unit. When the first data input signal D1 is the same as the second data input signal D0, the XOR gate output is 0, and when the first data input signal D1 is different from the second data input signal D0, the XOR gate output is 1. At this time, when the comparison result is 1, it indicates that the first data input signal is inconsistent with the second data input signal.
[0068] In one implementation, when the first logic gate is an XNOR gate, the comparison unit may include: an XNOR gate, wherein the first input end of the XNOR gate is used to receive the first data input signal, the second input end of the XNOR gate is used to receive the second data input signal, and the output end of the XNOR gate is connected to the control unit. When the first data input signal D1 is the same as the second data input signal D0, the XNOR gate output is 1, and when the first data input signal D1 is different from the second data input signal D0, the XNOR output is 0. At this time, when the comparison result is 0, it indicates that the first data input signal is inconsistent with the second data input signal.
[0069] Among them, the XNOR gate is also called the XNOR gate, and an XNOR gate can be formed by adding a NOT gate to the output end of the XOR gate. In one implementation, the XNOR gate can be formed by only a NAND gate or a NOR gate.
[0070] In one implementation, the comparison unit may further include a comparator, which is used to perform consistency comparison, wherein the first input terminal of the comparator is used to receive a first data input signal, the second input terminal of the comparator is used to receive a second data input signal, and the output terminal of the comparator is connected to the control unit.
[0071] In one implementation, when the comparison result indicates that the first data input signal is consistent with the second data input signal, the control unit turns off the clock of the register. When the first data input signal is consistent with the second data input signal, it means that the input of the register in the current cycle has not changed compared with the previous cycle, and the register does not need to collect the current value to output the correct value, because the register will save the value of the previous cycle by default. When the register does not need to collect the current value, by turning off the clock of the register, the register will not sample the current value, thereby saving dynamic power consumption on the clock.
[0072] A register is a circuit for storing one or more bits of binary information. The sampling mode of the register is usually related to the edge of the clock signal, which is used to determine the time when the data is read or written to the register. According to different sampling modes, the register can be divided into falling edge triggered sampling and rising edge triggered sampling. The register in the embodiment of the present application can be a register for falling edge triggered sampling or a register for rising edge triggered sampling.
[0073] In one possible implementation, the control unit may include: a second logic gate, a first input end of the second logic gate is used to receive a comparison result, a second input end of the second logic gate is used to receive a clock of a register, and an output end of the second logic gate is connected to the clock input end of the register, wherein the second logic gate is one of an AND gate, a NAND gate, an OR gate, and a NOR gate.
[0074] In a possible implementation manner, the structure of the control unit in the application embodiment can be determined according to the structure of the comparison unit. For example, if the comparison unit includes an XOR gate, the control unit can include an AND gate or a NAND gate. If the comparison unit includes an XOR gate, the control unit can include an OR gate or a NOR gate.
[0075] In a possible implementation manner, the structure of the control unit in the application embodiment can be determined according to the sampling method of the register and the comparison result.
[0076] For example, in one implementation, when the sampling mode of the register is rising edge triggered sampling, and when the comparison result is 1, indicating that the first data input signal is inconsistent with the second data input signal, the control unit may include: an AND gate, wherein the first input end of the AND gate is used to receive the comparison result, the second input end of the AND gate is used to receive the clock of the register, and the output end of the AND gate is connected to the clock input end of the register. At this time, the output of the AND gate depends on the clock of the register.
[0077] In one implementation, when the sampling mode of the register is rising edge triggered sampling, and when the comparison result is 0, indicating that the first data input signal is inconsistent with the second data input signal, the control unit may include: a NOR gate, wherein the first input end of the NOR gate is used to receive the comparison result, the second input end of the NOR gate is used to receive the clock of the register, and the output end of the NOR gate is connected to the clock input end of the register. At this time, the output of the NOR gate depends on the clock of the register.
[0078] In one implementation, when the sampling mode of the register is falling edge triggered sampling, and when the comparison result is 1, indicating that the first data input signal is inconsistent with the second data input signal, the control unit may include: a NAND gate, wherein the first input end of the NAND gate is used to receive the comparison result, the second input end of the NAND gate is used to receive the clock of the register, and the output end of the NAND gate is connected to the clock input end of the register. At this time, the output of the NAND gate depends on the clock of the register.
[0079] In one implementation, when the sampling mode of the register is falling edge triggered sampling, and when the comparison result is 0, indicating that the first data input signal is inconsistent with the second data input signal, the control unit may include: an OR gate, wherein the first input end of the OR gate is used to receive the comparison result, the second input end of the OR gate is used to receive the clock of the register, and the output end of the OR gate is connected to the clock input end of the register. At this time, the output of the OR gate depends on the clock of the register.
[0080] In one implementation, the AND gate, NAND gate, NOR gate or OR gate mentioned above can also be replaced by an integrated clock gating (ICG) control unit that realizes the same function. In this case, the control unit can include the ICG.
[0081] In order to better understand the above clock gating circuit, in one implementation, the schematic diagram of the clock gating circuit can be as follows: Figure 5 As shown. It is understandable that Figure 5 Only an embodiment in which the comparison unit includes an exclusive OR gate XOR and the control unit includes an AND gate AND is shown.
[0082] Assume that there is a 1.5-cycle delay from the output of the gated logic AND gate (AND / OUT) to the clock of the register (REG / CLK). When the data input D changes, a clock pulse needs to be generated at the output of the gated logic (AND / OUT), and then the register (REG) will flip from 0->1 or 1->0 after a delay of 1.5 clock cycles. Therefore, for the gated logic of the AND gate, the enable signal of the gated logic (XOR output) must be withdrawn after the clock flips from high level to low level, and the withdrawal time must be guaranteed to be completed before the next clock flip, otherwise multiple clock pulses will be generated. Figure 5 The waveform timing diagram of the clock gating circuit shown is as follows Figure 6 shown. Figure 6 The CLR in is the reset signal of the register (RNG), and high level is valid.
[0083] Assume that there is a 1.5-cycle delay from the output of the gated logic AND gate (AND / OUT) to the clock end of the register (REG / CLK), the other signals are ideal signals, and the delay between the two inputs of the XOR gate (XOR / IN1, XOR / IN0) is 1.5 clock cycles.
[0084] An embodiment of the present application also provides a chip, which includes the above-mentioned clock gating circuit. The chip shown in the present application may be a chip including a register, and the dynamic power consumption of the register can be optimized by adding a clock gating circuit to the chip.
[0085] In some possible implementations, the above-mentioned chips include but are not limited to processor chips, and processor chips include but are not limited to central processing unit (CPU), graphics processing unit (GPU), digital signal processor (DSP), application specific integrated circuit (ASIC), field programmable gate array (FPGA), etc.
[0086] The chip provided in the embodiment of the present application has the same implementation principle and technical effects as those in the aforementioned clock gating circuit embodiment. For the sake of brief description, for matters not mentioned in the chip embodiment, reference may be made to the corresponding contents in the aforementioned clock gating circuit embodiment.
[0087] The present application also provides an electronic device, which includes the above-mentioned chip. In a possible implementation manner, Figure 7 As shown, the electronic device 200 provided in the embodiment of the present application includes: a transceiver 210, a memory 220, a communication bus 230 and a processor 240.
[0088] The transceiver 210, the memory 220, and the processor 240 are electrically connected to each other directly or indirectly to realize data transmission or interaction. For example, these elements can be electrically connected to each other through one or more communication buses 230 or signal lines. Among them, the transceiver 210 is used to send and receive data. The memory 220 is used to store computer programs, wherein the computer program includes at least one software function module that can be stored in the memory 220 in the form of software or firmware (Firmware) or solidified in the operating system (Operating System, OS) of the electronic device 200. The processor 240 is used to execute the software function module or computer program stored in the memory 220.
[0089] Among them, the memory 220 can be, but is not limited to, random access memory (Random Access Memory, RAM), read only memory (Read Only Memory, ROM), programmable read-only memory (Programmable Read-Only Memory, PROM), erasable programmable read-only memory (Erasable Programmable Read-Only Memory, EPROM), electrically erasable read-only memory (Electric Erasable Programmable Read-Only Memory, EEPROM), etc.
[0090] The processor 240 may be an integrated circuit chip with signal processing capabilities. The above-mentioned processor may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), a graphics processing unit (GPU), an accelerated processing unit (Accelerated Processing Unit), a multimedia application processor (MAP), a microprocessor, etc.; it may also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. Or the processor 240 may also be any conventional processor, etc.
[0091] The electronic device 200 mentioned above includes but is not limited to mobile devices such as smart phones, tablets, and laptop computers.
[0092] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.
[0093] In addition, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
[0094] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.
Claims
1. A clock gating circuit, characterized in that: include: An inverter, wherein the input end of the inverter is used to connect to the data output end of the register, and the output end of the inverter is used to connect to the data input end of the register; a comparison unit, configured to compare the first data input signal with the second data input signal for consistency, and output a comparison result, wherein the second data input signal is obtained by delaying the first data input signal, the first data input signal is a data output signal of a previous stage circuit of the clock gating circuit, and a delay difference between the first data input signal and the second data input signal is greater than or equal to one time of the clock cycle of the register, and less than two times of the clock cycle of the register; A control unit, wherein the input end of the control unit is used to receive the comparison result and the clock input to the register, and the output end of the control unit is connected to the clock input end of the register; the control unit is used to determine whether to turn off the clock of the register according to the comparison result.
2. The clock gating circuit according to claim 1, characterized in that: The clock gating circuit further includes: A delay unit is connected to the comparison unit, and is used to delay the received first data input signal to obtain the second data input signal.
3. The clock gating circuit according to claim 1, characterized in that: The clock gating circuit further includes: A buffer unit, wherein the output end of the control unit is connected to the clock input end of the register through the buffer unit.
4. The clock gating circuit according to claim 3, characterized in that: If the time required for the first data input signal to reach a stable state is k times the clock period of the register, k is greater than or equal to (xy) and less than or equal to x; The maximum delay of the buffer unit is (x-1) times the clock period of the register, and the minimum delay of the buffer unit is (xy) times the clock period of the register; wherein x and y are both integers greater than or equal to 1, and (xy) is an integer greater than or equal to 0.
5. The clock gating circuit according to claim 1, characterized in that: The comparison unit includes: a first logic gate, a first input end of the first logic gate is used to receive the first data input signal, a second input end of the first logic gate is used to receive the second data input signal, and an output end of the first logic gate is connected to the control unit, wherein the first logic gate is an XOR gate or an XOR gate.
6. The clock gating circuit according to claim 1, characterized in that: The control unit includes: a second logic gate, a first input end of the second logic gate is used to receive the comparison result, a second input end of the second logic gate is used to receive the clock of the register, and an output end of the second logic gate is connected to the clock input end of the register, wherein the second logic gate is one of an AND gate, a NAND gate, an OR gate, and a NOR gate.
7. The clock gating circuit according to claim 6, characterized in that: If the comparison unit includes an XOR gate, the control unit includes an AND gate or a NAND gate.
8. The clock gating circuit according to claim 6, characterized in that: If the comparison unit includes an XNOR gate, the control unit includes an OR gate or a NOR gate.
9. The clock gating circuit according to any one of claims 1 to 8, characterized in that: The clock gating circuit further includes: An isolation unit, the isolation unit is used to be connected to the data output end of the register, and the isolation unit is used to isolate the reverse influence of the subsequent circuit on the register, wherein the subsequent circuit is a circuit connected to the output end of the isolation unit.
10. A chip, characterized in that: Comprising the clock gating circuit as described in any one of claims 1-9.
11. An electronic device, characterized in that: Comprising the chip as claimed in claim 10.