Pixel and image sensor

Abstract

The invention discloses a pixel and an image sensor, and relates to the technical field of image sensors, and the pixel comprises a light sensing unit which is used for sensing light to generate charges; the transmission unit is used for transmitting charges generated by the photosensitive unit to the floating diffusion node; the reset unit is used for resetting the pixels; the amplification unit is used for amplifying and outputting the voltage of the floating diffusion node to the storage unit; the storage unit is used for storing reset voltage and signal voltage; the switching unit is used for switching the exposure mode of the pixel and switching the conversion gain of the pixel in the exposure mode; the exposure mode comprises a global exposure mode and a roller exposure mode; the output unit is used for outputting reset voltage and signal voltage. The pixel supports global exposure and roller exposure, and supports a high dynamic range in a global exposure mode and a high dynamic range in a roller exposure mode.

Description

Technical Field

[0001] The present application relates to the technical field of image sensors, and in particular to a pixel and an image sensor. Background Art

[0002] The exposure methods of CMOS image sensors are divided into two categories: global exposure and drum exposure. Since global exposure is completed at the same time, no motion artifacts will be generated, which is suitable for imaging high-speed moving objects. Global exposure requires exposure at the same time, so the common multi-frame synthesis algorithm for achieving high dynamic range cannot be used during global exposure. Therefore, at this stage, most high dynamic range CMOS image sensors are drum exposure, and most technologies for improving dynamic range are developed based on drum exposure pixels. Therefore, how to achieve high dynamic range under global exposure has become a technical problem that needs to be solved urgently by technicians in this field. Summary of the invention

[0003] The purpose of the present application is to provide a pixel and an image sensor that supports global exposure and drum exposure, and supports a high dynamic range under a global exposure mode and a high dynamic range under a drum exposure mode.

[0004] In order to solve the above technical problems, the present application provides a pixel, comprising:

[0005] A photosensitive unit, a transmission unit, a reset unit, an amplification unit, a storage unit, a switching unit, and an output unit;

[0006] The photosensitive unit is used to generate charges by sensing light;

[0007] The transmission unit is used to transmit the charge generated by the photosensitive unit to the floating diffusion node when the transmission unit is turned on; the input end of the amplification unit serves as the floating diffusion node;

[0008] The reset unit is used to reset the pixel;

[0009] The amplifying unit is used to amplify the voltage of the floating diffusion node and output it to the storage unit;

[0010] The storage unit is used to store the reset voltage and the signal voltage;

[0011] The switching unit is used to switch the exposure mode of the pixel and the conversion gain of the pixel under the exposure mode; the exposure mode includes a global exposure mode and a drum exposure mode;

[0012] The output unit is used to output a reset voltage and a signal voltage.

[0013] In some embodiments, the switching unit includes:

[0014] a first switch unit, configured to connect the target capacitor in the storage unit to the input terminal of the output unit, and connect the target capacitor in the storage unit to the second switch unit when the first switch unit is turned on;

[0015] The second switch unit is used to connect the floating diffusion node with the input end of the output unit and the first switch unit when the second switch unit is turned on.

[0016] In some embodiments, the storage unit includes:

[0017] A first storage unit and a second storage unit;

[0018] The first storage unit is used to store one of a reset voltage and a signal voltage;

[0019] The second storage unit is used to store one of a reset voltage and a signal voltage;

[0020] The first storage unit and the second storage unit store different voltage types.

[0021] In some embodiments, the storage unit includes a third switch unit, a fourth switch unit, a first capacitor and a second capacitor; one end of the third switch unit is connected to the output end of the amplification unit, the other end of the third switch unit is connected to one end of the first capacitor and one end of the fourth switch unit, the other end of the first capacitor is grounded, the other end of the fourth switch unit is connected to one end of the second capacitor and the first switch unit, and the other end of the second capacitor is grounded.

[0022] In some embodiments, the transmission unit is controlled by a first control signal, and when the first control signal is a first level signal, the transmission unit is turned on; the reset unit is controlled by a second control signal, and when the second control signal is a first level signal, the reset unit is turned on, so that the floating diffusion node is connected to the power supply connected to the reset unit; the amplification unit is controlled by a third control signal, and when the third control signal is a first level signal, the output end of the amplification unit is grounded; the third switch unit is controlled by a fourth control signal, and when the fourth control signal is a first level signal, the third switch unit is turned on; the fourth switch unit is controlled by a fifth control signal, and when the fifth control signal is a first level signal, the fourth switch unit is turned on; the first switch unit is controlled by a sixth control signal, and when the sixth control signal is a first level signal, the first switch unit is turned on; the second switch unit is controlled by a seventh control signal, and when the seventh control signal is a first level signal, the second switch unit is turned on; the output unit is controlled by an eighth control signal, and when the eighth control signal is a first level signal, the output unit outputs a voltage.

[0023] In some embodiments, in the storage unit reset stage, the third control signal, the seventh control signal, and the sixth control signal are first level signals, and the fourth control signal and the fifth control signal are changed from second level signals to first level signals at a first preset time in the storage unit reset stage, and the second control signal, the first control signal, and the eighth control signal are second level signals; in the photosensitive unit reset stage, the third control signal and the eighth control signal are second level signals, and the fourth control signal, the fifth control signal, the second control signal, the first control signal, the seventh control signal, and the sixth control signal are first level signals; in the exposure stage, the third control signal and the first control signal are second level signals, and the fourth control signal, the fifth control signal, the second control signal, the eighth control signal, the seventh control signal, and the sixth control signal are first level signals; in the frame header time , the third control signal and the second control signal are second level signals, the eighth control signal, the seventh control signal and the sixth control signal are first level signals, the fifth control signal changes from the first level signal to the second level signal at the second preset time of the frame header time, the fourth control signal changes from the first level signal to the second level signal at the third preset time of the frame header time, and the first control signal changes from the second level signal to the first level signal at the fourth preset time of the frame header time; the fourth preset time is later than the third preset time, and the third preset time is later than the second preset time; in the readout stage, the third control signal, the fourth control signal, the second control signal and the first control signal are second level signals, the eighth control signal, the seventh control signal and the sixth control signal are first level signals; the fifth control signal changes from the second level signal to the first level signal between the read signal voltage and the read reset voltage and then changes to the second level signal.

[0024] In some embodiments, in the storage unit reset stage, the third control signal and the sixth control signal are first level signals, the fourth control signal and the fifth control signal are changed from second level signals to first level signals at a first preset time in the storage unit reset stage, and the second control signal, the first control signal, the eighth control signal and the seventh control signal are second level signals; in the photosensitive unit reset stage, the third control signal, the eighth control signal and the seventh control signal are second level signals, and the fourth control signal, the fifth control signal, the second control signal, the first control signal and the sixth control signal are first level signals; in the exposure stage, the third control signal, the first control signal and the seventh control signal are second level signals, and the fourth control signal, the fifth control signal, the second control signal, the first control signal and the eighth control signal are changed from second level signals to first level signals. and the sixth control signal is a first level signal; at the frame header time, the third control signal, the second control signal and the seventh control signal are second level signals, the fourth control signal, the eighth control signal and the sixth control signal are first level signals, the fifth control signal changes from the first level signal to the second level signal at the second preset time of the frame header time, and the first control signal changes from the second level signal to the first level signal at the third preset time of the frame header time; the third preset time is later than the second preset time; in the readout stage, the third control signal, the second control signal, the first control signal and the seventh control signal are second level signals, the fourth control signal, the eighth control signal and the sixth control signal are first level signals; the fifth control signal changes from the second level signal to the first level signal between the read signal voltage and the read reset voltage and then changes to the second level signal.

[0025] In some embodiments, in the storage unit reset stage, the third control signal and the seventh control signal are first level signals, the fourth control signal and the fifth control signal are changed from second level signals to first level signals at a first preset time in the storage unit reset stage, and the second control signal, the first control signal, the eighth control signal and the sixth control signal are second level signals; in the photosensitive unit reset stage, the third control signal, the fourth control signal, the fifth control signal, the eighth control signal and the sixth control signal are second level signals, and the second control signal, the first control signal and the seventh control signal are first level signals; in the exposure stage, the third control signal, the fourth control signal, the fifth control signal, the eighth control signal and the sixth control signal are second level signals. The third control signal, the fourth control signal, the fifth control signal, the first control signal, and the sixth control signal are second level signals, and the second control signal, the eighth control signal, and the seventh control signal are first level signals; at the frame header time, the third control signal, the fourth control signal, the fifth control signal, the second control signal, and the sixth control signal are second level signals, and the eighth control signal and the seventh control signal are first level signals, and the first control signal changes from the second level signal to the first level signal at the second preset moment of the frame header time; at the frame header time and when the first control signal is the second level signal, the reset voltage is read; after the frame header time and after the first control signal changes to the second level signal, the signal voltage is read.

[0026] In some embodiments, in the storage unit reset stage, the third control signal, the seventh control signal, and the sixth control signal are first level signals, the fourth control signal and the fifth control signal are changed from second level signals to first level signals at a first preset time in the storage unit reset stage, and the second control signal, the first control signal, and the eighth control signal are second level signals; in the photosensitive unit reset stage, the third control signal, the fourth control signal, the fifth control signal, and the eighth control signal are second level signals, and the second control signal, the first control signal, the seventh control signal, and the sixth control signal are first level signals; in the exposure stage, the third control signal, the fourth control signal, the fifth control signal, and the eighth control signal are second level signals. , the fifth control signal and the first control signal are second level signals, and the second control signal, the eighth control signal, the seventh control signal and the sixth control signal are first level signals; at the frame header time, the third control signal, the fourth control signal, the fifth control signal and the second control signal are second level signals, the eighth control signal, the seventh control signal and the sixth control signal are first level signals, and the first control signal changes from the second level signal to the first level signal at the second preset moment of the frame header time; at the frame header time and when the first control signal is the second level signal, read the reset voltage; after the frame header time and after the first control signal changes to the second level signal, read the signal voltage.

[0027] In some embodiments, the first switch unit includes:

[0028] a first transistor; a first end of the first transistor is connected to the storage unit, and a second end of the first transistor is connected to the second switch unit and the input end of the output unit; the first transistor is controlled by the sixth control signal.

[0029] In some embodiments, the second switch unit includes:

[0030] a second transistor; a first end of the second transistor is connected to the input end of the amplifying unit, a second end of the second transistor is connected to the input end of the first switching unit and the output unit, and the second transistor is controlled by the seventh control signal.

[0031] In some embodiments, the photosensitive unit includes:

[0032] A photosensitive diode; an anode of the photosensitive diode is grounded, and a cathode of the photosensitive diode is connected to the transmission unit.

[0033] In some embodiments, the transmission unit includes:

[0034] a third transistor; a first end of the third transistor is connected to the photosensitive unit, a second end of the third transistor is connected to the input end of the amplifying unit, and the third transistor is controlled by the first control signal.

[0035] In some embodiments, the resetting unit comprises:

[0036] a fourth transistor; a first end of the fourth transistor is connected to the input end of the amplifying unit, a second end of the fourth transistor is connected to a power supply, and the fourth transistor is controlled by the second control signal.

[0037] In some embodiments, the amplification unit comprises:

[0038] A fifth transistor and a sixth transistor; the first end of the fifth transistor is connected to the second end of the sixth transistor and serves as the output end of the amplifying unit, the second end of the fifth transistor is connected to a power supply, the third end of the fifth transistor serves as the input end of the amplifying unit, the first end of the sixth transistor is grounded, and the sixth transistor is controlled by the third control signal.

[0039] In some embodiments, the third switch unit includes:

[0040] a seventh transistor; a first end of the seventh transistor is connected to the output end of the amplifying unit, a second end of the seventh transistor is connected to one end of the first capacitor and one end of the fourth switch unit, and the seventh transistor is controlled by the fourth control signal.

[0041] In some embodiments, the fourth switch unit includes:

[0042] an eighth transistor; a first end of the eighth transistor is connected to the third switch unit, a second end of the eighth transistor is connected to one end of the second capacitor and the first switch unit, and the eighth transistor is controlled by the fifth control signal.

[0043] In some embodiments, the output unit includes:

[0044] A ninth transistor and a tenth transistor; the first end of the ninth transistor is connected to the second end of the tenth transistor, the second end of the ninth transistor is connected to a power supply, the third end of the ninth transistor serves as the input end of the output unit, the first end of the tenth transistor serves as the output end of the output unit, and the tenth transistor is controlled by the eighth control signal.

[0045] In order to solve the above technical problem, the present application also provides an image sensor, comprising the pixels as described above.

[0046] The pixel provided in the present application includes: a photosensitive unit, a transmission unit, a reset unit, an amplification unit, a storage unit, a switching unit and an output unit; the photosensitive unit is used to generate charge by sensing light;

[0047] The transmission unit is used to transmit the charge generated by the photosensitive unit to the floating diffusion node when the transmission unit is turned on; the input end of the amplification unit serves as the floating diffusion node; the reset unit is used to reset the pixel; the amplification unit is used to amplify the voltage of the floating diffusion node and output it to the storage unit; the storage unit is used to store the reset voltage and the signal voltage; the switching unit is used to switch the exposure mode of the pixel and the conversion gain of the switching pixel in the exposure mode; the exposure mode includes a global exposure mode and a drum exposure mode; the output unit is used to output the reset voltage and the signal voltage.

[0048] It can be seen that the pixel provided in the present application is provided with a switching unit, and the exposure mode of the pixel can be switched to a global exposure mode or a drum exposure mode by the switching unit. In the global exposure mode, the switching of different conversion gains can be achieved by the switching unit. In the drum exposure mode, the switching of different conversion gains can be achieved by the switching unit. Thereby, the pixel supports global exposure and drum exposure, and supports a high dynamic range under the global exposure mode and a high dynamic range under the drum exposure mode.

[0049] The image sensor provided in this application also has the above-mentioned technical effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the prior art and the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0051] Figure 1 A schematic diagram of a pixel provided in an embodiment of the present application;

[0052] Figure 2 A schematic diagram of a specific pixel provided in an embodiment of the present application;

[0053] Figure 3 The first signal timing diagram provided in the embodiment of the present application;

[0054] Figure 4 A second signal timing diagram provided in an embodiment of the present application;

[0055] Figure 5 A third signal timing diagram provided in an embodiment of the present application;

[0056] Figure 6 A fourth signal timing diagram provided in an embodiment of the present application;

[0057] Figure 7 A schematic diagram of another specific pixel provided in an embodiment of the present application;

[0058] Figure 8 A schematic diagram of another specific pixel provided in an embodiment of the present application;

[0059] Fig. 9 A schematic diagram of another specific pixel provided in an embodiment of the present application. DETAILED DESCRIPTION

[0060] The core of this application is to provide a pixel and image sensor that supports global exposure and drum exposure, and supports high dynamic range under global exposure mode and high dynamic range under drum exposure mode.

[0061] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0062] Please refer to Figure 1 , Figure 1 A schematic diagram of a pixel provided in an embodiment of the present application, referring to Figure 1 As shown, the pixel includes:

[0063] A photosensitive unit 10, a transmission unit 20, a reset unit 30, an amplification unit 40, a storage unit 50, a switching unit 60 and an output unit 70;

[0064] The photosensitive unit 10 is used for generating charges by sensing light;

[0065] The transmission unit 20 is used to transmit the charge generated by the photosensitive unit 10 to the floating diffusion node when the transmission unit 20 is turned on; the input end of the amplification unit 40 serves as the floating diffusion node;

[0066] The reset unit 30 is used to reset the pixel;

[0067] The amplifying unit 40 is used to amplify the voltage of the floating diffusion node and output it to the storage unit 50;

[0068] The storage unit 50 is used to store the reset voltage and the signal voltage;

[0069] The switching unit 60 is used to switch the exposure mode of the pixel and the conversion gain of the pixel under the exposure mode; the exposure mode includes a global exposure mode and a drum exposure mode;

[0070] The output unit 70 is used to output a reset voltage and a signal voltage.

[0071] In this embodiment, the pixel includes a photosensitive unit 10, a transmission unit 20, a reset unit 30, an amplifying unit 40, a storage unit 50, a switching unit 60 and an output unit 70. The photosensitive unit 10 is connected to the transmission unit 20, and the transmission unit 20 and the reset unit 30 are both connected to the input end of the amplifying unit 40, and the input end of the amplifying unit 40 serves as a floating diffusion node. The output end of the amplifying unit 40 is connected to the storage unit 50. The switching unit 60 connects the floating diffusion node, the storage unit 50 and the output unit 70. The exposure mode of the pixel can be switched to a global exposure mode or a drum exposure mode by the switching unit 60. In the global exposure mode, the switching of different conversion gains can be achieved by the switching unit 60. In the drum exposure mode, the switching of different conversion gains can be achieved by the switching unit 60.

[0072] refer to Figure 2 As shown, in some embodiments, the switching unit 60 includes:

[0073] a first switch unit 601, configured to connect the target capacitor in the storage unit to the input terminal of the output unit, and connect the target capacitor in the storage unit to the second switch unit 602 when the first switch unit 601 is turned on;

[0074] The second switch unit 602 is used to connect the floating diffusion node with the input end of the output unit and the first switch unit 601 when the second switch unit 602 is turned on.

[0075] One end of the first switch unit 601 is connected to the storage unit 50, the other end of the first switch unit 601 is connected to one end of the second switch unit 602 and the input end of the output unit 70, and the other end of the second switch unit 602 is connected to the floating diffusion node. When the first switch unit 601 is turned on, the storage unit 50 is connected to the output unit 70 and the second switch unit 602. When the second switch unit 602 is turned on, the floating diffusion node is connected to the first switch unit 601 and the output unit 70. Thus, by controlling the first switch unit 601 and the second switch unit 602 to be turned on or off, drum exposure and global exposure can be achieved, and different conversion gains can be achieved in different exposure modes. The first switch unit 601 is turned on, the second switch unit 602 is turned off, and the target capacitor in the storage unit 50 is not connected to the floating diffusion node. At this time, the conversion gain is the first conversion gain. The first switch unit 601 is turned on, the second switch unit 602 is turned on, the target capacitor in the storage unit 50 is connected to the floating diffusion node, and the capacitance of the floating diffusion node increases. At this time, the conversion gain is the second conversion gain. The second conversion gain is less than the first conversion gain. The storage unit 50 stores the reset voltage and the signal voltage, the output unit 70 outputs the voltage stored in the storage unit 50, and the pixel works in the global exposure mode. The storage unit 50 does not store the reset voltage and the signal voltage, the second switch unit 602 is turned on, the floating diffusion node is connected to the output unit 70, the direct output unit 70 outputs the reset voltage and the signal voltage at the floating diffusion node, and the pixel works in the rolling exposure mode.

[0076] In some embodiments, the storage unit includes:

[0077] A first storage unit and a second storage unit;

[0078] The first storage unit is used to store one of a reset voltage and a signal voltage;

[0079] The second storage unit is used to store one of a reset voltage and a signal voltage;

[0080] The first storage unit and the second storage unit store different voltage types.

[0081] When the first storage unit is responsible for storing the reset voltage, the second storage unit is responsible for storing the signal voltage. When the first storage unit is responsible for storing the signal voltage, the second storage unit is responsible for storing the reset voltage.

[0082] refer to Figure 2As shown, in some embodiments, the storage unit 50 includes a third switch unit 501, a fourth switch unit 502, a first capacitor C1 and a second capacitor C2; one end of the third switch unit 501 is connected to the output end of the amplifying unit 40, the other end of the third switch unit 501 is connected to one end of the first capacitor C1 and one end of the fourth switch unit 502, the other end of the first capacitor C1 is grounded, the other end of the fourth switch unit 502 is connected to one end of the second capacitor C2 and the first switch unit 601, and the other end of the second capacitor C2 is grounded.

[0083] In this embodiment, the storage unit 50 includes two switch units and two capacitors, and the two capacitors are responsible for sampling and storing voltage. The third switch unit 501 and the first capacitor C1 constitute the first storage unit. The fourth switch unit 502 and the second capacitor C2 constitute the second storage unit.

[0084] In some embodiments, the transmission unit 20 is controlled by a first control signal. When the first control signal is a first level signal, the transmission unit 20 is turned on. The reset unit 30 is controlled by a second control signal. When the second control signal is a first level signal, the reset unit 30 is turned on, so that the power supply connecting the floating diffusion node and the reset unit 30 is turned on. The amplification unit 40 is controlled by a third control signal. When the third control signal is a first level signal, the output end of the amplification unit 40 is grounded. The third switch unit 501 is controlled by a fourth control signal. When the fourth control signal is a first level signal, the floating diffusion node is turned on. The third switch unit 501 is turned on; the fourth switch unit 502 is controlled by the fifth control signal, and when the fifth control signal is a first level signal, the fourth switch unit 502 is turned on; the first switch unit 601 is controlled by the sixth control signal, and when the sixth control signal is a first level signal, the first switch unit 601 is turned on; the second switch unit 602 is controlled by the seventh control signal, and when the seventh control signal is a first level signal, the second switch unit 602 is turned on; the output unit 70 is controlled by the eighth control signal, and when the eighth control signal is a first level signal, the output unit 70 outputs a voltage.

[0085] The first level signal may be a high level.

[0086] This embodiment controls corresponding units through eight control signals, thereby realizing global exposure, drum exposure and switching between different conversion gains.

[0087] In some embodiments, in the reset stage of the storage unit 50, the third control signal, the seventh control signal, and the sixth control signal are first level signals, and the fourth control signal and the fifth control signal are changed from second level signals to first level signals at a first preset moment in the reset stage of the storage unit 50, and the second control signal, the first control signal, and the eighth control signal are second level signals; in the reset stage of the photosensitive unit 10, the third control signal and the eighth control signal are second level signals, and the fourth control signal, the fifth control signal, the second control signal, the first control signal, the seventh control signal, and the sixth control signal are first level signals; in the exposure stage, the third control signal and the first control signal are second level signals, and the fourth control signal, the fifth control signal, the second control signal, the eighth control signal, the seventh control signal, and the sixth control signal are first level signals; in the frame header time, the third control signal and the second control signal are second level signals, the eighth control signal, the seventh control signal and the sixth control signal are first level signals, the fifth control signal changes from the first level signal to the second level signal at the second preset time of the frame header time, the fourth control signal changes from the first level signal to the second level signal at the third preset time of the frame header time, and the first control signal changes from the second level signal to the first level signal at the fourth preset time of the frame header time; the fourth preset time is later than the third preset time, and the third preset time is later than the second preset time; in the readout stage, the third control signal, the fourth control signal, the second control signal and the first control signal are second level signals, the eighth control signal, the seventh control signal and the sixth control signal are first level signals; the fifth control signal changes from the second level signal to the first level signal and then to the second level signal between the read signal voltage and the read reset voltage.

[0088] The first level signal may be a high level, and the second level signal may be a low level.

[0089] This embodiment aims to achieve a global exposure mode under a second conversion gain. The second conversion gain is less than the first conversion gain. Figure 3 The timing diagram of the control signal shown in FIG. Figure 2 The pixel shown works as follows:

[0090] Figure 3 Among them, TX is the first control signal, RX is the second control signal, PC is the third control signal, S1 is the fourth control signal, S2 is the fifth control signal, VGS is the sixth control signal, VD is the seventh control signal, and SEL is the eighth control signal.

[0091] During the reset phase of the storage unit 50 (i.e. Figure 3 ), the third control signal is at a high level, the output end of the amplifying unit 40 is grounded, the fourth control signal and the fifth control signal are changed from a low level to a high level at the first preset moment of the resetting phase of the storage unit 50, so that the third switch unit 501 and the fourth switch unit 502 are turned on, and both ends of the first capacitor C1 and the second capacitor C2 are grounded, thereby resetting the first capacitor C1 and the second capacitor C2. In addition to the above formula for resetting the first capacitor C1 and the second capacitor C2, the voltage of the power supply connected to the amplifying unit 40 can also be set to ground, and both ends of the first capacitor C1 and the second capacitor C2 are grounded, thereby resetting the first capacitor C1 and the second capacitor C2.

[0092] During the reset phase of the photosensitive unit 10 (i.e. Figure 3 PD reset shown in ), the third control signal and the eighth control signal are low level, the second control signal, the first control signal, the fourth control signal, the fifth control signal, the seventh control signal, and the sixth control signal are high level, the reset unit 30, the transmission unit 20, the third switch unit 501, the fourth switch unit 502, the second switch unit 602, and the first switch unit 601 are all turned on, so as to realize the resetting of the photosensitive unit 10.

[0093] In the exposure phase, the photosensitive unit 10 generates charges by sensing light, and the first control signal is at a low level, so the transmission unit 20 is turned off and the photosensitive unit 10 accumulates charges.

[0094] At the beginning of the frame header time, the second control signal becomes low level, the fifth control signal and the fourth control signal successively change from high level to low level, and after the second control signal becomes low level and the reset unit 30 is turned off, when the fourth control signal and the fifth control signal are both high level, the first capacitor C1 and the second capacitor C2 sample the reset voltage Vrst. After the fifth control signal and the fourth control signal become low level, the fourth switch unit 502 and the third switch unit 501 are turned off. After the fourth control signal and the fifth control signal both become low level, the first control signal becomes high level, and the transmission unit 20 is turned on, so at this time the seventh control signal and the sixth control signal are both high level, the first switch unit 601 and the second switch unit 602 are both turned on, so the second capacitor C2 samples the signal voltage Vsig.

[0095] In the readout stage, the readout circuit first reads Vrst-Vsig on the second capacitor C2, the fifth control signal changes from a low level to a high level and then to a low level, the fourth switch unit 502 is turned on and then turned off, and the reset voltage Vrst on the first capacitor C1 is read. At this time, the charges on the first capacitor C1 and the second capacitor C2 are redistributed. According to the charge distribution conservation principle, the final output signal voltage Vsign=Vrst-0.5 Vsig can be obtained. After correlated double sampling, the obtained signal voltage is 0.5Vsig.

[0096] During the whole process, the seventh control signal and the sixth control signal are always at a high level, the second switch unit 602 and the first switch unit 601 are always turned on, and the target capacitor (the second capacitor C2) in the storage unit 50 is connected to the floating diffusion node, and the conversion gain is the second conversion gain. The second conversion gain is less than the first conversion gain.

[0097] In some embodiments, in the reset stage of the storage unit 50, the third control signal and the sixth control signal are first level signals, the fourth control signal and the fifth control signal are changed from second level signals to first level signals at the first preset moment in the reset stage of the storage unit 50, and the second control signal, the first control signal, the eighth control signal and the seventh control signal are second level signals; in the reset stage of the photosensitive unit 10, the third control signal, the eighth control signal and the seventh control signal are second level signals, and the fourth control signal, the fifth control signal, the second control signal, the first control signal and the sixth control signal are first level signals; in the exposure stage, the third control signal, the first control signal and the seventh control signal are second level signals, and the fourth control signal, the fifth control signal, the second control signal, the eighth control signal and the seventh control signal are second level signals. The signal and the sixth control signal are first level signals; at the frame header time, the third control signal, the second control signal and the seventh control signal are second level signals, the fourth control signal, the eighth control signal and the sixth control signal are first level signals, the fifth control signal changes from the first level signal to the second level signal at the second preset time of the frame header time, and the first control signal changes from the second level signal to the first level signal at the third preset time of the frame header time; the third preset time is later than the second preset time; in the readout stage, the third control signal, the second control signal, the first control signal and the seventh control signal are second level signals, the fourth control signal, the eighth control signal and the sixth control signal are first level signals; the fifth control signal changes from the second level signal to the first level signal between the read signal voltage and the read reset voltage and then changes to the second level signal.

[0098] The first level signal may be a high level, and the second level signal may be a low level.

[0099] This embodiment aims to realize the global exposure mode under the first conversion gain. Figure 4 The timing diagram of the control signal shown in FIG. Figure 2 The pixel shown works as follows:

[0100] Figure 4 Among them, TX is the first control signal, RX is the second control signal, PC is the third control signal, S1 is the fourth control signal, S2 is the fifth control signal, VGS is the sixth control signal, VD is the seventh control signal, and SEL is the eighth control signal.

[0101] During the reset phase of the storage unit 50 (i.e. Figure 4 ), the third control signal is high level, the output end of the amplifying unit 40 is grounded, the fourth control signal and the fifth control signal are changed from low level to high level at the first preset moment of the resetting stage of the storage unit 50, so that the third switch unit 501 and the fourth switch unit 502 are turned on, and both ends of the first capacitor C1 and the second capacitor C2 are grounded, thereby resetting the first capacitor C1 and the second capacitor C2. In addition to the above formula to reset the first capacitor C1 and the second capacitor C2, the voltage of the power supply connected to the amplifying unit 40 can also be set to ground, and both ends of the first capacitor C1 and the second capacitor C2 can also be grounded, thereby resetting the first capacitor C1 and the second capacitor C2.

[0102] During the reset phase of the photosensitive unit 10 (i.e. Figure 4 PD reset shown in ), the third control signal, the eighth control signal, and the seventh control signal are low level, the second control signal, the first control signal, the fourth control signal, the fifth control signal, and the sixth control signal are high level, the reset unit 30, the transmission unit 20, the third switch unit 501, the fourth switch unit 502, and the first switch unit 601 are all turned on to achieve the resetting of the photosensitive unit 10.

[0103] In the exposure phase, the photosensitive unit 10 generates charges by sensing light, and the first control signal is at a low level, so the transmission unit 20 is turned off and the photosensitive unit 10 accumulates charges.

[0104] At the beginning of the frame header time, the second control signal changes to a low level, the fourth control signal remains at a high level, and the fifth control signal changes from a high level to a low level at the second preset time after the beginning of the frame header time. When the fourth control signal and the fifth control signal are both at a high level, the third switch unit 501 and the fourth switch unit 502 are turned on, and after the second control signal changes to a low level and the reset unit 30 is turned off, the first capacitor C1 and the second capacitor C2 sample the reset voltage Vrst. The first control signal changes from a low level to a high level at the third preset time of the frame header time, and the transmission unit 20 is turned on. Since the fourth control signal is at a high level at this time, the third switch unit 501 is turned on, so the first capacitor C1 samples the signal voltage Vsig.

[0105] When reading the reset voltage, the reset voltage Vrst sampled on the second capacitor C2 is read. When reading the signal voltage, the fifth control signal is first changed from a low level to a high level to turn on the fourth switch unit 502, and then the signal voltage Vsig on the first capacitor C1 is read. The fourth switch unit 502 is turned on, and the sampled charges on the first capacitor C1 and the second capacitor C2 are redistributed to obtain the final output signal voltage Vsign. After correlated double sampling, the obtained signal voltage is 0.5Vsig.

[0106] During the whole process, the seventh control signal is always at a low level, the second switch unit 602 is always turned off, and the target capacitor (the second capacitor C2) in the storage unit 50 is not connected to the floating diffusion node. At this time, the conversion gain is the first conversion gain.

[0107] In some embodiments, in the reset stage of the storage unit 50, the third control signal and the seventh control signal are first level signals, the fourth control signal and the fifth control signal are changed from second level signals to first level signals at the first preset moment in the reset stage of the storage unit 50, and the second control signal, the first control signal, the eighth control signal and the sixth control signal are second level signals; in the reset stage of the photosensitive unit 10, the third control signal, the fourth control signal, the fifth control signal, the eighth control signal and the sixth control signal are second level signals, and the second control signal, the first control signal and the seventh control signal are first level signals; in the exposure stage, the third control signal, the fourth control signal, the fifth control signal, the eighth control signal and the sixth control signal are second level signals. The control signal, the fifth control signal, the first control signal, and the sixth control signal are second level signals, and the second control signal, the eighth control signal, and the seventh control signal are first level signals; at the frame header time, the third control signal, the fourth control signal, the fifth control signal, the second control signal, and the sixth control signal are second level signals, and the eighth control signal and the seventh control signal are first level signals, and the first control signal changes from the second level signal to the first level signal at the second preset moment of the frame header time; at the frame header time and when the first control signal is the second level signal, read the reset voltage; after the frame header time and after the first control signal changes to the second level signal, read the signal voltage.

[0108] The first level signal may be a high level, and the second level signal may be a low level.

[0109] This embodiment aims to realize the rolling shutter exposure mode under the first conversion gain. Figure 5 The timing diagram of the control signal shown in FIG. Figure 2 The pixel shown works as follows:

[0110] Figure 5 Among them, TX is the first control signal, RX is the second control signal, PC is the third control signal, S1 is the fourth control signal, S2 is the fifth control signal, VGS is the sixth control signal, VD is the seventh control signal, and SEL is the eighth control signal.

[0111] During the reset phase of the storage unit 50 (i.e. Figure 5), the third control signal is at a high level, the output end of the amplifying unit 40 is grounded, the fourth control signal and the fifth control signal are changed from a low level to a high level at the first preset moment of the resetting phase of the storage unit 50, so that the third switch unit 501 and the fourth switch unit 502 are turned on, and both ends of the first capacitor C1 and the second capacitor C2 are grounded, thereby resetting the first capacitor C1 and the second capacitor C2. In addition to the above formula for resetting the first capacitor C1 and the second capacitor C2, the voltage of the power supply connected to the amplifying unit 40 can also be set to ground, and both ends of the first capacitor C1 and the second capacitor C2 are grounded, thereby resetting the first capacitor C1 and the second capacitor C2.

[0112] During the reset phase of the photosensitive unit 10 (i.e. Figure 5 PD reset shown in ), the third control signal, the fourth control signal, the fifth control signal, the eighth control signal, and the sixth control signal are low levels, the second control signal, the first control signal, and the seventh control signal are high levels, the reset unit 30, the transmission unit 20, and the second switch unit 602 are all turned on to achieve the resetting of the photosensitive unit 10.

[0113] In the exposure phase, the photosensitive unit 10 generates charges by sensing light, and the first control signal is at a low level, so the transmission unit 20 is turned off and the photosensitive unit 10 accumulates charges.

[0114] At the beginning of the frame header time, the second control signal changes to a low level, the seventh control signal remains at a high level, the second switch unit 602 is turned on, and the reset voltage Vrst is read out. The first control signal changes from a low level to a high level at the second preset moment of the frame header time, the transmission unit 20 is turned on, and the charge generated by the photosensitive unit 10 is transferred to the input end of the output unit 70 via the transmission unit 20 and the second switch unit 602. The eighth control signal is at a high level, the output unit 70 is turned on, and the signal voltage Vsig is output. The signal voltage obtained after the correlated double sampling is Vrst-Vsig.

[0115] During the whole process, the sixth control signal is at a low level, the first switch unit 601 is always turned off, and the target capacitor (the second capacitor C2) in the storage unit 50 is not connected to the floating diffusion node. At this time, the conversion gain is the first conversion gain.

[0116] In some embodiments, in the reset stage of the storage unit 50, the third control signal, the seventh control signal, and the sixth control signal are first level signals, the fourth control signal and the fifth control signal are changed from second level signals to first level signals at the first preset moment in the reset stage of the storage unit 50, and the second control signal, the first control signal, and the eighth control signal are second level signals; in the reset stage of the photosensitive unit 10, the third control signal, the fourth control signal, the fifth control signal, and the eighth control signal are second level signals, and the second control signal, the first control signal, the seventh control signal, and the sixth control signal are first level signals; in the exposure stage, the third control signal, the fourth control signal, the fifth control signal, and the eighth control signal are second level signals. The control signal, the fifth control signal, and the first control signal are second level signals, and the second control signal, the eighth control signal, the seventh control signal, and the sixth control signal are first level signals; at the frame header time, the third control signal, the fourth control signal, the fifth control signal, and the second control signal are second level signals, and the eighth control signal, the seventh control signal, and the sixth control signal are first level signals, and the first control signal changes from the second level signal to the first level signal at the second preset moment of the frame header time; at the frame header time and when the first control signal is the second level signal, the reset voltage is read; after the frame header time and after the first control signal changes to the second level signal, the signal voltage is read.

[0117] The first level signal may be a high level, and the second level signal may be a low level.

[0118] This embodiment aims to realize the rolling shutter exposure mode under the second conversion gain. Figure 6 In the timing diagram of the control signal shown in FIG. 1 , the first conversion gain is less than the second conversion gain. Under this timing, Figure 2 The pixel shown works as follows:

[0119] Figure 6 Among them, TX is the first control signal, RX is the second control signal, PC is the third control signal, S1 is the fourth control signal, S2 is the fifth control signal, VGS is the sixth control signal, VD is the seventh control signal, and SEL is the eighth control signal.

[0120] During the reset phase of the storage unit 50 (i.e. Figure 6), the third control signal is at a high level, the output end of the amplifying unit 40 is grounded, the fourth control signal and the fifth control signal are changed from a low level to a high level at the first preset moment of the resetting phase of the storage unit 50, so that the third switch unit 501 and the fourth switch unit 502 are turned on, and both ends of the first capacitor C1 and the second capacitor C2 are grounded, thereby resetting the first capacitor C1 and the second capacitor C2. In addition to the above formula for resetting the first capacitor C1 and the second capacitor C2, the voltage of the power supply connected to the amplifying unit 40 can also be set to ground, and both ends of the first capacitor C1 and the second capacitor C2 are grounded, thereby resetting the first capacitor C1 and the second capacitor C2.

[0121] During the reset phase of the photosensitive unit 10 (i.e. Figure 6 PD reset shown in ), the third control signal, the fourth control signal, the fifth control signal, the eighth control signal, and the sixth control signal are low levels, the second control signal, the first control signal, and the seventh control signal are high levels, the reset unit 30, the transmission unit 20, and the second switch unit 602 are all turned on to achieve the resetting of the photosensitive unit 10.

[0122] In the exposure phase, the photosensitive unit 10 generates charges by sensing light, and the first control signal is at a low level, so the transmission unit 20 is turned off and the photosensitive unit 10 accumulates charges.

[0123] At the beginning of the frame header time, the second control signal changes to a low level, the seventh control signal remains at a high level, the second switch unit 602 is turned on, and the reset voltage Vrst is read out. The first control signal changes from a low level to a high level at the second preset moment of the frame header time, the transmission unit 20 is turned on, and the charge generated by the photosensitive unit 10 is transferred to the input end of the output unit 70 via the transmission unit 20 and the second switch unit 602. The eighth control signal is at a high level, the output unit 70 is turned on, and the signal voltage Vsig is output. The signal voltage obtained after the correlated double sampling is Vrst-Vsig.

[0124] During the whole process, the sixth control signal and the seventh control signal are at high level, the first switch unit 601 and the second switch unit 602 are always turned on, and the target capacitor (second capacitor C2) in the storage unit 50 is connected to the floating diffusion node. At this time, the conversion gain is the second conversion gain.

[0125] refer to Figure 7 As shown, in some embodiments, the first switch unit 601 includes: a first transistor M1; a first end of the first transistor M1 is connected to the storage unit 50, and a second end of the first transistor M1 is connected to the second switch unit 602 and the input end of the output unit 70; the first transistor M1 is controlled by the sixth control signal.

[0126] The second switch unit 602 includes: a second transistor M2; a first end of the second transistor M2 is connected to the input end of the amplifying unit 40, a second end of the second transistor M2 is connected to the first switch unit 601 and the input end of the output unit 70, and the second transistor M2 is controlled by the seventh control signal.

[0127] The photosensitive unit 10 includes a photosensitive diode PD; an anode of the photosensitive diode PD is grounded, and a cathode of the photosensitive diode PD is connected to the transmission unit 20 .

[0128] The transmission unit 20 includes: a third transistor M3; a first end of the third transistor M3 is connected to the photosensitive unit 10, a second end of the third transistor M3 is connected to the input end of the amplification unit 40, and the third transistor M3 is controlled by the first control signal.

[0129] The reset unit 30 includes: a fourth transistor M4; a first end of the fourth transistor M4 is connected to the input end of the amplifying unit 40, a second end of the fourth transistor M4 is connected to a power supply, and the fourth transistor M4 is controlled by the second control signal.

[0130] The amplifying unit 40 includes: a fifth transistor M5 and a sixth transistor M6; the first end of the fifth transistor M5 is connected to the second end of the sixth transistor M6 and serves as the output end of the amplifying unit 40, the second end of the fifth transistor M5 is connected to a power supply, the third end of the fifth transistor M5 serves as the input end of the amplifying unit 40, the first end of the sixth transistor M6 is grounded, and the sixth transistor M6 is controlled by the third control signal.

[0131] The third switch unit 501 includes: a seventh transistor M7; a first end of the seventh transistor M7 is connected to the output end of the amplifying unit 40, a second end of the seventh transistor M7 is connected to one end of the first capacitor C1 and one end of the fourth switch unit 502, and the seventh transistor M7 is controlled by the fourth control signal.

[0132] The fourth switch unit 502 includes: an eighth transistor M8; a first end of the eighth transistor M8 is connected to the third switch unit 501, a second end of the eighth transistor M8 is connected to one end of the second capacitor C2 and the first switch unit 601, and the eighth transistor M8 is controlled by the fifth control signal.

[0133] The output unit 70 includes: a ninth transistor M9 and a tenth transistor M10; the first end of the ninth transistor M9 is connected to the second end of the tenth transistor M10, the second end of the ninth transistor M9 is connected to a power supply, the third end of the ninth transistor M9 serves as the input end of the output unit 70, the first end of the tenth transistor M10 serves as the output end of the output unit 70, and the tenth transistor M10 is controlled by the eighth control signal.

[0134] The first transistor M1 to the tenth transistor M10 can all be MOS tubes, the first end of the first transistor M1 to the tenth transistor M10 is the source of the MOS tube, the second end of the first transistor M1 to the tenth transistor M10 is the drain of the MOS tube, and the third end of the first transistor M1 to the tenth transistor M10 is the gate of the MOS tube.

[0135] refer to Figure 3 The timing diagram of the control signal shown in FIG. Figure 7 The pixel shown works as follows:

[0136] During the reset phase of the storage unit 50 (i.e. Figure 3 ), the third control signal is at a high level, the first end of the fifth transistor M5 is grounded, the fourth control signal and the fifth control signal are changed from a low level to a high level at the first preset moment of the reset phase of the storage unit 50, so that the seventh transistor M7 and the eighth transistor M8 are turned on, and both ends of the first capacitor C1 and the second capacitor C2 are grounded, thereby resetting the first capacitor C1 and the second capacitor C2. In addition to resetting the first capacitor C1 and the second capacitor C2 by the above formula, the voltage of the power supply connected to the fifth transistor M5 can also be set to ground, and both ends of the first capacitor C1 and the second capacitor C2 are grounded at this time, thereby resetting the first capacitor C1 and the second capacitor C2.

[0137] During the photodiode PD reset phase (i.e. Figure 3 ), the third control signal and the eighth control signal are at a low level, the second control signal, the first control signal, the fourth control signal, the fifth control signal, the seventh control signal, and the sixth control signal are at a high level, the fourth transistor M4, the third transistor M3, the seventh transistor M7, the eighth transistor M8, the second transistor M2, and the first transistor M1 are all turned on, thereby resetting the photosensitive diode PD.

[0138] In the exposure phase, the photodiode PD generates charges by sensing light, and the first control signal is at a low level, so the third transistor M3 is turned off, and the photodiode PD accumulates charges.

[0139] At the beginning of the frame header time, the second control signal becomes low level, the fifth control signal and the fourth control signal successively change from high level to low level, and after the second control signal becomes low level and the fourth transistor M4 is turned off, when the fourth control signal and the fifth control signal are both high level, the first capacitor C1 and the second capacitor C2 sample the reset voltage Vrst. After the fifth control signal and the fourth control signal become low level, the eighth transistor M8 and the seventh transistor M7 are turned off. After the fourth control signal and the fifth control signal both become low level, the first control signal becomes high level, and the third transistor M3 is turned on, so at this time the seventh control signal and the sixth control signal are both high level, the first transistor M1 and the second transistor M2 are both turned on, so the second capacitor C2 samples the signal voltage Vsig.

[0140] In the readout stage, the readout circuit first reads Vrst-Vsig on the second capacitor C2, the fifth control signal changes from a low level to a high level and then to a low level, the eighth transistor M8 is turned on and then turned off, and the reset voltage Vrst on the first capacitor C1 is read. At this time, the charges on the first capacitor C1 and the second capacitor C2 are redistributed. According to the charge distribution conservation principle, the final output signal voltage Vsign=Vrst-0.5 Vsig can be obtained. After correlated double sampling, the obtained signal voltage is 0.5Vsig.

[0141] During the whole process, the seventh control signal and the sixth control signal are always at a high level, the second transistor M2 and the first transistor M1 are always turned on, and the target capacitor (the second capacitor C2) in the storage unit 50 is connected to the floating diffusion node, and the conversion gain is the second conversion gain. The second conversion gain is less than the first conversion gain.

[0142] refer to Figure 4 The timing diagram of the control signal shown in FIG. Figure 7 The pixel shown works as follows:

[0143] During the reset phase of the storage unit 50 (i.e. Figure 4 ), the third control signal is at a high level, the first end of the fifth transistor M5 is grounded, the fourth control signal and the fifth control signal are changed from a low level to a high level at the first preset moment of the reset phase of the storage unit 50, so that the seventh transistor M7 and the eighth transistor M8 are turned on, and both ends of the first capacitor C1 and the second capacitor C2 are grounded, thereby resetting the first capacitor C1 and the second capacitor C2. In addition to resetting the first capacitor C1 and the second capacitor C2 using the above formula, the voltage of the power supply connected to the fifth transistor M5 can also be set to ground, and both ends of the first capacitor C1 and the second capacitor C2 can also be grounded, thereby resetting the first capacitor C1 and the second capacitor C2.

[0144] During the photodiode PD reset phase (i.e. Figure 4 ), the third control signal, the eighth control signal, and the seventh control signal are low level, the second control signal, the first control signal, the fourth control signal, the fifth control signal, and the sixth control signal are high level, the fourth transistor M4, the third transistor M3, the seventh transistor M7, the eighth transistor M8, and the first transistor M1 are all turned on, thereby resetting the photosensitive diode PD.

[0145] In the exposure phase, the photodiode PD senses light and generates charges, and the first control signal is at a low level, so the third transistor M3 is turned off, and the photodiode PD accumulates charges.

[0146] At the beginning of the frame header time, the second control signal changes to a low level, the fourth control signal remains at a high level, the fifth control signal changes from a high level to a low level at the second preset time after the frame header time starts, when the fourth control signal and the fifth control signal are both at a high level, the seventh transistor M7 and the eighth transistor M8 are turned on, the second control signal changes to a low level and the fourth transistor M4 is turned off, and the first capacitor C1 and the second capacitor C2 sample the reset voltage Vrst. The first control signal changes from a low level to a high level at the third preset time of the frame header time, the third transistor M3 is turned on, and since the fourth control signal is at a high level at this time, the seventh transistor M7 is turned on, so the first capacitor C1 samples the signal voltage Vsig.

[0147] When reading the reset voltage, the reset voltage Vrst sampled on the second capacitor C2 is read. When reading the signal voltage, the fifth control signal is first changed from a low level to a high level to turn on the eighth transistor M8, and then the signal voltage Vsig on the first capacitor C1 is read. The eighth transistor M8 is turned on, and the sampled charges on the first capacitor C1 and the second capacitor C2 are redistributed to obtain the final output signal voltage Vsign. After correlated double sampling, the obtained signal voltage is 0.5Vsig.

[0148] During the whole process, the seventh control signal is always at a low level, the second transistor M2 is always turned off, and the target capacitor (the second capacitor C2) in the storage unit 50 is not connected to the floating diffusion node. At this time, the conversion gain is the first conversion gain.

[0149] refer to Figure 5 The timing diagram of the control signal shown in FIG. Figure 7 The pixel shown works as follows:

[0150] During the reset phase of the storage unit 50 (i.e. Figure 5), the third control signal is at a high level, the first end of the fifth transistor M5 is grounded, the fourth control signal and the fifth control signal are changed from a low level to a high level at the first preset moment of the reset phase of the storage unit 50, so that the seventh transistor M7 and the eighth transistor M8 are turned on, and both ends of the first capacitor C1 and the second capacitor C2 are grounded, thereby resetting the first capacitor C1 and the second capacitor C2. In addition to resetting the first capacitor C1 and the second capacitor C2 by the above formula, the voltage of the power supply connected to the fifth transistor M5 can also be set to ground, and both ends of the first capacitor C1 and the second capacitor C2 are grounded at this time, thereby resetting the first capacitor C1 and the second capacitor C2.

[0151] During the photodiode PD reset phase (i.e. Figure 5 ), the third control signal, the fourth control signal, the fifth control signal, the eighth control signal, and the sixth control signal are low levels, the second control signal, the first control signal, and the seventh control signal are high levels, and the fourth transistor M4, the third transistor M3, and the second transistor M2 are all turned on to achieve the resetting of the photosensitive diode PD.

[0152] In the exposure phase, the photodiode PD senses light and generates charges, and the first control signal is at a low level, so the third transistor M3 is turned off, and the photodiode PD accumulates charges.

[0153] At the beginning of the frame header time, the second control signal changes to a low level, the seventh control signal remains at a high level, the second transistor M2 is turned on, and the reset voltage Vrst is read out. The first control signal changes from a low level to a high level at the second preset moment of the frame header time, the third transistor M3 is turned on, and the charge generated by the photodiode PD is transferred to the input end of the output unit 70 via the third transistor M3 and the second transistor M2. The eighth control signal is at a high level, the output unit 70 is turned on, and the signal voltage Vsig is output. The signal voltage obtained after the correlated double sampling is Vrst-Vsig.

[0154] During the whole process, the sixth control signal is at a low level, the first transistor M1 is always turned off, and the target capacitor (the second capacitor C2 ) in the storage unit 50 is not connected to the floating diffusion node. At this time, the conversion gain is the first conversion gain.

[0155] refer to Figure 6 In the timing diagram of the control signal shown in FIG. 1 , the first conversion gain is less than the second conversion gain. Under this timing, Figure 7 The pixel shown works as follows:

[0156] During the reset phase of the storage unit 50 (i.e. Figure 6), the third control signal is at a high level, the first end of the fifth transistor M5 is grounded, the fourth control signal and the fifth control signal are changed from a low level to a high level at the first preset moment of the reset phase of the storage unit 50, so that the seventh transistor M7 and the eighth transistor M8 are turned on, and both ends of the first capacitor C1 and the second capacitor C2 are grounded, thereby resetting the first capacitor C1 and the second capacitor C2. In addition to resetting the first capacitor C1 and the second capacitor C2 by the above formula, the voltage of the power supply connected to the fifth transistor M5 can also be set to ground, and both ends of the first capacitor C1 and the second capacitor C2 are grounded at this time, thereby resetting the first capacitor C1 and the second capacitor C2.

[0157] During the photodiode PD reset phase (i.e. Figure 6 ), the third control signal, the fourth control signal, the fifth control signal, the eighth control signal, and the sixth control signal are low levels, the second control signal, the first control signal, and the seventh control signal are high levels, and the fourth transistor M4, the third transistor M3, and the second transistor M2 are all turned on to achieve the resetting of the photosensitive diode PD.

[0158] In the exposure phase, the photodiode PD senses light and generates charges, and the first control signal is at a low level, so the third transistor M3 is turned off, and the photodiode PD accumulates charges.

[0159] At the beginning of the frame header time, the second control signal changes to a low level, the seventh control signal remains at a high level, the second transistor M2 is turned on, and the reset voltage Vrst is read out. The first control signal changes from a low level to a high level at the second preset moment of the frame header time, the third transistor M3 is turned on, and the charge generated by the photodiode PD is transferred to the input end of the output unit 70 via the third transistor M3 and the second transistor M2. The eighth control signal is at a high level, the output unit 70 is turned on, and the signal voltage Vsig is output. The signal voltage obtained after the correlated double sampling is Vrst-Vsig.

[0160] During the whole process, the sixth control signal and the seventh control signal are at high level, the first transistor M1 and the second transistor M2 are always turned on, and the target capacitor (second capacitor C2) in the storage unit 50 is connected to the floating diffusion node. At this time, the conversion gain is the second conversion gain.

[0161] It should be noted that, in addition to the structure of the storage unit 50 shown in the above embodiment, the storage unit 50 may also adopt other structures. Figure 8 As shown, the storage unit 50 may include transistors Q1 to Q4, capacitors C1 and C2. The storage unit 50 adopts Figure 8In the case of the structure shown, the storage unit 50 can be directly connected to the output unit 70, the switching unit 60 can only be provided with the second switch unit 602, and the transistors Q2 and Q4 in the storage unit 50 can both play the role of the first switch unit. Fig. 9 As shown, the memory cell 50 may include transistors Q5 to Q7 , capacitors C1 and C2 .

[0162] In summary, the pixel provided in the present application is provided with a switching unit, and the exposure mode of the pixel can be switched to a global exposure mode or a drum exposure mode through the switching unit. In the global exposure mode, the switching of different conversion gains can be achieved through the switching unit. In the drum exposure mode, the switching of different conversion gains can be achieved through the switching unit. Thereby, the pixel supports global exposure and drum exposure, and supports a high dynamic range under the global exposure mode and a high dynamic range under the drum exposure mode.

[0163] The present application also provides an image sensor, which includes the pixel described in the above embodiment. For the introduction of the image sensor provided by the present application, reference can be made to the above pixel embodiment, which will not be repeated here.

[0164] Because the situation is complicated, it is impossible to list them one by one for explanation. Those skilled in the art should be able to realize that there may be multiple examples based on the basic principles of the embodiments provided in this application and combined with actual conditions, and they should all be within the scope of this application without paying enough creative work.

[0165] The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0166] The above is a detailed introduction to the pixels and image sensors provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

[0167] It should also be noted that, in this specification, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or equipment including the elements.

Claims

1. A pixel, characterized in that: include: A photosensitive unit, a transmission unit, a reset unit, an amplification unit, a storage unit, a switching unit, and an output unit; The photosensitive unit is used to generate charges by sensing light; The transmission unit is used to transmit the charge generated by the photosensitive unit to the floating diffusion node when the transmission unit is turned on; the input end of the amplification unit serves as the floating diffusion node; The reset unit is used to reset the pixel; The amplifying unit is used to amplify the voltage of the floating diffusion node and output it to the storage unit; The storage unit is used to store the reset voltage and the signal voltage; The switching unit is used to switch the exposure mode of the pixel and the conversion gain of the pixel under the exposure mode; the exposure mode includes a global exposure mode and a drum exposure mode; The output unit is used to output a reset voltage and a signal voltage.

2. The pixel according to claim 1, characterized in that The switching unit comprises: a first switch unit, configured to connect the target capacitor in the storage unit to the input terminal of the output unit, and connect the target capacitor in the storage unit to the second switch unit when the first switch unit is turned on; The second switch unit is used to connect the floating diffusion node with the input end of the output unit and the first switch unit when the second switch unit is turned on.

3. The pixel according to claim 2, characterized in that The storage unit comprises: A first storage unit and a second storage unit; The first storage unit is used to store one of a reset voltage and a signal voltage; The second storage unit is used to store one of a reset voltage and a signal voltage; The first storage unit and the second storage unit store different voltage types.

4. The pixel according to claim 3, characterized in that The storage unit includes a third switch unit, a fourth switch unit, a first capacitor and a second capacitor; one end of the third switch unit is connected to the output end of the amplifying unit, the other end of the third switch unit is connected to one end of the first capacitor and one end of the fourth switch unit, the other end of the first capacitor is grounded, the other end of the fourth switch unit is connected to one end of the second capacitor and the first switch unit, and the other end of the second capacitor is grounded.

5. The pixel according to claim 4, characterized in that The transmission unit is controlled by a first control signal. When the first control signal is a first level signal, the transmission unit is turned on. The reset unit is controlled by a second control signal. When the second control signal is a first level signal, the reset unit is turned on to connect the floating diffusion node to the power supply connected to the reset unit. The amplification unit is controlled by a third control signal. When the third control signal is a first level signal, the output end of the amplification unit is grounded. The third switch unit is controlled by a fourth control signal. When the fourth control signal is a first level signal, the third switch unit is turned on. The fourth switch unit is controlled by a fifth control signal. When the fifth control signal is a first level signal, the fourth switch unit is turned on. The first switch unit is controlled by a sixth control signal. When the sixth control signal is a first level signal, the first switch unit is turned on. The second switch unit is controlled by a seventh control signal. When the seventh control signal is a first level signal, the second switch unit is turned on. The output unit is controlled by an eighth control signal. When the eighth control signal is a first level signal, the output unit outputs a voltage.

6. The pixel according to claim 5, characterized in that In the storage unit reset stage, the third control signal, the seventh control signal, and the sixth control signal are first level signals, the fourth control signal and the fifth control signal are changed from second level signals to first level signals at a first preset time in the storage unit reset stage, and the second control signal, the first control signal, and the eighth control signal are second level signals; In the photosensitive unit resetting stage, the third control signal and the eighth control signal are second level signals, and the fourth control signal, the fifth control signal, the second control signal, the first control signal, the seventh control signal and the sixth control signal are first level signals; In the exposure stage, the third control signal and the first control signal are second level signals, and the fourth control signal, the fifth control signal, the second control signal, the eighth control signal, the seventh control signal and the sixth control signal are first level signals; At the frame header time, the third control signal and the second control signal are second level signals, the eighth control signal, the seventh control signal and the sixth control signal are first level signals, the fifth control signal changes from the first level signal to the second level signal at the second preset time of the frame header time, the fourth control signal changes from the first level signal to the second level signal at the third preset time of the frame header time, and the first control signal changes from the second level signal to the first level signal at the fourth preset time of the frame header time; The fourth preset time is later than the third preset time, and the third preset time is later than the second preset time; In the readout stage, the third control signal, the fourth control signal, the second control signal, and the first control signal are second level signals, and the eighth control signal, the seventh control signal, and the sixth control signal are first level signals; The fifth control signal changes from a second level signal to a first level signal and then to a second level signal between the read signal voltage and the read reset voltage.

7. The pixel according to claim 5, characterized in that In a storage unit reset phase, the third control signal and the sixth control signal are first level signals, the fourth control signal and the fifth control signal are changed from second level signals to first level signals at a first preset time in the storage unit reset phase, and the second control signal, the first control signal, the eighth control signal and the seventh control signal are second level signals; In the photosensitive unit resetting stage, the third control signal, the eighth control signal and the seventh control signal are second level signals, and the fourth control signal, the fifth control signal, the second control signal, the first control signal and the sixth control signal are first level signals; In the exposure stage, the third control signal, the first control signal and the seventh control signal are second level signals, and the fourth control signal, the fifth control signal, the second control signal, the eighth control signal and the sixth control signal are first level signals; At the frame header time, the third control signal, the second control signal and the seventh control signal are second level signals, the fourth control signal, the eighth control signal and the sixth control signal are first level signals, the fifth control signal changes from the first level signal to the second level signal at the second preset time of the frame header time, and the first control signal changes from the second level signal to the first level signal at the third preset time of the frame header time; The third preset time is later than the second preset time; In the readout stage, the third control signal, the second control signal, the first control signal, and the seventh control signal are second level signals, and the fourth control signal, the eighth control signal, and the sixth control signal are first level signals; The fifth control signal changes from a second level signal to a first level signal and then to a second level signal between the read signal voltage and the read reset voltage.

8. The pixel according to claim 5, characterized in that In the storage unit reset stage, the third control signal and the seventh control signal are first level signals, the fourth control signal and the fifth control signal are changed from second level signals to first level signals at a first preset moment in the storage unit reset stage, and the second control signal, the first control signal, the eighth control signal and the sixth control signal are second level signals; in the photosensitive unit reset stage, the third control signal, the fourth control signal, the fifth control signal, the eighth control signal and the sixth control signal are second level signals, and the second control signal, the first control signal and the seventh control signal are first level signals; In the exposure stage, the third control signal, the fourth control signal, the fifth control signal, the first control signal, and the sixth control signal are second level signals, and the second control signal, the eighth control signal, and the seventh control signal are first level signals; At the frame header time, the third control signal, the fourth control signal, the fifth control signal, the second control signal, and the sixth control signal are second level signals, the eighth control signal and the seventh control signal are first level signals, and the first control signal changes from the second level signal to the first level signal at a second preset moment of the frame header time; At the frame header time and when the first control signal is a second level signal, reading a reset voltage; After the frame header time and after the first control signal becomes a second level signal, the signal voltage is read.

9. The pixel according to claim 5, characterized in that In the storage unit reset stage, the third control signal, the seventh control signal, and the sixth control signal are first level signals, the fourth control signal and the fifth control signal are changed from second level signals to first level signals at a first preset time in the storage unit reset stage, and the second control signal, the first control signal, and the eighth control signal are second level signals; In the photosensitive unit resetting stage, the third control signal, the fourth control signal, the fifth control signal, and the eighth control signal are second level signals, and the second control signal, the first control signal, the seventh control signal, and the sixth control signal are first level signals; In the exposure stage, the third control signal, the fourth control signal, the fifth control signal, and the first control signal are second level signals, and the second control signal, the eighth control signal, the seventh control signal, and the sixth control signal are first level signals; At the frame header time, the third control signal, the fourth control signal, the fifth control signal, and the second control signal are second level signals, the eighth control signal, the seventh control signal, and the sixth control signal are first level signals, and the first control signal changes from the second level signal to the first level signal at a second preset moment of the frame header time; At the frame header time and when the first control signal is a second level signal, reading a reset voltage; After the frame header time and after the first control signal becomes a second level signal, the signal voltage is read.

10. The pixel according to any one of claims 5 to 9, characterized in that: The first switch unit comprises: a first transistor; a first end of the first transistor is connected to the storage unit, and a second end of the first transistor is connected to the second switch unit and the input end of the output unit; the first transistor is controlled by the sixth control signal.

11. The pixel according to any one of claims 5 to 9, characterized in that: The second switch unit comprises: a second transistor; a first end of the second transistor is connected to the input end of the amplifying unit, a second end of the second transistor is connected to the input end of the first switching unit and the output unit, and the second transistor is controlled by the seventh control signal.

12. The pixel according to claim 1, characterized in that The photosensitive unit comprises: A photosensitive diode; an anode of the photosensitive diode is grounded, and a cathode of the photosensitive diode is connected to the transmission unit.

13. The pixel according to claim 5, characterized in that The transmission unit comprises: a third transistor; a first end of the third transistor is connected to the photosensitive unit, a second end of the third transistor is connected to the input end of the amplifying unit, and the third transistor is controlled by the first control signal.

14. The pixel according to claim 5, characterized in that The reset unit comprises: a fourth transistor; a first end of the fourth transistor is connected to the input end of the amplifying unit, a second end of the fourth transistor is connected to a power supply, and the fourth transistor is controlled by the second control signal.

15. The pixel according to claim 5, characterized in that The amplification unit comprises: A fifth transistor and a sixth transistor; the first end of the fifth transistor is connected to the second end of the sixth transistor and serves as the output end of the amplifying unit, the second end of the fifth transistor is connected to a power supply, the third end of the fifth transistor serves as the input end of the amplifying unit, the first end of the sixth transistor is grounded, and the sixth transistor is controlled by the third control signal.

16. The pixel according to claim 5, characterized in that The third switch unit comprises: a seventh transistor; a first end of the seventh transistor is connected to the output end of the amplifying unit, a second end of the seventh transistor is connected to one end of the first capacitor and one end of the fourth switch unit, and the seventh transistor is controlled by the fourth control signal.

17. The pixel according to claim 5, characterized in that The fourth switch unit comprises: an eighth transistor; a first end of the eighth transistor is connected to the third switch unit, a second end of the eighth transistor is connected to one end of the second capacitor and the first switch unit, and the eighth transistor is controlled by the fifth control signal.

18. The pixel according to claim 5, characterized in that The output unit comprises: A ninth transistor and a tenth transistor; the first end of the ninth transistor is connected to the second end of the tenth transistor, the second end of the ninth transistor is connected to a power supply, the third end of the ninth transistor serves as the input end of the output unit, the first end of the tenth transistor serves as the output end of the output unit, and the tenth transistor is controlled by the eighth control signal.

19. An image sensor, characterized in that: Comprising a pixel as claimed in any one of claims 1 to 18.

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