A semiconductor structure and a method of fabricating the same

Abstract

Disclosed are a semiconductor structure and a preparation method thereof. The preparation method comprises the following steps: providing a substrate, the substrate having a plurality of first grooves arranged at intervals therein; forming a conductive layer, the conductive layer filling the first grooves and covering the surface of the substrate; forming a mask layer arranged at intervals on the surface of the conductive layer, the mask layer partially overlapping the first grooves; performing pretreatment on the conductive layer, the pretreatment comprising: taking the mask layer as a mask, patterning the conductive layer and forming second grooves, wherein the sidewalls of the conductive layer are exposed through the second grooves; forming a barrier film on the sidewall surface; performing an etching process on the conductive layer to form third grooves from the upper end of the conductive layer, wherein, in the etching process, the etching rate of the conductive layer covered by the barrier film is less than the etching rate of the conductive layer not covered by the barrier film; and forming a conductive column, the conductive column filling the third grooves. The semiconductor structure and the preparation method thereof provided by the embodiment of the present disclosure at least have the advantages of reducing the contact resistance between the conductive plug and the conductive layer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] With the continuous development of integrated circuit process technology, in order to improve the integration density of integrated circuits, while increasing the operating speed of memory and reducing its power consumption, the feature size of metal-oxide-semiconductor field-effect transistor (MOSFET) devices continues to shrink, and MOSFET devices face a series of challenges.

[0003] The reduction in feature size leads to an increase in integration, but at the same time, it also causes problems in the contact performance between the lower electrode of the transistor and the contact window, as well as between the contact plug and the conductive layer. For example, due to the requirement for the storage area of ​​the transistor, the ratio of the height to the width of the lower electrode in the vertical direction is relatively large. In the process of forming the capacitor hole for accommodating the lower electrode, due to the etching effect of the aspect ratio, it may be impossible to etch through, that is, the bottom of the capacitor hole does not expose the contact window or the area of ​​the bottom of the capacitor hole is relatively small, and thus cannot meet the needs of the device. How to improve the contact performance between the lower electrode and the contact window, as well as between the conductive plug and the conductive layer, has become an important problem that needs to be solved urgently by those skilled in the art. Summary of the Invention

[0004] The embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, which are at least beneficial in reducing the contact resistance between a conductive plug and a conductive layer in the semiconductor structure.

[0005] According to some embodiments of the present disclosure, on the one hand, an embodiment of the present disclosure provides a method for preparing a semiconductor structure, comprising: providing a substrate having a plurality of first grooves arranged at intervals; forming a conductive layer, the conductive layer filling the first grooves and covering the surface of the substrate; forming a mask layer arranged at intervals on the surface of the conductive layer, the mask layer partially overlapping with the first grooves; pre-treating the conductive layer, the pre-treatment comprising: using the mask layer as a mask, patterning the conductive layer and forming a second groove, wherein the side wall of the conductive layer is exposed through the second groove; forming a barrier film on the side wall surface; performing an etching process on the conductive layer to form a third groove from the upper end of the conductive layer, wherein, in the etching process, the etching rate of the conductive layer covered with the barrier film is less than the etching rate of the conductive layer not covered with the barrier film; and forming a conductive column, the conductive column filling the third groove.

[0006] In some embodiments, the pretreatment process steps include: providing a first source gas and a second source gas, the first source gas is used to etch the conductive layer, and the second source gas is used to form a barrier film; removing a portion of the thickness of the conductive layer not covered by the mask layer to form a second groove, and forming a continuous barrier film on the inner wall surface of the second groove and the surface of the conductive layer exposed at the bottom of the second groove.

[0007] In some embodiments, the second source gas is further used to remove the mask layer, and an etching selectivity ratio of the second source gas to the mask layer is less than or equal to a thickness of the mask layer.

[0008] In some embodiments, the second source gas includes monofluoromethane and oxygen, and a flow rate of the monofluoromethane is greater than a flow rate of the oxygen.

[0009] In some embodiments, the substrate includes an array region and a peripheral region, and the conductive layer is located in the array region and / or the peripheral region.

[0010] In some embodiments, before forming the conductive pillar, the method further includes: removing the barrier film.

[0011] In some embodiments, a cleaning gas is used to remove the barrier film, and the cleaning gas includes any one of NF3, O2, Ar, or CF4, or a combination of multiple thereof.

[0012] According to some embodiments of the present disclosure, on the other hand, an embodiment of the present disclosure further provides a semiconductor structure, including: a substrate, wherein the substrate has a contact window, and the contact window protrudes from the surface of the substrate; a conductive column, wherein part of the conductive column is located in the contact window, and part of the conductive column is located on the surface of the contact window.

[0013] In some embodiments, the conductive column includes a continuous first conductive column and a second conductive column, the first conductive column is located in the contact window, and the second conductive column is located on the surface of the contact window; along the direction from the second conductive column to the first conductive column, the line width of the first conductive column decreases.

[0014] In some embodiments, a cross-sectional shape of the first conductive pillar along a direction perpendicular to the surface of the substrate includes: a U-shape or a V-shape.

[0015] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0016] In the technical solution provided by the embodiments of the present disclosure, the conductive layer is pretreated to form a barrier film on the inner wall surface of the second groove. In the subsequent etching process, the etching rate of the conductive layer covered with the barrier film is lower than the etching rate of the conductive layer not covered with the barrier film. In this way, only one step of etching the conductive layer to form a third groove can be added to change the contact area between the conductive pillar and the conductive layer. Compared with the conventional process of forming a mask and patterning the third groove, the process steps and preparation costs can be reduced, thereby saving process time and improving the process rate. In addition, the barrier film covers the side of the conductive layer, so that the barrier film can protect the outer side of the conductive layer, thereby ensuring the morphology of the conductive layer is intact. The formed third groove can increase the contact area between the conductive pillar and the contact window, thereby reducing the contact resistance between the conductive pillar and the conductive layer, thereby improving the electrical performance of the semiconductor structure, reducing electrical losses, and increasing the response speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1 A process flow chart of a method for preparing a semiconductor structure provided in one embodiment of the present disclosure;

[0019] Figures 2 to 8 A schematic flow chart of the structure of a semiconductor structure corresponding to each step in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0020] Figures 9 to 16 A schematic flow chart of the structure of a semiconductor structure corresponding to each step in a method for preparing a semiconductor structure provided in another embodiment of the present disclosure;

[0021] Figure 17 This is a structural block diagram of a terminal provided in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0022] As known from the background art, the contact resistance between the conductive plug and the conductive layer of the current semiconductor structure is relatively large.

[0023] The disclosed embodiments provide a method for fabricating a semiconductor structure. By pre-treating the conductive layer, a barrier film is formed on the inner wall surface of a second groove. In a subsequent etching process, the etching rate of the conductive layer covered with the barrier film is lower than the etching rate of the conductive layer not covered with the barrier film. Thus, only one step of etching the conductive layer to form a third groove is added, thereby changing the contact area between the conductive pillar and the conductive layer. Compared with conventional processes that involve forming a mask and patterning the third groove, this method reduces process steps and manufacturing costs, thereby saving process time and increasing process speed. Furthermore, since the barrier film covers the side surfaces of the conductive layer, it can protect the outer surface of the conductive layer, thereby maintaining the morphology of the conductive layer intact. The formed third groove can increase the contact area between the conductive pillar and the contact window, thereby reducing the contact resistance between the conductive pillar and the conductive layer, thereby improving the electrical performance of the semiconductor structure, reducing electrical losses, and increasing response speed.

[0024] The following describes various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to facilitate a better understanding of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can still be implemented.

[0025] Figure 1 A process flow chart of a method for preparing a semiconductor structure provided in one embodiment of the present disclosure.

[0026] refer to Figure 1 According to some embodiments of the present disclosure, one aspect of the present disclosure provides a method for preparing a semiconductor structure, comprising:

[0027] S10, providing a substrate, wherein the substrate has a plurality of first grooves arranged at intervals.

[0028] In some embodiments, the semiconductor structure can be a memory device. The substrate includes an array region and a peripheral region. The array region is the core area of ​​the memory device, used for storing data; the peripheral region is the control region of the memory device, used for controlling the writing and reading of data from the array region. The array region includes storage capacitors and switches, wherein the storage capacitors are used for storing data; the switches in the array region are used to control the input and output of data in the storage capacitors. The peripheral region also includes switches that form a control circuit to control the writing and reading of data from the array region.

[0029] S20 , forming a conductive layer, wherein the conductive layer completely fills the first groove and covers the surface of the substrate.

[0030] In some embodiments, the conductive layer is located in the array region (eg Figures 2 to 8The conductive layer serves as a capacitor window, and the conductive pillar formed subsequently serves as a lower electrode of the capacitor structure.

[0031] In some embodiments, the conductive layer is located in the peripheral region (eg Figures 9 to 16 The conductive layer and the conductive pillar serve as contact plugs, and the contact plugs may be any one of source contact plugs, drain contact plugs, or gate contact plugs.

[0032] S30 , forming mask layers arranged at intervals on the surface of the conductive layer, wherein the mask layers partially overlap with the first grooves.

[0033] S40 , pre-treating the conductive layer, the pre-treating comprising: using the mask layer as a mask, patterning the conductive layer and forming a second groove, wherein the sidewall of the conductive layer is exposed through the second groove; and forming a barrier film on the sidewall surface.

[0034] S50 , performing an etching process on the conductive layer to form a third groove from the upper end of the conductive layer, wherein, in the etching process, an etching rate of the conductive layer covered with the barrier film is lower than an etching rate of the conductive layer not covered with the barrier film.

[0035] S50 , forming a conductive column, wherein the conductive column fills the third groove.

[0036] The following will be combined Figures 2 to 8 The preparation method of the conductive layer array region provided in the above embodiment is described in detail with respect to each step corresponding to the array region.

[0037] Figures 2 to 8 This is a schematic flow chart of the structure of the semiconductor structure corresponding to each step in the method for preparing the semiconductor structure provided in one embodiment of the present disclosure.

[0038] refer to Figure 2 , providing a substrate 10 having a plurality of first grooves 106 arranged at intervals.

[0039] In some embodiments, the base 10 may include a stacked substrate 100 and an isolation layer 102 , and the first groove 106 is located in the isolation layer 102 .

[0040] In some embodiments, the substrate 100 may be a semiconductor material including silicon, silicon germanium, or germanium. The substrate may contain a P-type dopant element or an N-type dopant element. The N-type dopant element may be a Group V element such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As). The P-type dopant element may be a Group III element such as boron (B), aluminum (Al), gallium (Ga), or indium (In).

[0041] In some embodiments, the isolation layer 102 may be made of silicon oxide, silicon nitride, silicon carbonitride, or other materials with a high dielectric constant. Exemplarily, the isolation layer 102 is made of silicon nitride, which not only has high dielectric properties but also has a high hardness. This reduces the likelihood of profile deformation of the bit line 108 and capacitor plug 104 within the isolation layer 102, thereby improving the yield of the semiconductor structure. In some embodiments, the isolation layer 102 may be a multi-layer stacked film, wherein the film layers may be made of any two or more of silicon oxide, silicon nitride, silicon carbonitride, or other materials with a high dielectric constant.

[0042] In some embodiments, substrate 10 further includes an active layer 101, located between substrate 100 and isolation layer 102. Active layer 101 may include a channel region and first and second source / drain regions located at opposite ends of the channel region. Bit line 108 and capacitor plug 104 are electrically connected to the first or second source / drain region of active layer 101, respectively. For example, bit line 108 is electrically connected to the first source / drain region, while capacitor plug 104 is electrically connected to the second source / drain region of active layer 101.

[0043] In some embodiments, the active layer 101 and the substrate 100 can be prepared from the same original substrate. Part of the thickness of the original substrate is patterned to form an active layer 101 arranged at intervals, and the remaining original substrate serves as the substrate 100. There is no interface state between the active layer 101 and the substrate 100. Instead, they are two different film layers divided due to different definitions of different functional defined areas. The two are actually the same film layer.

[0044] In some embodiments, isolation structures 105 are included between adjacent active layers 101. Isolation structures 105 are used to separate and isolate the spaced active layers 101, thereby defining individual transistors in subsequent processes and selecting a specific transistor through bit lines and word lines for writing and reading data. Isolation structures 105 may be shallow trench isolation (STI).

[0045] In some embodiments, the isolation structure 105 is an isolation structure made of an isolation material. The isolation structure 105 can be a single-layer film layer or a multi-layer film layer.

[0046] In some embodiments, the semiconductor structure includes bit lines 108 and word lines. Bit lines 108 are made of at least one of tungsten, tantalum, titanium, tantalum nitride, or titanium nitride, which helps reduce the resistance of bit lines 108. The word lines are located within isolation structures 105 on one side of the channel region. The word lines are made of at least one of tungsten, tantalum, titanium, tantalum nitride, or titanium nitride.

[0047] In some embodiments, a barrier layer 109 is formed at one end of the bit line 108 away from the substrate 100 . The barrier layer 109 is used to isolate the bit line 108 from the capacitor structure. The material of the barrier layer 109 may be silicon nitride or silicon oxynitride.

[0048] In some embodiments, substrate 10 further includes a capacitor plug 104 located within isolation layer 102 and electrically connected to active layer 101. Capacitor plug 104 may be a metal silicide layer or a polysilicon layer. The metal silicide layer can reduce the contact resistance between the capacitor contact plug and active layer 101.

[0049] In some embodiments, the bottom of the first recess 106 exposes the capacitor plug 104 , and the first recess 106 is used to form a capacitor contact plug.

[0050] refer to Figure 3 , forming a conductive layer 110, the conductive layer 110 fills the first groove 106 (refer to Figure 2 ) and covers the surface of the isolation layer 102.

[0051] In some embodiments, the material of the conductive layer 110 may include at least one of tungsten, tantalum, tungsten nitride, or tantalum nitride.

[0052] Continue to refer Figure 3 , a mask layer 103 is formed on the surface of the conductive layer 110, and the mask layer 103 and the first groove 106 (refer to Figure 2 ) partially overlap.

[0053] In some embodiments, the mask layer 103 may be photoresist or any material having an etching rate different from that of the conductive layer 110 and the barrier layer under the same etching process. For example, the mask layer 103 may be made of carbon.

[0054] In some embodiments, the mask layer 103 has an opening 107, and a portion of the opening 107 is aligned with the first groove 106 (refer to FIG. Figure 2 ) overlaps, and also overlaps with part of the blocking layer 109. In this way, the original square arrangement of the standard pyramid can be transformed into a hexagonal closest arrangement, thereby increasing the storage area within a limited space and reducing the difficulty of the preparation process, thereby accurately controlling the distance between each capacitor hole and ensuring a high yield of the capacitor hole based on the capacitor hole with a high aspect ratio.

[0055] refer to Figure 4 , the conductive layer 110 is pre-treated, the pre-treatment comprising: using the mask layer 103 as a mask, patterning the conductive layer 110 and forming a second groove 116, wherein the sidewall of the conductive layer 110 is exposed through the second groove 116; and forming a barrier film 115 on the sidewall surface.

[0056] In some embodiments, the pretreatment process steps include: providing a first source gas and a second source gas, the first source gas is used to etch the conductive layer 110, and the second source gas is used to form a barrier film 115; removing a portion of the thickness of the conductive layer 110 not covered by the mask layer 103 to form a second groove 116, and forming a continuous barrier film 115 on the surface of the conductive layer 110 exposed by the inner wall surface of the second groove 116 and the bottom of the second groove 116.

[0057] It is understandable that the second groove 116 does not completely penetrate the conductive layer 110 , thereby increasing the contact area between the conductive layer 110 and the capacitor plug 104 , thereby reducing the contact resistance between the conductive layer 110 and the capacitor plug 104 .

[0058] In some embodiments, during the pre-treatment process, not only the conductive layer 110 is etched, but also a portion of the barrier layer 109 is etched.

[0059] In some embodiments, the first source gas includes chlorine gas. The conductive layer 110 is removed by chlorine gas, and the etching rate is relatively high, so that the second groove 116 can be formed quickly.

[0060] In some embodiments, the second source gas is also used to remove the mask layer 103, and the etching selectivity ratio of the second source gas to the mask layer 103 is less than or equal to the thickness of the mask layer 103. In this way, during the process of forming the second groove 116, the mask layer 103 is always present, and after the second groove 116 is formed, the mask layer 103 is still present or has just been completely etched. In this way, the barrier film 115 will not be formed on the surface of the conductive layer 110 covered by the mask layer 103. Subsequently, due to the different etching rates of the uncovered conductive layer 110 and the covered conductive layer 110, a third groove can be formed, thereby increasing the contact area between the capacitor contact window and the lower electrode.

[0061] In addition, during the process of forming the second groove 116 , the mask layer 103 is always present, which can reduce surface defects and etching damage of the conductive layer 110 , thereby improving the performance and stability of the conductive layer 110 itself.

[0062] When the etching selection ratio of the second source gas to the mask layer 103 is equal to the thickness of the mask layer 103 , the mask layer is removed simultaneously during the process of forming the barrier film 115 , thereby omitting a portion of the step of removing the mask layer.

[0063] In some embodiments, the second source gas includes monofluoromethane and oxygen, with the flow rate of monofluoromethane being greater than the flow rate of oxygen. Since oxygen can remove mask layer 103, the flow rate of monofluoromethane being greater than the flow rate of oxygen ensures that the proportion of the second source gas that forms barrier film 115 is greater than the proportion that removes mask layer 103, thereby forming barrier film 115 before removing mask layer 103.

[0064] In some embodiments, the pretreatment is a dry etching process, and a portion of the conductive layer 110 and the barrier layer 109 are etched by plasma etching with the aid of a mask.

[0065] In some embodiments, the pretreatment process and process principle include: first, loading the semiconductor structure with the mask layer 103 formed thereon into the equipment, then increasing the pressure and source power of the existing process equipment. Increasing the pressure can enhance the ability of the second source gas to deposit on the sidewalls of the conductive layer 110. Then, increasing the flow rate of the second source gas and simultaneously adding an appropriate amount of oxidizing gas (oxygen). The second source gas and the oxidizing gas have relatively high specific gravity and can be easily deposited on the sidewalls of the conductive layer 110. In addition, increasing the bias power of the equipment increases the bombardment capability and directionality of the plasma, thereby assisting the first source gas in etching the conductive layer 110 while assisting the second source gas in depositing on the surface of the conductive layer 110 and forming the barrier film 115.

[0066] It can be understood that the blocking film 115 is a chemical reaction between the second source gas and the plasma to produce new species. The embodiment of the present disclosure does not limit the specific structure of the blocking film 115. It is only necessary to know that the etching rate of the conductive layer 110 containing the blocking film is less than the etching rate of the conductive layer 110 not containing the blocking film.

[0067] In addition, the barrier film 115 may be a film layer composed of an amorphous gas, ie, a compound that has not formed a specific state.

[0068] The deposition principle is as follows: the power in the device is changed from pulse mode to continue mode. During the continuous generation of plasma, ions and electrons will continue to etch the conductive layer 110 on the surface of the semiconductor structure. However, since the plasma is continuous, the etching by-products are not easy to be extracted. The etching gas in the pretreatment is a heavy polymer gas, and the pressure set by the device is relatively high, which causes the gas molecules to easily vaporize onto the side walls of the conductive layer 110.

[0069] In some embodiments, when the material of the mask layer 103 is carbon, oxygen also has a certain etching ability on the mask layer 103. By adjusting the selection ratio, the conductive layer 110 is etched to a preset depth set by the process while the mask layer 103 is etched away.

[0070] In some embodiments, the pre-treatment process step includes providing He gas, where the He gas serves as a diluent, thereby reducing partial discharge and improving the yield of the semiconductor structure.

[0071] refer to Figure 5 , remove the mask layer to expose the top surface of the conductive layer 110.

[0072] refer to Figure 5 as well as Figure 6 , an etching process is performed on the conductive layer 110 to form a third groove 126 from the upper end of the conductive layer 110 , wherein in the etching process, the etching rate of the conductive layer 110 covered with the barrier film 115 is lower than the etching rate of the conductive layer 110 not covered with the barrier film 115 .

[0073] In some embodiments, the process steps of the etching process include: reducing the pressure and source power in the equipment, slowing down the flow rate of the etching gas and the deposition gas, and adjusting the bias power to 0 at the same time to slow down the flow rate of the etching gas and the deposition gas, so as to accurately control the etching morphology and etching rate of the third groove. Since a large amount of barrier film 115 and the gas composed of the barrier film 115 are deposited on the side wall of the conductive layer 110, the etching rate of the center of the conductive layer 110 will be fast and the etching rate of the edge of the conductive layer 110 will be slow during etching. After the etching is completed, a third groove 126 with a gradually decreasing line width is obtained, such as a V-shaped or U-shaped structure.

[0074] In some embodiments, the pretreatment and the formation of the third recess 126 can be performed in the same apparatus. Since the second source gas has an etching effect on the mask layer 103, after forming the second recess 116, the pressure and bias power of the apparatus can be adjusted to avoid forming a barrier film on the top of the conductive layer 110. However, the second source gas continues to etch the mask layer 103 until the mask layer 103 is completely removed. The first source gas then etches the top of the conductive layer 110, thereby forming the third recess 126. In this way, only the process parameter settings for forming the second recess 116 can be changed, so that the second recess 116 and the third recess 126 can be formed, thereby increasing the contact area between the capacitor contact window and the lower electrode, saving process steps, and reducing process costs.

[0075] In some embodiments, the process parameters of the pretreatment can be: pressure of 30Pa~100Pa, source power of 800W~1500W, bias power of 100W~200W, chlorine flow rate of 5sccm~15sccm, monofluoromethane flow rate of 150sccm~260sccm, oxygen flow rate of 5sccm~15sccm, and He flow rate of 50sccm~150sccm.

[0076] In some embodiments, the process parameters of the etching process are: pressure of 10~50Pa, source power of 200W~800W, bias power of 10W~100W, chlorine flow rate of 5sccm~15sccm, monofluoromethane flow rate of 150sccm~260sccm, oxygen flow rate of 5sccm~15sccm, and He flow rate of 50sccm~150sccm.

[0077] In some embodiments, the etched conductive layer 110 serves as a contact window 117 .

[0078] refer to Figure 7 , remove the barrier film.

[0079] In some embodiments, a cleaning gas is used to remove the barrier film, and the cleaning gas includes any one or a combination of NF3, O2, Ar, or CF4.

[0080] Continue to refer Figure 7 , forming a sacrificial layer 118 , the sacrificial layer 118 is located on the surface of the isolation layer 102 .

[0081] refer to Figure 8 , forming a fourth groove, the fourth groove is located in the sacrificial layer 118, the fourth groove corresponds to the third groove and is connected; forming a conductive column 120, the conductive column 120 fills the third groove and the fourth groove.

[0082] In some embodiments, the conductive column 120 includes a continuous first conductive column 121 and a second conductive column 122, the first conductive column 121 is located in the contact window 117, and the second conductive column 122 is located on the surface of the contact window 117; along the direction from the second conductive column 122 to the first conductive column 121, the line width of the first conductive column 121 decreases.

[0083] In some embodiments, the cross-sectional shape of the first conductive pillar 121 along a direction perpendicular to the substrate surface includes: U-shape or V-shape.

[0084] In some embodiments, the material of the conductive pillar 120 includes at least one of tungsten, tantalum, titanium, tantalum nitride, or titanium nitride.

[0085] In some embodiments, the conductive pillar 120 serves as the lower electrode of the capacitor structure, and subsequent steps include forming a capacitor dielectric layer and an upper electrode, which will not be described in detail here.

[0086] In the above-mentioned process steps of forming the contact window 117 and the conductive pillar 120 in the array area, the conductive layer 110 is pretreated to form a barrier film 115 on the inner wall surface of the second groove 116, and in the subsequent etching process, the etching rate of the conductive layer 110 covered with the barrier film 115 is lower than the etching rate of the conductive layer 110 not covered with the barrier film 115. In this way, only one step of etching the conductive layer 110 and modifying the process parameters for forming the second groove 116 to form the third groove 126 can be added to change the contact area between the conductive pillar and the conductive layer 110. Compared with forming a mask and patterning the third groove in the conventional process, the process steps and preparation costs can be reduced, thereby saving process time and improving the process rate.

[0087] In addition, the blocking film 115 covers the side of the conductive layer 110, and the blocking film 115 can protect the outer side of the conductive layer 110 so that the morphology of the conductive layer 110 is complete. The formed third groove 126 can increase the contact area between the conductive column and the contact window, thereby reducing the contact resistance between the conductive column 120 and the conductive layer 110, thereby improving the electrical performance of the semiconductor structure, reducing electrical loss, and increasing the response speed.

[0088] The following will be combined Figures 9 to 16 The steps corresponding to the peripheral region of the preparation method provided in the above embodiment are described in detail. Technical features that are the same as or corresponding to the above embodiment will not be further described here.

[0089] Figures 9 to 16 This is a schematic flow chart of the structure of a semiconductor structure corresponding to each step in a method for preparing a semiconductor structure provided in another embodiment of the present disclosure.

[0090] refer to Figure 9 , providing a substrate 20 having a plurality of first grooves 206 arranged at intervals.

[0091] In some embodiments, the base 20 may include a stacked substrate 200 and an isolation layer 202 , and the first groove 206 is located in the isolation layer 202 .

[0092] In some embodiments, the base 20 further includes an active layer 201 located between the substrate 200 and the isolation layer 202. The active layer 201 may include a channel region and first and second source / drain regions located at opposite ends of the channel region. The first recess 206 exposes a surface of the first or second source / drain region.

[0093] In some embodiments, the active layer 201 and the substrate 200 can be prepared from the same original substrate. Part of the thickness of the original substrate is patterned to form an active layer 201 arranged at intervals, and the remaining original substrate serves as the substrate 200. There is no interface state between the active layer 201 and the substrate 200. Instead, they are two different film layers divided due to different definitions of different functional defined areas. The two are actually the same film layer.

[0094] In some embodiments, an isolation structure 205 is included between adjacent active layers 201, and the isolation structure 205 is used to separate and isolate the spaced active layers 201. The isolation structure 205 may be a shallow trench isolation structure.

[0095] In some embodiments, the isolation structure 205 is an isolation structure made of an isolation material. The isolation structure 205 can be a single-layer film layer or a multi-layer film layer.

[0096] In some embodiments, the substrate 20 includes a gate structure comprising a stacked gate dielectric layer 211, a first film layer 212, and a second film layer 213; and a third film layer 214 covering the surfaces of the gate dielectric layer 211, the first film layer 212, and the second film layer 213. The gate dielectric layer 211 may be made of silicon dioxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3), tantalum pentoxide (Ta2O5), yttrium oxide (Y2O3), hafnium oxide (HfSiO4), hafnium dioxide (HfO2), lanthanum oxide (La2O3), zirconium dioxide (ZrO2), strontium titanate (SrTiO3), or zirconium oxide (ZrSiO4). The gate structure is a high-k metal gate (HKMG) or a doped polysilicon gate. The first film layer 212 is a barrier layer or work function layer. When the first film layer 212 is a barrier layer, the material of the first film layer can be titanium nitride or other metal nitride. Firstly, it is used to improve the gate polysilicon depletion problem, and secondly, it prevents the top metal gate material from penetrating downward into the gate dielectric layer 211 and affecting the gate dielectric layer. When the first film layer 212 is a work function layer, the first film layer can be aluminum oxide or lanthanum oxide. The material of the second film layer 213 includes metal or doped polysilicon. The material of the third film layer 214 includes silicon nitride, silicon oxide, or silicon oxynitride.

[0097] In some embodiments, the first groove exposes a surface of the second film layer.

[0098] refer to Figure 10 , forming a conductive layer 210 , which fills the first groove 206 and covers the surface of the isolation layer 202 .

[0099] In some embodiments, the material of the conductive layer 210 may include at least one of tungsten, tantalum, tungsten nitride, or tantalum nitride.

[0100] refer to Figure 11 , mask layers 203 are formed on the surface of the conductive layer 210 with intervals, the mask layers 203 completely overlap with the first grooves 206, and the area of ​​the mask layer 203 is larger than the area of ​​the first grooves 206, thereby ensuring that the top surface size of the subsequently formed conductive layer 210 away from the substrate 20 is larger than the bottom surface size, thereby giving full play to the role of the contact plug, improving the alignment accuracy, increasing the contact area and reducing the contact resistance.

[0101] Furthermore, the mask layer 203 has an opening 207 .

[0102] In some embodiments, the mask layer 203 may be photoresist or any material having an etching rate different from that of the conductive layer 210 and the barrier layer under the same etching process. For example, the mask layer 203 may be made of carbon.

[0103] refer to Figure 12 , the conductive layer 210 is pre-treated, and the pre-treatment includes: using the mask layer 203 as a mask, patterning the conductive layer 210 and forming a second groove 216, wherein the sidewall of the conductive layer 210 is exposed through the second groove 216; and forming a barrier film 215 on the sidewall surface.

[0104] In some embodiments, the pretreatment process steps include: providing a first source gas and a second source gas, the first source gas is used to etch the conductive layer 210, and the second source gas is used to form a blocking film 215; removing a portion of the thickness of the conductive layer 210 not covered by the mask layer 203 to form a second groove 216, and forming a continuous blocking film 215 on the surface of the conductive layer 210 exposed by the inner wall surface of the second groove 216 and the bottom of the second groove 216.

[0105] It can be understood that the second groove 216 is carved through the conductive layer 210 and exposes the top surface of the isolation layer 202 to achieve electrical insulation between the conductive layers 210 .

[0106] In some embodiments, the first source gas includes chlorine gas. The conductive layer 210 is removed by chlorine gas, and the etching rate is high, so the second groove can be formed quickly.

[0107] In some embodiments, the second source gas includes monofluoromethane and oxygen, and the flow rate of monofluoromethane is greater than the flow rate of oxygen.

[0108] In some embodiments, reference Figure 13The second source gas is also used to remove the mask layer 203. The etching selectivity ratio between the second source gas and the mask layer 203 is less than or equal to the thickness of the mask layer. Thus, during the formation of the second recess, the mask layer 203 remains in place. After the second recess 216 is formed, the mask layer 203 is still in place or is completely removed. As a result, the barrier film 215 is not formed on the surface of the conductive layer 210 covered by the mask layer 203. Subsequently, the third recess can be formed by the different etching rates of the uncovered conductive layer 210 and the covered conductive layer 210.

[0109] In some embodiments, the pretreatment is a dry etching process, and a portion of the conductive layer 210 and the barrier layer are etched by plasma etching and with the aid of a mask.

[0110] In some embodiments, when the material of the mask layer 203 is carbon, oxygen also has a certain etching ability on the mask layer 203. By adjusting the selection ratio, the conductive layer 210 is etched to a preset depth set by the process while the mask layer is etched away.

[0111] In some embodiments, the pre-treatment process step includes providing He gas, where the He gas serves as a diluent, thereby reducing partial discharge and improving the yield of the semiconductor structure.

[0112] refer to Figure 13 , remove the mask layer to expose the top surface of the conductive layer 210.

[0113] refer to Figure 13 as well as Figure 14 , an etching process is performed on the conductive layer 210 to form a third groove 226 from the upper end of the conductive layer 210 , wherein in the etching process, the etching rate of the conductive layer 210 covered with the barrier film 215 is lower than the etching rate of the conductive layer 210 not covered with the barrier film 215 .

[0114] In some embodiments, you can jump Figure 13 The steps included, namely pretreatment and formation of the third groove 226, can be performed in the same device. Since the second source gas has an etching effect on the mask layer 203, after the second groove 216 is formed, the pressure and bias power of the device can be adjusted to avoid the formation of a blocking film 215 on the top of the conductive layer 210, but the second source gas continues to etch the mask layer 203 until the mask layer 203 is completely removed, and then the first source gas etches the top of the conductive layer 210 to form the third groove 226.

[0115] In some embodiments, the process parameters of the pretreatment can be: pressure of 30Pa~100Pa, source power of 800W~1500W, bias power of 100W~200W, chlorine flow rate of 5sccm~15sccm, monofluoromethane flow rate of 150sccm~260sccm, oxygen flow rate of 5sccm~15sccm, and He flow rate of 50sccm~150sccm.

[0116] In some embodiments, the process parameters of the etching process are: pressure of 10~50Pa, source power of 200W~800W, bias power of 10W~100W, chlorine flow rate of 5sccm~15sccm, monofluoromethane flow rate of 150sccm~260sccm, oxygen flow rate of 5sccm~15sccm, and He flow rate of 50sccm~150sccm.

[0117] In some embodiments, the etched conductive layer 210 serves as a contact window 217 .

[0118] refer to Figure 15 , remove the barrier film.

[0119] In some embodiments, a cleaning gas is used to remove the barrier film, and the cleaning gas includes any one or a combination of NF3, O2, Ar, or CF4.

[0120] Continue to refer Figure 15 , forming a sacrificial layer 218 , the sacrificial layer 218 is located on the surface of the isolation layer 202 .

[0121] refer to Figure 16 , forming a fourth groove, the fourth groove is located in the sacrificial layer 218, the fourth groove corresponds to the third groove and is connected; forming a conductive column 220, the conductive column 220 fills the third groove and the fourth groove.

[0122] In some embodiments, the conductive column 220 includes a continuous first conductive column 221 and a second conductive column 222, the first conductive column 221 is located in the contact window 217, and the second conductive column 222 is located on the surface of the contact window 217; along the direction from the second conductive column 222 to the first conductive column 221, the line width of the first conductive column 221 decreases.

[0123] In some embodiments, the cross-sectional shape of the first conductive pillar 221 along a direction perpendicular to the surface of the substrate 10 includes: U-shape or V-shape.

[0124] In some embodiments, the material of the conductive pillar 220 includes at least one of tungsten, tantalum, titanium, tantalum nitride, or titanium nitride.

[0125] In some embodiments, the conductive pillar 220 serves as a second contact structure.

[0126] In the above-mentioned process steps of forming the contact window 217 and the second contact structure in the peripheral area, the conductive layer 210 is pre-treated to form a barrier film 215 on the inner wall surface of the second groove 216, and in the subsequent etching process, the etching rate of the conductive layer 210 covered with the barrier film is lower than the etching rate of the conductive layer 210 not covered with the barrier film. In this way, only one step of etching the conductive layer 210 to form the third groove can be added or the process parameters for forming the second groove 216 can be changed to change the contact area between the conductive column 220 and the conductive layer 210. Compared with forming a mask and patterning the third groove in the conventional process, the process steps and preparation costs can be reduced, thereby saving process time and improving the process rate. In addition, the barrier film covers the side of the conductive layer 210, and the barrier film can protect the outer side of the conductive layer 210 so that the morphology of the conductive layer 210 is complete. The formed third groove can increase the contact area between the conductive column and the contact window, thereby reducing the contact resistance between the conductive column and the conductive layer 210, thereby improving the electrical performance of the semiconductor structure, reducing electrical loss, and increasing the response speed.

[0127] In addition, in the same process step, the conductive layers in the array area and the peripheral area can be pretreated and etched at the same time, thereby simultaneously forming a capacitor contact window with a third groove and a first contact structure, thereby reducing the contact resistance between the first contact structure and the second contact structure in the peripheral area and the contact resistance between the lower electrode and the capacitor contact window. When the voltage remains unchanged, the current is increased, making it easier to output the signal to the outside world and improving the performance of the chip.

[0128] Accordingly, according to some embodiments of the present disclosure, the embodiments of the present disclosure also provide a semiconductor structure on the other hand, which can be prepared using the preparation method provided by the above embodiments. The technical features that are the same as or corresponding to the above embodiments will not be elaborated here.

[0129] When the substrate is an array area, refer to Figure 8 The semiconductor structure includes: a substrate 10 having a contact window 117 therein, the contact window 117 protruding from the surface of the substrate 10; a conductive column 120, part of the conductive column 120 being located in the contact window 117, and part of the conductive column 120 being located on the surface of the contact window 117.

[0130] In some embodiments, the substrate 10 may include a stacked substrate 100 and an isolation layer 102, with a first recess 106 located within the isolation layer 102. The substrate 10 also includes an active layer 101 located between the substrate 100 and the isolation layer 102. The active layer 101 may include a channel region and first and second source / drain regions located at opposite ends of the channel region. The bit line 108 and the capacitor plug 104 are electrically connected to the first and second source / drain regions of the active layer 101, respectively.

[0131] In some embodiments, an isolation structure 105 is included between adjacent active layers 101 , and the isolation structure 105 is used to separate and isolate the active layers 101 that are arranged at intervals.

[0132] In some embodiments, the semiconductor structure includes a bit line 108 and a word line. The word line is located within the isolation structure 105 on one side of the channel region. The end of the bit line 108 away from the substrate 100 has a barrier layer 109, which is used to isolate the bit line 108 from the capacitor structure.

[0133] In some embodiments, substrate 10 further includes a capacitor plug 104 located within isolation layer 102 and electrically connected to active layer 101. Capacitor plug 104 may be a metal silicide layer or a polysilicon layer and electrically contact contact window 117.

[0134] In some embodiments, the conductive column 120 includes a continuous first conductive column 121 and a second conductive column 122, the first conductive column 121 is located in the contact window 117, and the second conductive column 122 is located on the surface of the contact window 117; along the direction from the second conductive column 122 to the first conductive column 121, the line width of the first conductive column 121 decreases.

[0135] In some embodiments, the cross-sectional shape of the first conductive pillar 121 along a direction perpendicular to the substrate surface includes: U-shape or V-shape.

[0136] In some embodiments, the semiconductor structure further includes a sacrificial layer 118 , the sacrificial layer 118 is located on a surface of the isolation layer 102 , and the conductive pillar is located in the sacrificial layer 118 .

[0137] When the substrate is the peripheral region, refer to Figure 16 The semiconductor structure includes: a substrate 20 having a contact window 217 therein, the contact window 217 protruding from the surface of the substrate 20; a conductive column 220, part of the conductive column 220 being located in the contact window 217, and part of the conductive column 220 being located on the surface of the contact window 217.

[0138] In some embodiments, the base 20 may include a stacked substrate 200 and an isolation layer 202 , and the first groove 206 is located in the isolation layer 202 .

[0139] In some embodiments, the base 20 further includes an active layer 201 located between the substrate 200 and the isolation layer 202. The active layer 201 may include a channel region and first and second source / drain regions located at opposite ends of the channel region. The contact window 217 may be electrically connected to the first or second source / drain region.

[0140] In some embodiments, substrate 20 includes a gate structure comprising a stacked gate dielectric layer 211, a first film layer 212, and a second film layer 213; and a third film layer 214 covering the surfaces of gate dielectric layer 211, first film layer 212, and second film layer 213. A contact window extends through third film layer 214 and electrically contacts second film layer 213.

[0141] In some embodiments, the conductive column 220 includes a continuous first conductive column 221 and a second conductive column 222, the first conductive column 221 is located in the contact window 217, and the second conductive column 222 is located on the surface of the contact window 217; along the direction from the second conductive column 222 to the first conductive column 221, the line width of the first conductive column 221 decreases.

[0142] In some embodiments, the cross-sectional shape of the first conductive pillar 221 along a direction perpendicular to the surface of the substrate 10 includes: U-shape or V-shape.

[0143] In some embodiments, the semiconductor structure further includes a sacrificial layer 218 , the sacrificial layer 218 is located on a surface of the isolation layer 202 , and the conductive pillar is located in the sacrificial layer 218 .

[0144] Accordingly, another aspect of the embodiments of the present disclosure provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, it implements the method for preparing a semiconductor structure as described in any one of the above embodiments.

[0145] In some embodiments, the computer-readable storage medium may include, but is not limited to, a floppy disk, an optical disk, a compact disk-read only memory CD-ROM, a magneto-optical disk, a dynamic random access memory DRAM, a synchronous dynamic random access memory SDRAM, a double data rate synchronous dynamic random access memory DDR SDRAM, a low power double data rate synchronous dynamic random access memory LPDDR SDRAM, a graphic double data rate synchronous dynamic random access memory GDDR SDRAM, a double data rate type dual synchronous dynamic random access memory DDR2 SDRAM, a double data rate type triple synchronous dynamic random access memory DDR3 SDRAM, a double data rate fourth generation synchronous dynamic random access memory DDR4 SDRAM, a thyristor random access memory TRAM, etc.; or it may be a non-volatile memory, such as a phase change random access memory PRAM, a magnetic random access memory MRAM, a resistive random access memory RRAM, etc., a magnetic card or an optical card, a flash memory, or other types of media / machine-readable media suitable for storing machine-executable instructions. In addition, the computer-readable storage medium may be a product that is not connected to a computer device, or it may be a component that is connected to a computer device for use.

[0146] Figure 17 This is a structural block diagram of a terminal provided in one embodiment of the present disclosure.

[0147] Accordingly, some embodiments of the present disclosure further provide a terminal, referring to Figure 17 The terminal 30 includes a processor 32 and a memory 31. The memory 31 is used to store computer programs, and the processor 32 is used to execute the computer programs stored in the memory 31, so that the terminal 30 executes the method for preparing a semiconductor structure as described in any one of the above embodiments.

[0148] In some embodiments, the processor 32 may be a general-purpose processor, including one or more central processing units (CPUs), network processors (NPs), etc.; it may also be a microcontroller unit (MCU), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The memory 31 may include, but is not limited to, high-speed random access memory, non-volatile memory, such as one or more disk storage devices, flash memory devices, or other non-volatile solid-state storage devices. Random access memory includes dynamic random access memory DRAM, synchronous dynamic random access memory SDRAM, double data rate synchronous dynamic random access memory DDR SDRAM, low power double data rate synchronous dynamic random access memory LPDDR SDRAM, graphic double data rate synchronous dynamic random access memory GDDR SDRAM, double data rate type dual synchronous dynamic random access memory DDR2 SDRAM, double data rate type triple synchronous dynamic random access memory DDR3 SDRAM, double data rate fourth generation synchronous dynamic random access memory DDR4 SDRAM, thyristor random access memory TRAM, etc.; non-volatile memory includes phase change random access memory PRAM, magnetic random access memory MRAM, resistive random access memory RRAM, etc., magnetic card or optical card, flash memory, or other types of media / machine-readable media suitable for storing machine-executable instructions.

[0149] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present disclosure, and that in actual applications, various changes in form and detail may be made thereto without departing from the spirit and scope of the present disclosure. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be subject to the scope defined in the claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, wherein the substrate has a plurality of first grooves arranged at intervals; forming a conductive layer, wherein the conductive layer completely fills the first groove and covers the surface of the substrate; forming mask layers arranged at intervals on the surface of the conductive layer, wherein the mask layers partially overlap with the first grooves; Pre-processing the conductive layer, the pre-processing comprising: using the mask layer as a mask, patterning the conductive layer and forming a second groove, wherein the sidewall of the conductive layer is exposed through the second groove; and forming a barrier film on the sidewall surface; performing an etching process on the conductive layer to form a third groove from an upper end of the conductive layer, wherein, in the etching process, an etching rate of the conductive layer covered with the barrier film is lower than an etching rate of the conductive layer not covered with the barrier film; A conductive pillar is formed, where the conductive pillar fills the third groove.

2. The method for preparing a semiconductor structure according to claim 1, wherein: The process steps of the pretreatment include: providing a first source gas and a second source gas, wherein the first source gas is used to etch the conductive layer, and the second source gas is used to form a barrier film; A portion of the conductive layer not covered by the mask layer is removed to form a second groove, and a continuous barrier film is formed on the inner wall surface of the second groove and the surface of the conductive layer exposed at the bottom of the second groove.

3. The method for preparing a semiconductor structure according to claim 2, wherein: The second source gas is also used to remove the mask layer, and an etching selection ratio of the second source gas to the mask layer is less than or equal to the thickness of the mask layer.

4. The method for preparing a semiconductor structure according to claim 2, wherein: The second source gas includes monofluoromethane and oxygen, and a flow rate of the monofluoromethane is greater than a flow rate of the oxygen.

5. The method for preparing a semiconductor structure according to claim 1, wherein: The substrate includes an array region and a peripheral region, and the conductive layer is located in the array region and / or the peripheral region.

6. The method for preparing a semiconductor structure according to claim 1, wherein: Before forming the conductive pillar, the method further includes: removing the barrier film.

7. The method for preparing a semiconductor structure according to claim 6, wherein: The barrier film is removed by using a cleaning gas, wherein the cleaning gas includes any one of NF3, O2, Ar or CF4 or a combination of multiple thereof.

8. A semiconductor structure, characterized in that The semiconductor structure is prepared by the preparation method according to any one of claims 1 to 7, comprising: substrate; a contact window, wherein a portion of the contact window is located in the substrate, and a portion of the contact window protrudes from the surface of the substrate; Conductive pillars, part of which are located in the contact window, and part of which are located on the surface of the contact window.

9. The semiconductor structure according to claim 8, wherein: The conductive column includes a continuous first conductive column and a second conductive column, the first conductive column is located in the contact window, and the second conductive column is located on the surface of the contact window; along the direction from the second conductive column to the first conductive column, the line width of the first conductive column decreases.

10. The semiconductor structure according to claim 9, wherein: The cross-sectional shape of the first conductive pillar along a direction perpendicular to the surface of the substrate includes: U-shape or V-shape.

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