Semiconductor device and method for manufacturing semiconductor device

Abstract

The present disclosure provides a semiconductor device and a manufacturing method thereof. The semiconductor device includes a substrate and at least one functional layer. The functional layer includes: a first signal line and a second signal line, which are stacked in a vertical direction on the substrate, the second signal line is located on a side of the first signal line away from the substrate, and the first signal line and the second signal line are insulated from each other by an insulating film layer between the second signal line and the second signal line. The first signal line and the second signal line both extend in a first horizontal direction. The first signal line and the second signal line both have a main body extension and a lead-out end. In the first signal line and the second signal line: the lead-out end is located at at least one end of the main body extension in the first horizontal direction; the orthographic projection of the main body extension of the first signal line and the main body extension of the second signal line on the substrate overlap; and the orthographic projection of the lead-out end of the first signal line and the lead-out end of the second signal line on the substrate do not overlap. This scheme is conducive to independent lead-out of each layer of signal lines.

Description

TECHNICAL FIELD

[0001] The present disclosure belongs to the field of semiconductor, and particularly relates to a semiconductor device and a manufacturing method of the semiconductor device. BACKGROUND

[0002] With the development of the semiconductor industry, the market demand for DRAM (Dynamic Random Access Memory) storage density is increasing, but the existing 1T1C (T represents transistor and C represents capacitor) storage structure, i.e., a storage structure including one transistor and one capacitor, is difficult to realize three-dimensional stacking, and the storage density is affected by the critical dimension when arranged in a plane, and the critical dimension is limited by the development of a photolithography machine, so it is difficult to improve the storage density. The 2T0C storage structure (i.e., a storage structure including two transistors and no capacitor) can realize the increase of the storage density by continuously increasing the number of stacked layers without reducing the critical dimension, but for the 2T0C storage structure, there are multiple layers of signal lines, and how to lead out each layer of signal lines becomes a problem to be solved. SUMMARY

[0003] Embodiments of the present disclosure provide a semiconductor device and a manufacturing method of the semiconductor device, which are beneficial to leading out each layer of signal lines and interconnecting with other structures.

[0004] A first aspect of the present disclosure provides a semiconductor device, comprising a substrate and at least one functional layer, the functional layer comprising: a first signal line and a second signal line, stacked in a vertical direction on the substrate, the second signal line being located on a side of the first signal line away from the substrate and being insulated from the second signal line by an insulating film layer, the first signal line and the second signal line both extending in a first horizontal direction, wherein,

[0005] The first signal line and the second signal line both have a main extension part and a leading-out end part, and in the first signal line and the second signal line: the leading-out end part is located at at least one end of the main extension part in the first horizontal direction; the main extension part of the first signal line and the main extension part of the second signal line have an overlap in a normal projection on the substrate; and the leading-out end part of the first signal line and the leading-out end part of the second signal line do not have an overlap in the normal projection on the substrate.

[0006] A second aspect of the present disclosure provides a manufacturing method of a semiconductor device, the manufacturing method comprising:

[0007] providing a substrate; and

[0008] At least one functional layer is formed on the substrate, wherein the step of forming the functional layer includes:

[0009] A first signal line and a first insulating film layer covering the first signal line are formed on the substrate, and the first signal line extends in a first horizontal direction.

[0010] A second signal line extending in a first horizontal direction is formed on the side of the first insulating film layer away from the substrate; wherein,

[0011] Both the first signal line and the second signal line have a main body extension and a lead-out end. In the first signal line and the second signal line, the lead-out end is located at at least one end of the main body extension in a first horizontal direction.

[0012] The orthographic projections of the main extension portion of the first signal line and the main extension portion of the second signal line on the substrate overlap.

[0013] The orthographic projections of the lead-out ends of the first signal line and the lead-out ends of the second signal line onto the substrate do not overlap.

[0014] The technical solution provided by the embodiments of this disclosure has at least the following advantages: by staggering the lead-out ends of signal lines located on different layers and extending in the same direction, it is convenient for each layer of signal lines to be led out independently without interfering with each other. Attached Figure Description

[0015] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0016] Figure 1 A three-dimensional structural schematic diagram of a semiconductor device provided in an embodiment of the present disclosure is shown.

[0017] Figure 2 It shows Figure 1 The semiconductor device shown is a cross-sectional view along the AA direction.

[0018] Figure 3 It shows Figure 1 The semiconductor device shown is a cross-sectional view along the BB direction.

[0019] Figure 4 It shows Figure 1 The image shows a cross-sectional view of a memory cell in a semiconductor device along the AA direction.

[0020] Figure 5 It shows Figure 1 The image shows a cross-sectional view of a memory cell in a semiconductor device along the BB direction.

[0021] Figures 6 to 43 A schematic cross-sectional view of the semiconductor device manufacturing method according to an embodiment of the present disclosure is shown after each step has been performed. Detailed Implementation

[0022] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0023] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0024] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0025] This disclosure provides a semiconductor device, which may be DRAM, but is not limited thereto. It may also be other types of semiconductor devices such as ferroelectric random access memory (FeRAM), and no further limitations are made here.

[0026] The structure of the semiconductor device according to the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0027] like Figure 1 As shown, the semiconductor device may include a substrate 10 and a functional layer 20, wherein the functional layer 20 may be formed on the substrate 10. In this embodiment, the functional layer 20 of the semiconductor device is configured with two or more layers to increase the storage density of the semiconductor device, but it is not limited thereto and may also be configured with a single layer.

[0028] Wherein, when the functional layer 20 in the semiconductor device is provided with two layers or more than two layers, the semiconductor device can be understood as a three-dimensional stacked semiconductor device.

[0029] It should be understood that the semiconductor device is not limited to including the functional layer 20, and in addition to the functional layer 20, structures such as a control circuit (not shown in the figure) and a reading circuit can also be included, which will not be described in detail here.

[0030] In combination with Figure 2 and Figure 3 It is shown that the substrate 10 can include a semiconductor base 101 and an insulating isolation layer 102 formed on the semiconductor base 101. In the present embodiment, the insulating isolation layer 102 can be a laminated structure formed by sequentially stacking two or more film layers of different materials, but is not limited thereto, and the insulating isolation layer 102 can also be a single-layer structure.

[0031] For example, the material of the semiconductor base 101 can be an elemental semiconductor material such as silicon (Si) or germanium (Ge), but is not limited thereto, and can also be a crystalline inorganic compound semiconductor material such as silicon carbide (SiC) or silicon germanium (SiGe). The material of the insulating isolation layer 102 can include one or more of insulating materials such as silicon oxide (SiO2), silicon nitride (SiN), and silicon oxynitride (SiON), or can also include other low-K materials.

[0032] As shown in Figure 2 and Figure 3 The insulating isolation layer 102 can include a first film layer 1021 and a second film layer 1022 formed in sequence on the substrate 10, wherein the material of the first film layer 1021 can be a silicon oxide material, and the material of the second film layer 1022 can be a silicon nitride material, but is not limited thereto, and the materials of the first film layer 1021 and the second film layer 1022 can also use other insulating materials.

[0033] In combination with Figure 2 and Figure 3 The functional layer 20 can include a first signal line 203 and a second signal line 205, which are stacked on the substrate 10 in a vertical direction Z. It should be noted that the vertical direction Z can be a direction intersecting the substrate 10, and further, the vertical direction Z can be a direction perpendicular or approximately perpendicular to the substrate 10.

[0034] Wherein, the second signal line 205 is located on the side of the first signal line 203 away from the substrate 10, and is insulated from the first signal line 203 by an insulating film layer, and the first signal line 203 and the second signal line 205 both extend in a first horizontal direction X. It should be noted that the first horizontal direction X can be a direction parallel to the substrate 10.

[0035] The first signal line 203 and the second signal line 205 each have a main body extension (not shown in the figure) and a lead-out end (not shown in the figure), and in the first signal line 203 and the second signal line 205: the lead-out end is located at at least one end of the main body extension in the first horizontal direction X, and the lead-out end is used to receive a level signal output by the control circuit or output a level signal to the read circuit through a lead-out structure.

[0036] The main body extension of the first signal line 203 and the main body extension of the second signal line 205 have an overlap in the orthographic projection on the substrate 10; the lead-out end of the first signal line 203 and the lead-out end of the second signal line 205 do not have an overlap in the orthographic projection on the substrate 10, that is, the lead-out ends of the signal lines located in different layers and extending in the same direction are arranged in a staggered manner without overlapping.

[0037] In this embodiment, by arranging the lead-out ends of the signal lines located in different layers and extending in the same direction in a staggered manner without overlapping, the signal lines of each layer are conveniently independently led out and do not interfere with each other.

[0038] In the first signal line 203 and the second signal line 205: the lead-out end has a first surface close to the substrate 10 and a second surface away from the substrate; and in the first signal line 203 and the second signal line 205: the direction in which the first surface points to the second surface is the lead-out direction, but is not limited thereto, and the direction in which the second surface points to the first surface can also be the lead-out direction, so that the lead-out structure connected to the first signal line 203 and the lead-out structure connected to the second signal line 205 are led out on the same side, which is convenient for manufacturing.

[0039] It should be noted that if the direction in which the first surface points to the second surface is the lead-out direction, then the end of the lead-out structure connected to the corresponding lead-out end and away from the first surface is the terminal end in the lead-out direction, which is used to be connected to structures such as control circuits or read circuits; if the direction in which the second surface points to the first surface is the lead-out direction, then the end of the lead-out structure connected to the corresponding lead-out end and away from the second surface is the terminal end in the lead-out direction, which is used to be connected to structures such as control circuits or read circuits. In addition, it should be noted that the end opposite to the terminal end of the lead-out structure can be defined as the head end.

[0040] For example, the head end of the lead-out structure can be in contact with the first surface or the second surface of the corresponding lead-out end to realize electrical connection. Specifically, when the direction in which the second surface points to the first surface is the lead-out direction, the lead-out structure is in contact with the first surface of the corresponding lead-out end, and when the direction in which the first surface points to the second surface is the lead-out direction, the lead-out structure is in contact with the second surface of the corresponding lead-out end. The surface in contact with the head end of the lead-out structure can be defined as the lead-out surface.

[0041] In the embodiment, the first surface of the leading end of the first signal line 203 and the second signal line 205 can be the leading surface, or the second surface of the leading end of the first signal line 203 and the second signal line 205 can be the leading surface, to be in contact with the leading end of the leading structure to realize electrical connection; but not limited thereto, a groove or a through hole can also be formed on the leading end of the first signal line 203 and the second signal line 205, so that the leading end of the leading structure can be embedded in the groove or the through hole to be in contact with the leading end of the first signal line 203 and the second signal line 205, thereby realizing electrical connection of the two.

[0042] In the embodiment, the extension length of the second signal line 205 can be designed to be different from that of the first signal line 203, that is, the extension length of the signal line located in different layers and extending in the same direction is designed to be different, so that the longer signal line in the plurality of signal lines located in different layers and extending in the same direction is not shielded by the shorter signal line, and it should be noted that the unshielded part is the leading end, so that the plurality of signal lines located in different layers and extending in the same direction are arranged in a stepped manner, facilitating the signal lines of each layer to be led out through different leading structures.

[0043] Among them, the layering position of the longer signal line and the shorter signal line extending in the same direction can be determined according to the leading direction; for example, when the direction in which the second surface of the first signal line 203 and the second signal line 205 points to the first surface is the leading direction, the extension length of the first signal line 203 located in the same functional layer 20 is less than that of the second signal line 205; or when the direction in which the first surface of the first signal line 203 and the second signal line 205 points to the second surface is the leading direction, the extension length of the second signal line 205 located in the same functional layer 20 is less than that of the first signal line 203.

[0044] Optionally, in the first signal line 203 and the second signal line 205: the leading end is arranged at the opposite ends of the main body extension part in the first horizontal direction X, facilitating connection with the control circuit.

[0045] In the embodiment, the functional layer 20 can be provided in multiple layers and arranged in sequence in the vertical direction Z on the substrate 10.

[0046] In the case where a plurality of layers are provided in the functional layer 20, in adjacent two layers of the functional layer 20: when the direction in which the second surface is directed to the first surface in the first signal line 203 and the second signal line 205 is the lead-out direction, the extension length of the first signal line 203 of the functional layer 20 away from the substrate 10 is greater than the extension length of the second signal line 205 of the functional layer 20 close to the substrate 10; or when the direction in which the first surface is directed to the second surface in the first signal line 203 and the second signal line 205 is the lead-out direction, the extension length of the first signal line 203 of the functional layer 20 away from the substrate 10 is less than the extension length of the second signal line 205 of the functional layer 20 close to the substrate 10.

[0047] The functional layer 20 can further include a third signal line 204 extending in the second horizontal direction Y, the third signal line 204 having a main extension part and a lead-out end part, the lead-out end part of the third signal line 204 being located at at least one end of the main extension part of the third signal line 204 in the second horizontal direction Y. The third signal line 204 is arranged in a vertical direction Z with the first signal line 203 and the second signal line 205, and is insulated from each other by the insulating film layer and the signal lines adjacent thereto. It should be noted that the second horizontal direction Y is a direction parallel to the substrate 10, and the second horizontal direction Y intersects the first horizontal direction X, and further, the second horizontal direction Y can be perpendicular to the first horizontal direction X.

[0048] The functional layer 20 further includes a fourth signal line 206 extending in the second horizontal direction Y, the fourth signal line 206 having a main extension part and a lead-out end part, the lead-out end part of the fourth signal line 206 being located at at least one end of the main extension part of the fourth signal line 206 in the second horizontal direction Y, the fourth signal line 206 being arranged in a vertical direction Z with the first signal line 203, the second signal line 205 and the third signal line 204, and being insulated from each other by the insulating film layer and the signal lines adjacent thereto.

[0049] In the case where the fourth signal line 206 and the third signal line 204 are arranged in different layers and extend in the same direction, the main extension part of the fourth signal line 206 and the main extension part of the third signal line 204 have overlapping projections on the substrate 10; the lead-out end part of the fourth signal line 206 and the lead-out end part of the third signal line 204 have non-overlapping projections on the substrate 10, that is, the lead-out end part of the fourth signal line 206 and the lead-out end part of the third signal line 204 are arranged in different layers and do not overlap each other.

[0050] For example, in the functional layer 20: the third signal line 204 is formed between the first signal line 203 and the second signal line 205. In the functional layer 20: the fourth signal line 206 is formed between the third signal line 204 and the second signal line 205, or in the functional layer 20: the fourth signal line 206 is formed on the side of the second signal line 205 away from the third signal line 204.

[0051] It should be noted that, in the third signal line 204 and the fourth signal line 206: the leading end portion has a first surface close to the substrate 10 and a second surface away from the substrate 10; wherein, in the third signal line 204 and the fourth signal line 206: the direction in which the first surface points to the second surface is the leading direction or the direction in which the second surface points to the first surface is the leading direction, so that the leading structure connected with the third signal line 204 and the leading structure connected with the fourth signal line 206 are led out on the same side, which is convenient for manufacturing.

[0052] For example, the first surface of the leading end portion in the third signal line 204 and the fourth signal line 206 can be the leading surface, or the second surface of the leading end portion in the third signal line 204 and the fourth signal line 206 can be the leading surface, so as to be in contact with the leading end of the leading structure (i.e. the starting end of the leading direction) to realize electrical connection; but not limited thereto, a groove or a through hole can also be formed on the leading end portion in the third signal line 204 and the fourth signal line 206, so that the leading end of the leading structure can be embedded in the groove or the through hole to be in contact with the leading end portion in the third signal line 204 and the fourth signal line 206, thereby realizing electrical connection.

[0053] In the embodiment, the extension lengths of the third signal line 204 and the fourth signal line 206 can be designed to be different, that is, the extension lengths of the signal lines located in different layers and extending in the same direction are designed to be different, so that the longer signal line in the plurality of signal lines located in different layers and extending in the same direction is not shielded by the shorter signal line, and it should be noted that the unshielded portion is the leading end portion, so that the plurality of signal lines located in different layers and extending in the same direction are arranged in a stepped manner, which is convenient for the signal lines in each layer to be led out through different leading structures.

[0054] Wherein, the layering positions of the longer signal line and the shorter signal line extending in the same direction can be determined according to the specific position of the leading surface (i.e. the leading direction); for example, when the direction in which the second surface of the third signal line 204 and the fourth signal line 206 points to the first surface is the leading direction, the extension length of the third signal line 204 located in the same functional layer 20 is less than the extension length of the fourth signal line 206; or when the direction in which the first surface of the third signal line 204 and the fourth signal line 206 points to the second surface is the leading direction, the extension length of the fourth signal line 206 located in the same functional layer 20 is less than the extension length of the third signal line 204.

[0055] Optionally, in the third signal line 204 and the fourth signal line 206: the leading end portion is arranged at each of the opposite ends of the main body extension portion in the second horizontal direction Y, which is convenient for connecting with the control circuit.

[0056] When the plurality of layers are provided in the functional layer 20, in the two adjacent functional layers 20: when the direction in which the second surface of the third signal line 204 and the fourth signal line 206 points to the first surface is the leading-out direction, the length of the third signal line 204 of the functional layer 20 away from the substrate 10 is greater than the length of the fourth signal line 206 in the functional layer 20 close to the substrate 10; or when the direction in which the first surface of the third signal line 204 and the fourth signal line 206 points to the second surface is the leading-out direction, the length of the third signal line 204 of the functional layer 20 away from the substrate 10 is less than the length of the fourth signal line 206 in the functional layer 20 close to the substrate 10.

[0057] In addition, the semiconductor device can further include a first leading-out structure S1, a second leading-out structure S3, a third leading-out structure S2 and a fourth leading-out structure S4 which are arranged at intervals, and the first leading-out structure S1 to the fourth leading-out structure S4 all extend along the vertical direction Z and have different extension lengths.

[0058] The one end (i.e., the starting end in the leading-out direction, which can also be defined as the head end) of the first leading-out structure S1 is in contact with the leading-out end of the first signal line 203, and the other end (i.e., the terminal end in the leading-out direction, which can also be defined as the tail end) of the first leading-out structure S1 extends along the leading-out direction and penetrates through each insulating film layer; the one end (i.e., the starting end in the leading-out direction, which can also be defined as the head end) of the second leading-out structure S3 is in contact with the leading-out end of the second signal line 205, and the other end (i.e., the terminal end in the leading-out direction, which can also be defined as the tail end) of the second leading-out structure S3 extends along the leading-out direction and penetrates through each insulating film layer; the one end (i.e., the starting end in the leading-out direction, which can also be defined as the head end) of the third leading-out structure S2 is in contact with the leading-out end of the third signal line 204, and the other end (i.e., the terminal end in the leading-out direction, which can also be defined as the tail end) of the third leading-out structure S2 extends along the leading-out direction and penetrates through each insulating film layer; and the one end (i.e., the starting end in the leading-out direction, which can also be defined as the head end) of the fourth leading-out structure S4 is in contact with the leading-out end of the fourth signal line 206, and the other end (i.e., the terminal end in the leading-out direction, which can also be defined as the tail end) of the fourth leading-out structure S4 extends along the leading-out direction and penetrates through each insulating film layer.

[0059] The specific embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Figure 1 to the accompanying drawings. Figure 5 The specific embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0060] The functional layer 20 can include a plurality of memory cells 20a, and the plurality of memory cells 20a can be arranged in a matrix form. Figure 2 and Figure 3As shown, the plurality of memory cells 20a can be arranged in an array along the first horizontal direction X and the second horizontal direction Y, so that the functional layer 20 is an array type memory structure, which can increase the storage density of each functional layer 20, but is not limited thereto. The functional layer 20 can also include a single memory cell 20a, depending on the specific case.

[0061] In the present embodiment, the memory cell 20a can be a 2T0C structure. Specifically, referring to Figure 4 and Figure 5 As shown, the memory cell 20a can include at least a first transistor 201, a second transistor 202, a first signal line 203, a third signal line 204, a second signal line 205, and a fourth signal line 206.

[0062] As shown, the first signal line 203, the third signal line 204, the second signal line 205, and the fourth signal line 206 each include a main extension portion (not shown in the figure) and a lead-out portion (not shown in the figure), in combination with Figure 2 and Figure 3 As shown, the lead-out portion of the first signal line 203, the third signal line 204, the second signal line 205, and the fourth signal line 206 is located at opposite ends of the main extension portion in the extension direction thereof, for connection with the lead-out structure.

[0063] In addition, the first transistor 201 is connected to the main extension portion of the first signal line 203 and the main extension portion of the third signal line 204, and the second transistor 202 is connected to the main extension portion of the second signal line 205 and the main extension portion of the fourth signal line 206. One or more of the first signal line 203, the third signal line 204, the second signal line 205, and the fourth signal line 206 are used to receive a level signal output by the control circuit or output a level signal to the read circuit through the lead-out structure, to select the memory cell 20a to be read or written in the functional layer 20, thereby realizing the read and write operation of data.

[0064] In combination with Figure 4 and Figure 5 As shown, the first transistor 201 and the second transistor 202 each include a channel portion SD and a gate portion G disposed in mutual insulation with the channel portion SD. Specifically, a gate insulation portion GI is formed between the channel portion SD and the gate portion G. It should be understood that the channel portion SD includes a first connection region, a second connection region, and a channel region located between the first connection region and the second connection region, one of the first connection region and the second connection region being a source region and the other being a drain region. The gate portion G includes a gate region, and specifically, the gate portion G as a whole can be understood as the gate region.

[0065] The first connection region of the first transistor 201 is connected with the main extension of the first signal line 203, for example, the first connection region of the first transistor 201 can be in direct contact with the main extension of the first signal line 203, but is not limited thereto, and other conductive structures can also be indirectly connected; the second connection region of the first transistor 201 is connected with the main extension of the third signal line 204, for example, the second connection region of the first transistor 201 can be in direct contact with the main extension of the first signal line 203, but is not limited thereto, and other conductive structures can also be indirectly connected; the first connection region of the second transistor 202 is connected with the gate region of the first transistor 201, for example, the first connection region of the second transistor 202 can be in direct contact with the gate region of the first transistor 201, or the first connection region of the second transistor 202 can be in contact with the gate region of the first transistor 201 through the conductive contact pad 207; the second connection region of the second transistor 202 is connected with the main extension of the second signal line 205, for example, the second connection region of the second transistor 202 can be in direct contact with the main extension of the second signal line 205, but is not limited thereto, and other conductive structures can also be indirectly connected; the gate region of the second transistor 202 is connected with the main extension of the fourth signal line 206, for example, the gate region of the second transistor 202 is in direct contact with the main extension of the fourth signal line 206, but is not limited thereto, and other conductive structures can also be indirectly connected.

[0066] The storage unit 20a of the embodiment adopts a 2T0C structure, compared with a 1T1C storage structure, while ensuring the storage performance of a single storage unit 20a, the occupied area of the single storage unit 20a can be reduced, so that the number of storage units 20a in each functional layer 20 can be appropriately increased, to improve the storage density of each functional layer 20, and then improve the storage density of the entire semiconductor device.

[0067] For example, in the same functional layer 20: the first signal line 203, the third signal line 204, the second signal line 205 and the fourth signal line 206 are arranged in layers and are insulated from each other by an insulating film layer, so as to reduce the signal crosstalk of the first transistor 201 and the second transistor 202, and also reduce the area occupied by the storage unit 20a.

[0068] It should be noted that the layered arrangement mentioned in the embodiment means that each structure is located in different film layers, and each film layer is stacked in one direction; the mutual insulation mentioned in the embodiment means that an insulating film layer is arranged between adjacent two layers of structures.

[0069] For example, the material of the first signal line 203, the third signal line 204, the second signal line 205 and the fourth signal line 206 can include one or more of TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), ITO (indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), Ag (silver), and the like conductive materials; and the insulating material can include one or more of SiO2 (silicon dioxide), Al2O3 (aluminum oxide), HfO2 (hafnium dioxide), TiO2 (titanium dioxide), SiN (silicon nitride), and the like materials.

[0070] In the same functional layer 20, the first signal line 203 and the second signal line 205 can both extend in the first horizontal direction X, and the third signal line 204 and the fourth signal line 206 can both extend in the second horizontal direction Y. By designing the extension directions of the first signal line 203 and the third signal line 204 to be different, and designing the extension directions of the second signal line 205 and the fourth signal line 206 to be different, the design and control difficulty of the functional layer 20 is reduced while the transistor is controlled, and in addition, the parasitic capacitance between the two signal lines connected to the transistor can be reduced. By designing the extension directions of the first signal line 203 and the second signal line 205 to be the same, and designing the extension directions of the third signal line 204 and the fourth signal line 206 to be the same, the design difficulty of the storage unit 20a is further reduced and the area occupied by the storage unit 20a is reduced.

[0071] Further, the first horizontal direction X and the second horizontal direction Y are perpendicular to each other to reduce the area occupied by the storage unit 20a.

[0072] In addition, when the functional layer 20 includes a plurality of storage units 20a arranged in the first horizontal direction X and the second horizontal direction Y, the plurality of storage units 20a arranged in the first horizontal direction X share a first signal line 203 and a second signal line 205 extending in the first horizontal direction X, as shown in FIG. 2; and the plurality of storage units 20a arranged in the second horizontal direction Y share a third signal line 204 and a fourth signal line 206 extending in the second horizontal direction Y, so as to reduce the control difficulty of the functional layer 20, thereby reducing the cost. Figure 2

[0073] ​As the first signal line 203 and the second signal line 205 are arranged in a stacked manner in the functional layer 20 and extend in the same direction, and the third signal line 204 and the fourth signal line 206 are arranged in a stacked manner and extend in the same direction, in order to facilitate independent leading-out of the signal lines in different layers and extending in the same direction in the functional layer 20, the length of the signal lines in different layers and extending in the same direction can be designed to be different in the embodiment, that is, the second signal line 205 and the first signal line 203 have different extension lengths, and the fourth signal line 206 and the third signal line 204 have different extension lengths. In this way, part of the longer signal line among the multiple signal lines in different layers and extending in the same direction is not shielded by the shorter signal line, so that the multiple signal lines in different layers and extending in the same direction are arranged in a stepped manner, facilitating the leading-out of the signal lines in different layers.

[0074] In combination with Figures 1 to 3 As shown in FIG. 1, each functional layer 20 corresponds to a first leading-out structure S1, a third leading-out structure S2, a second leading-out structure S3, and a fourth leading-out structure S4 arranged at intervals. The leading-out end of the first signal line 203 is in contact with the first leading-out structure S1, the leading-out end of the third signal line 204 is in contact with the third leading-out structure S2, the leading-out end of the second signal line 205 is in contact with the second leading-out structure S3, and the leading-out end of the fourth signal line 206 is in contact with the fourth leading-out structure S4. Each signal line can be connected to a control circuit or a reading circuit through the leading-out structure in contact therewith, so as to realize independent leading-out of the signal lines in the storage unit 20a.

[0075] It should be noted that the position of the leading-out end of the signal line in contact with the leading-out structure can be the leading-out surface (i.e., the first surface or the second surface mentioned above), and at this time, the insulating film layer formed on the side of the leading-out surface of the signal line can be penetrated by the corresponding leading-out structure.

[0076] In combination with Figure 2 and Figure 3 As shown in FIG. 1, in the same functional layer 20: the first signal line 203, the third signal line 204, the second signal line 205, and the fourth signal line 206 are arranged in a stacked manner in the vertical direction Z.

[0077] In the embodiment, the first horizontal direction X and the second horizontal direction Y are directions parallel to the substrate 10, and the vertical direction Z is a direction perpendicular or approximately perpendicular to the substrate 10, that is, the extension directions of the first signal line 203, the third signal line 204, the second signal line 205, and the fourth signal line 206 are parallel to the substrate 10, and the first signal line 203, the third signal line 204, the second signal line 205, and the fourth signal line 206 are arranged in a stacked manner in the direction perpendicular to the substrate 10. In this way, the manufacturing difficulty and design cost can be reduced.

[0078] In addition, in combination with Figures 2 to 5As shown, when the first signal line 203, the third signal line 204, the second signal line 205 and the fourth signal line 206 are stacked in the vertical direction Z, the first transistor 201 and the second transistor 202 can also be stacked in the vertical direction Z on the substrate 10, reducing the area occupied by the storage unit 20a, thereby improving the storage density of the entire functional layer 20.

[0079] Wherein, when the direction in which the first surface of each signal line points to the second surface is the leading-out direction, that is, when the second signal line 205 is formed on the leading-out side of the first signal line 203, and the fourth signal line 206 is formed on the leading-out side of the third signal line 204, as shown in Figure 2 As shown, the extension length of the second signal line 205 is less than the extension length of the first signal line 203, as shown in Figure 3 As shown, the extension length of the fourth signal line 206 is less than the extension length of the third signal line 204, to facilitate the leading-out of each signal line through independent leading-out structures.

[0080] It should be noted that the orthogonal projection mentioned in the embodiments of the present disclosure refers to the projection generated by projecting in the direction perpendicular to the substrate 10.

[0081] Optionally, in the same functional layer 20: the orthogonal projections of the opposite ends of the second signal line 205 on the substrate 10 in the first horizontal direction X are both located within the orthogonal projection of the first signal line 203 on the substrate 10; the orthogonal projections of the opposite ends of the fourth signal line 206 on the substrate 10 in the second horizontal direction Y are both located within the orthogonal projection of the third signal line 204 on the substrate 10.

[0082] Further, in the same functional layer 20: as shown in Figure 2 As shown, the opposite edges of the first signal line 203 in the first horizontal direction X do not overlap with the orthogonal projection of the second signal line 205 on the substrate 10, that is, the opposite edges of the first signal line 203 in the first horizontal direction X are both free from the second signal line 205 on the side away from the substrate 10, and the opposite edges of the first signal line 203 in the first horizontal direction X can both be led out through the first leading-out structure S1; as shown in Figure 3 As shown, the opposite edges of the third signal line 204 in the second horizontal direction Y do not overlap with the orthogonal projection of the fourth signal line 206 on the substrate 10, that is, the opposite edges of the third signal line 204 in the second horizontal direction Y are both free from the fourth signal line 206 on the side away from the substrate 10, and the opposite edges of the third signal line 204 in the second horizontal direction Y can both be led out through the third leading-out structure S2, which facilitates the connection of the storage unit 20a and its surrounding circuit.

[0083] Continuing to refer to Figure 2As shown, the opposite edges of the second signal line 205 in the first horizontal direction X can be led out through the second leading-out structure S3, and the first signal line 203 is continued to be described Figure 3 As shown, the opposite edges of the fourth signal line 206 in the second horizontal direction Y can be led out through the fourth leading-out structure S4.

[0084] It should be noted that the opposite edges mentioned herein refer to the leading-out end portions of the signal lines located at the opposite ends of the main body extension in the extension direction thereof.

[0085] In addition, it should be noted that the first signal line 203 and the third signal line 204 are continued to be described Figure 3 As shown, the number of the first signal line 203 can be equal to that of the second signal line 205 and correspond to each other in the vertical direction Z, and the second signal line 205 is continued to be described Figure 2 As shown, the number of the third signal line 204 can be equal to that of the fourth signal line 206 and correspond to each other in the vertical direction Z, but is not limited thereto, and the number can also be unequal, which depends on the specific case.

[0086] In addition, the width and / or thickness of the first signal line 203, the third signal line 204, the second signal line 205 and the fourth signal line 206 can be designed to be equal, but is not limited thereto, and the width and / or thickness of the first signal line 203, the third signal line 204, the second signal line 205 and the fourth signal line 206 can also be designed to be slightly different according to the actual situation, which depends on the actual performance required by the semiconductor device and the processing conditions.

[0087] In the present embodiment, the direction in which the leading-out end portion of the signal line is away from the substrate 10 can be defined as the leading-out direction, and when the direction in which the leading-out end portion of the signal line is away from the substrate 10 is the leading-out direction: in combination with Figure 2 and Figure 3 As shown, the second signal line 205 can be formed on the side of the first signal line 203 away from the substrate 10, and the fourth signal line 206 can be formed on the side of the third signal line 204 away from the substrate 10, by designing the direction in which the leading-out end portion of the signal line is away from the substrate 10 as the leading-out direction, the first leading-out structure S1, the third leading-out structure S2, the second leading-out structure S3 and the fourth leading-out structure S4 can be uniformly formed after the formation of each film layer in the functional layer 20, which can realize the independent leading-out of each signal line, and also can reduce the manufacturing difficulty and improve the manufacturing efficiency.

[0088] It should be understood that when the direction in which the leading-out end portion of the signal line is away from the substrate 10 can be the leading-out direction, the end portion of the leading-out structure away from the substrate 10 can be connected with the control circuit or other circuit.

[0089] When the direction in which the leading end of the signal line is away from the substrate 10 is the leading direction, the first signal line 203 and the third signal line 204 can be designed to be arranged closer to the substrate 10 than the second signal line 205 and the fourth signal line 206, and the first transistor 201 can be designed to be arranged closer to the substrate 10 than the second transistor 202, so as to facilitate the connection of the first signal line 203 and the third signal line 204 with the first transistor 201, and the connection of the second signal line 205 and the fourth signal line 206 with the second transistor 202.

[0090] In combination Figures 2 to 5 As shown in FIG. 2, when the direction in which the leading end of the signal line is away from the substrate 10 is the leading direction, the first signal line 203, the third signal line 204, the second signal line 205, and the fourth signal line 206 are sequentially stacked on the substrate 10, so that the extension directions of the adjacent signal lines in the functional layer 20 in the vertical direction Z are different from each other, so as to reduce the parasitic capacitance generated between the adjacent signal lines.

[0091] It should be noted that the present scheme is not limited to the design that the direction in which the leading end of the signal line is away from the substrate 10 is the leading direction, but the direction in which the leading end of the signal line is close to the substrate 10 can also be defined as the leading direction, for example: when the direction in which the leading end of the signal line is close to the substrate 10 is the leading direction: the extension length of the second signal line 205 can be greater than the extension length of the first signal line 203, and the extension length of the fourth signal line 206 can be greater than the extension length of the third signal line 204, at this time, after the film layers of the functional layer 20 are sequentially formed, the leading structure can be uniformly formed on the side of the substrate 10.

[0092] In addition, taking the example that the direction in which the leading end of the signal line is away from the substrate 10 is the leading direction, when multiple layers of the functional layer 20 of the semiconductor device are arranged and sequentially stacked on the substrate 10 in the vertical direction Z, in the adjacent two layers of the functional layer 20: Figure 2 As shown in FIG. 2, the extension length of the first signal line 203 in the functional layer 20 away from the substrate 10 is less than the extension length of the second signal line 205 in the functional layer 20 close to the substrate 10, and Figure 3 As shown in FIG. 2, the extension length of the third signal line 204 in the functional layer 20 away from the substrate 10 is less than the extension length of the fourth signal line 206 in the functional layer 20 close to the substrate 10, so as to facilitate the independent leading of the signal lines located in different layers and having the same extension direction in the entire semiconductor device.

[0093] In other words, when the direction in which the leading end of the signal line is away from the substrate 10 is the leading direction, the extension lengths of the signal lines located in different layers and having the same extension direction in the entire semiconductor device sequentially decrease in the direction away from the substrate 10.

[0094] In order to protect the structure of each memory cell 20a in the functional layer 20, the functional layer 20 further comprises an insulating film layer covering the memory cells 20a.

[0095] In combination Figure 2 and Figure 3 As shown in FIG. 1, in the functional layer 20: the first lead-out structure S1 penetrates each insulating film layer on the lead-out direction side thereof, and the third lead-out structure S2 penetrates each insulating film layer on the lead-out direction side thereof; the second lead-out structure S3 penetrates each insulating film layer on the lead-out direction side thereof; and the fourth lead-out structure S4 penetrates each insulating film layer on the lead-out direction side thereof.

[0096] The first lead-out structure S1, the third lead-out structure S2, the second lead-out structure S3, and the fourth lead-out structure S4 all extend in the vertical direction Z and have different extension lengths. It should be understood that the closer the signal line is to the substrate 10, the greater the extension length of the lead-out structure connected by the signal line.

[0097] After the multilayer functional layer 20 is sequentially stacked on the substrate 10, the first lead-out structure S1, the third lead-out structure S2, the second lead-out structure S3, and the fourth lead-out structure S4 corresponding to each functional layer 20 are uniformly formed, so as to simplify the processing steps and reduce the cost.

[0098] In this embodiment, the second connection region of the channel portion SD of the transistor can be located on the side of the channel region away from the first connection region, that is, the channel region of the channel portion SD can extend in the vertical direction Z, so that the storage density can be improved and the leakage current can be reduced by increasing the length of the channel region without increasing the horizontal area of the memory cell 20a. Figures 2 to 5 As shown in FIG. 1, the gate portion G and the channel portion SD are oppositely arranged at least in the direction parallel to the substrate 10.

[0099] Optionally, the materials of the channel portion SD and the gate portion G are both semiconductor materials, and the gate portion G is made of semiconductor material, so as to easily control the threshold voltage of the transistor and reduce the contact surface defects.

[0100] The semiconductor material can be one of IGZO (indium gallium zinc oxide), IZO (indium zinc oxide), and ITO (indium tin oxide), which is beneficial to reduce the leakage current of the transistor and reduce the power consumption of the transistor, but is not limited thereto, and can also be other semiconductor materials such as silicon.

[0101] It should be understood that the semiconductor materials of the channel portion SD and the gate portion G can be the same or different. For example, the semiconductor material of the channel portion SD can include IGZO, and the semiconductor material of the gate portion G can include IZO.

[0102] For example, the first connection region of the channel portion SD of the first transistor 201 is formed between the gate portion G and the first signal line 203, and the channel region and the second connection region of the channel portion SD of the first transistor 201 are both arranged around the gate portion G. It should be understood that the channel region and the second connection region of the channel portion SD of the first transistor 201 are not limited to being arranged around the gate portion G, and can also be located on opposite sides of the gate portion G. The first connection region of the channel portion SD of the second transistor 202 is formed between the gate portion G and the gate portion G of the first transistor 201, and the channel region and the second connection region of the second transistor 202 are both arranged around the gate portion G. That is, the cross section of the channel portion SD of the first transistor 201 and the second transistor 202 in the vertical direction Z can be understood as a U-shaped design. Compared with a flat vertical transistor, the length of the channel region of the first transistor 201 and the second transistor 202 can be increased without changing the horizontal area, so as to improve the storage density.

[0103] Optionally, in combination with Figures 2 to 5 As shown, the third signal line 204 is arranged around the second connection region of the first transistor 201, and the second signal line 205 is arranged around the second connection region of the second transistor 202, so as to improve the integration density of the semiconductor structure.

[0104] In the embodiment, the first connection region of the channel portion SD of the second transistor 202 and the gate portion G of the first transistor 201 form a conductive contact pad 207; the orthographic projection of the gate portion G of the first transistor 201 and the gate portion G of the second transistor 202 on the substrate 10 all overlap with the orthographic projection of the conductive contact pad 207 on the substrate 10, and further, the orthographic projection of the gate portion G of the first transistor 201 and the gate portion G of the second transistor 202 on the substrate 10 can all be located within the orthographic projection of the conductive contact pad 207 on the substrate 10. By arranging the conductive contact pad 207, the conductive area between the gate portion G of the first transistor 201 and the first connection region of the second transistor 202 is ensured, so as to ensure the working performance of the storage unit 20a.

[0105] The embodiments of the present disclosure also provide a manufacturing method of a semiconductor device, which is used for manufacturing the semiconductor device described in any of the foregoing embodiments. The manufacturing method of the semiconductor device can include: providing a substrate 10; and forming at least one functional layer 20 on the substrate 10. The arrangement relationship between structures, the structure shape, the length relationship, the lead direction, etc. in the functional layer 20 can refer to the arrangement relationship between structures, the structure shape, the length relationship, the lead direction, etc. in the functional layer 20 described in any of the foregoing embodiments. Figure 1 to the drawings Figure 5 The content described in the foregoing and the content described in any of the foregoing solutions will not be described in detail here.

[0106] In the embodiment, the step of forming the functional layer 20 can include:

[0107] Step S1, forming the first signal line 203 extending in the first horizontal direction X and the first insulating film layer 209 covering the first signal line 203 on the substrate 10.

[0108] Step S2, forming the second signal line 205 extending in the first horizontal direction X on the side of the first insulating film layer 209 away from the substrate 10.

[0109] In the embodiment, the step of forming the functional layer 20 can further include:

[0110] Before forming the second signal line 205: sequentially forming the third signal line 204, the second insulating film layer 210, the fourth signal line 206 and the third insulating film layer 212 on the side of the first insulating film layer 209 away from the substrate 10, the third signal line 204 and the fourth signal line 206 both extending in the second horizontal direction Y, the third signal line 204 and the fourth signal line 206 being insulated from each other by the second insulating film layer 210, the fourth signal line 206 and the second signal line 205 being insulated from each other by the third insulating film layer 212; or

[0111] Before forming the second signal line 205: sequentially forming the third signal line 204 and the second insulating film layer 210 on the side of the first insulating film layer 209 away from the substrate 10, and after forming the second signal line 205: sequentially forming the third insulating film layer 212 and the fourth signal line 206, the third signal line 204 and the fourth signal line 206 both extending in the second horizontal direction Y, the third signal line 204 and the second signal line 205 being insulated from each other by the second insulating film layer 210, the second signal line 205 and the fourth signal line 206 being insulated from each other by the third insulating film layer 212.

[0112] The following will be described in detail with reference to the accompanying drawings. Figures 1 to 43 The manufacturing method of the embodiment of the present disclosure will be described in detail.

[0113] The step of forming the functional layer 20 on the substrate 10 can specifically include: step S100, step S102, step S104, step S106, step S108, step S110, step S112, step S114, step S116, etc.

[0114] In step S100, the first signal line 203 and the first insulating film layer 209 covering the first signal line 203 are sequentially formed on the substrate 10.

[0115] For example, when the substrate 10 includes the semiconductor substrate 101 and the insulating isolation layer 102 formed on the semiconductor substrate 101, forming the first signal line 203 on the substrate 10 can be understood as forming the first signal line 203 on the side of the insulating isolation layer 102 away from the semiconductor substrate 101.

[0116] The step of forming the first signal lines 203 can include, for example, a step S1001, a step S1002, and a step S1003.

[0117] In the step S1001, a plurality of first signal lines 203 are formed on the substrate 10 so as to be arranged at intervals in the second horizontal direction Y, as shown in Figure 6

[0118] In the step S1002, a first separation material thin film 213a is formed so as to cover the first signal lines 203 and fill between the adjacent first signal lines 203, as shown in Figure 7

[0119] In the step S1003, the part of the first separation material thin film 213a which is higher than the first signal lines 203 is removed, and a first separation pattern layer 213 is formed, the first separation pattern layer 213 being flush with the first signal lines 203 from the surface of the substrate 10, that is, the first signal lines 203 are exposed from the surface of the substrate 10, and the first separation pattern layer 213 includes at least a first separation portion 2131 which fills between the adjacent first signal lines 203, as shown in Figure 8

[0120] After the step S1003 is performed, the first insulating film layer 209 is formed so as to cover the first signal lines 203.

[0121] In the step S102, a third signal line 204 and a second insulating film layer 210 which covers the third signal line 204 are formed in this order on the side of the first insulating film layer 209 which is away from the substrate 10, the main body extension of the third signal line 204 and the main body extension of the first signal line 203 overlapping on the substrate 10.

[0122] The step of forming the third signal line 204 can include, for example, a step S1021, a step S1022, and a step S1023.

[0123] In the step S1021, a plurality of third signal lines 204 are formed on the side of the first insulating film layer 209 which is away from the substrate 10 so as to be arranged at intervals in the first horizontal direction X, as shown in Figure 9

[0124] In the step S1022, a second separation material thin film 214a is formed so as to cover the third signal lines 204 and fill between the adjacent third signal lines 204, as shown in Figure 10

[0125] ​​​​​In step S1023, the portion of the second isolation material film 214a that is higher than the third signal line 204 is removed, and a second isolation pattern layer 214 is formed. The second isolation pattern layer 214 is flush with the surface of the substrate 10 away from the surface of the substrate 10 of the third signal line 204, that is, the surface of the substrate 10 away from the surface of the substrate 10 of the third signal line 204 is exposed, and the second isolation pattern layer 214 at least includes a second isolation portion 2141 that fills between adjacent third signal lines 204, as shown in Figure 11

[0126] After step S1023 is performed, the second insulating film layer 210 covering the third signal line 204 is formed.

[0127] In step S104, a first via hole H1 is formed, which sequentially penetrates the second insulating film layer 210, the main extension portion of the third signal line 204, and the first insulating film layer 209. The first via hole H1 exposes the surface of the substrate 10 away from the surface of the substrate 10 of the main extension portion of the first signal line 203, as shown in Figure 12 Figure 13

[0128] In the orthographic projection on the substrate 10, the first via hole H1 is located in the intersection of the main extension portion of the first signal line 203 and the main extension portion of the third signal line 204, as shown in Figure 12 Figure 13 In the orthographic projection on the substrate 10, the first via hole H1 is located in the intersection of the main extension portion of the first signal line 203 and the main extension portion of the third signal line 204, as shown in

[0129] In step S106, the first transistor 201 is formed in the first via hole H1. The first connection region of the first transistor 201 is in contact with the main extension portion of the first signal line 203, and the second connection region of the first transistor 201 is in contact with the main extension portion of the third signal line 204, as shown in Figure 14 Figure 15

[0130] In step S108, an interlayer insulating film layer 211 is formed, which covers the first transistor 201 and the second insulating film layer 210.

[0131] In step S110, the second signal line 205 and the third insulating film layer 212 covering the second signal line 205 are sequentially formed on the side of the interlayer insulating film layer 211 away from the substrate 10.

[0132] For example, the step of forming the second signal line 205 can include step S1101, step S1102, and step S1103.

[0133] ​​​​​​In step S1101, a plurality of second signal lines 205 are formed on the side of the interlayer insulating film layer 211 away from the substrate 10, the second signal lines 205 being arranged at intervals in the second horizontal direction Y, as shown in Figure 16 .

[0134] In step S1102, a third insulating material film 215a is formed, the third insulating material film 215a covering the second signal lines 205 and filling between the adjacent second signal lines 205, as shown in Figure 17

[0135] In step S1103, the portion of the third insulating material film 215a that is higher than the second signal lines 205 is removed, and a third insulating pattern layer 215 is formed, the surface of the second signal lines 205 away from the substrate 10 being flush with the surface of the second insulating pattern layer 215 away from the substrate 10, that is, the surface of the second signal lines 205 away from the substrate 10 is exposed, and the third insulating pattern layer 215 includes at least a second insulating portion 2151 that fills between the adjacent second signal lines 205, as shown in Figure 18

[0136] After step S1103 is performed, a third insulating film layer 212 is formed to cover the second signal lines 205.

[0137] In step S112, a second through-hole H2 is formed to sequentially pass through the third insulating film layer 212, the second signal lines 205 and the interlayer insulating film layer 211, the second through-hole H2 overlapping the first through-hole H1 in the orthographic projection on the substrate 10, as shown in Figure 19 and Figure 20

[0138] In step S114, a second transistor 202 is formed in the second through-hole H2, the first connection region of the second transistor 202 being connected to the gate region (i.e., the gate portion G) of the first transistor 201, and the second connection region of the second transistor 202 being in contact with the main extension portion of the second signal line 205, as shown in Figure 21 and Figure 22

[0139] For example, in the orthographic projection on the substrate 10, the second through-hole H2 is located in the intersection of the main extension portion of the second signal line 205 and the main extension portion of the fourth signal line 206, so as to reduce the difficulty of connecting the second transistor 202 to the second signal line 205 and the fourth signal line 206.

[0140] For example, in order to realize the connection between the first connection region of the second transistor 202 and the gate region of the first transistor 201, a conductive contact pad 207 can be formed before the second transistor 202 is formed.

[0141] ​​​​Specifically, after forming the first transistor 201 and before forming the interlayer insulating film layer 211, the manufacturing method further includes: in step S107, forming a conductive contact pad 207, the conductive contact pad 207 being in contact with the gate region of the first transistor 201 on the side of the substrate 10, and the conductive contact pad 207 being in contact with the first connection region of the second transistor 202 on the side away from the substrate 10.

[0142] It should be noted that, in order to avoid the short circuit between the channel portion SD and the gate portion G of the first transistor 201, the conductive contact pad 207 and the channel portion SD of the first transistor 201 are insulated, for example, the side of the channel portion SD away from the substrate 10 is covered by the gate insulating portion GI, and the conductive contact pad 207 and the channel portion SD of the first transistor 201 are insulated from each other through the gate insulating portion GI, or other insulating film layers can also be provided.

[0143] Specifically, step S107 can include step S1071, step S1072, step S1073, step S1074, step S1075, step S1076, and step S1077.

[0144] In step S1071, a first conductive material film 301 and a first sacrificial material film 311 are sequentially formed, and the first conductive material film 301 and the first sacrificial material film 311 cover the second insulating film layer 210 and the first transistor 201.

[0145] For example, the first sacrificial material film 311 can include a laminated film of multiple film layers, such as a spin on carbon (SOC) film layer and a SiN film layer which are sequentially laminated, but is not limited thereto, and the first sacrificial material film 311 can also be a single-layer structure, and the material thereof can also include one or more of silicon oxynitride, silicon oxide, and the like.

[0146] In step S1072, a first photoresist mask pattern layer 321 is formed on the side of the first sacrificial material film 311 away from the first conductive material film 301, and the first photoresist mask pattern layer 321 includes a plurality of first photoetching holes 3210 arranged in a first horizontal direction X and a second horizontal direction Y, and the first photoetching holes 3210 correspond one-to-one to the first transistor 201, as shown in FIG. 3B. Figure 23

[0147] In step S1073, the first sacrificial material film 311 is patterned using the first photoresist mask pattern layer 321 to form a first sacrificial pattern layer 3110, and the first sacrificial pattern layer 3110 includes a plurality of first sacrificial holes 31101 arranged at intervals, and the first sacrificial holes 31101 correspond one-to-one to the first photoetching holes 3210, and the first sacrificial holes 31101 expose the surface of the first conductive material film 301 away from the substrate 10, as shown in FIG. 3C.​Figure 24 As shown.

[0148] In step S1074, the first photoresist mask pattern layer 321 is removed, and then a first intermediate mask material film is formed, which covers the surface of the first sacrificial pattern layer 3110 away from the substrate 10 and fills in the first sacrificial perforations 31101.

[0149] In step S1075, the part of the first intermediate mask material film that is higher than the first sacrificial pattern layer 3110 is removed to form a first intermediate mask pattern layer, which includes a plurality of first intermediate mask blocks 331 arranged at intervals, the first intermediate mask blocks 331 being located in the first sacrificial perforations 31101, and the surface of the first intermediate mask blocks 331 away from the substrate 10 being flush with the surface of the first sacrificial pattern layer 3110 away from the substrate 10, as shown. Figure 25 As shown.

[0150] In other embodiments, the first sacrificial material film 311 can be a plurality of sub-layers stacked in sequence. For example, when the first sacrificial material film 311 is a SOC film layer and a SiN film layer stacked in sequence, the material of the first intermediate mask material film can be SiN, reverse silicon nitride deposition can be achieved by removing the SiN higher than the upper surface of the SOC film layer, the removal process can be a planarization process, the removal process can take the SOC film layer as a stop layer, and the planarization process can be chemical mechanical polishing (CMP). However, the material of the first intermediate mask material film can also be one or more of SiON, SiO2, and other insulating materials, and other process methods such as etching can be selected for the removal process, and the end point of the removal process can be the upper surface of the entire first sacrificial material film 311 or any sub-layer thereof.

[0151] In step S1076, the first sacrificial pattern layer 3110 is removed, and the first intermediate mask blocks 331 are retained, as shown. Figure 26 As shown.

[0152] In step S1077, the first intermediate mask blocks 331 are used to pattern the first conductive material film 301 to form a plurality of conductive contact pads 207 arranged at intervals, the conductive contact pads 207 corresponding one-to-one to the first transistors 201, as shown. Figure 27 As shown.

[0153] After the conductive contact pads 207 are formed and before the interlayer insulating film layer 211 is formed, the manufacturing method can further include:

[0154] A fourth isolation material film 216a is formed on the side of the second insulating film layer 210 away from the substrate, the fourth isolation material film 216a covering each conductive contact pad 207 and filling between adjacent conductive contact pads 207, as shown. Figure 28As shown;

[0155] The portion of the fourth isolation material film 216a that is higher than the conductive contact pad 207 is removed, and a fourth isolation pattern layer 216 is formed. The fourth isolation pattern layer 216 is flush with the surface of the substrate 10 away from the substrate 10, that is, the surface of the conductive contact pad 207 away from the substrate 10 is exposed, and the fourth isolation pattern layer 216 at least includes a fourth isolation portion 2161 that fills between adjacent conductive contact pads 207, as shown. Figure 29 As shown.

[0156] In step S116, a fourth signal line 206 and a fourth insulating film layer 208 that covers the fourth signal line 206 are formed on the side of the second transistor 202 away from the substrate 10. The main body extension of the fourth signal line 206 is in contact with the gate region (i.e., the gate portion G) of the second transistor 202.

[0157] It should be noted that, in order to avoid shorting of the channel portion SD and the gate portion G of the second transistor 202, the main body extension of the fourth signal line 206 and the channel portion SD of the first transistor 201 are insulated, for example, the side of the channel portion SD away from the substrate 10 is covered by a gate insulating portion GI, and the main body extension of the fourth signal line 206 and the channel portion SD of the second transistor 202 are insulated from each other through the gate insulating portion GI, or other insulating film layers can also be provided.

[0158] Based on the foregoing, in the present embodiment, the manufacturing method of the first signal line 203 to the fourth signal line 206 can be the same. Specifically, the steps of forming the first signal line 203 to the fourth signal line 206 can include: first, forming a plurality of signal lines arranged at intervals (i.e., first forming a conductive pattern layer); then, forming an isolation material film that covers each signal line and fills between adjacent signal lines; and then, removing the portion of the isolation material film that is higher than the signal line to expose the upper surface of the signal line and form an isolation pattern layer. The isolation pattern layer is flush with the surface of the signal line away from the substrate, and the isolation pattern layer at least includes an isolation portion that fills between adjacent signal lines.

[0159] It should be noted that, after forming the plurality of fourth signal lines 206 arranged at intervals, the portion of the fourth insulating film layer 208 that is higher than the fourth signal line 206 can not be removed, but is not limited thereto. The portion of the fourth insulating film layer 208 that is higher than the fourth signal line 206 can also be removed first, and then subsequent manufacturing, such as covering other insulating film layers or conductive layers, can be performed, depending on the specific circumstances.

[0160] In the present embodiment, the manufacturing of the conductive contact pad 207 and the fourth isolation pattern layer 216 can also be omitted.

[0161] In an embodiment, the method of forming the plurality of spaced first signal lines 203, the third signal lines 204, the second signal lines 205, and the fourth signal lines 206 can be the same, and specifically, the steps of forming the plurality of spaced signal lines (i.e., the conductive pattern layer) can include steps S10, S11, S12, S13, S14, S15, S16, S17, S18, and S19.

[0162] In step 10, a second conductive material film 401, a hard mask material film 501, and a second sacrificial material film 411 are sequentially formed on the substrate 10.

[0163] The hardness of the hard mask material film 501 can be greater than the hardness of the second sacrificial material film 411 to ensure better collimation for downward etching.

[0164] For example, the hard mask material film 501 can be an amorphous carbon (A-C) film, but is not limited thereto and other materials can also be used. The second sacrificial material film 411 can include multiple film layers, such as SiON film layers, SOC film layers, SiON film layers, and the like, which are sequentially stacked, but is not limited thereto and other insulating materials can also be used, and can also be a single film layer, which is not described in detail herein.

[0165] It should be noted that the fabrication of the hard mask material film 501 can also be omitted in this embodiment, depending on the specific circumstances.

[0166] In step 11, a second photoresist mask pattern layer is formed on the side of the second sacrificial material film 411 away from the substrate 10, and the second photoresist mask pattern layer includes a plurality of photoresist mask strips 421 spaced apart in the P direction, as shown in Figure 31 .

[0167] In step 12, the second sacrificial material film 411 is patterned using the second photoresist mask pattern layer to form a second sacrificial pattern layer, as shown in Figure 32 . The second sacrificial pattern layer includes a plurality of sacrificial mask strips 4111 spaced apart in the P direction, and the sacrificial mask strips 4111 correspond one-to-one to the photoresist mask strips 421.

[0168] In step 13, the second photoresist mask pattern layer is removed, and then an intermediate mask material film 502 covering each sacrificial mask strip 4111 is formed, as shown in Figure 32 .

[0169] For example, the material of the intermediate mask material film 502 can be SiO2, but is not limited thereto and can also be an insulating material such as SiON or SiN.

[0170] In step 14, a trimming mask layer 503 is formed on the side of the intermediate mask material film 502 away from the substrate 10, and the sacrificial mask strips 4111 are not covered by the trimming mask layer 503 at least on the edge regions in the extension direction (for example, the Q direction) of the sacrificial mask strips 4111. Figure 33 Figure 33 The trimming mask layer 503 may, for example, be photoresist after a photoetching process, but is not limited thereto, and may be other materials, which will not be described in detail herein.

[0171] In step 15, the portions of the intermediate mask material film 502 not covered by the trimming mask layer 503 are removed by using the trimming mask layer 503, as shown in FIG. 5D, and the portions of the sacrificial mask strips 4111 not covered by the trimming mask layer 503 are exposed, but are not limited thereto. In this step, in addition to the portions of the intermediate mask material film 502 not covered by the trimming mask layer 503 being removed, the portions of the sacrificial mask strips 4111 not covered by the trimming mask layer 503 may also be removed.

[0172] In step 16, the trimming mask layer 503 is removed, and the intermediate mask material film 502 is patterned to form an intermediate mask pattern layer, which is composed of a plurality of intermediate mask strips 5021 separated from each other in the P direction, and each of the sacrificial mask strips 4111 has intermediate mask strips 5021 formed on opposite sides thereof, and the intermediate mask strips 5021 formed on the sides of adjacent sacrificial mask strips 4111 close to each other are separated from each other, that is, two intermediate mask strips separated from each other are arranged between adjacent sacrificial mask strips 4111 and are formed on the side walls of one of the sacrificial mask strips 4111, as shown in FIG. 5E. Figure 34 It should be noted that, when the intermediate mask material film 502 is patterned, only the intermediate mask material formed on the side walls of the sacrificial mask strips 4111 is retained to form the intermediate mask strips 5021, and the intermediate mask material at other positions (for example, the side of the sacrificial mask strips 4111 away from the substrate 10 and the hard mask material film 501) is removed to separate the sacrificial mask strips 4111 from each other.

[0173] Figure 35 In step S17, the sacrificial pattern layer is removed, and the hard mask material film 501 is patterned by using the intermediate mask pattern layer to form a hard mask pattern layer, as shown in FIG. 5F. The hard mask pattern layer includes a plurality of hard mask strips 5011 arranged at intervals in the P direction, and the hard mask strips 5011 correspond to the intermediate mask strips 5021 one by one.

[0174] It should be noted that, when the intermediate mask material film 502 is patterned, only the intermediate mask material formed on the side walls of the sacrificial mask strips 4111 is retained to form the intermediate mask strips 5021, and the intermediate mask material at other positions (for example, the side of the sacrificial mask strips 4111 away from the substrate 10 and the hard mask material film 501) is removed to separate the sacrificial mask strips 4111 from each other.

[0175] In step S17, the sacrificial pattern layer is removed, and the hard mask material film 501 is patterned by using the intermediate mask pattern layer to form a hard mask pattern layer, as shown in FIG. 5F. The hard mask pattern layer includes a plurality of hard mask strips 5011 arranged at intervals in the P direction, and the hard mask strips 5011 correspond to the intermediate mask strips 5021 one by one. Figure 36 It should be noted that, when the intermediate mask material film 502 is patterned, only the intermediate mask material formed on the side walls of the sacrificial mask strips 4111 is retained to form the intermediate mask strips 5021, and the intermediate mask material at other positions (for example, the side of the sacrificial mask strips 4111 away from the substrate 10 and the hard mask material film 501) is removed to separate the sacrificial mask strips 4111 from each other.

[0176] It should be noted that, when the intermediate mask material film 502 is patterned, only the intermediate mask material formed on the side walls of the sacrificial mask strips 4111 is retained to form the intermediate mask strips 5021, and the intermediate mask material at other positions (for example, the side of the sacrificial mask strips 4111 away from the substrate 10 and the hard mask material film 501) is removed to separate the sacrificial mask strips 4111 from each other.​In step S18, the intermediate mask strip 5021 is removed, and the second conductive material film 401 is patterned using the hard mask pattern layer to form a conductive pattern layer, as shown in FIG. 4C. Figure 37 As shown in FIG. 4C, the conductive pattern layer includes a plurality of signal lines 4011 arranged at intervals, and the signal lines 4011 correspond one-to-one to the hard mask strips 5011.

[0177] In step S19, the hard mask pattern layer is removed, as shown in FIG. 4D. Figure 38

[0178] It should be noted that when the signal lines 4011 formed by sequentially using the steps S10, S11, S12, S13, S14, S15, S16, S17, S18, and S19 are the first signal lines 203 or the second signal lines 205 mentioned above, the P direction can be understood as the second horizontal direction Y mentioned above, and the Q direction can be understood as the first horizontal direction X mentioned above; and when the signal lines 4011 formed by sequentially using the steps S10, S11, S12, S13, S14, S15, S16, S17, S18, and S19 are the third signal lines 204 or the fourth signal lines 206 mentioned above, the P direction can be understood as the first horizontal direction X mentioned above, and the Q direction can be understood as the second horizontal direction Y mentioned above.

[0179] The length of the trimming mask layer 503 used in the step of forming the first signal lines 203 in the first horizontal direction X is a first length, the length of the trimming mask layer 503 used in the step of forming the second signal lines 205 in the first horizontal direction X is a second length, the length of the trimming mask layer 503 used in the step of forming the third signal lines 203 in the second horizontal direction Y is a third length, and the length of the trimming mask layer 503 used in the step of forming the fourth signal lines 206 in the second horizontal direction Y is a fourth length.

[0180] In the same functional layer 20, when the first surface is the lead-out surface, the second length is greater than the first length, so that the extension length of the second signal lines 205 is greater than the extension length of the first signal lines 203, and the fourth length is greater than the third length, so that the extension length of the fourth signal lines 206 is greater than the extension length of the third signal lines 204; or when the second surface is the lead-out surface, the second length is less than the first length, so that the extension length of the second signal lines 205 is less than the extension length of the first signal lines 203, and the fourth length is less than the third length, so that the extension length of the fourth signal lines 206 is less than the extension length of the third signal lines 204.

[0181] ​For example, the second surface is taken as the leading surface, and the steps of forming the first signal line 203 and the second signal line 205 are the same, except that the extension length of the trimming mask layer 503 corresponding to the second signal line 205 in the Q direction is different from that of the first signal line 203, for example, the extension length of the trimming mask layer 503 corresponding to the second signal line 205 in the Q direction is smaller than that of the first signal line 203, so that the extension length of the second signal line 205 is smaller than that of the first signal line 203. Similarly, the steps of forming the third signal line 204 and the fourth signal line 206 are the same, except that the extension length of the trimming mask layer 503 corresponding to the fourth signal line 206 in the P direction is different from that of the third signal line 204, for example, the extension length of the trimming mask layer 503 corresponding to the fourth signal line 206 in the P direction is smaller than that of the third signal line 204, so that the extension length of the fourth signal line 206 is smaller than that of the third signal line 204.

[0182] For example, the conductive material film, the hard mask material film 501, and the second sacrificial material film 411 mentioned above can be formed by deposition processes, such as CVD (Chemical Vapor Deposition), PVD (Physical Vapor Deposition), ALD (Atomic Layer Deposition), etc., but are not limited thereto, and can also be formed by coating processes, etc., depending on the specific circumstances.

[0183] For example, the conductive material film mentioned above can be one or more of TiN (Titanium Nitride), Ti (Titanium), Au (Gold), W (Tungsten), Mo (Molybdenum), ITO (Indium Tin Oxide), Al (Aluminum), Cu (Copper), Ru (Ruthenium), Ag (Silver), etc.; and the insulating material can be one or more of SiO2 (Silicon Dioxide), Al2O3 (Aluminum Oxide), HfO2 (Hafnium Dioxide), TiO2 (Titanium Dioxide), SiN (Silicon Nitride), etc.

[0184] It should be noted that when the step S10 of manufacturing the hard mask material film 501 is omitted, the second conductive material film 401 can be directly patterned by the intermediate mask pattern layer after the sacrificial pattern layer is removed, to form the conductive pattern layer.

[0185] In a specific embodiment, the steps of forming the first via H1 and the second via H2 can each include the steps S20, S21, S22, S23, S24, S25, and S26.

[0186] In step S20, a third thin film of sacrificial material 601 is formed on the side of the stack structure away from the substrate 10, the stack structure comprising a bottom insulating film layer 602, a middle signal line 603 and a top insulating film layer 604 arranged in sequence on the substrate 10.

[0187] For example, the third thin film of sacrificial material 601 can comprise a plurality of film layers, such as a SiON film layer, a SOC film layer, a SiON film layer arranged in sequence, but is not limited thereto, and can also comprise a single film layer, and can also comprise other insulating materials, and will not be described in detail herein.

[0188] In step S21, a third photoresist mask pattern layer 605 is formed on the side of the third thin film of sacrificial material 601 away from the substrate 10, the third photoresist mask pattern layer 605 comprising a plurality of third photoetching holes 6051 arranged in an array in the first horizontal direction X and the second horizontal direction Y, as shown in Figure 39 .

[0189] In step S22, the third thin film of sacrificial material 601 is patterned using the third photoresist mask pattern layer 605 to form a third sacrificial pattern layer 6011, the third sacrificial pattern layer 6011 comprising a plurality of third sacrificial holes 60111 arranged at intervals, the third sacrificial holes 60111 corresponding one-to-one to the third photoetching holes 6051, and the third sacrificial holes 60111 exposing the surface of the top insulating film layer 604 away from the substrate 10, as shown in Figure 40 .

[0190] In step S23, the third photoresist mask pattern layer 605 is removed, and then an insulating material thin film 606 is formed, the insulating material thin film 606 covering the surface of the third sacrificial pattern layer 6011 away from the substrate 10 and filling in the third sacrificial holes 60111, the portion of the insulating material thin film 606 located in the third sacrificial holes 60111 being a blind groove structure 6061, as shown in Figure 41 .

[0191] For example, the insulating material thin film 606 can be silicon oxide, but is not limited thereto, and can also be other insulating materials. The insulating material can be formed using an ALD deposition process, but is not limited thereto, and can also be formed using a CVD or other deposition process.

[0192] In step S24, the portion of the insulating material thin film 606 above the third sacrificial pattern layer 6011 and the bottom wall of the blind groove structure 6061 are removed, and the side wall of the blind groove structure 6061 is retained, to form a target etching hole 60611, as shown in Figure 42 . The aperture of the target etching hole 60611 is smaller than the aperture of the third sacrificial hole 60111.

[0193] In step S25, the stack structure is patterned by using the target etching hole 60611 to form a via hole H, as shown in Figure 43

[0194] In step S26, the third sacrificial pattern layer 6011 and the sidewall of the blind slot structure 6061 on the stack structure are removed, as shown in Figure 43

[0195] In the step of forming the via hole H as the first via hole H1, the bottom insulating film layer 602 is the first insulating film layer 209, the middle signal line 603 is the third signal line 204, and the top insulating film layer 604 is the second insulating film layer 210; in the step of forming the via hole H as the second via hole H2, the bottom insulating film layer 602 is the interlayer insulating film layer 211, the middle signal line 603 is the second signal line 205 or the fourth signal line 206, and the top insulating film layer 604 is the third insulating film layer 212.

[0196] It should be noted that the material of the interlayer insulating film layer mentioned in the embodiment can be one or more of SiO2 (silicon dioxide), A12O3 (aluminum oxide), HfO2 (hafnium dioxide), TiO2 (titanium dioxide), SiN (silicon nitride), etc.

[0197] In an embodiment, the steps of forming the first transistor 201 and the second transistor 202 both include:

[0198] forming a channel film, the channel film covering the surface of the stack structure away from the substrate 10 and filling in the via hole of the stack structure;

[0199] patterning the channel film to form a channel portion SD in the via hole, the channel portion SD being in a groove shape, and the sidewall of the channel portion SD in the groove away from the surface of the substrate 10 being lower than the surface of the stack structure away from the substrate;

[0200] forming a gate insulating film and a gate film in sequence, the gate insulating film and the gate film covering the surface of the stack structure away from the substrate 10, the sidewall of the channel portion SD in the groove away from the surface of the substrate 10, and filling in the groove of the channel portion SD, the part of the gate insulating film in the via hole being a gate insulating portion GI, part of the gate insulating portion GI being in the groove of the channel portion SD, a part covering the sidewall of the channel portion SD in the groove away from the surface of the substrate 10, the part of the gate insulating portion GI in the groove of the channel portion SD being in a groove shape, the part of the gate film in the groove of the gate insulating portion GI being a gate portion G, and the groove of the gate insulating portion GI being filled with the gate portion G;

[0201] ​​The gate insulating film and the gate film are removed from portions of the stack structure that protrude above the stack structure, so that the stack structure, the gate insulating portion GI, and the gate portion G are exposed flush with each other from a surface of the substrate 10 to form a transistor inside the through hole.

[0202] In the step of forming the first transistor 201, the stack structure includes the first insulating film layer 209, the third signal line 204, and the second insulating film layer 210 stacked in this order, and the through hole is the first through hole H1. In the step of forming the second transistor 202, the stack structure includes the interlayer insulating film layer 211, the second signal line 205, and the third insulating film layer 212 stacked in this order, and the through hole is the second through hole H2.

[0203] For example, the channel film and the gate film can be one of IGZO (indium gallium zinc oxide), IZO (indium zinc oxide), and ITO (indium tin oxide), which are advantageous for reducing the leakage current of the transistor and reducing the power consumption of the transistor, but are not limited thereto and can be other semiconductor materials such as silicon. The material of the gate insulating film can be one or more of SiO2 (silicon dioxide), Al2O3 (aluminum oxide), HfO2 (hafnium dioxide), TiO2 (titanium dioxide), and SiN (silicon nitride).

[0204] In the step of forming at least one functional layer 20 on the substrate 10 in the present embodiment, specifically, the step can include: sequentially forming a plurality of functional layers 20 on the substrate 10, as shown in Figures 1 to 3 .

[0205] In combination with Figure 2 and Figure 3 , in the two adjacent functional layers 20: the functional layer 20 far from the substrate 10 is defined as an upper functional layer, and the functional layer 20 close to the substrate 10 is defined as a lower functional layer. When the second surface is the lead-out surface: the length of the trimming mask layer 503 used in the step of forming the first signal line 203 of the upper functional layer in the first horizontal direction X is less than the length of the trimming mask layer 503 used in the step of forming the second signal line 205 of the lower functional layer in the first horizontal direction X, so that the extension length of the first signal line 203 of the upper functional layer is less than the extension length of the second signal line 205 of the lower functional layer. The length of the trimming mask layer 503 used in the step of forming the third signal line 204 of the upper functional layer in the second horizontal direction Y is less than the length of the trimming mask layer 503 used in the step of forming the fourth signal line 206 of the lower functional layer in the second horizontal direction Y, so that the extension length of the third signal line 204 of the upper functional layer is less than the extension length of the fourth signal line 206 of the lower functional layer.

[0206] But not limited to, when the first surface is the leading surface: the length of the trimming mask layer 503 used in the step of forming the first signal line 203 of the upper functional layer in the first horizontal direction X is greater than the length of the trimming mask layer 503 used in the step of forming the second signal line 205 of the lower functional layer in the first horizontal direction X, so that the extension length of the first signal line 203 of the upper functional layer is greater than the extension length of the second signal line 205 of the lower functional layer, the length of the trimming mask layer 503 used in the step of forming the third signal line 204 of the upper functional layer in the second horizontal direction Y is greater than the length of the trimming mask layer 503 used in the step of forming the fourth signal line 206 of the lower functional layer in the second horizontal direction Y, so that the extension length of the third signal line 204 of the upper functional layer is greater than the extension length of the fourth signal line 206 of the lower functional layer.

[0207] It should be noted that, before the other functional layer 20 is stacked on the functional layer 20 formed on the substrate 10, an insulating isolation layer 102 can be formed on the surface of the lower functional layer (the functional layer 20 close to the substrate 10) away from the substrate 10, and then the upper functional layer (the functional layer 20 away from the substrate 10) is manufactured to form electrical isolation between the upper functional layer 20.

[0208] In the embodiment, after the step of forming at least one functional layer 20 on the substrate 10, the manufacturing method further comprises:

[0209] The first leading structure S1, the third leading structure S2, the second leading structure S3 and the fourth leading structure S4 extending in the vertical direction Z and arranged apart from each other are formed, and each functional layer 20 corresponds to the first leading structure S1, the third leading structure S2, the second leading structure S3 and the fourth leading structure S4, as shown in Figure 2 and Figure 3 .

[0210] For example, taking the second surface as the lead-out surface, the first lead-out structure S1 at least penetrates the fourth insulating film layer 208, the third insulating film layer 212, the interlayer insulating film layer 211, the second insulating film layer 210 and the first insulating film layer 209 of the functional layer 20 corresponding thereto, so as to be in contact with the lead-out surface of the lead-out end portion of the first signal line 203 of the functional layer 20 corresponding thereto; the third lead-out structure S2 at least penetrates the fourth insulating film layer 208, the third insulating film layer 212, the interlayer insulating film layer 211 and the second insulating film layer 210 of the functional layer 20 corresponding thereto, so as to be in contact with the lead-out surface of the lead-out end portion of the third signal line 204 of the functional layer 20 corresponding thereto; the second lead-out structure S3 at least penetrates the fourth insulating film layer 208 and the third insulating film layer 212 of the functional layer 20 corresponding thereto, so as to be in contact with the lead-out surface of the lead-out end portion of the second signal line 205 of the functional layer 20 corresponding thereto; and the fourth lead-out structure S4 at least penetrates the fourth insulating film layer 208 of the functional layer 20 corresponding thereto, so as to be in contact with the lead-out surface of the lead-out end portion of the fourth signal line 206 of the functional layer 20 corresponding thereto.

[0211] For example, the material of the first lead-out structure S1, the third lead-out structure S2, the second lead-out structure S3 and the fourth lead-out structure S4 can be one or more of TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), ITO (indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), Ag (silver) and the like conductive materials.

[0212] Although the embodiments of the present disclosure have been shown and described above, it should be understood that the above-mentioned embodiments are exemplary and should not be construed as limiting the present disclosure, and those of ordinary skill in the art can make changes, modifications, replacements and variations to the above-mentioned embodiments within the scope of the present disclosure, and any changes or modifications made in accordance with the claims and specification of the present disclosure shall be within the scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that, It includes a substrate and at least one functional layer, the functional layer including: a first signal line, a second signal line, a third signal line and a fourth signal line, which are stacked on the substrate in a vertical direction and are insulated from each other by an insulating film layer and adjacent signal lines; The second signal line is located on the side of the first signal line away from the substrate; the third signal line is formed between the first signal line and the second signal line; the fourth signal line is formed between the third signal line and the second signal line or on the side of the second signal line away from the third signal line; both the first and second signal lines extend in a first horizontal direction, and both the third and fourth signal lines extend in a second horizontal direction intersecting the first horizontal direction. The first signal line, the second signal line, the third signal line, and the fourth signal line all have a main body extension and a lead-out end; In the first signal line and the second signal line: the lead-out end is located at at least one end of the main body extension in the first horizontal direction; in the third signal line and the fourth signal line: the lead-out end is located at at least one end of the main body extension in the second horizontal direction; The orthographic projections of the main extension portion of the first signal line and the main extension portion of the second signal line on the substrate overlap; the orthographic projections of the lead-out end of the first signal line and the lead-out end of the second signal line on the substrate do not overlap; the orthographic projections of the main extension portion of the fourth signal line and the main extension portion of the third signal line on the substrate overlap; and the orthographic projections of the lead-out end of the fourth signal line and the lead-out end of the third signal line on the substrate do not overlap. In the first signal line, the second signal line, the third signal line, and the fourth signal line: the lead-out end has a first surface close to the substrate and a second surface away from the substrate; in the first signal line, the second signal line, the third signal line, and the fourth signal line: the direction in which the first surface points to the second surface or the direction in which the second surface points to the first surface is the lead-out direction; The functional layers are multiple in number and are stacked sequentially on the substrate along the vertical direction. In adjacent functional layers: When the direction from the second surface to the first surface is the lead-out direction, the extension length of the first signal line of the functional layer away from the substrate is greater than the extension length of the second signal line of the functional layer close to the substrate, and the length of the third signal line of the functional layer away from the substrate is greater than the length of the fourth signal line of the functional layer close to the substrate; or When the direction from the first surface to the second surface is the lead-out direction, the extension length of the first signal line of the functional layer away from the substrate is less than the extension length of the second signal line of the functional layer close to the substrate, and the length of the third signal line of the functional layer away from the substrate is less than the length of the fourth signal line of the functional layer close to the substrate.

2. The semiconductor device according to claim 1, characterized in that, When the direction from the second surface to the first surface is the lead-out direction, the extension length of the first signal line located in the same functional layer is less than the extension length of the second signal line. or When the direction from the first surface to the second surface is the lead-out direction, the extension length of the second signal line located in the same functional layer is less than the extension length of the first signal line.

3. The semiconductor device according to claim 1, characterized in that, When the direction from the second surface to the first surface is the lead-out direction, the extension length of the third signal line located in the same functional layer is less than the extension length of the fourth signal line. or When the direction from the first surface to the second surface is the lead-out direction, the extension length of the fourth signal line located in the same functional layer is less than the extension length of the third signal line.

4. The semiconductor device according to claim 1, characterized in that, It also includes a first lead-out structure, a second lead-out structure, a third lead-out structure and a fourth lead-out structure arranged at intervals between each other, wherein the first lead-out structure to the fourth lead-out structure all extend in the vertical direction and have different extension lengths; One end of the first lead-out structure is in contact with the lead-out end of the first signal line, and the other end extends along the lead-out direction and penetrates each insulating film layer; One end of the second lead-out structure is in contact with the lead-out end of the second signal line, and the other end extends along the lead-out direction and penetrates each insulating film layer; One end of the third lead-out structure is in contact with the lead-out end of the third signal line, and the other end extends along the lead-out direction and penetrates each insulating film layer; One end of the fourth lead-out structure is in contact with the lead-out end of the fourth signal line, and the other end extends along the lead-out direction and penetrates each insulating film layer; Each of the functional layers corresponds to the first lead-out structure, the second lead-out structure, the third lead-out structure, and the fourth lead-out structure.

5. The semiconductor device according to claim 4, characterized in that, When the direction from the second surface to the first surface is the lead-out direction, the lead-out structure and the first surface of the corresponding lead-out end are in contact; or When the direction from the first surface to the second surface is the lead-out direction, the lead-out structure and the second surface of the corresponding lead-out structure are in contact.

6. The semiconductor device according to claim 1, characterized in that, The functional layer also includes a first transistor and a second transistor stacked sequentially in a vertical direction, and both the first transistor and the second transistor include a gate region, a first connection region and a second connection region. Wherein, the first connection region of the first transistor is connected to the main body extension of the first signal line, the second connection region of the first transistor is connected to the main body extension of the third signal line, the first connection region of the second transistor is connected to the gate region of the first transistor, the second connection region of the second transistor is connected to the main body extension of the second signal line, and the gate region of the second transistor is connected to the main body extension of the fourth signal line.

7. The semiconductor device according to claim 6, characterized in that, In the functional layer: the fourth signal line is formed on the side of the second signal line away from the third signal line, and both the first transistor and the second transistor include: The channel portion includes a first connecting area, a second connecting area, and a channel area located between the first connecting area and the second connecting area, wherein the second connecting area is located on the side of the channel area away from the first connecting area; The gate portion is insulated from the channel portion by a gate insulating portion, and the gate portion and the channel portion are disposed opposite each other at least in the horizontal direction. The gate portion includes the gate region.

8. The semiconductor device according to claim 7, characterized in that, The first connection region of the first transistor is formed between its gate portion and the main body extension of the first signal line, and the channel region and the second connection region of the first transistor are both disposed around its gate portion. The first connection region of the second transistor is formed between its gate portion and the gate portion of the first transistor, and the channel region and the second connection region of the second transistor are both disposed around its gate portion.

9. The semiconductor device according to claim 8, characterized in that, The main body extension of the third signal line is arranged around the second connection region of the first transistor; The main body extension of the second signal line is disposed around the second connection region of the second transistor.

10. The semiconductor device according to claim 8, characterized in that, A conductive contact pad is formed between the first connection region of the second transistor and the gate portion of the first transistor; In this configuration, the orthographic projections of the gate portions of the first transistor and the second transistor onto the substrate overlap with the orthographic projections of the conductive contact pad onto the substrate.

11. A method for manufacturing a semiconductor device, characterized in that, The manufacturing method includes: Provide substrate; and At least one functional layer is formed on the substrate, wherein the step of forming the functional layer includes: A first signal line, a first insulating film layer, a third signal line, a second insulating film layer, a fourth signal line, a third insulating film layer, and a second signal line are sequentially stacked on the substrate. The third signal line is insulated from the fourth signal line through the second insulating film layer and from the first signal line through the first insulating film layer. The fourth signal line is insulated from the second signal line through the third insulating film layer. Alternatively, a first signal line, a first insulating film layer, a third signal line, a second insulating film layer, a second signal line, a third insulating film layer, and a fourth signal line are sequentially stacked on the substrate. The third signal line is insulated from the second signal line through the second insulating film layer and from the first signal line through the first insulating film layer. The second signal line is insulated from the fourth signal line through the third insulating film layer. The first signal line and the second signal line extend in a first horizontal direction, and the third signal line and the fourth signal line both extend in a second horizontal direction intersecting the first horizontal direction. Each of the first, second, third, and fourth signal lines has a main extension and a lead-out end. In the first and second signal lines, the lead-out end is located at at least one end of the main extension in the first horizontal direction; in the third and fourth signal lines, the lead-out end is located at at least one end of the main extension in the second horizontal direction. The main extensions of the first and second signal lines are located on the substrate. The orthographic projections of the first signal line and the second signal line on the substrate overlap, but their orthographic projections do not overlap. The orthographic projections of the main extension of the third signal line and the main extension of the fourth signal line on the substrate overlap, but their orthographic projections do not overlap. Among the first, second, third, and fourth signal lines: the lead-out end has a first surface close to the substrate and a second surface away from the substrate, and the direction from the first surface to the second surface or the direction from the second surface to the first surface is the lead-out direction. The steps for forming the first signal line, the second signal line, the third signal line, and the fourth signal line all include: A conductive material thin film, a sacrificial material thin film, and a photoresist mask pattern layer are sequentially formed on a substrate. The photoresist mask pattern layer includes multiple spaced photoresist mask strips. The sacrificial material film is patterned using the photoresist mask pattern layer to form a sacrificial pattern layer, which includes multiple spaced sacrificial mask strips that correspond one-to-one with the photoresist mask strips. After removing the photoresist mask pattern layer, an intermediate mask material film is formed covering each of the sacrificial mask strips; A trimmed mask layer is formed on the side of the intermediate mask material film away from the substrate, wherein at least one edge region of the sacrificial mask strip in its extension direction is not covered by the trimmed mask layer; The trimming mask layer is used to remove the portion of the intermediate mask material film that is not covered by the trimming mask layer; After removing the trimmed mask layer, the intermediate mask material film is patterned to form an intermediate mask pattern layer. The intermediate mask pattern layer consists of multiple inter-disconnected intermediate mask strips. Intermediate mask strips are formed on opposite sides of each of the sacrificial mask strips, and the intermediate mask strips formed on the sides of adjacent sacrificial mask strips that are close to each other are disconnected. The sacrificial pattern layer is removed, and the conductive material film is patterned using the intermediate mask pattern layer to form a conductive pattern layer. The conductive pattern layer includes multiple spaced signal lines, and the signal lines correspond one-to-one with the intermediate mask strips. Remove the intermediate mask pattern layer; The step of forming at least one functional layer on the substrate includes: Multiple functional layers are formed on the substrate in a sequentially stacked manner. In two adjacent functional layers: the functional layer farther from the substrate is defined as the upper functional layer, and the functional layer closer to the substrate is defined as the lower functional layer; wherein, When the first surface is the lead-out surface: the length of the trimming mask layer used in the step of forming the first signal line of the upper functional layer in the first horizontal direction is greater than the length of the trimming mask layer used in the step of forming the second signal line of the lower functional layer in the first horizontal direction, so that the extension length of the first signal line of the upper functional layer is greater than the extension length of the second signal line of the lower functional layer; the length of the trimming mask layer used in the step of forming the third signal line of the upper functional layer in the second horizontal direction is greater than the length of the trimming mask layer used in the step of forming the fourth signal line of the lower functional layer in the second horizontal direction, so that the extension length of the third signal line of the upper functional layer is greater than the extension length of the fourth signal line of the lower functional layer; or When the second surface is the lead-out surface: the length of the trimming mask layer used in the step of forming the first signal line of the upper functional layer in the first horizontal direction is less than the length of the trimming mask layer used in the step of forming the second signal line of the lower functional layer in the first horizontal direction, so that the extension length of the first signal line of the upper functional layer is less than the extension length of the second signal line of the lower functional layer; the length of the trimming mask layer used in the step of forming the third signal line of the upper functional layer in the second horizontal direction is less than the length of the trimming mask layer used in the step of forming the fourth signal line of the lower functional layer in the second horizontal direction, so that the extension length of the third signal line of the upper functional layer is less than the extension length of the fourth signal line of the lower functional layer.

12. The manufacturing method according to claim 11, characterized in that, The step of forming the first signal line, the second signal line, the third signal line, and the fourth signal line further includes: after forming the conductive material thin film on the substrate and before forming the sacrificial material thin film, forming a hard mask material thin film, wherein the hardness of the hard mask material thin film is greater than the hardness of the sacrificial material thin film; The step of patterning the conductive material thin film using the intermediate mask patterning layer to form a conductive pattern layer includes: The hard mask material film is patterned using the intermediate mask pattern layer to form a hard mask pattern layer, which includes multiple spaced hard mask strips that correspond one-to-one with the intermediate mask strips. Remove the intermediate mask strip and use the hard mask patterning layer to pattern the conductive material film to form a conductive patterning layer.

13. The manufacturing method according to claim 11, characterized in that, After forming the conductive pattern layer, the manufacturing method further includes: An insulating material film is formed, which covers each of the signal lines and fills the spaces between adjacent signal lines; The portion of the isolation material film that protrudes above the signal line is removed to form an isolation pattern layer. The surface of the isolation pattern layer away from the substrate is flush with the surface of the signal line away from the substrate, and the isolation pattern layer includes at least an isolation portion filled between adjacent signal lines.

14. The manufacturing method according to claim 11, characterized in that, The trimming mask layer used in the step of forming the first signal line has a first length in the first horizontal direction; the trimming mask layer used in the step of forming the second signal line has a second length in the first horizontal direction; the trimming mask layer used in the step of forming the third signal line has a third length in the second horizontal direction; and the trimming mask layer used in the step of forming the fourth signal line has a fourth length in the second horizontal direction; wherein, within the same functional layer: When the first surface is the lead-out surface, the second length is greater than the first length, so that the extension length of the second signal line is greater than the extension length of the first signal line; the fourth length is greater than the third length, so that the extension length of the fourth signal line is greater than the extension length of the third signal line; or When the second surface is the lead-out surface, the second length is less than the first length, so that the extension length of the second signal line is less than the extension length of the first signal line, and the fourth length is less than the third length, so that the extension length of the fourth signal line is less than the extension length of the third signal line.

15. The manufacturing method according to claim 11, characterized in that, After the step of forming at least one functional layer on the substrate, the manufacturing method further includes: A first lead-out structure, a second lead-out structure, a third lead-out structure, and a fourth lead-out structure are formed, extending vertically and spaced apart from each other. Each functional layer corresponds to the first lead-out structure, the second lead-out structure, the third lead-out structure, and the fourth lead-out structure. One end of the first lead-out structure is in contact with the lead-out end of the first signal line, and the other end extends along the lead-out direction and penetrates each insulating film layer; One end of the second lead-out structure is in contact with the lead-out end of the second signal line, and the other end extends along the lead-out direction and penetrates each insulating film layer; One end of the third lead-out structure is in contact with the lead-out end of the third signal line, and the other end extends along the lead-out direction and penetrates each insulating film layer; One end of the fourth lead-out structure is in contact with the lead-out end of the fourth signal line, and the other end extends along the lead-out direction and penetrates each insulating film layer.

16. The manufacturing method according to claim 11, characterized in that, The fourth signal line is formed on the side of the second signal line away from the substrate; The step of forming the functional layer after forming the second insulating film layer and before forming the second signal line further includes: A first through-hole is formed that sequentially penetrates the second insulating film layer, the main extension portion of the third signal line, and the first insulating film layer, with the first through-hole exposing the surface of the main extension portion of the first signal line away from the substrate. A first transistor is formed in the first through hole, a first connection area of ​​the first transistor is in contact with the main body extension of the first signal line, and a second connection area of ​​the first transistor is in contact with the main body extension of the third signal line. An interlayer insulating film layer is formed, which covers the first transistor and the second insulating film layer and is located on the side of the second signal line closer to the substrate; The step of forming the functional layer after forming the third insulating film layer and before forming the fourth signal line further includes: A second via is formed that sequentially penetrates the third insulating film layer, the second signal line, and the interlayer insulating film layer, and the orthographic projection of the second via overlaps with that of the first via on the substrate. A second transistor is formed in the second via, the first connection region of the second transistor is connected to the gate region of the first transistor, the second connection region of the second transistor is in contact with the main body extension of the second signal line, and the main body extension of the subsequently formed fourth signal line is in contact with the gate region of the second transistor. The step of forming the functional layer after forming the fourth signal line further includes: A fourth insulating film layer is formed to cover the fourth signal line.

17. The manufacturing method according to claim 16, characterized in that, The steps of forming the first through hole and the second through hole can both include: A sacrificial material film is formed on the side of the stacked structure away from the substrate. The stacked structure includes a bottom insulating film layer, an intermediate signal line and a top insulating film layer sequentially stacked on the substrate. A photoresist mask pattern layer is formed on the side of the sacrificial material film away from the substrate, the photoresist mask pattern layer including a plurality of photolithographic vias arranged in an array in a first horizontal direction and a second horizontal direction; The sacrificial material thin film is patterned using the photoresist mask pattern layer to form a sacrificial pattern layer. The sacrificial pattern layer includes a plurality of spaced sacrificial vias, each of which corresponds to a photolithographic via, and the sacrificial vias expose the surface of the top insulating film layer away from the substrate. After removing the photoresist mask pattern, an insulating material film is formed. The insulating material film covers the surface of the sacrificial pattern layer away from the substrate and fills the sacrificial vias. The portion of the insulating material film located within the sacrificial vias is a blind trench structure. Remove the portion of the insulating material film that protrudes above the sacrificial pattern layer and the bottom wall of the blind trench structure, while retaining the sidewalls of the blind trench structure, to form a target etched hole. The diameter of the target etched hole is smaller than the diameter of the sacrificial through-hole. The stacked structure is patterned using the target etched holes to form through-holes that penetrate the stacked structure; Remove the sacrificial pattern layer and the sidewalls of the blind slot structure from the stacked structure; In the step of forming the first through-hole, the bottom insulating film layer is the first insulating film layer, the intermediate signal line is the third signal line, and the top insulating film layer is the second insulating film layer; in the step of forming the second through-hole, the bottom insulating film layer is the interlayer insulating film layer, the intermediate signal line is the second or fourth signal line, and the top insulating film layer is the third insulating film layer.

18. The manufacturing method according to claim 16, characterized in that, The steps for forming the first transistor and the second transistor both include: A channel film is formed, which covers the surface of the stacked structure away from the substrate and fills the vias of the stacked structure; The channel film is patterned to form a channel portion located within the through hole. The channel portion is groove-shaped, and the surface of the groove sidewall away from the substrate in the channel portion is lower than the surface of the stacked structure away from the substrate. The channel portion includes a first connection region, a second connection region, and a channel region located between the first connection region and the second connection region. The second connection region is located on the side of the channel region away from the first connection region. A gate insulating film and a gate film are sequentially formed. The gate insulating film and the gate film cover the surface of the stacked structure away from the substrate, the surface of the trench sidewall of the channel portion away from the substrate, and fill the trench of the channel portion. The portion of the gate insulating film located in the via is the gate insulating portion. A portion of the gate insulating portion is located in the trench of the channel portion and a portion covers the surface of the trench sidewall of the channel portion away from the substrate. The portion of the gate insulating portion located in the trench of the channel portion is groove-shaped. The portion of the gate film located in the trench of the gate insulating portion is the gate portion. The gate portion includes the gate region, and the trench of the gate insulating portion is filled by the gate portion. The portions of the gate insulating film and the gate film that protrude above the stacked structure are removed, so that the surfaces of the stacked structure, the gate insulating portion, and the gate portion away from the substrate are exposed and flush with each other, in order to form a transistor located in the via; In the step of forming the first transistor, the stacked structure includes a first insulating film layer, a third signal line, and a second insulating film layer stacked sequentially, and the via is a first via; in the step of forming the second transistor, the stacked structure includes an interlayer insulating film layer, a second signal line, and a third insulating film layer stacked sequentially, and the via is a second via.

19. The manufacturing method according to claim 16, characterized in that, After forming the first transistor and before forming the interlayer insulating film layer, the manufacturing method further includes: A conductive contact pad is formed, wherein the side of the conductive contact pad closest to the substrate contacts the gate region of the first transistor, and the side of the conductive contact pad furthest from the substrate contacts the first connection region of the second transistor.

20. The manufacturing method according to claim 19, characterized in that, The step of forming the conductive contact pad includes: A conductive material film and a sacrificial material film are formed sequentially, the conductive material film and the sacrificial material film covering the second insulating film layer and the first transistor; A photoresist mask pattern layer is formed on the side of the sacrificial material film away from the conductive material film. The photoresist mask pattern layer includes a plurality of photolithographic vias arranged in a first horizontal direction and a second horizontal direction. Each photolithographic via corresponds to one of the first transistors. The sacrificial material film is patterned using the photoresist mask pattern layer to form a sacrificial pattern layer. The sacrificial pattern layer includes a plurality of spaced sacrificial vias, each of which corresponds to a photolithographic via, and the sacrificial vias are exposed on the surface of the conductive material film away from the substrate. After removing the photoresist mask pattern layer, an intermediate mask material film is formed, which covers the surface of the sacrificial pattern layer away from the substrate and fills the sacrificial vias. The portion of the intermediate mask material film that protrudes above the sacrificial pattern layer is removed to form an intermediate mask pattern layer. The intermediate mask pattern layer includes a plurality of spaced intermediate mask blocks located within the sacrificial vias. The surface of the intermediate mask blocks away from the substrate is flush with the surface of the sacrificial pattern layer away from the substrate. Remove the sacrificial pattern layer and retain the intermediate mask block; The conductive material film is patterned using the intermediate mask block to form multiple spaced conductive contact pads, each of which corresponds to one of the first transistors.

Images