Semiconductor device structure and forming method thereof

Abstract

Semiconductor device structures and methods of forming the same are described. The structure includes a gate dielectric layer disposed over a substrate; a gate electrode layer disposed over the gate dielectric layer; and a first gate spacer disposed adjacent to the gate dielectric layer, where the first gate spacer includes an inner surface facing the gate dielectric layer and an outer surface opposite the inner surface, and the first gate spacer includes an oxygen concentration that decreases from the inner surface toward the outer surface of the first gate spacer.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor device structures and methods for forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced multiple generations of ICs, each with smaller and more complex circuits than the previous generation. In the course of IC development, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This shrinking process generally provides benefits by increasing production efficiency and reducing associated costs. Such shrinking has also increased the complexity of processing and manufacturing ICs.

[0003] Therefore, there is a need for improvements in the processing and manufacturing of ICs. Summary of the invention

[0004] Some embodiments of the present application provide a semiconductor device structure, including: a gate dielectric layer, disposed above a substrate; a gate electrode layer, disposed above the gate dielectric layer; and a first gate spacer, disposed adjacent to the gate dielectric layer, wherein the first gate spacer includes an inner surface facing the gate dielectric layer and an outer surface opposite to the inner surface, and the first gate spacer includes an oxygen concentration that decreases from the inner surface toward the outer surface of the first gate spacer.

[0005] Other embodiments of the present application provide a method for forming a semiconductor device structure, comprising: forming a sacrificial gate structure and a gate spacer above a portion of a fin structure formed above a substrate, the fin structure comprising a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked; removing a portion of the fin structure to expose a portion of the substrate; removing a portion of each of the second semiconductor layers and replacing it with a dielectric spacer; forming a source / drain region on opposite sides of the sacrificial gate structure; removing the sacrificial gate structure and the second semiconductor layer to expose the gate spacer and the dielectric spacer; subjecting the gate spacer and the dielectric spacer to an oxidation treatment to oxidize a portion of the gate spacer; and forming a gate dielectric layer and a gate electrode layer above the oxidized gate spacer.

[0006] Still other embodiments of the present application provide a method for forming a semiconductor device structure, comprising: forming a sacrificial gate structure above a fin structure comprising a first plurality of semiconductor layers and a second plurality of semiconductor layers; depositing a gate spacer structure on the sacrificial gate structure; removing a portion of the fin structure to expose a portion of the substrate; recessing the second plurality of semiconductor layers to form a cavity; forming a dielectric spacer in the cavity; forming a source / drain region from the portion of the substrate; removing the sacrificial gate structure and the second plurality of semiconductor layers; forming an interface layer on a portion of each of the first plurality of semiconductor layers; and doping fluorine into the gate spacer and the dielectric spacer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0008] Figures 1 to 5 is a perspective view of various stages in the fabrication of a semiconductor device structure according to some embodiments.

[0009] Figures 6 to 9 According to some embodiments, Figure 5 Cross-sectional side views of various stages in the manufacture of a semiconductor device structure taken along line AA.

[0010] Fig.10 According to some embodiments Fig. 9 A three-dimensional diagram of a semiconductor device structure.

[0011] Figures 11 to 28 According to some embodiments, Figure 5 Cross-sectional side views of various stages in the manufacture of a semiconductor device structure taken along line AA.

[0012] Figure 16-1 , Figure 16-2 , Figure 16-3 , Figure 17-1 , Figure 17-2 , Figure 27-1 and Figure 27-2 is an enlarged view of a portion of a semiconductor device structure showing oxidation profiles according to some embodiments.

[0013] Fig.29 According to some embodiments Fig.28 Part of a semiconductor device structure. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0015] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "above," "on," "top," "upper," and the like may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0016] Although embodiments of the present disclosure are discussed with respect to nanostructured channel FETs, such as full-all-around gate (GAA) FETs, for example, horizontal full-all-around gate (HGAA) FETs or vertical full-all-around gate (VGAA) FETs, implementations of some aspects of the present disclosure embodiments may be used in other processes and / or other devices, such as planar FETs, fin FETs, and other suitable devices. It will be readily understood by those of ordinary skill in the art that other modifications that may be made are contemplated within the scope of the present disclosure embodiments. In instances where a full-gate (GAA) transistor structure is employed, the GAA transistor structure may be patterned by any suitable method. For example, the structure may be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Typically, double patterning or multiple patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns having, for example, a spacing that is less than that obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and then, the remaining spacers may be used to pattern the GAA structure.

[0017] Figures 1 to 29 FIG. 1 shows an exemplary process for manufacturing a semiconductor device structure 100 according to an embodiment of the present disclosure. It should be understood that Figures 1 to 29Additional operations are provided before, during, and after the processes shown, and some of the operations described below may be replaced or eliminated for additional embodiments of the method. The order of the operations / processes is not limiting and may be interchanged.

[0018] Figures 1 to 5 1 is a perspective view of various stages of manufacturing a semiconductor device structure 100 according to some embodiments. Figure 1 As shown in , the semiconductor device structure 100 includes a semiconductor layer stack 104 formed above the front side of a substrate 101. The substrate 101 may be a semiconductor substrate. The substrate 101 may include a crystalline semiconductor material, such as but not limited to silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium arsenic antimonide (GaAsSb) and indium phosphide (InP). In some embodiments, the substrate 101 is a silicon on insulator (SOI) substrate having an insulating layer (not shown) disposed between two silicon layers for enhancement. In one aspect, the insulating layer is an oxygen-containing layer.

[0019] The substrate 101 may include various regions that have been doped with impurities (e.g., dopants having p-type or n-type conductivity). Depending on the circuit design, the dopant may be, for example, phosphorus for n-type field effect transistors (NFETs) and boron for p-type field effect transistors (PFETs).

[0020] The semiconductor layer stack 104 includes alternating semiconductor layers made of different materials to facilitate the formation of nanostructured channels in multi-gate devices, such as nanostructured channel FETs. In some embodiments, the semiconductor layer stack 104 includes a first semiconductor layer 106 and a second semiconductor layer 108. In some embodiments, the semiconductor layer stack 104 includes alternating first semiconductor layers 106 and second semiconductor layers 108. The first semiconductor layer 106 and the second semiconductor layer 108 are made of semiconductor materials having different etching selectivities and / or oxidation rates. For example, the first semiconductor layer 106 may be made of Si, and the second semiconductor layer 108 may be made of SiGe. In some instances, the first semiconductor layer 106 may be made of SiGe, and the second semiconductor layer 108 may be made of Si. Alternatively, in some embodiments, any one of the semiconductor layers 106, 108 may be or include other materials, such as Ge, SiC, GeAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, or any combination thereof.

[0021] The first semiconductor layer 106 and the second semiconductor layer 108 are formed by any suitable deposition process, such as epitaxy. For example, the epitaxial growth of the layers of the semiconductor stack 104 can be performed by a molecular beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes.

[0022] The first semiconductor layer 106 or a portion thereof may form a nanostructure channel of the semiconductor device structure 100 in a later manufacturing stage. The term nanostructure is used herein to refer to any material portion having nanometer-scale or even micrometer-scale dimensions and having an elongated shape, regardless of the cross-sectional shape of the portion. Therefore, the term refers to an elongated material portion of a circular and substantially circular cross section and a beam-shaped or strip-shaped material portion including, for example, a cylindrical or substantially rectangular cross section. The nanostructure channel of the semiconductor device structure 100 may be surrounded by a gate electrode. The semiconductor device structure 100 may include a nanostructure transistor. The nanostructure transistor may be referred to as a nanosheet transistor, a nanowire transistor, a full-ring gate (GAA) transistor, a multi-bridge channel (MBC) transistor, or any transistor having a gate electrode surrounding a channel. The use of the first semiconductor layer 106 to define one or more channels of the semiconductor device structure 100 is further discussed below.

[0023] Each first semiconductor layer 106 may have a thickness in a range between about 5 nm and about 30 nm. Each second semiconductor layer 108 may have a thickness equal to, less than, or greater than the thickness of the first semiconductor layer 106. In some embodiments, each second semiconductor layer 108 has a thickness in a range between about 2 nm and about 50 nm. The three first semiconductor layers 106 and the three second semiconductor layers 108 are alternately arranged, such as Figure 1 , which is for illustrative purposes and is not intended to be limiting beyond what is specifically recited in the claims. It is understood that any number of first semiconductor layers 106 and second semiconductor layers 108 may be formed in the semiconductor layer stack 104, and the number of layers depends on the predetermined number of channels for the semiconductor device structure 100.

[0024] like Figure 2As shown in , the fin structure 112 is formed by the semiconductor layer stack 104. Each fin structure 112 has an upper portion including semiconductor layers 106, 108 and a well portion 116 formed by the substrate 101. The fin structure 112 can be formed by patterning a hard mask layer (not shown) formed on the semiconductor layer stack 104 using a multiple patterning operation including a lithography and etching process. The etching process may include dry etching, wet etching, reactive ion etching (RIE) and / or other suitable processes. The lithography process may include: forming a photoresist layer (not shown) above the hard mask layer; exposing the photoresist layer to a pattern; performing a post-exposure baking process; and developing the photoresist layer to form a masking element including the photoresist layer. In some embodiments, patterning the photoresist layer to form a masking element can be implemented using an electron beam (e-beam) lithography process. The etching process forms a trench 114 through the hard mask layer, through the semiconductor layer stack 104 and into the substrate 101 in the unprotected area, thereby leaving a plurality of extended fin structures 112. The trench 114 extends along the X direction. The trench 114 may be etched using dry etching (eg, RIE), wet etching, and / or a combination thereof.

[0025] like Figure 3 As shown in , after forming the fin structure 112, an insulating material 118 is formed on the substrate 101. The insulating material 118 fills the trenches 114 between adjacent fin structures 112 until the fin structure 112 is embedded in the insulating material 118. Then, a planarization operation, such as a chemical mechanical polishing (CMP) method and / or an etch-back method, is performed to expose the top of the fin structure 112. The insulating material 118 can be made of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), low-K dielectric material, or any suitable dielectric material. The insulating material 118 can be formed by any suitable method, such as low pressure chemical vapor deposition (LPCVD), plasma enhanced CVD (PECVD), or flowable CVD (FCVD).

[0026] like Figure 4 As shown in , the insulating material 118 is recessed to form the isolation region 120. Recessing the insulating material 118 exposes a portion of the fin structure 112, such as the semiconductor layer stack 104. Recessing the insulating material 118 exposes the trench 114 between adjacent fin structures 112. The isolation region 120 can be formed using a suitable process, such as a dry etching process, a wet etching process, or a combination thereof. The top surface of the insulating material 118 can be flush with or below the surface of the second semiconductor layer 108 that contacts the well portion 116 formed by the substrate 101.

[0027] like Figure 5As shown in , one or more sacrificial gate structures 130 (only one is shown) are formed over the semiconductor device structure 100. The sacrificial gate structure 130 is formed over a portion of the fin structure 112. Each sacrificial gate structure 130 may include a sacrificial gate dielectric layer 132, a sacrificial gate electrode layer 134, and a mask layer 136. The sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136 may be formed by sequentially depositing blanket layers of the sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136, and then patterning those layers into the sacrificial gate structure 130. Although one sacrificial gate structure 130 is shown, in some embodiments, two or more sacrificial gate structures 130 may be arranged along the X direction.

[0028] The sacrificial gate dielectric layer 132 may include one or more dielectric material layers, such as a silicon oxide-based material. The sacrificial gate electrode layer 134 may include silicon, such as polysilicon or amorphous silicon. The mask layer 136 may include more than one layer, such as an oxide layer and a nitride layer. The portion of the fin structure 112 covered by the sacrificial gate electrode layer 134 of the sacrificial gate structure 130 serves as a channel region for the semiconductor device structure 100.

[0029] Figures 6 to 9 According to some embodiments, Figure 5 The cross-sectional side views of various stages of manufacturing the semiconductor device structure 100 are taken along the line AA. Figure 6 As shown in , a first gate spacer 138 is deposited on the exposed surface of the semiconductor device structure 100. For example, the first gate spacer 138 is deposited on the fin structure 112, the isolation region 120, and the sacrificial gate structure 130. The first gate spacer 138 can be made of a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiCON, and / or a combination thereof. In one embodiment, the first gate spacer 138 is SiCN or SiOC. The first gate spacer 138 can be formed by any suitable process. In some embodiments, the first gate spacer 138 is a conformal layer formed by a conformal process, such as an atomic layer deposition (ALD) process.

[0030] like Figure 7 As shown in FIG. 1 , a second gate spacer 139 is deposited on the first gate spacer 138. The second gate spacer 139 may include any suitable dielectric material, such as SiO x, SiON, SiN, SiCON or SiCO. The first gate spacer 138 and the second gate spacer 139 may include the same material. In some embodiments, the first gate spacer 138 and the second gate spacer 139 may include materials that are chemically different from each other. For example, the first gate spacer 138 may be SiCN or SiOC, and the second gate spacer 139 may be SiCON. The second gate spacer 139 may have a thickness in the range from about 0.5nm to about 5nm. The second gate spacer 139 may be formed by any suitable process. In some embodiments, the second gate spacer 139 is deposited by CVD, PECVD or electron cyclotron resonance CVD (ECR-CVD). The plasma source may be an inductively coupled plasma source or a capacitively coupled plasma source. The plasma power may be in the range from about 100W to about 500W, and the processing temperature may be in the range from about 100 degrees Celsius to about 600 degrees Celsius. In some embodiments, a layer is deposited, and a processing process is performed to form the second gate spacer 139. For example, a layer such as an amorphous silicon layer, a silicon carbide layer, a SiCN layer, or a SiCON layer is first deposited on the first gate spacer 138, and then the layer is exposed to a processing gas to form the second gate spacer 139. The processing gas may be an oxygen-containing gas, a nitrogen-containing gas, or a combination thereof. In some embodiments, the processing gas includes N2O, NH3, O2, or a combination of N2 and O2.

[0031] like Figure 8 , horizontal portions of the first gate spacer 138 and the second gate spacer 139 are removed. In some embodiments, the horizontal portions of the first gate spacer 138 and the second gate spacer 139 are removed by an anisotropic etching process. The anisotropic etching process may be a selective etching process that does not substantially affect the mask layer 136, the semiconductor layer stack 104, and the isolation region 120. The first gate spacer 138 and the second gate spacer 139 may have a combined thickness T1 in the range of about 4 nm to about 10 nm. The thickness range applies to a single gate spacer (i.e., the first gate spacer 138 and the second gate spacer 139 are formed of the same material).

[0032] like Fig. 9 As shown in , the portion of the fin structure 112 not covered by the sacrificial gate structure 130 and the first gate spacer 138 and the second gate spacer 139 is recessed to a level above, at, or below the top surface of the isolation region 120. Recessing the portion of the fin structure 112 can be accomplished by an etching process. The etching process can be a dry etch (such as RIE, NBE, etc.) or a wet etch, such as using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or any suitable etchant.

[0033] Fig.10 According to some embodiments Fig. 9 A three-dimensional view of a semiconductor device structure 100 is shown. Figures 11 to 20 According to some embodiments, Fig.10 A cross-sectional side view of various stages of manufacturing a semiconductor device structure taken along line AA. Fig.11 As shown in , edge portions of each second semiconductor layer 108 of the semiconductor stack 104 are horizontally removed along the X direction. The removal of the edge portions of the second semiconductor layer 108 forms a cavity. In some embodiments, portions of the second semiconductor layer 108 are removed by a selective wet etching process. In an example where the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of silicon, the second semiconductor layer 108 can be selectively etched using a wet etchant, such as, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine catechol (EDP), or potassium hydroxide (KOH) solution.

[0034] After removing the edge portion of each second semiconductor layer 108, a dielectric layer is deposited in the cavity to form a dielectric spacer 144. The dielectric spacer 144 may be made of a low-K dielectric material, such as SiON, SiCN, SiOC, SiOCN, or SiN. In one embodiment, the dielectric spacer 144 includes SiONC. The dielectric spacer 144 may be formed by first forming a conformal dielectric layer using a conformal deposition process (such as ALD) and then anisotropic etching to remove portions of the conformal dielectric layer except the dielectric spacer 144. During the anisotropic etching process, the dielectric spacer 144 is protected by the first semiconductor layer 106. The remaining second semiconductor layer 108 is covered between the dielectric spacers 144 along the X direction. The dielectric spacer 144 may have a thickness T2 in the range of about 4 nm to about 10 nm. In some embodiments, the thickness T2 of the dielectric spacer 144 and the combined thickness T1 of the first gate spacer 138 and the second gate spacer 139 may be different from each other.

[0035] like Fig.12As shown in , a source / drain (S / D) region 146 is formed from the well portion 116. The S / D region 146 can grow vertically and horizontally to form a facet, which can correspond to a crystal plane of the material used for the well portion 116. In the disclosed embodiments, the source region and the drain region are used interchangeably, and their structures are substantially the same. In addition, the source / drain region can refer to the source or drain, individually or together depending on the context. The S / D region 146 can be made of one or more layers of Si, SiP, SiC and SiCP for n-channel FETs or Si, SiGe, Ge for p-channel FETs. For p-channel FETs, p-type dopants such as boron (B) can also be included in the S / D region 146. The S / D region 146 can be formed by an epitaxial growth method using CVD, ALD or MBE.

[0036] like Fig.13 As shown in , a contact etch stop layer (CESL) 162 is conformally formed on the exposed surface of the semiconductor device structure 100. The CESL 162 covers the second gate spacer 139, the isolation region 120, and the S / D region 146. The CESL 162 may include an oxygen-containing material or a nitrogen-containing material, such as silicon nitride, silicon carbonitride, silicon oxynitride, carbon nitride, silicon oxide, silicon oxycarbide, etc., or a combination thereof, and may be formed by CVD, PECVD, ALD, or any suitable deposition technique. In some embodiments, the CESL 162 is a single layer, such as Fig.13 . In some embodiments, CESL 162 includes two or more layers. Next, an interlayer dielectric (ILD) layer 164 is formed on CESL 162. The material used for ILD layer 164 may include a compound including Si, O, C and / or H, such as silicon oxide, SiCOH or SiOC. Organic materials such as polymers may also be used for ILD layer 164. ILD layer 164 may be deposited by a PECVD process or other suitable deposition techniques. In some embodiments, after forming ILD layer 164, semiconductor device structure 100 may be subjected to a thermal process to anneal ILD layer 164.

[0037] After forming the ILD layer 164, a planarization operation, such as CMP, is performed on the semiconductor device structure 100 until the sacrificial gate electrode layer 134 is exposed. Fig.13 as shown in .

[0038] like Fig.14As shown in , the sacrificial gate structure 130 and the second semiconductor layer 108 are removed. Removing the sacrificial gate structure 130 and the semiconductor layer 108 forms an opening between the first gate spacers 138 and an opening between the first semiconductor layer 106. The ILD layer 164 protects the S / D region 146 during the removal process. The sacrificial gate structure 130 can be removed using plasma dry etching and / or wet etching. First, the sacrificial gate electrode layer 134 can be removed by any suitable process, such as dry etching, wet etching, or a combination thereof, followed by removing the sacrificial gate dielectric layer 132, which can also be implemented by any suitable process, such as dry etching, wet etching, or a combination thereof. In some embodiments, a wet etchant such as tetramethylammonium hydroxide (TMAH) solution can be used to selectively remove the sacrificial gate electrode layer 134, but the first gate spacers 138, the ILD layer 164, and the CESL 162 are not removed.

[0039] The second semiconductor layer 108 can be removed using dry etching, wet etching, or a combination thereof. In an example where the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of Si, the chemistry used in the selective wet etching process removes SiGe while substantially not affecting Si, the dielectric material of the first gate spacer 138, and the dielectric spacer 144. In one embodiment, the second semiconductor layer 108 can be removed using a wet etchant such as, but not limited to, hydrofluoric acid (HF), nitric acid (HNO3), hydrochloric acid (HCl), or phosphoric acid (H3PO4).

[0040] like Fig.15 As shown in , an interfacial layer (IL) 178 is formed to surround the exposed surface of the first semiconductor layer 106. IL 178 may include or be made of an oxygen-containing material or a silicon-containing material, such as silicon oxide, silicon oxynitride, oxynitride, hafnium silicate, etc. In one embodiment, IL 178 is silicon oxide. IL 178 may be formed by CVD, ALD, a cleaning process, or any suitable process. IL 178 may have a thickness of about 0.5 nm to about 1.5 nm.

[0041] like Fig.16As shown in , the first gate spacer 138 and the portion of the dielectric spacer 144 are oxidized by the oxidation process 147. The oxidation process 147 can be any suitable oxidation process capable of driving oxygen atoms or oxygen radicals of a substance into the first gate spacer 138 and the dielectric spacer 144 and converting the first gate spacer 138 and the portion of the dielectric spacer 144 into an oxidized first gate spacer 138' and an oxidized dielectric spacer 144', respectively. For example, the oxidation process can use a reactive substance generated in situ by an oxygen-containing gas (e.g., O2, H2O, NO, etc.) in the reaction chamber or upstream of the reaction chamber (e.g., from a remote plasma generator). Exemplary reactive substances may include oxygen plasma or neutral radical substances of oxygen, such as oxygen radicals or atomic oxygen. In some embodiments, the first gate spacer 138 and the dielectric spacer 144 may be further exposed to H2, N2, NH3, etc., which may be used as a dilution gas and / or to assist the oxidation process. Other suitable oxidation processes, such as dry thermal oxidation processes or wet oxidation processes, may also be used. In some exemplary embodiments employing a wet oxidation process, the first gate spacer 138 and the dielectric spacer 144 may be exposed to water vapor or steam as an oxidant at a pressure of about 1 Torr to about 40 ATM, in a temperature range of about 200 degrees Celsius to about 900 degrees Celsius, such as about 400 degrees Celsius to about 600 degrees Celsius, and for a time period of about 1 minute to about 2 hours.

[0042] The temperature of the oxidation process 147 may cause oxygen atoms or radicals to diffuse laterally and vertically in the first gate spacers 138 and the dielectric spacers 144 . Figure 16-1 and Figure 16-2 1 is an enlarged view of a portion of the semiconductor device structure 100 showing oxidation profiles corresponding to the oxidized first gate spacer 138' and the oxidized dielectric spacer 144', respectively. In an embodiment where the first gate spacer 138 is formed of SiCN, the nitrogen (N) or carbon (C) concentration gradually decreases from the outer surface 138o' to the inner surface 138i' of the oxidized first gate spacer 138', while the oxygen (O) concentration gradually increases from the inner surface 138i' to the outer surface 138o' of the oxidized first gate spacer 138', as shown in FIG. Figure 16-1 In some embodiments, the oxidized first gate spacer 138' has a first oxygen concentration, and the first gate spacer 138 disposed between the oxidized first gate spacer 138' and the second gate spacer 139 has a second oxygen concentration lower than the first oxygen concentration.

[0043] Likewise, in the embodiment where the dielectric spacer 144 is formed of SiCN or SiOCN, the nitrogen (N) or carbon (C) concentration gradually decreases from the outer surface 144o' to the inner surface 144i' of the oxidized dielectric spacer 144', while the oxygen (O) concentration gradually increases from the inner surface 144i' to the outer surface 144o' of the oxidized dielectric spacer 144', as shown in FIG. Figure 16-2 In some embodiments, the oxidized dielectric spacer 144' has a first oxygen concentration, and the dielectric spacer 144 disposed between the oxidized dielectric spacer 144' and the dielectric spacer 144 has a second oxygen concentration lower than the first oxygen concentration.

[0044] In some embodiments, the oxidized dielectric spacers 144 ′ have a first oxygen concentration, and the oxidized first gate spacers 138 ′ have a second oxygen concentration greater than the first oxygen concentration.

[0045] In various embodiments, after the oxidation process 147, the oxidized first gate spacer 138' and the dielectric spacer 144' may have about 10 at.% or less nitrogen, about 20 at.% or less carbon, and about 35 at.% or more oxygen. In some embodiments, after the oxidation process 147, the oxidized first gate spacer 138' may have an oxygen atomic percentage increased from 15-20 at.% to about 35-65 at.%. In some embodiments, the atomic percentages of carbon, nitrogen, and oxygen in the oxidized first gate spacer 138' may be different from the atomic percentages of carbon, nitrogen, and oxygen in the oxidized dielectric spacer 144'. A high concentration of oxygen and a low concentration of carbon and / or nitrogen will produce a lower K value (e.g., 4.5 or less) for the oxidized first gate spacer 138' and the dielectric spacer 144'. Therefore, parasitic capacitance is reduced and overall device performance is improved.

[0046] In some embodiments, after the oxidation process 147, the first gate spacers 138 and the oxidized portions of the dielectric spacers 144 may include substantially the same material as the IL 178. In some embodiments, after the oxidation process 147, the IL 178 is further oxidized, and the IL 178, the oxidized first gate spacers 138', and the oxidized dielectric spacers 144' include substantially the same material.

[0047] In some optional embodiments, the oxidation process 147 is performed to completely oxidize the first gate spacer 138. In some embodiments, the oxidation process 147 is performed so that oxygen atoms or radicals further diffuse into the second gate spacer 139, converting part or the entire second gate spacer 139 into an oxidized second gate spacer 139'. In such an example, the entire first gate spacer 138 is oxidized, and the oxidized second gate spacer 139' may follow the same oxidation profile as the oxidized first gate spacer 138'. In some embodiments, the deposited first gate spacer 138 includes SiCN, and the oxidized first gate spacer 138' includes SiO2 after the oxidation process 147. In an example where the second gate spacer 139 is formed of SiCON, the nitrogen (N) or carbon (C) concentration gradually decreases from the outer surface 139o' to the inner surface 139i' of the oxidized second gate spacer 139, while the oxygen (O) concentration gradually increases from the inner surface 139i' to the outer surface 139o' of the oxidized second gate spacer 139'. Figure 16-3 is an enlarged view of a portion of the semiconductor device structure 100 showing an oxidation profile corresponding to the profile of the oxidized first gate spacer 138' and the second gate spacer 139'. In some embodiments, the oxidized first gate spacer 138' may have an oxygen atomic percentage increasing from 15-20 at.% to about 35-65 at.%, and the oxidized second gate spacer 139' may have an oxygen atomic percentage increasing from 5 at.% or less to about 20-65 at.%.

[0048] In some embodiments, the oxidized dielectric spacer 144' has a first oxygen concentration and the oxidized second gate spacer 139' has a second oxygen concentration greater than the first oxygen concentration. In some embodiments, the oxidized first gate spacer 138' has a third oxygen concentration greater than the first and second oxygen concentrations.

[0049] In some alternative embodiments, a single layer is used for the gate spacers (ie, the first gate spacers 138 and the second gate spacers 139 include the same material), and the gate spacers and the dielectric spacers 144 may be partially or fully oxidized after the oxidation process 147 . Fig.17 (Alternative Embodiment 1) shows an embodiment in which the gate spacer 137 and the dielectric spacer 145 are completely oxidized after the oxidation process 147. Figure 17-1 and Figure 17-21 is an enlarged view of a portion of the semiconductor device structure 100 showing a fully oxidized gate spacer 137 and dielectric spacer 145 according to some embodiments. In some embodiments, the deposited gate spacer and dielectric spacer include SiCN or SiCON, and the oxidized gate spacer 137 and dielectric spacer 145 after the oxidation process 147 include SiO2, showing the chemical bond conversion from Si-C-Si and Si-N-Si to Si-O-Si. In some embodiments, after the oxidation process 147, the gate spacer 137, the dielectric spacer 145, and the IL 178 include substantially the same material (e.g., silicon oxide). In such an example, the composition percentage of the silicon oxide can be at a ratio of about 1:2 [Si]:[O]. Although the gate spacer 137 and the dielectric spacer 145 are fully or substantially oxidized, in some examples, traceable amounts of nitrogen and carbon can still be detected in the gate spacer 137 and / or the dielectric spacer 145. For example, the gate spacer 137 may have a nitrogen atomic percentage of about 1 at.% or less and a carbon atomic percentage of about 3 at.% or less. Likewise, the dielectric spacer 145 may have a nitrogen atomic percentage of about 1 at.% or less and a carbon atomic percentage of about 3 at.% or less.

[0050] In some optional embodiments, after forming the IL 178, the semiconductor device structure 100 is subjected to an ion implantation process 149. In particular, the ion implantation process 149 is performed so that most of the ion species (dopants) are implanted into the first gate spacer 138, the IL 178, and the dielectric spacer 144. The implanted regions of the first gate spacer 138, the IL 178, and the dielectric spacer 144 are then oxidized. Fig.19 ) to form a dielectric region or an oxidized region. The ion implantation process 149 changes the material properties of the first gate spacer 138, IL 178, and dielectric spacer 144 so that the implanted region can be oxidized at a faster rate. For example, the implanted dopant can be selected to increase the oxidation rate of the implanted region by converting the implanted region into an amorphous state. Additionally or alternatively, the implanted dopant can be selected to reduce the temperature of the subsequent oxidation process, which in turn increases the reaction rate of the oxidation process. Additionally or alternatively, the implanted dopant can be selected to promote oxidation of the implanted region while preventing loss of the dielectric region during a subsequent gate replacement process.

[0051] The ion implantation process 149 may employ one or more ion species. In some embodiments, the ion implantation process 149 employs a first ion species group ("Group 1") including fluorine (F) or atoms having an atomic radius of about 0.5 times to about 1.5 times the atomic radius of silicon, a second ion species group ("Group 2") including an inert gas such as neon (Ne), argon (Ar), krypton (Kr), xenon (Xe), or any combination thereof, and a third ion species group ("Group 3") including oxygen (O). When the F ion species is implanted, the first ion species group (e.g., F) may be employed to promote the growth of oxide on the first gate spacer 138, the IL 178, and the dielectric spacer 144. The second ion species group (e.g., Ar) may be employed to reduce the activation energy of oxygen and promote chemical reactions between the implanted ions and the first gate spacer 138, the IL 178, and the dielectric spacer 144. As a result, the oxidation rate of the implanted region is increased. A third ion species group may be employed to provide oxygen into the implanted region, which enhances oxidation of the first gate spacers 138 , the IL 178 , and the dielectric spacers 144 .

[0052] The ion implantation process 149 may be a zero-degree tilt implantation process performed at a low temperature range (e.g., 25 degrees Celsius to about 150 degrees Celsius). Although the various ion species may be distributed over the implantation region in the lateral and vertical directions, the implantation dose and ion kinetic energy for each ion species group may be selected to achieve a desired implantation concentration distribution in the target region. Each group of ion species may be implanted at a kinetic energy in the range of about 0.3 KeV to about 10 KeV, such as about 0.5 KeV to about 5 KeV, and the implantation dose of each ion species group may be about 1E10 12 Atom / cm 2 to about 3E10 22 Atom / cm 2 In the range of about 1E10 16 Atom / cm 2 to about 6E10 15 Atom / cm 2 , which can vary depending on the mass of the ion and the intended purpose.

[0053] In some embodiments, an annealing process may be performed to oxidize the implanted region. The annealing process may be controlled to have minimal effect on the implanted region in the amorphous state. In some embodiments, the annealing process is RTA, which heats the semiconductor device structure 100 to a target temperature in the range of about 600 degrees Celsius to about 1200 degrees Celsius. The annealing process may be performed in an environment including O2, H2O, NO, H2, N2, NH3, Ar, He, etc. or any combination thereof and at a pressure of about 1 Torr to about 40 ATM. The annealing process may further diffuse the implanted ion species into the first gate spacer 138, the IL 178, and the dielectric spacer 144.

[0054] like Fig.19 As shown in (Optional Embodiment 2), after the ion implantation process 149, the semiconductor device structure 100 is subjected to an oxidation process 151 to further oxidize the implanted region and convert the implanted region into a dielectric region or an oxidized region (e.g., an oxidized first gate spacer 138' and an oxidized dielectric spacer 144'). During the oxidation process, the implanted region may be partially or completely oxidized. Due to the chemical / physical effect provided by the implanted ion species, the implanted region is oxidized at a faster rate. The oxidation process may be the oxidation process 147 discussed above or any suitable oxidation process.

[0055] like Fig. 20As shown in , after the oxidation process 147, a gate dielectric layer 170 is formed on the IL 178 around the exposed portion of the first semiconductor layer 106, and a gate electrode layer 172 is formed above the gate dielectric layer 170. The gate dielectric layer 170 and the gate electrode layer 172 may be collectively referred to as a gate structure 174. In some embodiments, the gate dielectric layer 170 includes one or more dielectric material layers, such as silicon oxide, silicon nitride or high-K dielectric materials, other suitable dielectric materials, and / or combinations thereof. Examples of high-K dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloys, other suitable high-K dielectric materials, and / or combinations thereof. The gate dielectric layer 170 may be formed by CVD, ALD, or any suitable deposition technique. The gate electrode layer 172 may include one or more conductive material layers, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials and / or any combination thereof. The gate electrode layer 172 may be formed by CVD, ALD, electroplating or other suitable deposition techniques. The gate electrode layer 172 may also be deposited over the upper surface of the ILD layer 164. Then, the gate dielectric layer 170 and the gate electrode layer 172 formed over the ILD layer 164 are removed by using, for example, CMP until the top surface of the ILD layer 164 is exposed.

[0056] It should be understood that the semiconductor device structure 100 may undergo further processing to form conductive contacts in the ILD layer 164 to electrically connect to the S / D regions 146, and to form conductive contacts to electrically connect to the gate electrode layer 172. An interconnect structure may be formed over the semiconductor device structure 100 to provide an electrical path to the device formed on the substrate 101.

[0057] Figure 21 to Figure 26 According to some optional embodiments, Figure 5 AA is a cross-sectional side view of various stages of manufacturing a semiconductor device structure. After removing the sacrificial gate structure 130 and the second semiconductor layer 108 (for example, Fig.14), a dummy hard mask layer 148 is formed on the exposed surfaces of the first gate spacer 138, the first semiconductor layer 106, and the dielectric spacer 144. The dummy hard mask layer 148 also fills the opening between the first semiconductor layer 106. The dummy hard mask layer 148 protects the dielectric spacer 144 from being oxidized in a subsequent oxidation process. The hard mask layer 148 may include an oxide, a nitride, a dielectric, or any combination thereof, and may be formed by CVD, PECVD, ALD, or any suitable deposition technique. In some embodiments, the hard mask layer 148 is formed of a material different from that of the first gate spacer 138. In some embodiments, the hard mask layer 148 may be formed of a material having an etching selectivity relative to the dielectric spacer 144.

[0058] exist Fig. 22 In the embodiment of the present invention, the dummy hard mask layer 148 on the first gate spacer 138 is removed. The dummy hard mask layer 148 can be removed using any suitable etching process. The etching process can be time-controlled so that the dummy hard mask layer 148 on the first gate spacer 138 is removed without substantially affecting the dummy hard mask layer 148 between the first semiconductor layers 106. After the etching process, the first gate spacer 138 is exposed.

[0059] exist Fig.23 In the embodiment of the present invention, the first gate spacer 138 is subjected to an oxidation process, such as the oxidation process 147 discussed above. Figure 16-1 , Figure 16-3 and Fig.17 The first gate spacer 138 is partially or fully oxidized in a similar manner as discussed. After the oxidation process 147, a portion of the exposed surface of the topmost first semiconductor layer 106 may also be oxidized. Additionally or alternatively, after the oxidation process 147, a thin oxide layer may be formed on the exposed surface of the topmost first semiconductor layer 106. Fig.23 1 shows an embodiment in which the first gate spacer 138 is completely oxidized to become an oxidized first gate spacer 138'. Likewise, the oxidized first gate spacer 138' may have a shape corresponding to the above description of Figure 16-1 , Figure 16-3 and Fig.17 The oxidation distribution of the oxidized first gate spacer 138' is discussed. In the embodiment where the first gate spacer 138 is formed of SiCN, the nitrogen (N) or carbon (C) concentration gradually decreases from the outer surface 138o' to the inner surface 138i' of the oxidized first gate spacer 138', while the oxygen (O) concentration gradually increases from the inner surface 138i' to the outer surface 138o' of the oxidized first gate spacer 138'.

[0060] exist Fig.24In the embodiment of the present invention, the dummy hard mask layer 148 between the first semiconductor layers 106 is removed. The dummy hard mask layer 148 can be removed by an etching process using an etchant that selectively removes the dummy hard mask layer 148 without substantially affecting the oxidized first gate spacers 138', the dielectric spacers 144, and the first semiconductor layer 106. The etching process can be anisotropic so that the dummy hard mask layer 148 on the exposed surface of the topmost first semiconductor layer 106 is also removed.

[0061] exist Fig.25 In the embodiment of the present invention, an interfacial layer (IL) 278 (such as IL 178) is formed to surround the exposed surface of the first semiconductor layer 106. The IL 278 may be formed in a manner similar to that described above with respect to Fig.15 The manner in which IL 178 is formed is discussed.

[0062] exist Fig.26 In the embodiment, a gate dielectric layer 270 (such as gate dielectric layer 170) is formed on IL 278 around the exposed portion of the first semiconductor layer 106, and a gate electrode layer 272 (such as gate electrode layer 172) is formed over the gate dielectric layer 270. The gate dielectric layer 270 and the gate electrode layer 272 may be formed in a manner similar to that described above with respect to Fig. 20 The gate dielectric layer 170 and the gate electrode layer 172 are formed in the manner discussed. Thus, the first gate spacer 138 and the second gate spacer 139 are partially or completely oxidized, while the material of the dielectric spacer 144 remains substantially unchanged before and after the oxidation process.

[0063] Figure 27 to Figure 28 According to some optional embodiments, Figure 5 AA is a cross-sectional side view of various stages of manufacturing a semiconductor device structure. After forming IL 178 (e.g., Fig.15), portions of the first gate spacer 138 and the dielectric spacer 144 are fluorinated by a fluorination process 153 and converted into a fluorinated first gate spacer 238 and a fluorinated dielectric spacer 244. The fluorination process 153 can be any suitable fluorination process. In some embodiments, the fluorination process is a fluorine soaking process. The fluorine soaking process can include exposing the first gate spacer 138 and the dielectric spacer 144 to a fluorine-containing precursor at a processing temperature of less than about 100 degrees Celsius. In some embodiments, the fluorine-containing precursor includes a combination of HF, CF4, F2, C2F6, HF and F2 or other suitable fluorine-containing precursors. The processing temperature can be in the range of about 20 degrees Celsius to about 250 degrees Celsius, and the processing pressure can be in the range of about 0.1 Torr to about 10 Torr. The first gate spacer 138 and the dielectric spacer 144 can be exposed to the fluorine-containing precursor for a duration in the range of about 15 seconds to about 30 minutes. In some embodiments, the fluorine-containing precursor is F2, and the first gate spacers 138 and the dielectric spacers 144 may be exposed to F2 for a duration in a range from about 5 minutes to about 20 minutes.

[0064] Alternatively, the fluorination process can be performed by exposing the first gate spacer 138 and the dielectric spacer 144 to reactive species generated in situ from a fluorine-containing precursor (e.g., F2) in the reaction chamber or upstream of the reaction chamber (e.g., from a remote plasma generator). Exemplary reactive species can include fluorine plasma or neutral radical species of fluorine, such as fluorine radicals or atomic fluorine.

[0065] In some embodiments, before the fluorination process, the deposited first gate spacer 138 and the dielectric spacer 144 may be subjected to a plasma treatment process. The plasma treatment process includes exposing the first gate spacer 138 and the dielectric spacer 144 to a hydrogen-containing plasma. The hydrogen-containing plasma may be formed by activating a hydrogen-containing gas by a low-power plasma source or a remote plasma source. The hydrogen-containing gas may be any suitable hydrogen-containing gas. In some embodiments, the hydrogen-containing gas is hydrogen (H2). In some embodiments, the low-power plasma source is a capacitively coupled plasma source, and the plasma power is in the range of from about 10W to about 250W. The plasma generated by the capacitively coupled plasma source or the remote plasma source includes more hydrogen radicals than ions. In addition, the processing temperature of the plasma treatment process is relatively low, such as from about 20 degrees Celsius to about 100 degrees Celsius. Therefore, hydrogen radicals replace methyl end groups or attach to hanging Si bonds to form Si-H bonds. The plasma treatment process allows more Si-H bonds to be generated so that the subsequent fluorination process can be performed with relatively low energy, such as at low temperature (e.g., about 150 degrees Celsius or less) without plasma. The low energy fluorination process can avoid making the fluorine-containing precursor an etchant.

[0066] After the fluorination process 153 , the fluorinated first gate spacers 238 and the dielectric spacers 244 may include about 2 at. % to about 20 at. % fluorine, eg, about 10 at. % or less fluorine. Figure 27-1 and Figure 27-2 2 is an enlarged view of a portion of the semiconductor device structure 100 showing the fluorination profiles corresponding to the profiles of the fluorinated first gate spacers 238 and the fluorinated dielectric spacers 244, respectively. Figure 27-1 As shown in , the fluorinated first gate spacer 238 has an outer surface 238o and an inner surface 238i. The concentration of fluorine decreases from the outer surface 238o to the inner surface 238i because the outer surface 238o is exposed to the fluorine-containing precursor. In some embodiments, the fluorinated first gate spacer 238 has a first fluorine concentration, and the first gate spacer 138 disposed between the fluorinated first gate spacer 238 and the second gate spacer 139 has a second fluorine concentration lower than the first fluorine concentration. In some examples, the first gate spacer 138 is not fluorinated and therefore has little or no fluorine.

[0067] Likewise, the fluorinated dielectric spacer 244 has an outer surface 244o and an inner surface 244i, and the concentration of fluorine decreases from the outer surface 244o to the inner surface 244i. The fluorinated dielectric spacer 244 can have a first fluorine concentration, and the dielectric spacer 144 between the fluorinated dielectric spacer 244 and the S / D region 146 can have a second fluorine concentration lower than the first fluorine concentration. In some examples, the dielectric spacer 144 is not fluorinated and therefore has little or no fluorine.

[0068] In some embodiments, each of the fluorinated dielectric spacers 244 may include a fluorine concentration that is less than a fluorine concentration of the fluorinated first gate spacers 238 .

[0069] The K value of the fluorinated first gate spacer 238 and the dielectric spacer 244 can be increased by about 0.1 to about 0.5. Therefore, the leakage current is reduced and the thermal stability is improved. In some embodiments, the fluorinated first gate spacer 238 and the dielectric spacer 244 can be formed by the same or different materials (e.g., SiCN or SiCON), and can include about 2at.% to about 20at.% carbon and about 0at.% to about 20at.% nitrogen. In the example where the fluorinated first gate spacer 238 and the dielectric spacer 244 include oxygen, the atomic percentage of oxygen can be about 15at.% to about 35at.%. In some embodiments, the carbon, nitrogen and oxygen components may not have a significant gradient in the fluorinated first gate spacer 238. However, the dielectric spacer 244 may have a concentration gradient of fluorine, wherein the fluorine concentration closer to the S / D region 146 is relatively lower. In some embodiments, the atomic percentages of carbon, nitrogen, and oxygen in the fluorinated first gate spacer 238 may be different from the atomic percentages of carbon, nitrogen, and oxygen in the fluorinated dielectric spacer 244. The above atomic percentage ranges also apply to a single gate spacer (i.e., the first gate spacer 138 and the second gate spacer 139 are formed of the same material).

[0070] The remaining first gate spacer 138 and / or the second gate spacer 139 may serve as a capping layer for the fluorinated first gate spacer 238. Likewise, the remaining dielectric spacer 144 may serve as a capping layer for the fluorinated dielectric spacer 244. Subsequent processes (such as etching or epitaxial growth processes) may cause the fluorine in the fluorinated first gate spacer 238 and the dielectric spacer 244 to be released, which may damage the exposed surface of the semiconductor device structure 100.

[0071] In some embodiments, one or more processes are optionally implemented to further incorporate fluorine into the second gate spacer 139. The second gate spacer 139 may not be fully fluorinated to maintain the mechanical strength of the second gate spacer 139. In addition, subsequent processes (such as etching and thermal processes) may cause the fluorine in the second gate spacer 139 to be released, which may damage the exposed surface of the semiconductor device structure 100. In the example of fluorinating the second gate spacer 139, the CESL 162 may also be used as a capping layer for the fluorinated second gate spacer 139. The one or more processes for incorporating fluorine into the second gate spacer 139 may be the same as or different from the one or more processes for incorporating fluorine into the first gate spacer 138. In some embodiments, the above-described embodiments are implemented with respect to the fluorinated second gate spacer 139. Fig. 27The plasma treatment process and the fluorination process described above are performed to fluorinate the second gate spacer 139. In some embodiments, the fluorination process with higher energy is performed to fluorinate the second gate spacer 139 without the plasma treatment process. In some embodiments, without the plasma treatment process, the first gate spacer 138 is fluorinated by the fluorination process with higher energy, and the second gate spacer 139 is fluorinated by the fluorination process with higher energy. Fig. 27 139. During the fluorination process with higher energy, a small portion of the first gate spacer 138 may be removed by fluorine, and other components of the semiconductor device structure 100 are protected by the first gate spacer 138. Components of the semiconductor device structure 100 are exposed during the fluorination of the second gate spacer 139. Therefore, a plasma treatment process and a fluorination with low energy are performed to fluorinate the second gate spacer 139 to protect other components of the semiconductor device structure 100. In other words, in some embodiments, different processes are used to fluorinate the first gate spacer 138 and the second gate spacer 139 to protect other components of the semiconductor device structure 100.

[0072] In some embodiments, the fluorination of the first gate spacer 138, the second gate spacer 139, and / or the dielectric spacer 144 can be enhanced by: maintaining the fluorinated layer in a nitrogen environment immediately after the fluorination process; exposing the fluorinated layer to a water-free environment immediately after the fluorination process; and forming a capping layer on the fluorinated layer immediately after the fluorination process. For example, after the fluorination process 153, the semiconductor device structure 100 can be transferred to another chamber / system for subsequent processes (e.g., forming a gate dielectric layer 270) in a nitrogen-filled container. The subsequent process is free of water. In other words, a wet etching process may not be performed immediately after the fluorination process. After the fluorination process 153, the gate dielectric layer 270 (which serves as a capping layer for the fluorinated first gate spacer 238 and the dielectric spacer 244) is immediately formed on the fluorinated first gate spacer 238 and the dielectric spacer 244. With these enhancements, the fluorine concentration in the fluorinated layer is substantially higher than that of the fluorinated layer without the enhancement.

[0073] exist Fig.28 In the embodiment, a gate dielectric layer 270 (such as gate dielectric layer 170) is formed on IL 178 around the exposed portion of the first semiconductor layer 106, and a gate electrode layer 272 (such as gate electrode layer 172) is formed over the gate dielectric layer 270. The gate dielectric layer 270 and the gate electrode layer 272 may be formed in a manner similar to that described above with respect to Fig. 20 The gate dielectric layer 170 and the gate electrode layer 172 are formed in the manner discussed.

[0074] Fig.29According to some embodiments Fig.28 In some embodiments, the IL 178 may also be formed by Fig. 27 In some embodiments, the fluorine may be fluorinated by the process described in , and the fluorine may diffuse to the interface between the IL 178 and the first semiconductor layer 106 and form Si-F bonds. In some embodiments, the fluorine has a first concentration at the interface between the IL 178 and the first semiconductor layer 106, and has a second concentration between the top surface and the bottom surface of the first semiconductor layer 106, wherein the first concentration is greater than the second concentration. The fluorine may repair defects at the interface between the IL 178 and the first semiconductor layer 106. In some embodiments, the fluorine replaces oxygen vacancies at the interface between the IL 178 and the first semiconductor layer 106, which in turn improves the interface state density (Dit).

[0075] Embodiments of the present disclosure provide semiconductor device structures having fully or partially oxidized gate spacers and oxidized dielectric spacers between channel layers. In some optional embodiments, the gate spacers and dielectric spacers are fluorinated. The increased oxygen or fluorine content in the oxidized or fluorinated gate spacers and dielectric spacers leads to reduced mechanical strength of the gate spacers and dielectric spacers, and thus reduced dielectric constant (K) values ​​of the gate spacers and dielectric spacers. Therefore, leakage current is reduced, and thermal stability and parasitic capacitance are improved.

[0076] The embodiment is a semiconductor device structure. The structure includes: a gate dielectric layer disposed above a substrate; a gate electrode layer disposed above the gate dielectric layer; and a first gate spacer disposed adjacent to the gate dielectric layer, wherein the first gate spacer includes an inner surface facing the gate dielectric layer and an outer surface opposite to the inner surface, and the first gate spacer includes an oxygen concentration that decreases from the inner surface toward the outer surface of the first gate spacer.

[0077] Another embodiment is a method for forming a semiconductor device structure. The method includes: forming a sacrificial gate structure and a gate spacer over a portion of a fin structure formed over a substrate, the fin structure including a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked alternately. The method also includes: removing a portion of the fin structure to expose a portion of the substrate; removing a portion of each of the second semiconductor layers and replacing it with a dielectric spacer; forming a source / drain region on opposite sides of the sacrificial gate structure; removing the sacrificial gate structure and the second semiconductor layer to expose the gate spacer and the dielectric spacer; subjecting the gate spacer and the dielectric spacer to an oxidation process to oxidize a portion of the gate spacer; and forming a gate dielectric layer and a gate electrode layer over the oxidized gate spacer.

[0078] A further embodiment is a method. The method includes: forming a sacrificial gate structure over a fin structure including a first plurality of semiconductor layers and a second plurality of semiconductor layers; depositing a gate spacer structure on the sacrificial gate structure; removing a portion of the fin structure to expose a portion of a substrate; recessing the second plurality of semiconductor layers to form a cavity; forming a dielectric spacer in the cavity; forming a source / drain region from a portion of the substrate; removing the sacrificial gate structure and the second plurality of semiconductor layers; forming an interfacial layer on a portion of each of the first plurality of semiconductor layers; and doping fluorine into the gate spacer and the dielectric spacer.

[0079] Some embodiments of the present application provide a semiconductor device structure, including: a gate dielectric layer, disposed above a substrate; a gate electrode layer, disposed above the gate dielectric layer; and a first gate spacer, disposed adjacent to the gate dielectric layer, wherein the first gate spacer includes an inner surface facing the gate dielectric layer and an outer surface opposite to the inner surface, and the first gate spacer includes an oxygen concentration that decreases from the inner surface toward the outer surface of the first gate spacer.

[0080] In some embodiments, the semiconductor device structure further comprises: a plurality of semiconductor layers vertically stacked above the substrate, wherein the gate electrode layer surrounds a portion of each of the semiconductor layers; and a dielectric spacer disposed between two adjacent semiconductor layers of the plurality of semiconductor layers, wherein the dielectric spacer comprises an inner surface facing the gate dielectric layer and an outer surface opposite to the inner surface of the dielectric spacer, and the dielectric spacer comprises an oxygen concentration decreasing from the inner surface of the dielectric spacer toward the outer surface. In some embodiments, the semiconductor device structure further comprises: a second gate spacer disposed on the outer surface of the first gate spacer, wherein the second gate spacer comprises an inner surface in contact with the outer surface of the first gate spacer and an outer surface opposite to the inner surface, and the second gate spacer comprises an oxygen concentration decreasing from the inner surface of the second gate spacer toward the outer surface. In some embodiments, each of the first gate spacer and the second gate spacer comprises SiCON. In some embodiments, the dielectric spacer comprises SiCON. In some embodiments, the first gate spacer has a nitrogen or carbon concentration increasing from the inner surface toward the outer surface of the first gate spacer. In some embodiments, the semiconductor device structure further comprises: an interface layer contacting each semiconductor layer of the plurality of semiconductor layers, wherein the interface layer and the dielectric spacer comprise the same material. In some embodiments, the dielectric spacer comprises an oxygen concentration less than the oxygen concentration of the first gate spacer.

[0081] Other embodiments of the present application provide a method for forming a semiconductor device structure, comprising: forming a sacrificial gate structure and a gate spacer above a portion of a fin structure formed above a substrate, the fin structure comprising a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked; removing a portion of the fin structure to expose a portion of the substrate; removing a portion of each of the second semiconductor layers and replacing it with a dielectric spacer; forming a source / drain region on opposite sides of the sacrificial gate structure; removing the sacrificial gate structure and the second semiconductor layer to expose the gate spacer and the dielectric spacer; subjecting the gate spacer and the dielectric spacer to an oxidation treatment to oxidize a portion of the gate spacer; and forming a gate dielectric layer and a gate electrode layer above the oxidized gate spacer.

[0082] In some embodiments, the oxidation process is performed to oxidize the entire gate spacer. In some embodiments, the gate spacer has an oxygen concentration that gradually changes along the thickness of the gate spacer. In some embodiments, the method further includes: after removing the sacrificial gate structure and the second semiconductor layer and before the oxidation process, forming an interfacial layer on the exposed surface of each first semiconductor layer. In some embodiments, the oxidation process is performed to oxidize a portion of the dielectric spacer. In some embodiments, each dielectric spacer has an oxygen concentration that gradually changes along the thickness of the dielectric spacer. In some embodiments, the method further includes: after removing the sacrificial gate structure and the second semiconductor layer and before the oxidation process, forming a dummy hard mask layer on each of the gate spacer and the dielectric spacer. In some embodiments, the method further includes: after forming the dummy hard mask layer and before the oxidation process, selectively removing the dummy hard mask layer from the gate spacer. In some embodiments, the method further includes: after the oxidation process, removing the dummy hard mask layer from each of the dielectric spacers; and before forming a gate dielectric layer and a gate electrode layer over the oxidized gate spacer, forming an interfacial layer on the exposed surface of each first semiconductor layer.

[0083] Still other embodiments of the present application provide a method for forming a semiconductor device structure, comprising: forming a sacrificial gate structure above a fin structure comprising a first plurality of semiconductor layers and a second plurality of semiconductor layers; depositing a gate spacer structure on the sacrificial gate structure; removing a portion of the fin structure to expose a portion of the substrate; recessing the second plurality of semiconductor layers to form a cavity; forming a dielectric spacer in the cavity; forming a source / drain region from the portion of the substrate; removing the sacrificial gate structure and the second plurality of semiconductor layers; forming an interface layer on a portion of each of the first plurality of semiconductor layers; and doping fluorine into the gate spacer and the dielectric spacer.

[0084] In some embodiments, the gate spacer structure includes a first gate spacer and a second gate spacer, wherein the first gate spacer is disposed adjacent to the sacrificial gate structure and the second gate spacer is disposed away from the sacrificial gate structure, and wherein fluorine is doped such that the first gate spacer has a first fluorine concentration and the second gate spacer has a second fluorine concentration lower than the first fluorine concentration. In some embodiments, the method further includes: during the doping of fluorine into the gate spacer and the dielectric spacer, doping fluorine into an interface between the interfacial layer and the first semiconductor layer.

[0085] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and in examples that do not deviate from the spirit and scope of the embodiments of the present disclosure, they can make various changes, substitutions and modifications herein.

Claims

1. A semiconductor device structure, comprising: a gate dielectric layer disposed above the substrate; A gate electrode layer, disposed above the gate dielectric layer; as well as A first gate spacer is disposed adjacent to the gate dielectric layer, wherein the first gate spacer includes an inner surface facing the gate dielectric layer and an outer surface opposite to the inner surface, and the first gate spacer includes an oxygen concentration that decreases from the inner surface toward the outer surface of the first gate spacer.

2. The semiconductor device structure according to claim 1, further comprising: a plurality of semiconductor layers vertically stacked above the substrate, wherein the gate electrode layer surrounds a portion of each of the semiconductor layers; and A dielectric spacer is disposed between two adjacent semiconductor layers of the plurality of semiconductor layers, wherein the dielectric spacer includes an inner surface facing the gate dielectric layer and an outer surface opposite to the inner surface of the dielectric spacer, and the dielectric spacer includes an oxygen concentration that decreases from the inner surface toward the outer surface of the dielectric spacer.

3. The semiconductor device structure according to claim 1, further comprising: a second gate spacer disposed on the outer surface of the first gate spacer, wherein the second gate spacer includes an inner surface in contact with the outer surface of the first gate spacer and an outer surface opposite to the inner surface, and the second gate spacer includes an oxygen concentration that decreases from the inner surface toward the outer surface of the second gate spacer.

4. The semiconductor device structure according to claim 3, wherein: Each of the first gate spacer and the second gate spacer includes SiCON.

5. The semiconductor device structure according to claim 4, wherein: The dielectric spacer includes SiCON.

6. The semiconductor device structure according to claim 1, wherein: The first gate spacer has a nitrogen or carbon concentration that increases from the inner surface toward the outer surface of the first gate spacer.

7. The semiconductor device structure according to claim 3, further comprising: An interface layer contacts each semiconductor layer of the plurality of semiconductor layers, wherein the interface layer and the dielectric spacer comprise a same material.

8. The semiconductor device structure according to claim 1, wherein: The dielectric spacers include an oxygen concentration that is less than the oxygen concentration of the first gate spacers.

9. A method for forming a semiconductor device structure, comprising: forming a sacrificial gate structure and a gate spacer over a portion of a fin structure formed over the substrate, the fin structure comprising a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked alternately; removing a portion of the fin structure to expose a portion of the substrate; removing a portion of each of the second semiconductor layers and replacing it with a dielectric spacer; forming source / drain regions on opposite sides of the sacrificial gate structure; removing the sacrificial gate structure and the second semiconductor layer to expose the gate spacer and the dielectric spacer; subjecting the gate spacers and the dielectric spacers to an oxidation process, thereby oxidizing portions of the gate spacers; as well as A gate dielectric layer and a gate electrode layer are formed over the oxidized gate spacers.

10. A method for forming a semiconductor device structure, comprising: forming a sacrificial gate structure over the fin structure including the first plurality of semiconductor layers and the second plurality of semiconductor layers; depositing a gate spacer structure on the sacrificial gate structure; removing a portion of the fin structure to expose a portion of the substrate; recessing the second plurality of semiconductor layers to form a cavity; forming a dielectric spacer in the cavity; forming source / drain regions from said portion of said substrate; removing the sacrificial gate structure and the second plurality of semiconductor layers; forming an interfacial layer on a portion of each of the first plurality of semiconductor layers; as well as Fluorine is doped into the gate spacers and the dielectric spacers.

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