Display panel

Abstract

The invention provides a display panel, and relates to the technical field of display. The display panel is provided with a substrate and a driving layer located on the substrate. The driving layer is provided with a transistor which is provided with a first conductive part, a second conductive part and a metal connecting part; the first conductive part is provided with a first active layer and a first grid, the second conductive part is provided with a second active layer and a second grid, and the metal connecting part is provided with a first metal part and a second metal part; the first metal part is connected with the first pole of the first active layer and the first pole of the second active layer, and the second metal part is connected with the second pole of the first active layer and the second pole of the second active layer; the channel region of the first active layer is provided with at least one first bulge, or the channel region of the first active layer is provided with at least one first groove; the channel region of the second active layer is provided with at least one second protrusion, or the channel region of the second active layer is provided with at least one second groove.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular, to a display panel. Background Art

[0002] To increase the on-state current, the transistor needs to have a large width-to-length ratio, which results in a larger area occupied by the peripheral circuits located in the peripheral area of ​​the display panel, which in turn causes the frame size of the display panel to increase.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0004] The purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art and provide a display panel that can improve mobility and on-state current.

[0005] According to one aspect of the present disclosure, there is provided a display panel having a base substrate and a driving layer disposed on the base substrate;

[0006] The driving layer has at least one transistor, and the transistor has a first conductive part, a second conductive part, and a metal connecting part; the first conductive part has a first active layer and a first gate, the second conductive part has a second active layer and a second gate, and the metal connecting part has a first metal part and a second metal part; the first metal part is connected to a first electrode of the first active layer and a first electrode of the second active layer, and the second metal part is connected to a second electrode of the first active layer and a second electrode of the second active layer;

[0007] The channel region of the first active layer has at least one first protrusion extending in a direction away from the substrate, or the channel region of the first active layer has at least one first groove extending in a direction close to the substrate; the channel region of the second active layer has at least one second protrusion extending in a direction away from the substrate, or the channel region of the second active layer has at least one second groove extending in a direction close to the substrate.

[0008] In one embodiment of the present disclosure, the first conductive portion is located between the base substrate and the second conductive portion;

[0009] The driving layer comprises a first semiconductor layer, a first gate layer, a second semiconductor layer, a second gate layer and a source-drain metal layer located on one side of the base substrate; the first active layer is located in the first semiconductor layer, the second active layer is located in the second semiconductor layer, the first gate is located in the first gate layer, the second gate is located in the second gate layer, and the first metal part and the second metal part are located in the source-drain metal layer;

[0010] The driving layer further comprises a first insulating layer located between the first conductive portion and the second conductive portion;

[0011] A first supporting portion is provided on the surface of the base substrate, and a part of the channel region of the first active layer is provided on a side of the first supporting portion away from the base substrate, thereby forming the first protrusion;

[0012] A second supporting portion is disposed on a surface of the first insulating layer away from the base substrate, and a portion of the channel region of the second active layer is disposed on a side of the second supporting portion away from the base substrate, thereby forming the second protrusion.

[0013] In one embodiment of the present disclosure, the first conductive portion is located between the base substrate and the second conductive portion;

[0014] The driving layer comprises a first semiconductor layer, a first gate layer, a second semiconductor layer, a second gate layer and a source-drain metal layer located on one side of the base substrate; the first active layer is located in the first semiconductor layer, the second active layer is located in the second semiconductor layer, the first gate is located in the first gate layer, the second gate is located in the second gate layer, and the first metal part and the second metal part are located in the source-drain metal layer;

[0015] The driving layer further comprises a first insulating layer and a second insulating layer, wherein the first insulating layer is located between the first conductive portion and the second conductive portion, and the second insulating layer is located between the base substrate and the first conductive portion;

[0016] A second supporting portion is disposed on a surface of the first insulating layer away from the base substrate, and a portion of the channel region of the second active layer is disposed on a side of the second supporting portion away from the base substrate, thereby forming the second protrusion;

[0017] A surface of the second insulating layer away from the base substrate has a third groove, and a portion of the channel region of the first active layer extends into the third groove, thereby forming the first groove.

[0018] In one embodiment of the present disclosure, the second support portion is made of inorganic material, and the thickness of the second support portion is 3000-10000A; or the second support portion is made of organic material, and the thickness of the second support portion is 5000-30000A.

[0019] In one embodiment of the present disclosure, the first support portion is made of inorganic material, and the thickness of the first support portion is 3000-10000A; or the first support portion is made of organic material, and the thickness of the first support portion is 5000-30000A.

[0020] In one embodiment of the present disclosure, the second supporting portion and the first insulating layer are prepared on the same layer.

[0021] In one embodiment of the present disclosure, the thickness of the first support portion is equal to the thickness of the second support portion.

[0022] In one embodiment of the present disclosure, the depth of the first groove is equal to the thickness of the second supporting portion.

[0023] In one embodiment of the present disclosure, the display panel further comprises a pixel layer located on a side of the driving layer away from the base substrate;

[0024] The pixel layer includes a pixel electrode, and the pixel electrode is electrically connected to the second metal portion.

[0025] In one embodiment of the present disclosure, the material of the first active layer is metal oxide, and the material of the second active layer is metal oxide.

[0026] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0028] Figure 1 A schematic diagram of a gate drive circuit principle.

[0029] Figure 2 FIG. 1 is a schematic diagram of the structure of a display panel in one embodiment of the present disclosure.

[0030] Figure 3FIG. 1 is a schematic diagram of the structure of a display panel in one embodiment of the present disclosure.

[0031] Figure 4 FIG. 1 is a schematic diagram of the structure of a display panel in one embodiment of the present disclosure.

[0032] Figure 5 It is a schematic diagram of the structure of a display panel in one embodiment of the present disclosure.

[0033] Description of reference numerals:

[0034] BP, base substrate; DRL, driving layer; AL1, first active layer; G1, first gate; AL2, second active layer; G2, second gate; MP1, first metal part; MP2, second metal part; BP1, first protrusion; BP2, second protrusion; GR1, first groove; SCL1, first semiconductor layer; GT1, first gate layer; SCL2, second semiconductor layer; GT2, second gate layer; SD, source and drain metal layer; II1, first insulating layer; SDP1, first supporting part; GR3, third groove; SDP2, second supporting part; II2, second insulating layer; PIXL, pixel layer; PE, pixel electrode; PNL, display panel; GI1, first gate insulating layer; GI2, second gate insulating layer; II3, third insulating layer; LD, light-emitting element; PEL, pixel electrode layer; ELU, light-emitting functional unit; ELM, light-emitting functional layer; COML, common electrode layer; MP3, third metal part. DETAILED DESCRIPTION

[0035] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0036] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as according to the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0037] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used merely as labels and are not intended to limit the quantity of their objects.

[0038] The structure layer A is located on the side of the structure layer B away from the substrate, which can be understood as the structure layer A being formed on the side of the structure layer B away from the substrate. When the structure layer B is a patterned structure, a portion of the structure layer A may also be located at the same physical thickness as the structure layer B or lower than the physical thickness of the structure layer B, wherein the substrate is the thickness reference.

[0039] A transistor is an element including three terminals: a gate, a drain, and a source. The transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. The channel region refers to the region where the current mainly flows, the channel region maintains semiconductor properties, and the source and the drain are both conductorized. In the embodiment of the present disclosure, the first pole and the second pole are used as the source and the drain. In the case of using transistors with opposite polarities or the case of a change in the current direction during circuit operation, the functions of the "first pole" and the "second pole" are sometimes interchanged, that is, the "first pole" and the "second pole" can be interchanged.

[0040] The present disclosure provides a display panel PNL, which can be applied to electronic devices with display functions such as mobile phones, tablet computers, desktop computers, and laptop computers, which are not listed one by one here.

[0041] In one embodiment of the present disclosure, see Figure 2 The display panel PNL includes a display area AA and a peripheral area BB located at least on one side of the display area AA, for example, the peripheral area BB surrounds the display area AA. In the display area AA, the display panel PNL is provided with sub-pixels for display; in the peripheral area BB, the display panel PNL may not be provided with sub-pixels for display, or the provided sub-pixels are not used for displaying images.

[0042] In one embodiment of the present disclosure, the sub-pixels in the display panel PNL may be thin-film self-luminous light-emitting elements LD, such as OLEDs and the like. Furthermore, the light-emitting elements LD located in the display area AA include light-emitting elements LD of a plurality of different colors. For example, the light-emitting elements LD may include a red light-emitting element for emitting red light, a blue light-emitting element for emitting blue light, and a green light-emitting element for emitting green light. It is to be understood that in other embodiments of the present disclosure, the light-emitting elements LD in the display area AA may also be light-emitting elements LD of only one color, or may also have light-emitting elements LD of other colors (e.g., a yellow light-emitting element for emitting yellow light, a cyan light-emitting element for emitting cyan light, a white light-emitting element for emitting white light, etc.).

[0043] In one embodiment of the present disclosure, see Figure 3 The display panel PNL may include a base substrate BP, a driving layer DRL, and a pixel layer PIXL which are sequentially stacked.

[0044] In one embodiment of the present disclosure, the substrate BP may be a substrate of an inorganic material, or a substrate of an organic material; of course, it may also be a composite substrate formed by stacking a substrate of an inorganic material and a substrate of an organic material. For example, in some embodiments of the present disclosure, the material of the substrate BP may be a glass material such as soda-lime glass, quartz glass, or sapphire glass. In some other embodiments of the present disclosure, the material of the substrate BP may be polymethyl methacrylate, polyvinyl alcohol, polyvinyl phenol, polyether sulfone, polyimide, polyamide, polyacetal, polycarbonate, polyethylene terephthalate, polyethylene naphthalate, or a combination thereof. In some other embodiments of the present disclosure, the substrate BP may also be a flexible substrate BP, for example, the material of the substrate BP may include polyimide.

[0045] In one embodiment of the present disclosure, the driving layer DRL is provided with a driving circuit PDC, wherein the driving circuit PDC includes a source driving circuit and a gate driving circuit. Both the source driving circuit and the gate driving circuit may use a plurality of thin film transistors and capacitors, and the specific structure is not particularly limited here. Further, the thin film transistor may be selected from a top-gate thin film transistor, a bottom-gate thin film transistor or a double-gate thin film transistor, each of which may include at least one overlapping active layer and a gate, and the active layer of each thin film transistor may be arranged in the same semiconductor layer in the same layer; or, it may also be arranged in multiple semiconductor layers, and the active layers of different transistors may be distributed in different semiconductor layers. The material of the active layer of the thin film transistor may be an amorphous silicon semiconductor material, a low-temperature polycrystalline silicon semiconductor material, a metal oxide semiconductor material, an organic semiconductor material, a carbon nanotube semiconductor material or other types of semiconductor materials; the thin film transistor may be an N-type thin film transistor or a P-type thin film transistor.

[0046] It can be understood that, among the thin film transistors in the driving circuit PDC, the types of any two thin film transistors may be the same or different. Exemplarily, in some embodiments, in a driving circuit PDC, some thin film transistors may be N-type thin film transistors and some thin film transistors may be P-type thin film transistors. Again exemplarily, in other embodiments, in a driving circuit PDC, the material of the active layer of some thin film transistors may be a low-temperature polycrystalline silicon semiconductor material, and the material of the active layer of some thin film transistors may be a metal oxide semiconductor material. In some embodiments of the present disclosure, the thin film transistor is a metal oxide thin film transistor, and in other embodiments of the present disclosure, the thin film transistor is a low-temperature polycrystalline silicon thin film transistor. In other embodiments of the present disclosure, some thin film transistors are low-temperature polycrystalline silicon thin film transistors, and some thin film transistors are metal oxide thin film transistors.

[0047] In the related art, the low mobility of oxide thin-film transistors (OxideTFT) limits their application in high-resolution and narrow-frame products. For example, a gate drive circuit (Gate GOA circuit) has a drive unit and an output unit. Take the 7T2C drive circuit as an example, see Figure 1, the driving unit includes transistor T1, transistor T2, transistor T3, transistor T6, transistor T7 and transistor T8, the output unit includes transistor T4 and transistor T5, capacitor C1 and capacitor C2, in this circuit, transistor T4 and transistor T5 as output transistors require higher on-state current. Usually, the active layer of the transistor is set to a large width-to-length ratio to increase the on-state current of the transistor. However, the use of this solution will cause the Gate GOA circuit to occupy a large area, which will lead to an increase in the size of the display panel, which is not conducive to achieving a narrow frame, or will lead to a reduction in the resolution of the display panel.

[0048] In order to solve one of the above problems, in one embodiment of the present disclosure, at least some of the thin film transistors in the driving circuit PDC are dual-channel thin film transistors. The use of dual-channel thin film transistors can obtain relatively high mobility and on-state current. For example, some of the thin film transistors in the driving circuit PDC are dual-channel thin film transistors, and some of the thin film transistors are single-channel thin film transistors. For another example, all thin film transistors in the driving circuit PDC are dual-channel thin film transistors. The dual-channel thin film transistor has two active layers and two gates, and the two gates share the same first electrode and second electrode. It can be understood that in the present disclosure, the use of dual-channel thin film transistors can obtain relatively high mobility and on-state current.

[0049] In one embodiment of the present disclosure, a double-channel thin-film transistor includes a first conductive portion, a second conductive portion, and a metal connection portion. The first conductive portion includes a first active layer AL1 and a first gate G1, the second conductive portion includes a second active layer AL2 and a second gate G2, and the metal connection portion includes a first metal portion MP1 and a second metal portion MP2; the first active layer AL1 has a first pole and a second pole, and a channel region located between the first pole and the second pole, and the second active layer AL2 has a first pole and a second pole, and a channel region located between the first pole and the second pole. The first metal portion MP1 is connected to the first pole of the first active layer AL1 and the first pole of the second active layer AL2, and the second metal portion MP2 is connected to the second pole of the first active layer AL1 and the second pole of the second active layer AL2.

[0050] The first gate G1 overlaps with the channel region of the first active layer AL1, and the second gate G2 overlaps with the channel region of the second active layer AL2. It can be understood that, in this example, the orthographic projection of the first gate G1 on the substrate substrate BP at least covers the orthographic projection of the channel region of the first active layer AL1 on the substrate substrate BP, and the orthographic projection of the second gate G2 on the substrate substrate BP at least covers the orthographic projection of the channel region of the second active layer AL2 on the substrate substrate BP. In the present disclosure, the first gate G1, the first active layer AL1, the first metal part MP1 and the second metal part MP2 can form a channel thin film transistor structure, and the second gate G2, the second active layer AL2, the first metal part MP1 and the second metal part MP2 can form a channel thin film transistor structure, thereby forming a double-channel thin film transistor structure. When the first gate G1 and the second gate G2 are both in a high level state, the thin film transistor structures of the two channels are both turned on. Since the first gate G1 and the second gate G2 share a set of source and drain structures, when they are turned on at the same time, the current between the first metal part MP1 and the second metal part MP2 can be doubled, that is, the mobility and on-state current of the transistor are improved, and the screen display brightness can be better, and the first active layer AL1 and the second active layer AL2 are arranged in sequence in a direction away from the substrate BP. In the present disclosure, although a gate structure is added and the current is doubled, the surface area of ​​the display panel PNL is not increased. Therefore, the solution in the present disclosure can reduce the area occupied by the thin film transistor under the premise of meeting the current demand, thereby improving the resolution and facilitating the realization of a narrow frame.

[0051] In this example, the driving layer DRL comprises a source-drain metal layer SD, a first semiconductor layer SCL1, a first gate insulating layer GI1, a first gate layer GT1, a first insulating layer II1, a second semiconductor layer SCL2, a second gate insulating layer GI2 and a second gate layer GT2 stacked on the base substrate BP. Among them, the first metal part MP1 and the second metal part MP2 are located in the source-drain metal layer SD; the first metal part MP1 and the second metal part MP2 are independently spaced and not connected to each other, the first active layer AL1 is located in the first semiconductor layer SCL1, the first pole of the first active layer AL1 is located on the side of the first metal part MP1 away from the base substrate BP, the first pole of the first active layer AL1 is electrically connected to the first metal part MP1, the second pole of the first active layer AL1 is located on the side of the second metal part MP2 away from the base substrate BP, and the second pole of the first active layer AL1 is electrically connected to the second metal part MP2. The first gate G1 is located on the first gate layer GT1, the first gate insulating layer GI1 is located on the side of the first active layer AL1 away from the substrate BP, and the first gate insulating layer GI1 at least covers the channel region of the first active layer AL1, so as to insulate the first active layer AL1 from the first gate G1. In this example, the first gate insulating layer GI1 completely covers the first active layer AL1, and it can be understood that the orthographic projection of the first gate insulating layer GI1 on the substrate BP covers the orthographic projection of the first active layer AL1 on the substrate BP. The first insulating layer II1 is arranged on the surface of the first gate G1 layer away from the substrate BP, as an interlayer dielectric layer, for planarization. The second active layer AL2 is located on the second semiconductor layer SCL2, the second active layer AL2 is arranged on the surface of the first insulating layer II1 away from the substrate BP, and the first pole of the second active layer AL2 is electrically connected to the first pole of the first active layer AL1 through the via hole on the first insulating layer II1 and the via hole on the first gate insulating layer GI1, thereby realizing the electrical connection between the second active layer AL2 and the first metal part MP1. The second electrode of the second active layer AL2 is electrically connected to the second electrode of the first active layer AL1 through the via hole on the first insulating layer II1 and the via hole on the first gate insulating layer GI1, thereby realizing electrical connection between the second active layer AL2 and the second metal part MP2. The second gate G2 is located on the second gate layer GT2.

[0052] In one embodiment of the present disclosure, the driving layer DRL further includes a third insulating layer II3 disposed on a side of the second gate layer GT2 away from the substrate BP, and the third insulating layer II3 serves as an interlayer dielectric layer for achieving planarization.

[0053] In other examples of the present disclosure, the positional relationship of each film layer can be determined according to the film layer structure of the thin film transistor. For example, the first metal part MP1 and the second metal part MP2 can be arranged on the side of the first active layer AL1 away from the substrate BP. It can be understood that the drive layer DRL can also adopt other types of film layer structures, and the drive layer DRL can also include other film layers not shown.

[0054] In the present disclosure, the channel region of the first active layer AL1 and the channel region of the second active layer AL2 are optimized so that at least the first active layer AL1 and the second active layer AL2 form a vertical channel, thereby increasing the channel region area of ​​the first active layer AL1 and the channel region area of ​​the second active layer AL2, so that the on-state current can be further increased. In this example, the channel region area of ​​the first active layer AL1 is increased by providing a protrusion or a groove, and the channel region area of ​​the second active layer AL2 is increased by providing a protrusion or a groove.

[0055] Specific:

[0056] In the first embodiment of the present disclosure, see Figure 4 , the channel region of the first active layer AL1 has a first protrusion BP1 along a direction away from the substrate BP, and the channel region of the second active layer AL2 has a second protrusion BP2 along a direction away from the substrate BP. In this way, the channel region of the first active layer AL1 forms a vertical channel, and the channel region of the second active layer AL2 forms a vertical channel. In this way, the present disclosure increases the area of ​​the channel region of the first active layer AL1 and the channel region of the second active layer AL2 (increasing the width-to-length ratio of the transistor) through the first protrusion BP1 of the channel region of the first active layer AL1 and the second protrusion BP2 of the channel region of the second active layer AL2. The increase in the area of ​​the channel region allows more carriers to pass through the transistor at the same time, thereby increasing the on-state current. In addition, since the larger the width-to-length ratio of the transistor, the larger the current passing through, therefore, under the premise of meeting the current demand, the transistor can be made smaller by adopting the solution in the present disclosure, which can significantly improve the aperture ratio of the display panel PNL. In addition, in the present disclosure, a vertical channel transistor is used, and the channel region is in the vertical direction, so the lateral space occupied by the transistor is reduced, and the pixel density can be correspondingly increased to meet the high-resolution requirements. At the same time, the short channel effect caused by the shortening of the channel can be alleviated; the channel is less affected by bending or tensile stress, and is particularly suitable for flexible application environments. And the present disclosure uses a dual-channel transistor, which can obtain a relatively high mobility and on-state current.

[0057] In one embodiment of the present disclosure, a first protrusion and a second protrusion are formed by setting a support portion. In one example, a first support portion SDP1 is provided between the channel region of the first active layer AL1 and the substrate BP, and the channel region of the first active layer AL1 forms a first protrusion BP1 at the first support portion SDP1, and a second support portion SDP2 is provided between the channel region of the second active layer AL2 and the first insulating layer II1, and the channel region of the second active layer AL2 forms a second protrusion BP2 at the second support portion SDP2. In the present disclosure, the first support portion SDP1 is provided to form the first protrusion BP1 in the channel region of the first active layer AL1, and the second support portion SDP2 is provided to form the second protrusion BP2 in the channel region of the second active layer AL2, which is convenient for preparation and easy to control the setting positions of the first protrusion BP1 and the second protrusion BP2.

[0058] In one embodiment of the present disclosure, the first support part SDP1 is made of inorganic material, and the thickness of the first support part SDP1 is 3000-10000A; or the first support part SDP1 is made of organic material, and the thickness of the first support part SDP1 is 5000-30000A; the second support part SDP2 is made of inorganic material, and the thickness of the second support part SDP2 is 3000-10000A; or the second support part SDP2 is made of organic material, and the thickness of the second support part SDP2 is 5000-30000A. With this thickness, the splitting phenomenon caused by the first support part SDP1 and the second support part SDP2 being too thin will not occur, and the phenomenon of multiple preparations caused by the first support part SDP1 and the second support part SDP2 being too thick will not occur.

[0059] In one example, the material of the first support part SDP1 is the same as the material of the second support part SDP2, and the thickness of the first support part SDP1 is the same as the thickness of the second support part SDP2, so that the uniformity of the current in the two channel regions can be achieved. For example, the material of the first support part SDP1 and the material of the second support part SDP2 are both inorganic materials, and the thickness of the first support part SDP1 and the thickness of the second support part SDP2 are both 3000A. For another example, the material of the first support part SDP1 and the material of the second support part SDP2 are both inorganic materials, and the thickness of the first support part SDP1 and the thickness of the second support part SDP2 are both 5000A. For another example, the material of the first support part SDP1 and the material of the second support part SDP2 are both inorganic materials, and the thickness of the first support part SDP1 and the thickness of the second support part SDP2 are both 8000A. For another example, the material of the first support part SDP1 and the material of the second support part SDP2 are both inorganic materials, and the thickness of the first support part SDP1 and the thickness of the second support part SDP2 are both 10000A. For another example, the material of the first support part SDP1 and the material of the second support part SDP2 are both organic materials, and the thickness of the first support part SDP1 and the thickness of the second support part SDP2 are both 5000A. For another example, the material of the first support part SDP1 and the material of the second support part SDP2 are both organic materials, and the thickness of the first support part SDP1 and the thickness of the second support part SDP2 are both 10000A. For another example, the material of the first support part SDP1 and the material of the second support part SDP2 are both organic materials, and the thickness of the first support part SDP1 and the thickness of the second support part SDP2 are both 18000A. For another example, the material of the first support part SDP1 and the material of the second support part SDP2 are both organic materials, and the thickness of the first support part SDP1 and the thickness of the second support part SDP2 are both 25000A. For another example, the material of the first support part SDP1 and the material of the second support part SDP2 are both organic materials, and the thickness of the first support part SDP1 and the thickness of the second support part SDP2 are both 30000 A. Of course, the first support part SDP1 and the second support part SDP2 can also have other thicknesses not listed above.

[0060] In other examples, the thickness of the first supporting portion SDP1 and the thickness of the second supporting portion SDP2 may also be different.

[0061] In another example, the materials of the first supporting part SDP1 and the second supporting part SDP2 may be different. For example, the material of the first supporting part SDP1 is an inorganic material, and the thickness of the first supporting part SDP1 is 3000A, and the material of the second supporting part SDP2 is an organic material, and the thickness of the second supporting part SDP2 is 5000A. For another example, the material of the first supporting part SDP1 is an inorganic material, and the thickness of the first supporting part SDP1 is 8000A, and the material of the second supporting part SDP2 is an organic material, and the thickness of the second supporting part SDP2 is 10000A. For another example, the material of the first supporting part SDP1 is an inorganic material, and the thickness of the first supporting part SDP1 is 10000A, and the material of the second supporting part SDP2 is an organic material, and the thickness of the second supporting part SDP2 is 28000A. On the contrary, for another example, the material of the first support part SDP1 is an organic material, the thickness of the first support part SDP1 is 5000A, the material of the second support part SDP2 is an inorganic material, and the thickness of the second support part SDP2 is 3000A. For another example, the material of the first support part SDP1 is an organic material, the thickness of the first support part SDP1 is 10000A, the material of the second support part SDP2 is an inorganic material, and the thickness of the second support part SDP2 is 8000A. For another example, the material of the first support part SDP1 is an organic material, the thickness of the first support part SDP1 is 28000A, the material of the second support part SDP2 is an inorganic material, and the thickness of the second support part SDP2 is 10000A. Of course, the first support part SDP1 and the second support part SDP2 may also have other thicknesses not listed above.

[0062] In other examples, the thickness of the first supporting portion SDP1 and the thickness of the second supporting portion SDP2 may also be the same.

[0063] In one embodiment of the present disclosure, the area of ​​the channel region of the second active layer AL2 is equal to the surface area of ​​the channel region of the first active layer AL1, so as to facilitate the uniformity of the currents of the two channels.

[0064] In one embodiment of the present disclosure, the first support part SDP1 is independently prepared, and the second support part SDP2 is independently prepared. In other embodiments, the first support part SDP1 is independently prepared, and the second support part SDP2 can be prepared in the same layer as the second insulating layer II2II2, so that the preparation process can be reduced and the preparation cost can be reduced.

[0065] In one embodiment of the present disclosure, the orthographic projection of the first support portion SDP1 on the substrate BP coincides with the orthographic projection of the second support portion SDP2 on the substrate BP, which simplifies the preparation process and achieves uniformity of the two channel currents.

[0066] In one embodiment of the present disclosure, the number of the first support parts SDP1 can be multiple, and the number of the second support parts SDP2 can be multiple. In this example, the number of the first support parts SDP1 is 1, and the number of the second support parts SDP2 is 1. In other examples, the number of the first support parts SDP1 is 3, and the number of the second support parts SDP2 is 3. Of course, the number of the first support parts SDP1 and the number of the second support parts SDP2 can also be other numbers not listed.

[0067] Based on the structure of the driving layer DRL, the present disclosure provides a method for preparing the driving layer DRL, comprising the following steps:

[0068] S01, depositing a source-drain metal layer SD on a substrate BP, and patterning it to form a first metal portion MP1 and a second metal portion MP2;

[0069] S02, preparing a first supporting layer, and patterning it to form a first supporting portion SDP1;

[0070] S03, sequentially depositing and preparing a first active layer AL1, a first gate insulating layer GI1 and a first gate G1;

[0071] S04, using a self-aligned structure to implement doping of the first electrode and the second electrode of the first active layer AL1;

[0072] S05, depositing and preparing a first insulating layer II1;

[0073] S06, preparing a second supporting layer, and patterning it to form a second supporting portion SDP2;

[0074] S07, preparing via holes on the first insulating layer II1, wherein one via hole exposes at least a portion of the first pole of the first active layer AL1, and the other via hole exposes at least a portion of the second pole of the first active layer AL1;

[0075] S08, depositing in sequence a second active layer AL2, a second gate insulating layer GI2, and a second gate G2;

[0076] S09, implementing doping of the first electrode and the second electrode of the second active layer AL2 by using a self-aligned structure;

[0077] S010, preparing a third insulating layer II3 by deposition.

[0078] In other embodiments of the present disclosure, the source-drain metal layer SD may also be disposed on a side of the first semiconductor layer SCL1 away from the substrate BP (the first metal portion MP1 and the second metal portion MP2 are disposed on a side of the first active layer AL1 away from the substrate BP). For example, the source-drain metal layer SD may be located between the first semiconductor layer SCL1 and the second semiconductor layer SCL2 (the first metal portion MP1 and the second metal portion MP2 may be located between the first active layer AL1 and the second active layer AL2). For example, the source-drain metal layer SD may be located on a side of the second semiconductor layer SCL2 away from the substrate BP (the first metal portion MP1 and the second metal portion MP2 are disposed on a side of the second active layer AL2 away from the substrate BP).

[0079] In the second embodiment of the present disclosure, see Figure 5 The driving layer DRL further comprises a second insulating layer II2, which is located between the source-drain metal layer SD and the substrate BP. The second insulating layer II2 serves as a buffer layer to prevent the substrate BP from affecting the transistor device.

[0080] In this example, the channel region of the first active layer AL1 has a first groove GR1 arranged in a direction close to the substrate BP, and the channel region of the second active layer AL2 has a second protrusion BP2 arranged in a direction away from the substrate BP. In this way, the channel region of the first active layer AL1 forms a vertical channel, and the channel region of the second active layer AL2 forms a vertical channel, thereby forming a double vertical channel. In this way, by setting the first groove GR1 and the second protrusion BP2, the area of ​​the channel region of the first active layer AL1 and the channel region of the second active layer AL2 can be increased (increasing the width-to-length ratio of the transistor), and the increase in the area of ​​the channel region allows more carriers to pass through the transistor at the same time, thereby increasing the on-state current. In addition, since the larger the width-to-length ratio of the transistor, the larger the current passing through, therefore, under the premise of meeting the current demand, the transistor can be made smaller by adopting the solution in the present disclosure, which can significantly improve the aperture ratio of the display panel PNL.

[0081] In this example, a first groove GR1 is formed by setting a groove on the second insulating layer II2, and a second protrusion BP2 is formed by setting a support portion on the first insulating layer II1. It can be understood that the second insulating layer II2 has a third groove GR3 on one side close to the substrate BP, and the channel region of the first active layer AL1 forms the first groove GR1 at the third groove GR3 by setting the third groove GR3. The first insulating layer II1 has a second support portion SDP2 on one side close to the second active layer AL2, and the channel region of the second active layer AL2 covers the second support portion SDP2, so that the channel region of the second active layer AL2 forms a second protrusion BP2 at the second support portion SDP2.

[0082] In one embodiment of the present disclosure, a portion of the first gate G1 extends into the first groove GR1, thereby forming a fourth groove. In this example, the shadow of the fourth groove on the substrate BP coincides with the orthographic projection of the second support portion SDP2 on the substrate BP. A portion of the second gate G2 extends to the second protrusion BP2, thereby forming a fourth protrusion. The orthographic projection of the fourth protrusion on the substrate BP coincides with the orthographic projection of the third groove GR3 on the substrate BP. In this way, the double-channel transistor forms a symmetrical structure, improves the uniformity of the current, and reduces the difficulty of preparation.

[0083] In one embodiment of the present disclosure, the thickness of the second support portion SDP2 is equal to the depth of the third groove GR3, so that the uniformity of the dual-channel current can be improved. In the present disclosure, equal means that the two are equal within a certain error range.

[0084] Of course, based on the above concept and structure, the present disclosure may also adopt other structures to achieve the same function. For example, the first active layer AL1 has a protrusion, and the second active layer AL2 has a groove. For another example, the first active layer AL1 has a groove, and the second active layer AL2 has a groove. Of course, when the first active layer AL1 has a groove, there is a second insulating layer II2 between the first active layer AL1 and the substrate BP. It can be understood that when the first active layer AL1 has a protrusion (the protrusion is formed by setting the second support portion SDP2), there may also be a second insulating layer II2 between the first active layer AL1 and the substrate BP.

[0085] In one embodiment of the present disclosure, the material of the first active layer AL1 and the material of the second active layer AL2 may both be metal oxides. Of course, in other examples, the first active layer AL1 and the second active layer AL2 may also be made of other materials.

[0086] In one embodiment of the present disclosure, the first support portion SDP1 and the first insulating layer II1 are prepared in the same layer, which can simplify the preparation process.

[0087] In one embodiment of the present disclosure, when the second support portion SDP2 and the second insulating layer II2 are prepared in the same layer, the preparation process can be simplified.

[0088] In one embodiment of the present disclosure, the light-emitting element LD in the pixel layer PIXL is a thin-film light-emitting element, which may include two stacked electrodes and a light-emitting functional unit ELU sandwiched between the two electrodes. For example, the pixel layer PIXL may include a pixel electrode layer PEL, a light-emitting functional layer ELM, and a common electrode layer COML stacked in sequence. Among them, the pixel electrode layer PEL has a plurality of pixel electrodes PE in the display area AA of the display panel PNL; the portion of the light-emitting functional layer ELM connected to the pixel electrode PE serves as the light-emitting functional unit ELU of the light-emitting element LD, and the common electrode layer COML serves as a common electrode electrically connected to the light-emitting functional units ELU of each light-emitting element LD.

[0089] Further, the pixel layer PIXL may also include a pixel definition layer PDL located between the pixel electrode layer PEL and the light-emitting functional layer ELM. The pixel definition layer PDL has a plurality of through pixel openings arranged in one-to-one correspondence with the plurality of pixel electrodes PE, and any one of the pixel openings exposes at least a portion of the corresponding pixel electrode PE. For example, the pixel definition layer PDL covers the edge of the pixel electrode PE and exposes at least a portion of the internal area of ​​the pixel electrode PE, so that the pixel definition layer PDL can effectively define the actual effective area of ​​the pixel electrode PE (the area directly connected to the light-emitting functional unit ELU), thereby defining the light-emitting area and light-emitting area of ​​the light-emitting element LD. The light-emitting functional layer ELM at least covers the pixel electrode PE exposed by the pixel definition layer PDL. The common electrode layer may cover the light-emitting functional layer ELM in the display area AA. The pixel electrode PE and the common electrode layer COML provide carriers such as electrons and holes to the light-emitting functional layer ELM, so that the light-emitting functional layer ELM emits light. The portion of the light-emitting functional layer ELM located between the pixel electrode PE and the common electrode layer COML may serve as a light-emitting functional unit ELU. The pixel electrode PE, the common electrode layer COML, and the light-emitting functional unit ELU form a light-emitting element LD. Among them, one of the pixel electrode PE and the common electrode layer COML serves as the anode of the light-emitting element LD, and the other serves as the cathode of the light-emitting element LD. In one example, the pixel electrode PE serves as the anode of the light-emitting element LD, and the common electrode layer COML serves as the cathode of the light-emitting element LD.

[0090] In one embodiment of the present disclosure, the types of the light emitting elements LD are different, and the materials and film layers of the light emitting functional units are different.

[0091] In this example, the anode is connected to the third metal part MP3 on the source-drain metal layer SD through the via on the third insulating layer II3, the via on the second gate insulating layer GI2, the via on the first insulating layer II1, and the via on the first gate insulating layer GI1, and then connected to the second electrode (the second metal part MP2) of the transistor through the third metal part MP3.

[0092] In one embodiment of the present disclosure, see Figure 3 , the thin film encapsulation layer TFE can be arranged on the surface of the pixel layer PIXL away from the substrate BP, which may include an inorganic encapsulation layer and an organic encapsulation layer alternately stacked. The inorganic encapsulation layer can effectively block external moisture and oxygen, and prevent water and oxygen from invading the pixel layer PIXL and causing aging of the material in the pixel layer PIXL. Optionally, the edge of the inorganic encapsulation layer may be located in the peripheral area. The organic encapsulation layer is located between two adjacent inorganic encapsulation layers to achieve flattening and reduce the stress between the inorganic encapsulation layers. Among them, the edge of the organic encapsulation layer may be located between the edge of the display area and the edge of the inorganic encapsulation layer. Exemplarily, the thin film encapsulation layer TFE includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer sequentially stacked on the side of the pixel layer PIXL away from the substrate BP. Of course, in other embodiments of the present disclosure, the display panel PNL may not be provided with a thin film encapsulation layer, but the pixel layer PIXL may be encapsulated and protected in other ways.

[0093] In some embodiments of the present disclosure, see Figure 3 The display panel PNL may further include a touch buffer layer TSL, which may be disposed on a side of the thin film encapsulation layer TFE away from the driving backplane DBP, so that the display panel PNL has a touch function. Exemplarily, the touch buffer layer TSL includes a touch buffer layer, a first touch metal layer, a touch dielectric layer, and a second touch metal layer sequentially stacked on a side of the thin film encapsulation layer TFE away from the substrate BP.

[0094] It can be understood that the solution in the present disclosure can also be applied to other circuits that require high on-state current.

[0095] In the present disclosure, a vertical channel design is adopted, and the lateral space occupied by the transistor is reduced, and the pixel density can be correspondingly increased to meet the high-resolution requirements. At the same time, the short channel effect caused by the shortening of the channel can be alleviated, and the channel is less affected by bending or tensile stress, which is particularly suitable for flexible application environments.

[0096] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A display panel, characterized in that: A base substrate and a driving layer arranged on the base substrate; The driving layer has at least one transistor, the transistor has a first conductive part, a second conductive part and a metal connecting part; the first conductive part has a first active layer and a first gate, the second conductive part has a second active layer and a second gate, and the metal connecting part has a first metal part and a second metal part; The first metal portion is connected to a first electrode of the first active layer and a first electrode of the second active layer, and the second metal portion is connected to a second electrode of the first active layer and a second electrode of the second active layer; The channel region of the first active layer has at least one first protrusion extending in a direction away from the substrate, or the channel region of the first active layer has at least one first groove extending in a direction close to the substrate; the channel region of the second active layer has at least one second protrusion extending in a direction away from the substrate, or the channel region of the second active layer has at least one second groove extending in a direction close to the substrate.

2. The display panel according to claim 1, characterized in that: The first conductive portion is located between the base substrate and the second conductive portion; The driving layer comprises a first semiconductor layer, a first gate layer, a second semiconductor layer, a second gate layer and a source-drain metal layer located on one side of the base substrate; the first active layer is located in the first semiconductor layer, the second active layer is located in the second semiconductor layer, the first gate is located in the first gate layer, the second gate is located in the second gate layer, and the first metal part and the second metal part are located in the source-drain metal layer; The driving layer further comprises a first insulating layer located between the first conductive portion and the second conductive portion; A first supporting portion is provided on the surface of the base substrate, and a part of the channel region of the first active layer is provided on a side of the first supporting portion away from the base substrate, thereby forming the first protrusion; A second supporting portion is disposed on a surface of the first insulating layer away from the base substrate, and a portion of the channel region of the second active layer is disposed on a side of the second supporting portion away from the base substrate, thereby forming the second protrusion.

3. The display panel according to claim 1, characterized in that: The first conductive portion is located between the base substrate and the second conductive portion; The driving layer comprises a first semiconductor layer, a first gate layer, a second semiconductor layer, a second gate layer and a source-drain metal layer located on one side of the base substrate; the first active layer is located in the first semiconductor layer, the second active layer is located in the second semiconductor layer, the first gate is located in the first gate layer, the second gate is located in the second gate layer, and the first metal part and the second metal part are located in the source-drain metal layer; The driving layer further comprises a first insulating layer and a second insulating layer II2, wherein the first insulating layer is located between the first conductive portion and the second conductive portion, and the second insulating layer II2 is located between the base substrate and the first conductive portion; A second supporting portion is disposed on a surface of the first insulating layer away from the base substrate, and a portion of the channel region of the second active layer is disposed on a side of the second supporting portion away from the base substrate, thereby forming the second protrusion; A surface of the second insulating layer II2 away from the base substrate has a third groove, and a portion of the channel region of the first active layer extends into the third groove, thereby forming the first groove.

4. The display panel according to claim 2 or 3, characterized in that: The second supporting portion is made of inorganic material, and the thickness of the second supporting portion is 3000-10000 Å; or the second supporting portion is made of organic material, and the thickness of the second supporting portion is 5000-30000 Å.

5. The display panel according to claim 2, characterized in that: The first support portion is made of inorganic material, and the thickness of the first support portion is 3000-10000A; or the first support portion is made of organic material, and the thickness of the first support portion is 5000-30000A.

6. The display panel according to claim 2, characterized in that: The second supporting portion is prepared on the same layer as the first insulating layer.

7. The display panel according to claim 2, characterized in that: The thickness of the first supporting portion is equal to the thickness of the second supporting portion.

8. The display panel according to claim 3, characterized in that: The depth of the first groove is equal to the thickness of the second supporting portion.

9. The display panel according to claim 8, characterized in that: The display panel also has a pixel layer located on a side of the driving layer away from the base substrate; The pixel layer includes a pixel electrode, and the pixel electrode is electrically connected to the second metal portion.

10. The display panel according to claim 1, characterized in that: The material of the first active layer is metal oxide, and the material of the second active layer is metal oxide.

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