Manufacturing method for power semiconductor device and power semiconductor device

Abstract

The present disclosure relates to a manufacturing method for a power semiconductor device (20), the manufacturing method comprising: forming at least one insulating layer (3) on a surface (2a) of a crystal growth substrate (2), the at least one insulating layer (3) comprising at least one cavity (4) extending in a lateral direction (22) within the at least one insulating layer (3); selectively growing a wide band gap WBG semiconductor material within the cavity (4) to form a lateral epitaxial layer (9), in which a surface region of the growth substrate (2) exposed by forming at least one channel (5) between the at least one cavity (4) and the growth substrate (2) is used as a seed region for epitaxially growing the WBG semiconductor material; and forming at least one semiconductor junction, in particular a pn junction (6), np junction or Schottky junction (8), within or at an end of the selectively grown WBG semiconductor material. The present disclosure further relates to a power semiconductor device (20) and in particular a MISFET (25).

Description

Technical Field

[0001] The present disclosure relates to a manufacturing method for a power semiconductor device and a corresponding power semiconductor device having an epitaxial layer comprising a wide bandgap semiconductor material. Background Art

[0002] Wide bandgap (WBG) semiconductor materials, such as silicon carbide (SiC), have advantageous properties, including high critical electric field and electron mobility or high frequency switching. As a result, they produce much larger Baliga quality factors (BFOM) than commonly used semiconductor materials, such as silicon, making them good options for power semiconductor devices, such as power MISFETs. These advantages enable several applications for energy efficiency and power transportation. However, the relatively high cost and processing complexity involved in manufacturing power semiconductor devices including epitaxially grown layers (epitaxial layers) of WBG materials limits their application in many fields. Summary of the invention

[0003] Embodiments of the present disclosure relate to a method for manufacturing a power semiconductor device and a corresponding power semiconductor device, the power semiconductor device including a selectively grown lateral epitaxial layer that can be manufactured using less wide bandgap semiconductor material and / or in a shorter time.

[0004] According to a first aspect, a method for manufacturing a power semiconductor device is disclosed. The method comprises:

[0005] - forming at least one insulating layer on a surface of the crystalline growth substrate, the at least one insulating layer comprising at least one cavity extending in a lateral direction within the at least one insulating layer;

[0006] - selectively growing a wide band gap (WBG) semiconductor material within the cavity to form a lateral epitaxial layer, wherein a surface area of ​​the growth substrate exposed by at least one channel formed between the at least one cavity and the growth substrate is used as a seed area for epitaxially growing the WBG material; and

[0007] - forming at least one semiconductor junction, in particular a pn junction, an np junction or a Schottky junction, within the selectively grown WBG semiconductor material or at its ends.

[0008] Among other things, the inventors have found that the amount of WBG material required for manufacturing a power semiconductor device can be reduced if, for example, the WBG material used in the active region of the device is selectively grown rather than etched from a bulk epitaxial layer of the WBG material. In other words, an additive manufacturing method is used rather than a subtractive manufacturing method. The growth of the WBG material can be controlled in a desired direction (e.g., a lateral direction) by at least one insulating layer including a cavity, which serves as a growth template. This also allows the growth of WBG materials, such as 3C, 4H or 6H silicon carbide (SiC), on substrates made of different materials, such as doped or undoped silicon (Si), silicon carbide on silicon, silicon carbide on insulator (SiCOI), sapphire or gallium nitride (GaN), thereby further reducing the amount of WBG material required.

[0009] In at least one embodiment, the at least one channel is configured as a defect filter for the WBG material such that the lateral epitaxial layer is essentially defect-free. The smoother surface of the selectively grown, essentially defect-free WBG structure improves carrier mobility within the grown epitaxial layer compared to the dry-etched epitaxial layer.

[0010] In at least one embodiment, the at least one semiconductor junction is formed by incorporating at least one dopant during the selective growth of the WBG semiconductor material, in particular during the growth of the lateral epitaxial layer. In this way, the growth and doping of the active region can be performed in a single processing step, further simplifying the manufacturing process and allowing for well-defined carrier concentration differences in the corresponding regions of the epitaxial layer, for example corresponding to steps or boxes with respect to the concentration of the at least one dopant. Even more, the manufacturing costs will be greatly reduced by avoiding ion implantation and / or high temperature dopant activation processes required by some existing WBG semiconductor manufacturing methods.

[0011] In at least one embodiment, the step of forming at least one insulating layer includes: forming a first dielectric layer, in particular a first silicon dioxide layer, on the surface of the growth substrate; forming at least one hole in the first dielectric layer to form the at least one channel; depositing and structuring a sacrificial material in a region corresponding to the at least one cavity; forming a second dielectric layer, in particular a second silicon dioxide layer, on the first dielectric layer and the sacrificial material; and removing the sacrificial material to form the at least one cavity between the first dielectric layer and the second dielectric layer. In this way, the cavity forming the growth template can be formed using well-established semiconductor processing steps and environments, such as CMOS industrial reactors used to process conventional non-WBG semiconductor wafers (e.g., 200 mm silicon wafers).

[0012] According to a second aspect, a power semiconductor device is disclosed. The device comprises:

[0013] - a substrate comprising a first material;

[0014] - at least one insulating layer arranged on the surface of the substrate and comprising at least one cavity, said at least one cavity extending in a lateral direction within said at least one insulating layer;

[0015] - at least one channel formed between the at least one cavity and the substrate;

[0016] - at least one epitaxial layer comprising a second material, a first portion of the at least one epitaxial layer extending in a lateral direction in the at least one cavity, and at least a second portion of the at least one epitaxial layer extending in a vertical direction through the opening to contact the first material, wherein the second material is a wide bandgap (WBG) semiconductor material different from the first material; and

[0017] - At least one semiconductor junction, in particular a pn junction, an np junction or a Schottky junction, is formed within the at least one epitaxial layer or at an end thereof.

[0018] Such devices combine the favorable electrical properties of epitaxial layers comprising WGB semiconductor materials with the simple connectivity of lateral power semiconductor devices (such as lateral power MOSFETs) and the use of substrates formed from different, potentially cheaper bulk materials.

[0019] The disclosed structure provides a significant improvement in device capabilities compared to existing power semiconductor devices. Among other things, it allows to circumvent mobility degradation, which is a major problem in conventional SiC MOSFETs. The high density of interface states in SiC MOS structures limits the potential of WBG materials. In contrast, the potentially very high surface area to volume ratio of the proposed lateral epitaxial layer increases the channel density of, for example, MOSFETs and reduces the off-state current, thus providing lower static power consumption.

[0020] In at least one embodiment, the first material includes at least one of doped silicon (Si), undoped Si, 4H, 6H or 3C silicon carbide (SiC) (e.g., cubic silicon carbide on silicon (3C-on-Si)), silicon carbide on insulator (SiCOI), semi-insulating silicon carbide, sapphire or gallium nitride (GaN). Alternatively or in addition, the second material includes at least one of 3C, 4H or 6H silicon carbide. Alternatively or in addition, the at least one insulating layer includes silicon dioxide. The above materials are suitable for established semiconductor manufacturing processes and include several advantageous properties, such as low cost or good insulating properties, compared to devices including only a single WBG material. Therefore, those materials allow economical manufacturing of power semiconductor devices having epitaxial layers including WBG semiconductor materials.

[0021] In at least one embodiment, the first portion of the at least one epitaxial layer extends by 5 to 10 μm in the lateral direction and / or the first portion of the at least one epitaxial layer extends by 0.1 to 0.5 μm in the vertical direction. Alternatively or additionally, the first portion of the at least one epitaxial layer extends by a first length in the lateral direction that exceeds 10 times or more the depth of the cavity in the lateral direction, resulting in an extremely high surface area to volume ratio of the proposed lateral epitaxial layer.

[0022] Alternatively or additionally, the power semiconductor device comprises a plurality of lateral portions of the at least one epitaxial layer and / or a plurality of channels formed between the at least one cavity and the substrate, wherein the pitch distance of the plurality of lateral portions and / or the plurality of channels is respectively in the range of 50 to 5000 nm, such as 50 to 500 nm. For example, the active area of ​​each cell of the multi-cell semiconductor device may comprise a dense array of grown platelets, wherein the diameter and pitch of the platelets are only tens to hundreds of nanometers.

[0023] In at least one embodiment, a power semiconductor device includes a lateral drift structure, wherein the lateral drift structure includes at least a first section of a first portion of the at least one epitaxial layer, the first section including a first dopant to form a first type of semiconductor material, in particular an n-type WBG semiconductor material. When grown on a suitable substrate, such as a high purity semi-insulating (HPSI) substrate, a lateral drift layer of only a few μm is sufficient to block voltages up to 1 kV.

[0024] In at least one embodiment, the power semiconductor device comprises a lateral and / or vertical npn structure comprising the at least one semiconductor junction formed in the at least one epitaxial layer. In addition, the cavity allows the formation of both lateral and / or vertical npn structures, depending on the needs of the intended power semiconductor device.

[0025] In at least one embodiment, the power semiconductor device includes at least two lateral drift structures and / or lateral npn or pnp structures, wherein the at least two lateral drift structures and / or lateral npn or pnp structures are connected in at least one of a back-to-back or series manner. This enables high current or high voltage to be distributed across multiple active structures by electrically connecting individual structures (such as switching cells of a multi-cell switching device) in parallel or in series, respectively.

[0026] In at least one embodiment, the power semiconductor device includes a metal insulator semiconductor field effect transistor (MISFET), in particular one of a lateral superjunction MISFET, an IGBT or an AccuFET. The MISFET includes at least one of the following: at least one gate electrode partially or completely encloses the at least one epitaxial layer, in particular a central portion of a lateral npn structure or a vertical npn structure formed therein; at least one source region arranged at a first lateral end and / or in a central section of the epitaxial layer; and at least one drain region arranged in a central section and / or at a second lateral end of the epitaxial layer. Among other things, the described design uses a gate that is at least partially wrapped around a selectively grown epitaxial layer to achieve excellent gate control. The connection of such a wrapped gate results in a thicker inversion charge layer, which can improve the inversion channel carrier mobility by reducing Coulomb scattering, for example at the gate dielectric / SiC interface trap. This in turn leads to an additional boost in drain current density. It also allows the elimination of the conventionally used p+ plug, e.g. for grounding the well region in advanced process level SiC MOSFETs.

[0027] In at least one alternative embodiment, the power semiconductor device includes a lateral power diode.

[0028] In at least one embodiment, the power semiconductor devices have a voltage class or rating of 0.6 to 1.2 kV per device.Such devices may be used, for example, in inverters and other power control circuits of electric vehicles (EVs).

[0029] The manufacturing method according to the first aspect above is particularly suitable for manufacturing a power semiconductor device according to the second aspect. Therefore, the features and advantages described in conjunction with the method can be used in the device and vice versa. Therefore, each feature described in relation to one of the aspects is also disclosed in this document in relation to another aspect, even if the corresponding feature is not explicitly mentioned in the context of a particular aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The accompanying drawings are included to provide further understanding. In the drawings, elements with the same structure and / or function may be referenced by the same reference numerals, even if they are not identical in all respects. It will be understood that the embodiments shown in the drawings are only illustrative representations and are not necessarily drawn to scale.

[0031] Figure 1 is a schematic cross section through a semiconductor device having a selectively grown WBG epitaxial layer.

[0032] Figures 2 to 8 A perspective view showing processing steps of a method for manufacturing a power semiconductor device.

[0033] Fig. 9 A perspective view of a finished power semiconductor device including a plurality of cells is shown.

[0034] Fig.10 A schematic cross section through a semiconductor device having lateral and / or vertical channel regions formed in a selectively grown epitaxial layer is shown.

[0035] Fig.11 Another perspective view of a power semiconductor device having multiple cells is shown. DETAILED DESCRIPTION

[0036] Before describing specific power semiconductor devices and processing steps in detail, we first refer to Figure 1 To describe the selective growth of lateral epitaxial layers (epitaxial layers).

[0037] Figure 1 A semiconductor structure 1 is shown, which includes a substrate 2 and a main surface 2a (in Figure 1 Insulating layer 3 is formed on the top surface 3a of substrate 2. Insulating layer 3 is formed a cavity 4. Cavity 4 is connected to surface 2a of substrate 2 by means of channel 5. Cavity 4 further extends to two openings 7a and 7b leading to top surface 3a of insulating layer 3.

[0038] A suitable WBG material (such as 3CSiC) can be grown on a suitable substrate 2 (such as a Si substrate) and at low temperature to form an epitaxial growth layer 9. The crystalline material of the substrate 2 is used as a seed material for forming an epitaxial layer 9 selectively grown in the cavity 4. For example, chemical vapor deposition (CVD) can be used to introduce the growth material through the openings 7a and / or 7b. During epitaxy, the insulating layer 2 in which the cavity 4 is formed is used as a hollow growth mask for the WBG material and allows the epitaxial layer 9 to be selectively grown to a shape and size suitable for forming a power semiconductor device.

[0039] The growth starts from the seed region 10 at the bottom of the channel 5 and then first extends in the vertical direction to form a first vertical portion 11 of the epitaxial layer 9. Once the growth front reaches a larger lateral portion of the cavity 4, the growth extends laterally in both directions to form lateral portions 12 of the epitaxial layer 9. Once the growing material reaches the respective lateral ends of the cavity 4, the growth extends again in the vertical direction to form respective second vertical portions 13a and 13b of the epitaxial layer 9, which extend towards the openings 7a and 7b, respectively.

[0040] Preferably, the seed region 10 of the surface 2a exposed by the channel 5 is kept relatively small. For example, it may have a diameter of 10 to 500 nm. If the seed region 10 is small so that the wide bandgap material growth starts only from a single growth seed, defects due to the lattice mismatch between the growing WBG material of the epitaxial layer 9 and the material of the substrate 2 can be avoided. Even if there are some defects (for example, due to the larger opening of the channel 5), such defects can be filtered out in the first vertical portion 11 before the WBG material reaches the larger lateral portion 12 of the epitaxial layer 9, which is used to form the active portion of the finished semiconductor device, as described later. Therefore, the channel 5 effectively acts as a defect filter, resulting in an almost defect-free lateral portion 12 of the epitaxial layer 9 and the second vertical portions 13a and 13b.

[0041] In the described example, the substrate 2 may be a wafer formed of doped or undoped silicon (e.g., Si(001), Si(011), or Si(111)). The substrate 2 may also be formed of another crystalline material, such as a hexagonal crystal (e.g., hexagonal SiC, such as 4H or 6H SiC). Alternatively, the substrate may also be formed of or include other crystalline materials, such as gallium nitride (GaN), Ga2O3, semi-insulating (S) materials, such as SiC (on-axis), or Si-face or C-face SiC substrates. GaN, 3C SiC, 4HSiC, Ga2O3, or diamond may be used as suitable wide bandgap materials for selectively growing the epitaxial layer 9.

[0042] Figure 1 It is further shown that two semiconductor junctions are formed in or at the ends of the selectively grown epitaxial layer 9. In particular, a pn or np junction 6 is formed in the lateral portion 12, near the second vertical portion 13a. In addition, a Schottky junction 8 is formed between the upper end of the second vertical portion 13b and the metal material of the electrode 19 formed thereon. In order to form such junctions, any dopant and therefore any desired doping level can be combined along the growth direction during the selective growth of the epitaxial layer, as described in detail below.

[0043] Figures 2 to 8 It is shown in more detail how a corresponding semiconductor structure 1 may be formed.

[0044] Figure 2 A first stage of the manufacturing process is shown, in which a first dielectric layer 14 has been formed on the top surface 2a of the substrate 2. For example, a SiO2, Si3N4, Al2O3 or similar dielectric layer may be formed on a silicon or SiC substrate. At this stage, holes 15 are formed in the first dielectric layer 14, which holes will later form the channels 5. The holes 15 may be formed, for example, by dry etching.

[0045] although Figure 2 Although not shown, more than one hole 15 may be formed at a given pitch. Multiple holes may be used to simultaneously form multiple seed regions 10 for one or more cells of a semiconductor device, as described later.

[0046] Figure 3 Deposition of a sacrificial layer 16 is shown over the previously formed dielectric layer 14. The sacrificial layer 16 may include amorphous silicon (a-Si), carbon, or another suitable material.

[0047] Figure 4 FIG. 1 shows the formation of a growth template 17. Figure 4 As shown in the figure, a growth template 17 is formed by dry etching a portion of a previously formed sacrificial layer 16. The growth template 17 corresponds to the lateral portion 12 of the epitaxial layer 9 to be formed later by selective growth. As shown, the growth template 17 can take the form of a plate or a small flake (in particular a nano flake). Alternatively, the growth template 17 can also take the form of one or more interconnected strips, fins or wires, in particular a tree-shaped nanowire network (not shown).

[0048] Figure 5 The formation of a second dielectric layer 18 or cover is shown in the region of the growth template 17. Effectively, the second dielectric layer 18 covers the remaining sacrificial material of the growth template 17 on the top and side surfaces to completely embed the growth template 17 between the first dielectric layer 14 and the second dielectric layer 18. Similar to the first dielectric layer 14, the second dielectric layer 18 can be formed of SiO2, Si3N4, Al2O3 or other suitable insulating materials.

[0049] Figure 6 The formation of various openings in the second dielectric layer 18 is shown. Such openings can be formed using dry etching. These openings may correspond to terminal regions of the finished power semiconductor device, or may be auxiliary openings that allow the introduction of growth material into a cavity formed later. In the example described, two opposing first openings 7a correspond to the source regions of the dual MOSFET structure, while two second openings 7b correspond to the corresponding drain openings. The second openings 7b are arranged in the central portion of the growth template 17, in the middle of the two opposing first openings 7a.

[0050] Figure 7 Removal of the sacrificial material of the growth template 17 is shown. At this stage, a cavity 4 is formed within the insulating material of the first dielectric layer 14 and the second dielectric layer 18. This can be achieved, for example, by etching the sacrificial material using TMAH, KOH, XeF2 or similar etchants, which can be introduced through the openings 7a and 7b.

[0051] exist Figure 8In the step shown in FIG. 1 , the cavity 4 is filled with a suitable WBG material to form an epitaxial layer 9 therein. This is achieved by: Figure 8 The WBG material is selectively grown starting from the cavity 4 (which is no longer visible in FIG. 1 ), and then continues to grow through the cavity 4 until the growth front reaches the corresponding openings 7a and 7b. Such growth can be achieved, for example, using conventional semiconductor processing methods (such as CVD).

[0052] During growth, dopants may be introduced into the evaporated WBG material to form regions of increasing or decreasing carrier concentration as desired. Because the growth front of the WBG material follows the channel defined by the cavity 4, the step or box function of the dopant profile is well defined, as described later with respect to a specific power semiconductor device.

[0053] Fig. 9 A power semiconductor device 20 including a plurality of cells 21 is shown. Specifically, Fig. 9 The power semiconductor device 20 shown in FIG. 1 includes a total of four device units 21, which are arranged in parallel on the top surface 2a of the substrate 2. Each of the device units 21 includes the same Figures 2 to 8 The semiconductor structure described is similar to semiconductor structure 1. Since each of the device units 21 has essentially the same structure, the device units can be processed and grown in parallel using conventional semiconductor processing methods, potentially using different materials.

[0054] Fig. 9 It is further shown that each of the semiconductor structures extends primarily along a first lateral direction corresponding to the x-axis over a much greater length than along an orthogonal second lateral direction corresponding to the x-axis or a vertical direction 24 corresponding to the z-axis.

[0055] As described later, each of the cells 21 implements a dual MISFET structure connected back-to-back in the drain region 27. If the corresponding opposing source regions 31 are electrically connected in parallel, the voltage drop is spread over half the length of the lateral structure, and the current is halved.

[0056] Furthermore, to distribute even greater currents, individual device units 21 may be connected in parallel to allow for switching of higher currents. This is advantageous, among other things, for manufacturing power semiconductor devices having relatively high operating voltages (e.g., in the range of 600V to 1.2kV) and / or currents (e.g., in the range of 10 to 1000A per device).

[0057] Fig.10A cross section through a particular power semiconductor device is shown, the power semiconductor device being in the form of a MISFET 25. The MISFET 25 comprises: a semi-insulating substrate 2, which is formed, for example, of high purity semi-insulating (HPSI) silicon carbide (SiC); and an insulating layer 3, such as a SiO2 layer. The substrate 2 may be the actual growth substrate of the MISFET 25, or may be another substrate for supporting the insulating layer 3 of the MISFET 25. A plurality of lateral nanowires and / or a plurality of lateral nanosheets have been selectively grown in the cavities 4 of the insulating layer 3, such as described above with respect to Figures 2 to 9 Described in detail.

[0058] Fig.10 It is shown that two independent switching structures are formed in two parts of the epitaxial layer 9 selectively grown from two independent channels 5. The two switching structures differ in the configuration of the respective pnp structures 28 and 29 implementing the respective switching functions. Although not shown, depending on the materials used and the desired active structure, an npn structure (not shown) can also be implemented in the epitaxial layer 9. Please note the following facts: Fig.10 The particular architecture shown in FIG. 2 is for explanation only, and in a typical power semiconductor device, the two portions of the MISFET 25 may have similar or even identical configurations.

[0059] Each of the switching structures comprises a drift region 26 which is doped with charge donors to form n-type charge transfer elements in the epitaxial layer 9. - The drift region 26 may have a length l of 5 to 10 μm and a thickness d of 0.1 to 0.5 μm. In the central portion between the two channels 5, n + The drain region 27 is formed by doping the region. In the depicted embodiment, the drain region 27 is overgrown by the WBG material of the corresponding drift region 26. The other part of the drain region 27 is connected to the drain electrode, which is located at Fig.10 Outside the visible cross section.

[0060] exist Fig.10 In the left hand side of the lateral npn structure 28 is shown. The lateral npn structure 28 comprises, from right to left: a first lateral end of the drift region 26, which is located in the vertical portion of the epitaxial layer 9; a channel region 30, which is also arranged in the vertical portion of the epitaxial layer 9; and another n-doped portion of the epitaxial layer 9 forming a source region 31, which starts in the lateral portion of the epitaxial layer 9 and further extends into its second vertical portion 13a. A gate electrode 32 is arranged on top of the channel region 30, above the cavity 4, and is used to selectively switch the channel region 30 from a conductive state to a non-conductive state or vice versa.

[0061] exist Fig.10 In the right-hand side of the embodiment, a vertical npn structure 29 is shown, which is arranged in the second vertical portion 13b of the epitaxial layer 9. The vertical npn structure 29 includes the following from bottom to top: a second lateral end of the corresponding drift layer 26; a positively doped channel region 30; and a source region 31, which is formed at or near the top surface 3a of the insulating layer 3. The channel region 30 is surrounded by a gate electrode 32. In the depicted embodiment, the second vertical portion 13b of the epitaxial layer 9 and the channel region 30 itself form a relatively thin structure (similar to a nanowire). In addition, the gate electrode 32 surrounds the channel region 30 on all sides, which allows the switching response of the vertical npn structure 29 to be particularly fast.

[0062] It should be noted that the length of the channel region 30 of the lateral npn structure 28 along the lateral direction and the length of the channel region 30 of the vertical npn structure 29 along the corresponding vertical direction are shorter than the length of the corresponding drift layer 26 along the vertical direction. In the depicted embodiment, the length of the channel region 30 may be in the range of 100 to 1000 nm, while the length of the drift layer 26 may be in the range of 1 μm to 30 μm.

[0063] It should be further noted that in the described embodiment, the drift region 26 is configured as an n-type semiconductor material. For example, a relatively low concentration of dopants can be used during the selective growth of the drift region 26. On the other hand, the source region 31 is configured as an n-type semiconductor material. For example, a higher concentration of dopants can be used during the selective growth of the source region 31. Therefore, the respective np and pn junctions of the npn structures 29 and 30 are asymmetric because the drift layer 26 has a lower dopant concentration than the respective source region 31.

[0064] exist Fig.10 In the embodiment shown in FIG, a passivation layer 33 formed of an insulating material covers the source region 31 and the overgrown portion of the drain region 27. In addition, since the lateral npn structure 28 and the vertical npn structure 29 use a common drain electrode 26, they can be connected in parallel to obtain a higher current. It is also possible that they form part of a switching bridge between the corresponding source region 31 and the common drain region 27, i.e., are connected in series. Although Fig.10 Not shown in FIG. 4 , the drain region 27 may, however, also be located in the upper part of the cavity 4 , so that the corresponding drift region 26 is directly connected.

[0065] Fig.11 Another embodiment of a power semiconductor device 20 is shown in the form of a MISFET having a plurality of cells 21. Fig.11In the embodiment shown in FIG. 1 , a total of eight cells 21 are formed in an array structure, each cell including a lateral epitaxial layer 9. Each of the cells 21 is configured with a lateral npn structure 28, as described above with respect to FIG. Fig.10 The respective gate electrodes 32 may be switched individually or may be formed as a common gate strip (not shown). The connections to the central drain region 27 and the source region 31 at the lateral ends of the cell 21 are also not shown.

[0066] Fig.11 The dimensions of a power semiconductor device that can be used in a voltage range of 600 V to 1.2 kV are further shown. In particular, the drift region 26 extends over a length l from about 1 μm to 30 μm and has a width w of about 1 μm. The drift region 26 may have a height (not shown) of 0.1 to 0.5 μm. Thus, the lateral portions 12 of the epitaxial layer essentially form nanosheets of WBG material. Instead of nanosheets, fins or nanowires may also be used.

[0067] The described lateral WBG epitaxial layer can be used in different types of power semiconductor devices, such as superjunction MISFETs and / or AccuFETs. In addition, instead of an npn structure, a single pn or np junction can be implemented in the epitaxial layer to obtain a power diode. In addition, such a pn junction can also be replaced with a Schottky junction. In this case, the WBG semiconductor can extend all the way to a metal electrode formed on one or both of its lateral ends.

[0068] Unlike conventional (i.e., non-power) semiconductor devices, power semiconductor devices need to be able to block relatively high voltages in the so-called third quadrant (i.e., under reverse conditions). The device structures and dimensions described above (including a relatively long drift layer with a length in the micrometer range) are useful for achieving such blocking capabilities for voltages of about 1 kV. Therefore, power semiconductor devices may also be defined as including a drift structure suitable for the desired voltage level, preferably in a lateral configuration.

[0069] Although the present disclosure is susceptible to various modifications and alternative forms, the details thereof have been shown by way of example in the drawings and described above. However, it should be understood that it is not intended to limit the present disclosure to the specific embodiments described. On the contrary, it is intended to cover all modifications, equivalents and alternatives falling within the scope of the present disclosure as defined by the appended claims.

[0070] Reference numerals

[0071] 1 Semiconductor structure

[0072] 2 Substrate

[0073] 2a (substrate) surface

[0074] 3. Insulation layer

[0075] 3a (insulating layer) surface

[0076] 4 Cavity

[0077] 5 channels

[0078] 6 pn junction

[0079] 7a, 7b opening

[0080] 8 Schottky junction

[0081] 9 Epitaxial layer

[0082] 10 Seed Area

[0083] 11 First vertical section

[0084] 12 Lateral section

[0085] 13a, 13b second vertical portion

[0086] 14 First dielectric layer

[0087] 15 holes

[0088] 16 Sacrificial Layer

[0089] 17 Growth Template

[0090] 18 Second dielectric layer

[0091] 19 Electrodes

[0092] 20 Power semiconductor devices

[0093] Unit 21

[0094] 25MISFET

[0095] 26 Drift Zone

[0096] 27 Drain region

[0097] 28 lateral npn structure

[0098] 29 vertical npn structure

[0099] 30 Channel area

[0100] 31 Source region

[0101] 32. Gate electrode

[0102] 33 Passivation layer

Claims

1. A method for manufacturing a power semiconductor device (20), the method comprising: - forming at least one insulating layer (3) on a surface (2a) of a crystal growth substrate (2), the at least one insulating layer (3) comprising at least one cavity (4) extending in a lateral direction within the at least one insulating layer (3); - selectively growing a wide band gap (WBG) semiconductor material in the cavity (4) to form a lateral portion (12) of an epitaxial layer (9), the epitaxial layer comprising a lateral drift region (26) located in at least a first section of the lateral epitaxial layer (9), wherein a surface region of the growth substrate (2) is used as a seed region (10) for epitaxially growing the WBG semiconductor material, the surface region being exposed by at least one channel (5) formed between the at least one cavity (4) and the growth substrate (2), and the first section of the lateral portion (12) of the epitaxial layer (9) comprises a first dopant to form a first type of WBG semiconductor material, in particular an n-type WBG semiconductor material; and - forming at least one semiconductor junction, in particular a pn junction (6), an np junction or a Schottky junction (8), within or at an end of the selectively grown WBG semiconductor material.

2. The method according to claim 1, wherein: The WBG material includes at least one of 3C, 4H or 6H silicon carbide SiC.

3. The method according to claim 1 or 2, wherein: The growth substrate (2) comprises at least one of the following: doped silicon Si, undoped Si, 4H, 6H or 3C SiC, in particular cubic silicon carbide on silicon, silicon carbide on insulator SiCOI, semi-insulating silicon carbide, sapphire or gallium nitride.

4. The method according to any one of claims 1 to 3, wherein: The opening and / or length of the at least one channel (5) is selected such that the at least one channel (5) acts as a defect filter for the WBG material by filtering out any defects resulting from a lattice mismatch between the crystalline growth substrate (2) and the WBG material before the selectively grown WBG material reaches the lateral portion (12) of the epitaxial layer (9).

5. The method according to any one of claims 1 to 4, wherein: During the selective growth of the WBG material, dopants are introduced into the evaporated WBG material to form regions with increased or decreased carrier concentration.

6. The method according to claim 5, wherein: - the step of selectively growing a WBG semiconductor material in the cavity (4) further comprises: selectively growing a vertical portion (13a) of the epitaxial layer (9); and - The step of forming at least one semiconductor junction comprises forming a pn or np junction (6) within the lateral epitaxial layer (9) and close to a vertical portion (13a) of the epitaxial layer (9).

7. The method according to any one of claims 1 to 6, comprising: - forming n-type lateral epitaxial layers (9) by doping the first section of the WBG semiconductor material with a charge donor - area to form the lateral drift area (26).

8. The method according to any one of claims 1 to 7, wherein: The at least one semiconductor junction is formed by incorporating at least one dopant during selective growth of the WBG semiconductor material, in particular during growth of lateral portions (12) of the epitaxial layer (9).

9. The method according to claim 8, wherein: The dopant profile used during the selective growth of the WBG semiconductor material comprises at least one step or box regarding the concentration of the at least one dopant.

10. The method according to any one of claims 1 to 9, wherein: The step of forming at least one insulating layer (3) comprises: - forming a first dielectric layer (14), in particular a first silicon dioxide layer, on the surface (2a) of the growth substrate (2); - forming at least one hole (15) in said first dielectric layer (14) to form said at least one channel (5); - depositing and structuring a sacrificial material in a region corresponding to the at least one cavity (4); - forming a second dielectric layer (18), in particular a second silicon dioxide layer, on said first dielectric layer (14) and said sacrificial material; and - removing the sacrificial material to form the at least one cavity (4) between the first dielectric layer (14) and the second dielectric layer (18).

11. The method according to any one of claims 1 to 10, wherein: - the power semiconductor device (20) comprises a metal insulator semiconductor field effect transistor (MISFET) (25), in particular one of a lateral superjunction MISFET, an IGBT or an AccuFET; - in the step of selectively growing the WBG semiconductor material, growing a lateral drift region (26) of the MISFET (25); and - the at least one semiconductor junction is formed as part of a lateral npn structure (28), a lateral pnp structure, a vertical npn structure (29) or a vertical npn structure of the MISFET (25).

12. The method according to claim 11, further comprising the steps of: - forming at least one gate electrode (32), said at least one gate electrode (32) completely or partially surrounding said selectively grown WBG semiconductor material.

13. The method according to claim 11 or 12, further comprising at least one of the following steps: - forming a source region (31) at a first lateral end and / or in a central section of the lateral portion (12) of the epitaxial layer (9); and / or - forming a drain region (27) in a central section and / or at a second lateral end of the lateral portion (12) of the epitaxial layer (9).

14. A power semiconductor device (20), comprising: - a substrate (2) comprising a first material; - at least one insulating layer (3) arranged on the surface (2a) of the substrate (2) and comprising at least one cavity (4), the at least one cavity (4) extending in a lateral direction within the at least one insulating layer (3); - at least one channel (5) formed between the at least one cavity (4) and the substrate (2); - at least one epitaxial layer (9) comprising a second material, a first portion (12) of the at least one epitaxial layer (9) extending in the at least one cavity (4) along the lateral direction, and at least a second portion (11) of the at least one epitaxial layer (9) extending in the vertical direction through the channel (5) to contact the first material, wherein the second material is a wide bandgap (WBG) semiconductor material different from the first material; - a lateral drift region (26), wherein the lateral drift region (26) comprises at least a first section of a first part (12) of the at least one epitaxial layer (9), the first section comprising a first dopant to form a first type of semiconductor material, in particular an n-type WBG semiconductor material; and - at least one semiconductor junction, in particular a pn junction (6), an np junction or a Schottky junction (8), is formed within the at least one epitaxial layer (9) or at the end of the at least one epitaxial layer (9).

15. The power semiconductor device (20) according to claim 14, wherein: - the first material comprises at least one of the following: doped silicon Si, undoped Si, 4H, 6H or 3C silicon carbide, in particular cubic silicon carbide on silicon, silicon carbide on insulator SiCOI, semi-insulating silicon carbide, sapphire or gallium nitride; - the second material comprises at least one of 3C, 4H or 6H SiC; and / or - The at least one insulating layer (3) comprises at least one of SiO2, Si3N4 or Al2O3.

16. The power semiconductor device (20) according to claim 14 or 15, wherein: - the first portion (12) of the at least one epitaxial layer (9) extends in the lateral direction by 1 to 30 μm, preferably by 5 to 10 μm; - the first portion (12) of the at least one epitaxial layer (9) extends in the vertical direction by 0.1 to 0.5 μm; and / or The first portion (12) of the at least one epitaxial layer (9) extends in the lateral direction by a first length which exceeds the depth of the cavity (4) in the vertical direction (24) by 10 times or more.

17. The power semiconductor device (20) according to any one of claims 14 to 16, wherein: The lateral drift region (26) has a length of 5 to 10 μm and / or a thickness of 0.1 to 0.5 μm.

18. The power semiconductor device (20) according to any one of claims 14 to 17, wherein: - The power semiconductor device (20) comprises a plurality of lateral portions of the at least one epitaxial layer (9) and / or a plurality of channels (5) formed between the at least one cavity (4) and the substrate (2), wherein a pitch distance of the plurality of lateral portions and / or the plurality of channels (5) is respectively in the range of 50 to 5000 nm.

19. The power semiconductor device (20) according to any one of claims 14 to 18, comprising: - a lateral npn structure (28) and / or a vertical npn structure (29), said lateral npn structure (28) and / or vertical npn structure (29) comprising said at least one semiconductor junction formed in said at least one epitaxial layer (9).

20. The power semiconductor device (20) according to claim 19, wherein: The lateral npn structure (28) and / or the vertical npn structure (29) comprises: - an np junction between an n-type semiconductor material forming the lateral drift region (26) and a p-type semiconductor material forming the channel region (30); and - a pn junction between a p-type semiconductor material forming the channel region (30) and an n-type semiconductor material forming the source region (31); - wherein the dopant concentration in the source region (31) is higher than the dopant concentration in the lateral drift region (26).

21. The power semiconductor device (20) according to claim 19 or 20, comprising at least two lateral drift regions (26) and / or lateral npn structures (28), wherein: The at least two lateral drift structures (26) and / or lateral npn structures (28) are connected in at least one of a back-to-back manner or a series manner.

22. The power semiconductor device (20) according to claim 21, wherein: The at least two lateral drift regions (26) and / or the lateral npn structure (28) form part of a switching bridge between the respective source region (31) and a common drain region (27).

23. The power semiconductor device (20) according to any one of claims 14 to 22, wherein: The power semiconductor device (20) comprises a metal insulator semiconductor field effect transistor (MISFET) (25), in particular one of a lateral superjunction MISFET, an IGBT or an AccuFET, wherein the MISFET (25) comprises at least one of the following: at least one gate electrode (32, 36) partially or completely enclosing the at least one epitaxial layer (9), in particular enclosing a central part of a lateral npn structure (28) or a vertical npn structure (29) formed in the at least one epitaxial layer; - at least one source region (31) arranged at a first lateral end of the epitaxial layer (9); and - at least one drain region (27) arranged at a second lateral end or in a central section of the epitaxial layer (9).

24. The power semiconductor device (20) according to any one of claims 14 to 23, wherein: The power semiconductor devices have a voltage rating or value of 0.6 to 1.2 kV per device.

Images