MOSFET device

Abstract

Semiconductor devices and methods, including metal oxide silicon field effect transistor (MOSFET) devices and methods. A semiconductor device, such as a MOSFET, includes two source regions; a drain region; two main body areas; and a buffer region. Each of the two body regions is in contact with a different one of the two source regions. The buffer area is located between the two main body areas and makes contact with the two main body areas. The doping concentration of the buffer region is smaller than the doping concentration of the two main body regions.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices, and more particularly to metal oxide semiconductor field effect transistor (MOSFET) devices. Background Art

[0002] A MOSFET is an insulated gate field effect transistor that includes an intrinsic or parasitic body diode. MOSFET devices have many electrical characteristics or parameters. An example characteristic of a MOSFET is the reverse recovery charge (Q RR ). MOSFET’s Q RR It is related to the switching speed of MOSFETs in typical motor drive applications or DC-DC converters. During commutation when driving an inductive load, the MOSFET operates in the third quadrant, when the source-to-drain PN junction diode conducts and charge is injected into the epitaxial layer. When the device is turned off, the injected charge needs to be dissipated. Therefore, a large amount of reverse recovery charge (Q RR ) may slow down the turn-off of the device, reducing efficiency due to power dissipation, or the drain voltage may increase before the charge is removed, damaging the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The present invention can be more fully understood through the following examples with reference to the accompanying drawings:

[0004] Figure 1 is a cross-sectional view of an example power MOSFET;

[0005] Figure 2 is a cross-sectional view of another example power MOSFET;

[0006] Figure 3 Yes Description Figure 1 An example of a line graph of the intrinsic body diode characteristics of a power MOSFET;

[0007] Figure 4 Yes Description Figure 2 An example of a line graph of the intrinsic body diode characteristics of a power MOSFET;

[0008] Figure 5 It is a cross-sectional view of the intermediate structure of manufacturing power MOSFET;

[0009] Figure 6 is another cross-sectional view of the intermediate structure for manufacturing a power MOSFET;

[0010] Figure 7 is another cross-sectional view of the intermediate structure for manufacturing a power MOSFET;

[0011] Figure 8is another cross-sectional view of the intermediate structure for manufacturing a power MOSFET;

[0012] Fig. 9 is another cross-sectional view of the intermediate structure for manufacturing a power MOSFET;

[0013] Fig.10 is another cross-sectional view of the intermediate structure for manufacturing a power MOSFET;

[0014] Fig.11 is another cross-sectional view of the intermediate structure for manufacturing a power MOSFET;

[0015] Fig.12 is another cross-sectional view of the intermediate structure for manufacturing a power MOSFET;

[0016] Fig.13 is another cross-sectional view of the intermediate structure for manufacturing a power MOSFET;

[0017] Fig.14 is a flow chart illustrating a method of manufacturing a power MOSFET;

[0018] Fig.15 It is marked with axis A Figure 2 A cross-sectional view of an example power MOSFET;

[0019] Fig.16 Yes Description Figure 2 A line graph of relative doping concentrations in an example power MOSFET;

[0020] Fig.17 It is marked with axis A Figure 1 A cross-sectional view of an example power MOSFET; and

[0021] Fig.18 Yes Description Figure 1 A line graph of relative doping concentrations in an example power MOSFET.

[0022] Brief Description

[0023] Semiconductor devices and methods, including MOSFET devices and methods. The semiconductor device (such as MOSFET) includes two source regions, a drain region, two body regions and a buffer region. Each of the two body regions contacts a different source region of the two source regions. The buffer region is located between the two body regions and contacts the two body regions. The doping concentration of the buffer region is less than the doping concentration of the two body regions. DETAILED DESCRIPTION

[0024] Some embodiments provide a MOSFET. The MOSFET includes two source regions, a drain region, two body regions and a buffer region. Each of the two body regions contacts a different source region of the two source regions. The buffer region is located between the two body regions and contacts the two body regions. The doping concentration of the buffer region is less than the doping concentration of the two body regions.

[0025] In certain embodiments, the buffer region extends deeper into the epitaxial layer than each of the two body regions. In certain embodiments, the two body regions include p-type material, and the buffer region includes another p-type material, and the p-type material of the buffer region is less doped than the p-type material of the two body regions. In certain embodiments, the body diode of the MOSFET includes the buffer region. In certain embodiments, the body diode of the MOSFET includes a PN junction between the epitaxial layer of the MOSFET and the buffer region. In certain embodiments, when the source region and the drain region are reverse biased, the PN junction between the buffer region and the epitaxial layer of the MOSFET forms a depletion layer. In certain embodiments, when the source region and the drain region are reverse biased, the reverse recovery charge in the PN junction between the buffer region and the epitaxial layer of the MOSFET recombine to form a depletion layer.

[0026] Some embodiments provide a method for manufacturing a MOSFET. A doping material is implanted into a chip (bare die) between two main regions to form a buffer region between the two main regions. The buffer region has a lower doping level than the two main regions.

[0027] In certain embodiments, the buffer region extends deeper into the epitaxial layer than the two main body regions. In certain embodiments, the two main body regions include p-type material, and the buffer region includes another p-type material, and the p-type material of the buffer region is less doped than the p-type material of the two main body regions. In certain embodiments, the buffer region constitutes a part of the body diode of the MOSFET. In certain embodiments, the buffer region constitutes a part of the body diode of the MOSFET, and the body diode includes a PN junction between the buffer region and the epitaxial layer of the MOSFET. In certain embodiments, when the source region and the drain region of the MOSFET are reverse biased, the PN junction between the buffer region and the epitaxial layer of the MOSFET forms a depletion layer. In certain embodiments, when the source region and the drain region of the MOSFET are reverse biased, the reverse recovery charge in the PN junction between the buffer region and the epitaxial layer of the MOSFET is recombined to form a depletion layer.

[0028] Certain embodiments provide a semiconductor device. The semiconductor device includes a source and a drain. A diode of the semiconductor device is located between the source and the drain, and includes a buffer region located between two main regions. At least one of the two main regions is in contact with the source. The buffer region is doped less than the two main regions.

[0029] In some embodiments, the buffer region extends deeper into the epitaxial layer than the two main regions. In some embodiments, the main region includes a p-type material doped to a first doping concentration, and the buffer region includes a p-type material doped to a second doping concentration, the second doping concentration being lower than the first doping concentration. In some embodiments, the diode constitutes an intrinsic diode of the MOSFET. In some embodiments, the diode includes a PN junction between the buffer region and the epitaxial region. In some embodiments, when the source and drain are reverse biased, the PN junction between the buffer region and the epitaxial region forms a depletion layer.

[0030] Various embodiments of the present invention will now be described in detail, examples of which are illustrated in the accompanying drawings. Although the present invention will be described in conjunction with these embodiments, it will be appreciated that these embodiments are not intended to limit the present invention to these embodiments. On the contrary, the present invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the present invention as defined by the appended claims. In addition, in the following detailed description of the present invention, many specific details are listed to provide a thorough understanding of the present invention. However, those of ordinary skill in the art will recognize that the present invention may be implemented without these specific details. In other cases, well-known methods, procedures, components and circuits are not described in detail to avoid unnecessarily obscuring various aspects of the present invention.

[0031] Certain terms used in the following description are for convenience only and are not limiting. The words "right", "left", "top" and "bottom" indicate directions in the accompanying drawings. The words "a" and "an" used in the claims and corresponding parts of the specification are defined to include one or more of the items referred to, unless otherwise specifically stated. The term includes the words specifically mentioned above, their derivatives, and words of similar meanings. The phrase "at least one" followed by a list of two or more items, such as "A, B or C", refers to any one of A, B or C, and any combination thereof. It should be noted that some of the illustrations are partially transparent, which is for the purpose of explanation, illustration and demonstration only, and is not intended to indicate that the element itself is transparent in the final manufacturing form.

[0032] It is to be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may also be referred to as a first element, without departing from the scope of the present invention. The term "and / or" as used herein includes any and all combinations of one or more related listed items.

[0033] It will be understood that when an element (such as a layer, region, substrate, lead, clip, pad, or contact) is referred to as being "on" or "extending to" another element, it can be directly on or directly extending to the other element, or there can be intervening elements. Conversely, when an element is referred to as being "directly on" or "extending directly to" another element, there can be no intervening elements. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there can be intervening elements. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, there can be no intervening elements. It will be understood that these terms are intended to encompass different orientations of the elements in addition to any orientation depicted in the figures.

[0034] Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe the relationship of one element, layer or region to another element, layer or region. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0035] The illustrations are not drawn to scale, and only a portion of the structures and the various layers forming these structures may be shown in the drawings. In general, these illustrations are symbolic simplified structures drawn to convey an understanding of the present invention and are not intended to reproduce the physical structures in detail. In addition, various manufacturing processes and operations may be performed in conjunction with the processes and operations discussed herein; that is, there may be some process operations before, between, and / or after the operations shown and described herein. In addition, embodiments according to the present invention can be implemented in conjunction with these other (possibly conventional) processes and operations without causing significant interference therewith. In general, embodiments according to the present invention can replace and / or supplement a portion of a conventional process without significantly affecting peripheral processes and operations.

[0036] The term "MOSFET" is generally understood as a synonym for insulated gate field effect transistor (IGFET) because many modern MOSFETs include a non-metallic gate and / or a non-oxide gate insulator. As used herein, the term "MOSFET" does not necessarily mean or require that a field effect transistor (FET) includes a metal gate and / or an oxide gate insulator. Instead, the term "MOSFET" includes devices that are generally known or referred to as MOSFETs.

[0037] Throughout the specification and claims of this application, the term "substantially" refers to design intent, not physical results. Semiconductor technology has the ability to measure many aspects of semiconductors with high precision. Therefore, when measured with existing precision, generally speaking, any physical aspect of a semiconductor will not be exactly as designed. In addition, measurement technology can easily identify differences between structures that should be exactly the same. Therefore, terms such as "substantially equal" should be interpreted as equal by design, but subject to manufacturing variations and measurement precision.

[0038] Figure 1 is a cross-sectional view of an example power MOSFET 100. MOSFET 100 is shown as an n-channel enhancement mode MOSFET. It should be noted that the examples herein are described for n-channel enhancement mode MOSFETs, but this is for illustrative purposes only, and the techniques described herein are also applicable to p-channel devices. For example, a p-channel device may have a dopant of the opposite type to the n-channel device example. In some embodiments, a p-channel device has the same regions and the same doping concentration as described in the examples herein, but the dopant type is opposite (e.g., a P- region instead of an N- region, an N+ region instead of a P+ region, etc.). The techniques described herein are also applicable to depletion mode devices, in which applying a gate voltage can turn off the power MOSFET.

[0039] MOSFET 100 is formed in chip (wafer) 150 by implanting and / or diffusing materials (such as dopants) within chip 150 and depositing materials (such as metals and polysilicon) in region 160 on the top surface (upper surface) of chip 150. Wafer 150 is a semiconductor wafer made of any suitable material (such as silicon, silicon carbide, germanium, gallium nitride, and other semiconductors).

[0040] MOSFET 100 includes source region 102, drain region 104, gate region 106, and body region 108. Source region 102 is an n-doped region within body region 108 in wafer 150. Source region 102 is typically heavily doped compared to other n-type regions in MOSFET 100, such as drain region 104. For example, in some embodiments, the dopant concentration of the heavily doped region is between 1×10 18-5×10 20 Atom / cm 3 The drain region 104 is typically an n-doped region of an n-heavy doped substrate, and is used to form a low resistance current path on the side of the wafer 150 opposite to the region 160. The N-region 110 is an n-type material deposited on the substrate 104 as an intermediate layer between the drain region 104 and the n-epitaxial region 118. The doping level of the intermediate layer is slightly lower than that of the substrate (e.g., 30% lower, or less than one-third of it), but the doping level of the intermediate layer is much higher than that of the region 118 in the wafer 150 (e.g., at least one order of magnitude higher). The typical doping level ranges from about 1×10 11 / cm 3 To about 1×10 17 / cm 3 , depending on the maximum voltage that the device needs to handle. N-region 110 acts as a barrier to prevent defects in drain region 104 from entering region 118 , and also prevents outdiffusion of drain region 104 into n-epitaxial region 118 .

[0041] The gate region 106 is a region of polysilicon material located within an oxide region 112 disposed on the surface of the wafer 150 in region 160. The body region 108 is a p-type material well. It should be noted that polysilicon is exemplary. For example, in certain embodiments, the gate region can be implemented using a metal material such as tungsten silicide or aluminum. The doping concentration of the body region 108 is typically several times higher than the doping level in the epitaxial layer 118; for example, one or more orders of magnitude higher in the wafer 150. The source metal 114 can be composed of any suitable conductive material such as aluminum or copper, gold or alloys thereof, and is disposed between the oxide regions 112 in region 160 on the surface of the wafer 150. The source metal 114 forms a contact to the source region 102 and shorts the source region 102 to the p+ region 116 disposed in the body region 108 between the source regions 102. The p+ region 116 is a p-type material region disposed in the wafer 150 between the source regions 102. The P+ region 116 is more heavily doped relative to the body region 108 .

[0042] The body region 108 and the n-epitaxial region 118 share a PN junction and form an intrinsic (also called parasitic) body diode between the source metal 114 and the drain region 104, such as Figure 1 In some embodiments, the P+ region 116 is relatively heavily doped to provide a low resistance to the metal contact to short the emitter (ie, n+ source region 102 ) of the parasitic bipolar transistor to the p body 108 .

[0043] When the source metal 114 and the drain 104 are forward biased and the voltage of the gate 106 is higher than the threshold voltage (i.e., the minimum gate voltage that turns on the MOSFET of an n-channel device), an n-channel is formed in the body 108 below the gate region 106, and current flows between the source region 102 and the drain region 104 through the inversion layer in the body 108 and the n-epitaxial layer 118.

[0044] When the voltage between the source region 102 and the drain 104 switches from a forward bias state to a reverse bias state, and the voltage exceeds the reverse breakdown voltage of the PN junction between the body region 108 and the n-epitaxial region 118, the reverse recovery current (I RR ) flows from the drain 104 through the PN junction between the body region 108 and the n-epitaxial region 118 to the source contact 114 until the charge carriers stored in the PN junction recombine and form a depletion region at the PN junction, thereby blocking the reverse recovery current (or blocking most of the current). The amount of charge that recombines to block the reverse recovery current (or block most of the current) is called the reverse recovery charge (Q RR ), and the time required to block the reverse recovery current (or block most of the current) is called the reverse recovery time (tRR).

[0045] In certain embodiments, it is desirable to minimize, optimize, or reduce the reverse recovery charge (Q) of a power MOSFET. RR ) and / or reverse recovery time (t RR ).

[0046] Figure 2 2 is a cross-sectional view of an example power MOSFET 200. MOSFET 200 is shown as an n-channel enhancement mode MOSFET, except that MOSFET 200 includes a buffer region 270 and the body region 208 is divided as shown. Figure 1 MOSFET 200 is substantially similar to MOSFET 100 shown and described. MOSFET 200 is formed in wafer 250 by implanting and / or diffusing materials (e.g., dopants) in wafer 250 and depositing materials (e.g., metals and polysilicon) in region 260 on the top surface of wafer 250. Wafer 150 is a semiconductor wafer made of any suitable material, such as silicon or silicon carbide.

[0047] MOSFET 200 includes a source region 202, a drain region 204, a gate region 206, and a body region 208. Source region 202 is an n-doped region in wafer 250 that is located within body region 208. Source region 202 is typically heavily doped compared to other n-type regions in MOSFET 200, such as drain region 204. Drain region 204 is an n-doped region implanted in wafer 250 on the side opposite to region 260. N-region 210 is an n-type region in wafer 250 that is located between drain region 204 and n-epitaxial region 218. N-region 210 is more lightly doped than drain region 204.

[0048] The gate region 206 is a region of polysilicon material within the oxide region 212 disposed on the surface of the wafer 250 in region 260. The body region 208 is a well of p-type material within the wafer 250. The source metal 214 is disposed between the oxide regions 212 in the region 260 on the surface of the wafer 250. The source metal 214 forms a contact to the source region 202 and shorts the source region 202 to the p+ region 216 disposed between the body region 208 and between the source regions 202. The p+ region 216 is a region of p-type material disposed in the wafer 250 between the source regions 202. The p+ region 216 is more heavily doped relative to the body region 208.

[0049] The buffer region 270 is a region of p- material implanted between the body region 208 and between the p+ region 216 and the n-epitaxial region 218. The p-type material of the buffer region 270 is more lightly doped than the p+ region 216, thereby forming a high-low junction between the p+ region 216 and the buffer region 270. The p-type material of the buffer region 270 is also more lightly doped than the body region 208. The buffer region 270 and the n-epitaxial region 218 share a PN junction and form part of an intrinsic (also called parasitic) body diode between the source metal 214 and the drain region 204, as shown in FIG. Figure 2 The diode symbol is shown in Figure 2.

[0050] The buffer region 270 can prevent or inhibit the charges (holes in this example) of the p+ region 216 from being over-injected into the n-epi region 218, thereby forming a high-low junction between the p+ region 216 and the buffer region 270. The high-low junction has low efficiency in charge injection into the n-epi region 218. In addition, the buffer region 270 can prevent the breakdown voltage from occurring prematurely, that is, preventing the breakdown voltage from occurring before the body region 208 blocks the premature breakdown between the P+ 216 and the N-Epi 218.

[0051] When the source metal 214 and the drain 204 are forward biased and the voltage of the gate 206 is higher than the threshold, an n-channel is formed in the body 208 under the gate region 206 , and current flows between the source region 202 and the drain region 204 through the inversion layer in the body 208 and the n-epitaxial layer 218 .

[0052] When the voltage on the source region 202 and the drain 204 is switched from the forward bias state to the reverse bias state, and the voltage exceeds the reverse breakdown voltage of the PN junction between the buffer region 270 and the n-epitaxial region 218, the reverse recovery current (I RR ) flows from the drain 204 through the PN junction between the buffer region 270 and the n-epitaxial region 218 to the source contact 214 until the charge carriers stored in the PN junction recombine to form a depletion region at the PN junction, blocking the reverse recovery current (or blocking most of the current). The amount of charge recombined to block the reverse recovery current (or block most of the current) is called the reverse recovery charge (Q RR ), the time required to block the reverse recovery current (or block most of the current) is called the reverse recovery time (t RR ).

[0053] The characteristics of the PN junction of the body diode of the power MOSFET 200 are different from those of Figure 1 The body diode of the power MOSFET 100 shown and described has the characteristics of a PN junction because there are fewer charge carriers available in the buffer region 270 compared to the body region 108. This causes the intrinsic body diode of the power MOSFET 200 to recombine the reverse recovery charge QRR in a shorter time than the intrinsic body diode of the power MOSFET 100, and thus forms a depletion region and blocks most of the reverse recovery current in a shorter time than the power MOSFET 100.

[0054] In other words, since the doping level of the buffer region 270 is higher than that of the Figure 1 The body region 108 of the power MOSFET 100 shown and described is lighter, so the reverse recovery charge (Q RR ) is lower (less). Accordingly, the reverse recovery time (t RR The advantage of this is that the switching speed of the power MOSFET 200 can be increased.

[0055] Figure 3 It is about Figure 1A line graph of the intrinsic body diode characteristics of the illustrated and described example power MOSFET 100. The line graph illustrates the intrinsic body diode function I(t), i.e., the range of current through the intrinsic body diode in the time domain, over a period of time after the intrinsic body diode switches from a forward biased state to a reverse biased state.

[0056] At t0, the intrinsic body diode is forward biased. When the bias of the intrinsic body diode of the power MOSFET 100 switches from forward bias to reverse bias, the forward current I F After t0, the forward current I through the intrinsic body diode of the power MOSFET 100 is F Start decreasing until it reaches 0 volts (amperes).

[0057] At the forward current I F After reaching zero, the reverse current I R begins to flow through the intrinsic body diode (i.e., from the drain 104 to the source 102) because the PN junction of the intrinsic body diode remains on, but the charge carriers in the PN junction of the intrinsic body diode begin to recombine to form a depletion region. As the charge carriers recombine and the depletion region expands, I R It will decrease until it reaches the peak value I R (Also called reverse recovery current I RR ). At the reverse current I R Reverse recovery current I RR After reaching the peak value, the reverse current I R The reverse recovery current decreases, but continues to flow through the intrinsic body diode until the charges stored in the PN junction recombine to form a depletion region and the current flowing through the intrinsic body diode is zero (or close to zero, except for the reverse leakage current). By convention, the reverse recovery current starts to flow through the intrinsic body diode until the reverse recovery current reaches the reverse recovery current I RR After reaching I RR The time from 10% to 10% is called the reverse recovery time (t RR ).

[0058] In certain embodiments, the reverse recovery time (t RR ) is based on the peak reverse recovery current I RR The reverse recovery time t RR During this period, the amount of charge recombined during the formation of the depletion region is called the reverse recovery charge Q RR .

[0059] Figure 4 It is about Figure 2A graph of the characteristics of the intrinsic body diode of the illustrated and described example power MOSFET 200. The graph illustrates the intrinsic body diode function I(t), i.e., the range of current through the intrinsic body diode in the time domain, over a period of time after the intrinsic body diode switches from a forward biased state to a reverse biased state.

[0060] At t0, the intrinsic body diode is forward biased. When the bias of the intrinsic body diode of the power MOSFET 200 switches from forward bias to reverse bias, the forward current I F After t0, the forward current I through the intrinsic body diode of the power MOSFET 200 is F Start decreasing until it reaches 0 volts.

[0061] At the forward current I F After reaching zero, the reverse current I R The charge carriers in the PN junction of the intrinsic body diode begin to recombine to form a depletion region. As the charge carriers recombine and the depletion region expands, I R will decrease until the reverse recovery current I RR . At the reverse current I R The reverse recovery current I RR After reaching the peak value, the reverse current I R The reverse recovery time (t RR ) is considered to be the period from when the reverse recovery current starts to flow through the intrinsic body diode to when the reverse recovery current reaches the reverse recovery current I RR After reaching I RR 10% of the time.

[0062] In certain embodiments, the reverse recovery time (t RR ) is based on the peak reverse recovery current I RR The reverse recovery time t RR During this period, the reverse recovery charge Q RR Recombination occurs during the formation of the depletion region.

[0063] Since the reverse recovery charge (Q RR) is less than (less than) the reverse recovery charge (Q) stored in the PN junction of the intrinsic body diode of the power MOSFET 100. RR )(as described above), therefore, compared to the power MOSFET 100, these charge carriers recombine in a shorter time, and thus form a depletion layer and block the reverse current I in a shorter time. R In some embodiments, this has the advantage of providing a shorter reverse recovery time (t RR ). In some embodiments, this has the benefit of making the switching times faster.

[0064] Figure 5 2 is a cross-sectional view of an intermediate structure 500 for fabricating power MOSFET 200. Intermediate structure 500 includes wafer 250, drain region 204, n-region 210, and n-epitaxial region 218. Barrier material 502 (such as a photoresist material, or in a preferred embodiment, particularly for silicon carbide, the 502 material is a thick layer of deposited oxide, which may be referred to as a hard mask (HM)) is deposited in region 260 on the top surface of wafer 250. Barrier material 502 is disposed on the top surface of wafer 250 in region 260 to selectively prevent dopant material from diffusing into wafer 250.

[0065] Figure 6 2 is a cross-sectional view of an intermediate structure 600 for manufacturing power MOSFET 200. Intermediate structure 600 includes wafer 250, drain region 204, n-region 210, n-epitaxial region 218, and barrier material 502. Figure 6 As shown by the middle arrow, the P-type doping material is implanted into the n-epitaxial region 218 through the gap in the barrier material 502. As shown in the figure, the implanted P-type doping material forms the main body region 208 in the intermediate structure 600. It is worth noting that other main body regions are formed in the wafer 250 as shown. In some embodiments, these regions form part of other devices in the wafer. After the main body region 208 is formed in the intermediate structure 600, in some embodiments, if the barrier material 502 is HM, it is not removed. If the barrier material 502 is a photoresist, it can be removed with a suitable solvent.

[0066] Figure 72 is a cross-sectional view of an intermediate structure 700 for manufacturing a power MOSFET 200. The intermediate structure 700 includes a wafer 250, a drain region 204, an n-region 210, an n-epitaxial region 218, and a body region 208. The etching process leaves behind an oxide spacer (barrier material 702) having a specific base surface (cross-section) of a predetermined size, thereby forming a self-aligned (aligned) channel (channel) region on the top surface of the wafer 250. The barrier material 702 is disposed on the top surface of the wafer 250 in the region 260 to selectively prevent the diffusion of dopant materials into the wafer 250.

[0067] Figure 8 2 is a cross-sectional view of an intermediate structure 800 for manufacturing power MOSFET 200. Intermediate structure 800 includes wafer 250, drain region 204, n-region 210, n-epitaxial region 218, body region 208, and barrier material 702. Figure 8 As shown by the middle arrow, the N-type dopant material is implanted into the body region 208 through the gap in the barrier material 702. As shown in the figure, the implanted n-type dopant material forms the source region 202 in the intermediate structure 800. It is worth noting that other source regions are also formed in the wafer 250. In some embodiments, these regions form part of other devices in the wafer. After the source region 202 is formed in the intermediate structure 800, the barrier material 702 is removed, for example, by a suitable solvent.

[0068] Fig. 9 2 is a cross-sectional view of an intermediate structure 900 for fabricating power MOSFET 200. Intermediate structure 900 includes wafer 250, drain region 204, n-region 210, n-epitaxial region 218, body region 208, and source region 202. Barrier material 902 (e.g., photoresist material) is deposited in region 260 on the top surface of wafer 250. Barrier material 902 is disposed on the top surface of wafer 250 in region 260 to selectively prevent dopant material from diffusing into wafer 250.

[0069] As indicated by the arrows, the P-type dopant material is implanted into the n-epitaxial region 218 between the body regions 208 through the gaps in the barrier material 902. In a preferred embodiment, the buffer layer implant overlaps (e.g., slightly overlaps) the body layer 208. In some embodiments, the overlap of the buffer layer with the body region has the advantage of improving the breakdown voltage stability and / or lowering (reducing) Qrr as the overlap increases. In some embodiments, the buffer layer implant overlaps the body region, and the overlap does not extend beyond the outer edge of the body region (e.g., the buffer layer 270 does not extend beyond the outer edge of the body region). Fig.11 The right main body area 208 in the embodiment extends further to the right, and will not exceed Fig.11In some embodiments, this has the advantage of avoiding increasing the resistance of the MOSFET.

[0070] Fig.10 2 is a cross-sectional view of an intermediate structure 1000 for manufacturing a power MOSFET 200. The intermediate structure 1000 includes a wafer 250, a drain region 204, an n-region 210, an n-epitaxial region 218, a body region 208, and a source region 202. The buffer region 270 is shown by Fig. 9 The buffer region 270 is formed by implanting the p-type doping material. The p-type doping concentration of the buffer region 270 is lower than that of the main region 208, and is deeper than the main region 208, for example, preferably at least 30% deeper. In some embodiments, the benefit of doing so is to reduce the injection efficiency of the main body. Fig.15 and Fig.16 Detailed description is provided. In some embodiments, the light doping of the buffer region 270 is in contrast to known regions deeper than or associated with the body, which are typically doped as heavily as possible to prevent false triggering of parasitic transistors and / or to improve injection efficiency of the epitaxial layer from the body region. In contrast to the prior art, in some embodiments, the light doping of the buffer region 270 has the advantage of reducing Qrr while mitigating its effects.

[0071] The barrier material 902 remains in place, and further p-type material is implanted through the gaps in the barrier material 902 into the buffer region 270 and the body region 208 , as indicated by the arrows.

[0072] Fig.11 2 is a cross-sectional view of an intermediate structure 1100 for manufacturing power MOSFET 200. Intermediate structure 1000 includes wafer 250, drain region 204, n-region 210, n-epitaxial region 218, body region 208, source region 202, buffer region 270, and p+ region 216, which is formed by Fig.10 The p-type doping concentration of the P+ region 216 is higher than that of the main region 208 , and the p-type doping concentration of the P+ region 216 is higher than that of the buffer region 270 , but shallower than that of the main region 208 and the buffer region 270 .

[0073] Intermediate structure 1100 is shown with barrier material 902 removed using a suitable solvent or the like after forming p+ region 216 .

[0074] Fig.122 is a cross-sectional view of an intermediate structure 1200 for manufacturing a power MOSFET 200. Intermediate structure 1200 includes wafer 250, drain region 204, n-region 210, n-epitaxial region 218, body region 208, source region 202, buffer region 270, p+ region 216, and oxide layer 212, which forms a gate oxide thermally grown in region 260 on the top surface of wafer 250. Any suitable oxide or other insulator can be used in other embodiments. In this example, oxide layer 212 includes silicon dioxide (SiO2). In this example, oxide layer 212 is formed by first forming oxide layer 212A. Gate 206 (preferably polysilicon material) is deposited on oxide layer 212A and etched to a suitable size. Oxide layer 212B is deposited on top of gate 206 and oxide layer 212A to form oxide layer 212.

[0075] Fig.13 is a cross-sectional view of an intermediate structure 1300 for fabricating power MOSFET 200. Intermediate structure 1300 includes wafer 250, drain region 204, n-region 210, n-epitaxial region 218, body region 208, source region 202, buffer region 270, p+ region 216, and oxide layer 212.

[0076] The oxide layer 212 is selectively removed from a portion of the region 260, such as by a mask and etch process or other suitable process, to expose the p+ region 216 and the source region 202. The source metal 214 is deposited in the resulting gap in the oxide layer 212 so that it is deposited on top of the p+ region 216 and the source region 202. The p+ region 216 and the source region 202 are shorted together by the source metal 214. The source metal 214 is deposited by sputtering, vapor deposition, or any other suitable process.

[0077] By masking and etching or other suitable processes, a gate region 206 is grown on top of the field oxide portion of oxide 212, and further oxide 212 is grown on top of gate region 206. Gate region 206 is formed of polysilicon material or any other suitable material.

[0078] Fig.14 is a flow chart illustrating the Figure 5-13 The method for manufacturing a power MOSFET (such as Figure 2 1400 of the method for manufacturing a power MOSFET 200 as shown and described herein. It should be noted that some embodiments omit certain steps, reorder steps, and / or include additional steps.

[0079] In step 1402, a barrier material is deposited onto the surface of the intermediate structure and patterned to expose a region of the chip (intermediate structure) for implanting p-type dopants to form a body region in the chip for fabricating a power MOSFET.

[0080] In some embodiments, the intermediate structure includes wafer 250, drain region 204, n-region 210, and n-epitaxial region 218, as described with respect to Figure 5 As shown and described, a barrier material is deposited on the top surface of wafer 250 in region 260 to selectively prevent diffusion of dopant material into wafer 250, as described with respect to Figure 5 Shown and described.

[0081] In a preferred embodiment, the blocking material comprises silicon dioxide that is patterned and etched using a photoresist process. The photoresist is removed and the oxide layer remains as a hard mask (HM). In certain embodiments, this has the advantage of defining self-aligned areas relative to this layer by adding another oxide deposit layer and performing a so-called "spacer etch" (commonly referred to in the art as a spacer etch) to achieve the self-alignment capability of two independent implant layers.

[0082] In step 1404, a p-type material is implanted into the exposed regions of the intermediate structure to form a body region in the chip. After the body region is formed in the intermediate structure, the barrier material (HM) is not removed.

[0083] In some embodiments, the intermediate structure includes wafer 250, drain region 204, n-region 210, n-epitaxial region 218, and barrier material 502, as described with respect to Figure 6 As shown and described. Figure 6 As shown by the arrow in the figure, a p-type dopant material is implanted into the n-epitaxial region 218 through the gap in the barrier material 502. As shown, the implanted p-type dopant material forms the body region 208 in the intermediate structure 600. It is worth noting that other body regions are formed in the wafer 250 as shown. In some embodiments, these regions form part of other devices in the wafer.

[0084] In step 1406, a barrier material (preferably silicon dioxide) is deposited on top of the original HM defined in step 1404 and on the surface of the intermediate structure, and the barrier material is patterned by a spacer etching process (in some embodiments, a "dry" or plasma etching) to expose the area of ​​the chip for implanting n-type dopants to form the source region in the chip. In some embodiments, this has the advantage of aligning the n-source with the body region, thereby precisely controlling the channel length of the MOSFET.

[0085] In certain embodiments, such as Figure 7 As shown and described, the intermediate structure includes wafer 250, drain region 204, n-region 210, n-epitaxial region 218, and body region 208, and a barrier material (e.g., an oxide material) is deposited in region 260 on the top surface of wafer 250. The barrier material is disposed in region 260 on the top surface of wafer 250 and on top of the HM of step 1404 to selectively prevent dopant material from diffusing into wafer 250.

[0086] In step 1408, an n-type material is implanted into the exposed regions of the intermediate structure to form a source region in the chip. After the source region is formed in the intermediate structure, the blocking material is removed using a suitable solvent or the like.

[0087] In some embodiments, the intermediate structure includes wafer 250, drain region 204, n-region 210, n-epitaxial region 218, body region 208, and barrier material 702, as described with respect to Figure 8 As shown and described. Figure 8 As shown by the middle arrow, the n-type doping material is implanted into the main region 208 through the gap in the blocking material 702. The implanted n-type doping material forms the source region 202 in the intermediate structure, as shown in FIG. Figure 8 It is worth noting that other source regions are also formed in the wafer 250 as shown. In some embodiments, these regions form part of other devices in the wafer.

[0088] In step 1410, a barrier material is deposited onto the surface of the intermediate structure and the barrier material is patterned to expose an area of ​​the chip for implanting a p-type dopant to form a buffer region in the chip. Fig. 9 As shown and described, the intermediate structure includes wafer 250, drain region 204, n-region 210, n-epitaxial region 218, body region 208, and source region 202. A barrier material, such as a photoresist material, is deposited in region 260 on the top surface of wafer 250. The barrier material is disposed on the top surface of wafer 250 in region 260 to selectively prevent dopant material from diffusing into wafer 250.

[0089] In step 1412, a p-type dopant material is implanted into the exposed region of the intermediate structure to form a buffer region in the chip. Fig.10 As shown and described, p-type dopant material is implanted into n- epitaxial regions 218 between body regions 208 through gaps in barrier material 902 as indicated by arrows.

[0090] In step 1414, further p-type material is implanted into the exposed regions of the intermediate structure to form p+ regions in the chip, and the barrier material is removed using a suitable solvent or the like. Fig.10 As shown and described, further p-type material is implanted into the buffer region 270 and the body region 208 through the gaps in the barrier material 902 as indicated by the arrows to produce about Fig.11 Intermediate structures shown and described.

[0091] In step 1416, an insulator is thermally grown or deposited at high temperature on the surface of the intermediate structure. In some embodiments, any suitable oxide or other insulator may be used. In this example, the insulator includes silicon dioxide (SiO2). In some embodiments, as described with respect to Fig.12 As shown and described, the intermediate structure includes wafer 250, drain region 204, n- region 210, n-epitaxial region 218, body region 208, source region 202, buffer region 270, p+ region 216, and the insulator is an oxide layer 212 grown in region 260 on the top surface of wafer 250. After the oxide is thermally grown or deposited, a polysilicon layer is defined and patterned to form the gate of the MOSFET.

[0092] In step 1418, the insulator is patterned and etched to expose the source region and the p+ region, and in step 1420, metal is deposited onto the exposed source region and the p+ region to form a source contact and short the source region and the p+ region together. A gate region is formed on the thermally grown or deposited insulator by etching the deposited polysilicon layer to form the gate of the MOSFET. In some embodiments, as described with respect to Fig.13 As shown and described, the intermediate structure includes a wafer 250, a drain region 204, an n-region 210, an n-epitaxial region 218, a body region 208, a source region 202, a buffer region 270, a p+ region 216, and an oxide layer 212. For example, by a mask and etch process or other suitable process, an insulator (such as oxide layer 212) is selectively removed from a portion of region 260 to expose the p+ region 216 and the source region 202. A source metal 214 is deposited in the gap created thereby in the oxide layer 212 so that it is deposited on top of the p+ region 216 and the source region 202. The p+ region 216 and the source region 202 are shorted together by the source metal 214. The source metal 214 is deposited by sputtering, vapor deposition, or any other suitable process. By a mask and etch process or other suitable process, a gate region 206 is grown on top of the field oxide portion of the oxide 212, and further oxide 212 is grown on top of the gate region 206. The gate region 206 is formed of polysilicon material or any other suitable material.

[0093] Fig.15 About Figure 2 A cross-sectional view of an example power MOSFET 200 is shown and described with axis A labeled therein and relative doping types and concentrations of layers 216, 270, 218, 210, 204. Axis A passes through layers 216, 270, 218, 210, 204, respectively.

[0094] Fig.16 is to illustrate that the MOSFET 200 along Fig.15 2 is a line graph of relative doping concentrations in various regions along axis A of . The line graph illustrates the relative doping concentrations (expressed on a logarithmic scale) of regions 216, 270, 218, 210, and 204, respectively. Between each region along the axis is a transition region where the doping concentration gradually changes. For example, segment W of the line graph represents the transition region between regions 216 and 270. Segment X of the line graph represents the transition region between regions 270 and 218. Segment Y of the line graph represents the transition region between regions 218 and 210. Segment Z of the line graph represents the transition region between regions 210 and 204. It is noteworthy that the doping concentration transition between the buffer region 270 and the epitaxial region 218 (as shown in the segment X in the figure) is relatively small (minimal).

[0095] The minimum transition shown in the X segment causes the reverse recovery charge (Q RR ) is relatively lower (less than) a power MOSFET that does not have this characteristic. Accordingly, the reverse recovery time (t RR The advantage of this is that the switching speed of the power MOSFET 200 can be increased.

[0096] For ease of comparison, Fig.18 is to illustrate that MOSFET 100 along Fig.17 1 is a line graph of relative doping concentrations in various regions along axis A. The line graph illustrates the relative doping concentrations (expressed on a logarithmic scale) of regions 116, 108, 118, 110, and 104, respectively.

[0097] Between each region along the axis is a transition region where the doping concentration gradually changes. For example, segment Q of the line graph represents the transition region between regions 116 and 108. Segment R of the line graph represents the transition region between regions 108 and 118. Segment S of the line graph represents the transition region between regions 118 and 110. Segment T of the line graph represents the transition region between regions 110 and 104. It is worth noting that, as with respect to Fig.15 and Fig.16 As shown and described, the R segments represent a relatively greater transition in doping concentration between the body region 108 and the epitaxial region 118 compared to the X segments.

[0098] The relatively large transition represented by the R segment causes the reverse recovery charge (Q RR ) is relatively larger (greater) than the power MOSFET 200. Accordingly, the reverse recovery time (t RR ) is also relatively large (longer). Therefore, in some embodiments, the switching speed of power MOSFET 100 is slower than that of power MOSFET 200.

[0099] It should be understood that there are many variations according to what is disclosed herein. Although features and elements are described above in particular combinations, each feature or element can be used alone without other features and elements, and can also be used in various combinations with or without other features and elements.

Claims

1. A metal oxide silicon field effect transistor (MOSFET), comprising: two source regions; Drain region; two body regions, each of the two body regions being in contact with a different one of the two source regions; as well as a buffer region, the buffer region being disposed between the two main body regions and contacting the two main body regions; Wherein, the doping concentration of the buffer region is less than the doping concentration of the two main regions.

2. The MOSFET according to claim 1, wherein: The buffer region extends deeper into the epitaxial layer than each of the two body regions.

3. The MOSFET according to claim 1, wherein: The two body regions include a p-type material, and the buffer region includes another p-type material having a doping concentration lower than that of the p-type material of the two body regions.

4. The MOSFET according to claim 1, wherein: The body diode of the MOSFET includes the buffer region. 5 . The MOSFET of claim 1 , a body diode of the MOSFET comprising a PN junction between the buffer region and an epitaxial layer of the MOSFET.

6. The MOSFET according to claim 1, wherein: When the source region and the drain region are reverse biased, a PN junction between the buffer region and the epitaxial layer of the MOSFET forms a depletion layer.

7. The MOSFET according to claim 1, wherein: When the source region and the drain region are reverse biased, reverse recovery charges in a PN junction between the buffer region and an epitaxial layer of the MOSFET are recombined to form a depletion layer.

8. A method of manufacturing a metal oxide silicon field effect transistor (MOSFET), the method comprising: implanting a doping material into the chip between the two main regions to form a buffer region disposed between the two main regions; Wherein, the doping concentration of the buffer region is less than the doping concentration of the two main regions.

9. The method according to claim 8, wherein: The buffer region extends deeper into the epitaxial layer than the two body regions.

10. The method according to claim 8, wherein: The two body regions include a p-type material, and the buffer region includes another p-type material having a doping concentration lower than that of the p-type materials of the two body regions.

11. The method according to claim 8, wherein: The buffer region constitutes a portion of a body diode of the MOSFET.

12. The method according to claim 8, wherein: The buffer region constitutes a portion of a body diode of the MOSFET, the body diode comprising a PN junction between the buffer region and an epitaxial layer of the MOSFET.

13. The method according to claim 8, wherein: When the source region and the drain region of the MOSFET are reverse biased, a PN junction between the buffer region and the epitaxial layer of the MOSFET forms a depletion layer.

14. The method according to claim 8, wherein: When the source region and the drain region of the MOSFET are reverse biased, reverse recovery charges in a PN junction between the buffer region and an epitaxial layer of the MOSFET recombine to form a depletion layer.

15. A semiconductor device comprising: source; as well as Drain; The diode disposed between the source and the drain of the semiconductor device includes a buffer region disposed between two body regions, and at least one body region of the two body regions is in contact with the source; Wherein, the doping concentration of the buffer region is less than the doping concentration of the two main regions.

16. The semiconductor device according to claim 15, wherein: The buffer region extends deeper into the epitaxial layer than the two body regions.

17. The semiconductor device according to claim 15, wherein: The body region includes a p-type material doped to a first dopant concentration, and the buffer region includes a p-type material doped to a second dopant concentration that is lower than the first dopant concentration.

18. The semiconductor device according to claim 15, wherein: The diode constitutes the intrinsic diode of the metal oxide semiconductor field effect transistor (MOSFET).

19. The semiconductor device according to claim 15, wherein: The diode includes a PN junction between the buffer region and the epitaxial region.

20. The semiconductor device according to claim 15, wherein When the source and the drain are reverse biased, a PN junction between the buffer region and the epitaxial region forms a depletion layer.

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