Electric field enhancement type shield grid MOSFET and manufacturing method thereof

Abstract

The invention provides an electric field enhancement type shield gate MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), which comprises a substrate, an epitaxial layer formed on the substrate, a gate trench formed on a cellular region on the epitaxial layer, and a first gate dielectric layer formed at the bottom of the gate trench and a first polycrystalline silicon layer located in the first gate dielectric layer, a P-type epitaxial layer is formed on the first gate dielectric layer and the first polycrystalline silicon layer, and an isolation dielectric layer is formed on the P-type epitaxial layer; a second gate dielectric layer is formed on the side wall of the residual gate trench, and a second polycrystalline silicon layer is formed in the residual gate trench; a well region and a source region of a cellular region are formed on the epitaxial layer, and a contact hole dielectric layer is formed on the epitaxial layer; and contact holes communicated with the well region are formed on the contact hole dielectric layer and the epitaxial layer below the contact hole dielectric layer. By adding the shield grid P-type epitaxial layer, the electric field intensity in the middle of the drift region is effectively improved, the breakdown voltage is improved, and meanwhile, the conduction loss can be further reduced by adjusting epitaxy.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an electric field enhanced shielded gate MOSFET and a manufacturing method thereof. Background Art

[0002] The shielded gate MOSFET structure of the prior art is as follows Figure 1 As shown, the structures corresponding to the reference numerals include:

[0003] 1: silicon substrate and epitaxial layer; 2: shielding gate thick dielectric layer; 3: gate oxide dielectric layer; 4: second polysilicon; 5: well injection; 6: source injection; 7: contact hole dielectric layer; 8: first polysilicon; 9: isolation dielectric layer between first and second polysilicon;

[0004] In the prior art shielded gate MOSFET structure, the electric field in the drift region is concentrated at the bottom and the top, and the field strength in the middle of the drift region is relatively weak.

[0005] In order to solve the above problems, it is necessary to propose a novel electric field enhanced shielded gate MOSFET and a manufacturing method thereof. Summary of the invention

[0006] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide an electric field enhanced shielded gate MOSFET and a manufacturing method thereof, so as to solve the problem in the prior art that the electric field in the drift region of the shielded gate MOSFET structure is concentrated at the bottom and top, and the field strength in the middle of the drift region is relatively weak.

[0007] To achieve the above-mentioned and other related purposes, the present invention provides an electric field enhanced shielded gate MOSFET, comprising:

[0008] A substrate, an epitaxial layer is formed on the substrate, a gate trench is formed on a cell region on the epitaxial layer, a first gate dielectric layer and a first polysilicon layer located in the first gate dielectric layer are formed at the bottom of the gate trench;

[0009] A P-type epitaxial layer is formed on the first gate dielectric layer and the first polysilicon layer, and an isolation dielectric layer is formed on the P-type epitaxial layer;

[0010] A second gate dielectric layer is formed on the sidewalls of the remaining gate trench, and a second polysilicon layer is formed in the remaining gate trench;

[0011] A well region and a source region of the cell region are formed on the epitaxial layer, and a contact hole dielectric layer is formed on the epitaxial layer;

[0012] A contact hole connected to the well region is formed on the contact hole dielectric layer and the epitaxial layer therebelow.

[0013] Preferably, the MOSFET further comprises: the gate trench formed in the P-type epitaxial lead-out region, the first gate dielectric layer formed at the bottom of the gate trench in the P-type epitaxial lead-out region, and the first polysilicon layer located in the first gate dielectric layer.

[0014] Preferably, the MOSFET further comprises: forming the P-type epitaxial layer filling the gate trench in the P-type epitaxial lead-out region.

[0015] Preferably, the MOSFET further comprises: the contact hole dielectric layer also covers the P-type epitaxial lead-out region; and a contact hole connected to the P-type epitaxial layer in the P-type epitaxial lead-out region.

[0016] Preferably, the MOSFET further comprises: forming the P-type epitaxial layer having the same thickness as that in the cell region in the P-type epitaxial lead-out region and the isolation dielectric layer filling the remaining gate trench.

[0017] Preferably, the MOSFET further comprises: the contact hole dielectric layer also covers the P-type epitaxial lead-out region; and a contact hole connected to the first polysilicon layer.

[0018] The present invention also provides a method for manufacturing the above-mentioned electric field enhanced shielded gate MOSFET, comprising:

[0019] Step 1, providing a substrate, forming an epitaxial layer on the substrate, forming a gate trench on a cell region on the epitaxial layer, wherein a first gate dielectric layer and a first polysilicon layer located in the first gate dielectric layer are formed at the bottom of the gate trench;

[0020] Step 2: forming a P-type epitaxial layer on the first gate dielectric layer and the first polysilicon layer, and then forming an isolation dielectric layer on the P-type epitaxial layer;

[0021] Step 3, forming a second gate dielectric layer on the sidewalls of the remaining gate trenches, and then forming a second polysilicon layer filling the remaining gate trenches;

[0022] Step 4: forming a well region and a source region of the cell region on the epitaxial layer by ion implantation, and forming a contact hole dielectric layer on the epitaxial layer;

[0023] Step 5: forming a contact hole connected to the well region on the contact hole dielectric layer and the epitaxial layer thereunder.

[0024] Preferably, the method for forming the gate trench in step one includes: forming a hard mask layer on the substrate; opening the hard mask layer by photolithography and etching to define the formation position of the gate trench; forming the gate trench by etching; forming the first gate dielectric layer located in the gate trench; forming the first polysilicon layer by deposition and back etching; and etching the first gate dielectric layer to a desired height.

[0025] Preferably, the material of the hard mask layer in step 1 is silicon oxide.

[0026] Preferably, in step 2, the P-type epitaxial layer of the required height is formed by deposition and etching methods.

[0027] Preferably, in step 2, the isolation dielectric layer of required height is formed by deposition and etching methods.

[0028] Preferably, the method for forming the second gate dielectric layer and the second polysilicon layer in step 2 comprises: depositing the second gate dielectric layer; depositing the second polysilicon layer; and grinding the second polysilicon layer and the second gate dielectric layer onto the epitaxial layer.

[0029] Preferably, step one also includes forming the gate trench in the P-type epitaxial lead-out region, and forming the first gate dielectric layer and the first polysilicon layer in the first gate dielectric layer at the bottom of the gate trench in the P-type epitaxial lead-out region.

[0030] Preferably, in step 2, the P-type epitaxial layer is etched only in the cell region, and the P-type epitaxial layer filling the gate trench is retained from bottom to top in the P-type epitaxial layer lead-out region.

[0031] Preferably, the contact hole dielectric layer in step 4 also covers the P-type epitaxial lead-out region; and step 5 further comprises forming a contact hole communicating with the P-type epitaxial layer in the P-type epitaxial lead-out region.

[0032] Preferably, step two also includes simultaneously etching the P-type epitaxial layer in the P-type epitaxial lead-out region, but etching the isolation dielectric layer only in the cell region, to form the P-type epitaxial layer having the same thickness as that in the cell region and the isolation dielectric layer filling the remaining gate trench.

[0033] Preferably, the contact hole dielectric layer in step 4 also covers the P-type epitaxial lead-out region; and step 5 further includes forming a contact hole connected to the first polysilicon layer.

[0034] As described above, the electric field enhanced shielded gate MOSFET and the manufacturing method thereof of the present invention have the following beneficial effects:

[0035] The present invention effectively improves the electric field strength in the middle of the drift region and increases the breakdown voltage by adding a shielding gate P-type epitaxial layer, and can further reduce the conduction loss by adjusting the epitaxy. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 Shown is a schematic diagram of a shielded gate MOSFET and electric field in the prior art;

[0037] Figure 2 Shown is a schematic diagram of the process flow of the present invention;

[0038] Figure 3 It is a schematic diagram showing the formation of a first gate dielectric layer in a gate trench according to the present invention;

[0039] Figure 4 It is a schematic diagram of forming a first polycrystalline layer according to the present invention;

[0040] Figure 5 It is a schematic diagram showing etching the first gate dielectric layer to a desired height according to the present invention;

[0041] Figure 6 It is a schematic diagram showing the formation of a P-type epitaxial layer according to the present invention;

[0042] Figure 7 Shown is a schematic diagram of etching a P-type epitaxial layer according to the present invention;

[0043] Figure 8 It is a schematic diagram of forming an insulating dielectric layer according to the present invention;

[0044] Fig. 9 It is a schematic diagram showing the formation of a second gate dielectric layer and a second polysilicon layer according to the present invention;

[0045] Fig.10 Shown is a schematic diagram of the shielded gate MOSFET and electric field of the present invention;

[0046] Fig.11 Shown is a schematic diagram of a P-type epitaxial lead-out region according to an embodiment of the present invention;

[0047] Fig.12 Shown is a schematic diagram of a P-type epitaxial lead-out region according to another embodiment of the present invention. DETAILED DESCRIPTION

[0048] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0049] See also Fig.10 The present invention provides an electric field enhanced shielded gate MOSFET, comprising:

[0050] A substrate, an epitaxial layer is formed on the substrate, the substrate and the epitaxial layer are represented by reference numeral 101, a gate trench is formed on a cell region on the epitaxial layer, a first gate dielectric layer 102 and a first polysilicon layer 104 located in the first gate dielectric layer 102 are formed at the bottom of the gate trench, the first gate dielectric layer 102 serves as a shielding gate polysilicon layer, and the material of the first gate dielectric layer 102 is generally an oxide layer, which can be formed by thermal oxidation, chemical vapor deposition, atomic layer deposition, etc.;

[0051] A P-type epitaxial layer 105 is formed on the first gate dielectric layer 102 and the first polysilicon layer 104, and an isolation dielectric layer 106 is formed on the P-type epitaxial layer 105. The material of the isolation dielectric layer 106 may be silicon nitride or other materials;

[0052] A second gate dielectric layer 107 is formed on the sidewall of the remaining gate trench. The material of the second gate dielectric layer 107 is usually an oxide layer, which can be formed by thermal oxidation, chemical vapor deposition, atomic layer deposition, etc. A second polysilicon layer 108 is formed in the remaining gate trench;

[0053] A well region 109 and a source region 110 of a cell region are formed on the epitaxial layer, and a contact hole dielectric layer 111 is formed on the epitaxial layer;

[0054] A contact hole 112 connected to the well region 109 is formed on the contact hole dielectric layer 111 and the epitaxial layer thereunder.

[0055] In some embodiments, the MOSFET further includes: a P-type epitaxial layer 105 formed in the P-type epitaxial lead-out region to fill the gate trench.

[0056] In some embodiments, the MOSFET further includes: a contact hole dielectric layer 111 also covering the P-type epitaxial lead-out region; and a contact hole 112 connected to the P-type epitaxial layer 105 in the P-type epitaxial lead-out region.

[0057] In some embodiments, the MOSFET further includes: forming a P-type epitaxial layer 105 having the same thickness as that in the cell region in the P-type epitaxial lead-out region and an isolation dielectric layer 106 filling the remaining gate trench.

[0058] In some embodiments, the MOSFET further includes: a contact hole dielectric layer 111 also covering the P-type epitaxial lead-out region; and a contact hole 112 connected to the first polysilicon layer.

[0059] See also Fig.10By adding the shield gate P-type epitaxial layer 105, the electric field strength in the middle of the drift region is effectively increased, and the breakdown voltage is improved. At the same time, the conduction loss can be further reduced by adjusting the epitaxy.

[0060] See also Figure 2 The present invention also provides a method for manufacturing the above-mentioned electric field enhanced shielded gate MOSFET, comprising:

[0061] Step 1: providing a substrate, forming an epitaxial layer on the substrate, the substrate and the epitaxial layer are represented by reference numeral 101, forming a gate trench on a cell region on the epitaxial layer, a first gate dielectric layer 102 and a first polysilicon layer 104 located in the first gate dielectric layer 102 are formed at the bottom of the gate trench, the first gate dielectric layer 102 serves as a shielding gate polysilicon layer, the material of the first gate dielectric layer 102 is generally an oxide layer, and can be formed by thermal oxidation, chemical vapor deposition, atomic layer deposition, etc.;

[0062] In some embodiments, the method for forming the gate trench in step 1 includes: forming a hard mask layer 103 on the substrate; opening the hard mask layer 103 by photolithography and etching to define the formation position of the gate trench; forming the gate trench by etching; forming a first gate dielectric layer 102 located in the gate trench by deposition, and forming Figure 3 The structure shown in FIG. 1 is formed by a deposition and etching method to form a first polysilicon layer 104, forming a Figure 4 The structure shown; etching the first gate dielectric layer 102 to the desired height, forming a Figure 5 The structure shown.

[0063] In some embodiments, the material of the hard mask layer 103 in step 1 is silicon oxide.

[0064] Step 2: Form a P-type epitaxial layer 105 on the first gate dielectric layer 102 and the first polysilicon layer 104 to form a P-type epitaxial layer 105. Figure 7 The structure shown in FIG. 1 is then formed on the P-type epitaxial layer 105 to form an isolation dielectric layer 106. Figure 8 In the structure shown, the material of the isolation dielectric layer 106 may be silicon nitride or the like;

[0065] In some embodiments, in step 2, a P-type epitaxial layer 105 of a desired height is formed by deposition and etching. That is, a P-type epitaxial layer 105 is deposited to form Figure 5 The structure shown in FIG. 1 is then etched to a desired height by etching the P-type epitaxial layer 105 .

[0066] In some embodiments, in step 2, the isolation dielectric layer 106 of a desired height is formed by deposition and etching methods.

[0067] In some embodiments, the method for forming the second gate dielectric layer 107 and the second polysilicon layer 108 in step 2 includes: depositing the second gate dielectric layer 107; depositing the second polysilicon layer 108; and grinding the second polysilicon layer 108 and the second gate dielectric layer 107 onto the epitaxial layer.

[0068] Step 3: Form a second gate dielectric layer 107 on the sidewalls of the remaining gate trenches. The material of the second gate dielectric layer 107 is usually an oxide layer, which can be formed by thermal oxidation, chemical vapor deposition, atomic layer deposition, etc., and then form a second polysilicon layer 108 filling the remaining gate trenches to form a Fig. 9 The structure shown;

[0069] Step 4: forming a well region 109 and a source region 110 of a cell region on the epitaxial layer by ion implantation, and forming a contact hole dielectric layer 111 on the epitaxial layer;

[0070] Step 5: forming a contact hole 112 connected to the well region 109 on the contact hole dielectric layer 111 and the epitaxial layer thereunder, forming a contact hole 112 connected to the well region 109. Fig.10 The structure shown.

[0071] In some embodiments, step one also includes forming a gate trench in the P-type epitaxial lead-out region, and forming a first gate dielectric layer 102 and a first polysilicon layer 104 in the first gate dielectric layer 102 at the bottom of the gate trench in the P-type epitaxial lead-out region.

[0072] In some embodiments, see Fig.11 In step 2, the P-type epitaxial layer 105 is only etched in the cell region, and the P-type epitaxial layer 105 filling the gate trench is retained from bottom to top in the P-type epitaxial layer lead-out region.

[0073] In some embodiments, see Fig.11 The contact hole dielectric layer 111 in step 4 also covers the P-type epitaxial lead-out region; step 5 also includes forming a contact hole 112 connected to the P-type epitaxial layer 105 in the P-type epitaxial lead-out region.

[0074] In some embodiments, see Fig.12 Step 2 also includes etching the P-type epitaxial layer 105 in the cell region and the P-type epitaxial lead-out region at the same time, but etching the isolation dielectric layer 106 only in the cell region, forming a P-type epitaxial layer 105 with the same thickness as that in the cell region and an isolation dielectric layer 106 filling the remaining gate trench in the P-type epitaxial lead-out region.

[0075] In some embodiments, see Fig.12 The contact hole dielectric layer 111 in step 4 also covers the P-type epitaxial lead-out region; step 5 also includes forming a contact hole 112 connected to the first polysilicon layer.

[0076] See also Fig.10 By adding the shield gate P-type epitaxial layer 105, the electric field strength in the middle of the drift region is effectively increased, and the breakdown voltage is improved. At the same time, the conduction loss can be further reduced by adjusting the epitaxy.

[0077] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0078] In summary, the present invention effectively increases the electric field strength in the middle of the drift region and improves the breakdown voltage by adding a shielded gate P-type epitaxial layer, and can further reduce the conduction loss by adjusting the epitaxy. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0079] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A field-enhanced shielded gate MOSFET, characterized in that: include: A substrate, an epitaxial layer is formed on the substrate, a gate trench is formed on a cell region on the epitaxial layer, a first gate dielectric layer and a first polysilicon layer located in the first gate dielectric layer are formed at the bottom of the gate trench; A P-type epitaxial layer is formed on the first gate dielectric layer and the first polysilicon layer, and an isolation dielectric layer is formed on the P-type epitaxial layer; A second gate dielectric layer is formed on the sidewalls of the remaining gate trench, and a second polysilicon layer is formed in the remaining gate trench; A well region and a source region of the cell region are formed on the epitaxial layer, and a contact hole dielectric layer is formed on the epitaxial layer; A contact hole connected to the well region is formed on the contact hole dielectric layer and the epitaxial layer therebelow.

2. The electric field enhanced shielded gate MOSFET according to claim 1, characterized in that: The MOSFET further includes: the gate trench formed in the P-type epitaxial lead-out region, the first gate dielectric layer formed at the bottom of the gate trench in the P-type epitaxial lead-out region, and the first polysilicon layer located in the first gate dielectric layer.

3. The electric field enhanced shielded gate MOSFET according to claim 2, characterized in that: The MOSFET further includes: forming the P-type epitaxial layer filling the gate trench in the P-type epitaxial lead-out region.

4. The electric field enhanced shielded gate MOSFET according to claim 3, characterized in that: The MOSFET further comprises: the contact hole dielectric layer also covers the P-type epitaxial lead-out region; and a contact hole connected to the P-type epitaxial layer in the P-type epitaxial lead-out region.

5. The field-enhanced shielded gate MOSFET according to claim 2, characterized in that: The MOSFET further includes: forming the P-type epitaxial layer having the same thickness as that in the cell region in the P-type epitaxial lead-out region and the isolation dielectric layer filling the remaining gate trench.

6. The electric field enhanced shielded gate MOSFET according to claim 5, characterized in that: The MOSFET further includes: the contact hole dielectric layer also covers the P-type epitaxial lead-out region; and a contact hole connected to the first polysilicon layer.

7. The method for manufacturing a field-enhanced shielded gate MOSFET according to any one of claims 1 to 6, characterized in that: At least: Step 1, providing a substrate, forming an epitaxial layer on the substrate, forming a gate trench on a cell region on the epitaxial layer, wherein a first gate dielectric layer and a first polysilicon layer located in the first gate dielectric layer are formed at the bottom of the gate trench; Step 2: forming a P-type epitaxial layer on the first gate dielectric layer and the first polysilicon layer, and then forming an isolation dielectric layer on the P-type epitaxial layer; Step 3, forming a second gate dielectric layer on the sidewalls of the remaining gate trenches, and then forming a second polysilicon layer filling the remaining gate trenches; Step 4: forming a well region and a source region of the cell region on the epitaxial layer by ion implantation, and forming a contact hole dielectric layer on the epitaxial layer; Step 5: forming a contact hole connected to the well region on the contact hole dielectric layer and the epitaxial layer thereunder.

8. The method for manufacturing an electric field enhanced shielded gate MOSFET according to claim 7, characterized in that: The method for forming the gate trench in step one includes: forming a hard mask layer on the substrate; opening the hard mask layer by photolithography and etching to define the formation position of the gate trench; forming the gate trench by etching; forming the first gate dielectric layer located in the gate trench; forming the first polysilicon layer by deposition and back etching; and etching the first gate dielectric layer to a desired height.

9. The method for manufacturing an electric field enhanced shielded gate MOSFET according to claim 8, characterized in that: The material of the hard mask layer in step 1 is silicon oxide.

10. The method for manufacturing an electric field enhanced shielded gate MOSFET according to claim 7, characterized in that: In step 2, the P-type epitaxial layer of the required height is formed by deposition and etching methods.

11. The method for manufacturing an electric field enhanced shielded gate MOSFET according to claim 7, characterized in that: In step 2, the isolation dielectric layer of required height is formed by deposition and etching methods.

12. The method for manufacturing an electric field enhanced shielded gate MOSFET according to claim 7, characterized in that: The method for forming the second gate dielectric layer and the second polysilicon layer in step 2 includes: depositing the second gate dielectric layer; depositing the second polysilicon layer; and grinding the second polysilicon layer and the second gate dielectric layer onto the epitaxial layer.

13. The method for manufacturing an electric field enhanced shielded gate MOSFET according to claim 7, characterized in that: Step one also includes forming the gate trench in the P-type epitaxial lead-out region, and forming the first gate dielectric layer and the first polysilicon layer in the first gate dielectric layer at the bottom of the gate trench in the P-type epitaxial lead-out region.

14. The method for manufacturing an electric field enhanced shielded gate MOSFET according to claim 13, characterized in that: In step 2, the P-type epitaxial layer is only etched in the cell region, and the P-type epitaxial layer filling the gate trench is retained from bottom to top in the P-type epitaxial layer lead-out region.

15. The method for manufacturing an electric field enhanced shielded gate MOSFET according to claim 14, characterized in that: The contact hole dielectric layer in step 4 also covers the P-type epitaxial lead-out region; step 5 also includes forming a contact hole connected to the P-type epitaxial layer in the P-type epitaxial lead-out region.

16. The method for manufacturing an electric field enhanced shielded gate MOSFET according to claim 13, characterized in that: Step 2 also includes simultaneously etching the P-type epitaxial layer in the P-type epitaxial lead-out region, but etching the isolation dielectric layer only in the cell region, to form the P-type epitaxial layer having the same thickness as that in the cell region and the isolation dielectric layer filling the remaining gate trench.

17. The method for manufacturing an electric field enhanced shielded gate MOSFET according to claim 16, characterized in that: The contact hole dielectric layer in step 4 also covers the P-type epitaxial lead-out region; and step 5 also includes forming a contact hole connected to the first polysilicon layer.

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