Thin film transistor and electronic device

Abstract

A thin film transistor (10) is provided with: an oxide semiconductor layer (140) having a polycrystalline structure provided over a substrate (100); a gate electrode (160) provided over the oxide semiconductor layer; and a gate insulating layer (150) provided between the oxide semiconductor layer and the gate electrode. The oxide semiconductor layer includes: a first region (141) that overlaps the gate electrode and has a first carrier concentration (n1); a second region (142) that does not overlap the gate electrode and has a second carrier concentration (n2); and a third region (143) overlapping the gate electrode and located between the first region and the second region, the second carrier concentration being greater than the first carrier concentration, and the carrier concentration of the third region decreasing in the channel length direction from the second region toward the first region. The length of the third region in the channel length direction is 0.00 [mu] m or more and 0.60 [mu] m or less.

Description

Technical Field

[0001] One embodiment of the present invention relates to a thin film transistor including an oxide semiconductor having a polycrystalline structure (Poly-OS). In addition, one embodiment of the present invention relates to an electronic device including the thin film transistor. Background Art

[0002] In recent years, the development of thin film transistors using oxide semiconductors as channels instead of silicon semiconductors such as amorphous silicon, low-temperature polycrystalline silicon and single crystal silicon has been continuously developed (for example, see patent documents 1 to 6). Such thin film transistors including oxide semiconductors can be formed with a simple structure and by a low-temperature process, just like thin film transistors including amorphous silicon. In addition, it is known that thin film transistors including oxide semiconductors have higher mobility than thin film transistors including amorphous silicon.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2021-141338

[0006] Patent Document 2: Japanese Patent Application Publication No. 2014-099601

[0007] Patent Document 3: Japanese Patent Application Publication No. 2021-153196

[0008] Patent Document 4: Japanese Patent Application Publication No. 2018-006730

[0009] Patent Document 5: Japanese Patent Application Publication No. 2016-184771

[0010] Patent Document 6: Japanese Patent Application Publication No. 2021-108405 Summary of the invention

[0011] Problems to be solved by the invention

[0012] However, in the case of existing thin film transistors including oxide semiconductors, when the channel length becomes smaller, the threshold voltage in the electrical characteristics shifts in the negative direction or the deviation of the threshold voltage becomes larger, making it difficult to obtain stable thin film transistor characteristics. Therefore, in existing thin film transistors including oxide semiconductors, there is a situation where the design freedom of the channel length is low and the use of the thin film transistor is limited.

[0013] In view of the above problems, one object of one embodiment of the present invention is to provide a thin film transistor including an oxide semiconductor with a high degree of freedom in designing a channel length. Another object of one embodiment of the present invention is to provide an electronic device including a thin film transistor.

[0014] Means for solving problems

[0015] A thin film transistor involved in one embodiment of the present invention includes: an oxide semiconductor layer having a polycrystalline structure arranged on a substrate; a gate electrode arranged on the oxide semiconductor layer; and a gate insulating layer arranged between the oxide semiconductor layer and the gate electrode, the oxide semiconductor layer includes: a first region overlapping with the gate electrode and having a first carrier concentration; a second region not overlapping with the gate electrode and having a second carrier concentration; and a third region overlapping with the gate electrode and located between the first region and the second region, the second carrier concentration is greater than the first carrier concentration, the carrier concentration of the third region decreases in the channel length direction from the second region toward the first region, and the length of the third region in the channel length direction is greater than 0.00μm and less than 0.60μm.

[0016] An electronic device according to one embodiment of the present invention includes the above-mentioned thin film transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic cross-sectional view showing the structure of a thin film transistor according to one embodiment of the present invention.

[0018] Figure 2 It is a schematic plan view showing the structure of a thin film transistor according to one embodiment of the present invention.

[0019] Figure 3 It is a schematic diagram for explaining the carrier concentration in the oxide semiconductor layer of the thin film transistor according to one embodiment of the present invention.

[0020] Figure 4 It is a schematic diagram for explaining SCM observation of a thin film transistor according to one embodiment of the present invention.

[0021] Figure 5 It is a schematic cross-sectional view showing the structure of a thin film transistor according to one embodiment of the present invention.

[0022] Figure 6 This is a flowchart showing a method for manufacturing a thin film transistor according to one embodiment of the present invention.

[0023] Figure 7 It is a schematic cross-sectional view showing a method for manufacturing a thin film transistor according to one embodiment of the present invention.

[0024] Figure 8 It is a schematic cross-sectional view showing a method for manufacturing a thin film transistor according to one embodiment of the present invention.

[0025] Fig. 9It is a schematic cross-sectional view showing a method for manufacturing a thin film transistor according to one embodiment of the present invention.

[0026] Fig.10 It is a schematic cross-sectional view showing a method for manufacturing a thin film transistor according to one embodiment of the present invention.

[0027] Fig.11 It is a schematic cross-sectional view showing a method for manufacturing a thin film transistor according to one embodiment of the present invention.

[0028] Fig.12 It is a schematic cross-sectional view showing a method for manufacturing a thin film transistor according to one embodiment of the present invention.

[0029] Fig.13 It is a schematic cross-sectional view showing a method for manufacturing a thin film transistor according to one embodiment of the present invention.

[0030] Fig.14 It is a schematic diagram showing an electronic device according to one embodiment of the present invention.

[0031] Fig.15 This is a graph showing the electrical characteristics of Example Sample 1 and Comparative Example Sample 1.

[0032] Fig.16 This is a graph showing the results of TDS measurement of Example Sample 2 and Comparative Example Sample 2.

[0033] Fig.17 This is a graph showing the results of SCM observation of Example Sample 1.

[0034] Fig.18A This is a graph in which the ΔC / ΔV signal obtained by SCM observation of Example Sample 1 was fitted with a Gaussian function.

[0035] Fig.18B This is a graph showing the fitting of the ΔC / ΔV signal obtained by SCM observation of Example Sample 1 using a complementary error function.

[0036] Fig.18C This is a graph in which the ΔC / ΔV signal obtained by SCM observation of Example Sample 1 was fitted using a Lorentzian function.

[0037] Fig.19 This is a graph showing the results of SCM observation of Example Sample 3.

[0038] Fig. 20A This is a graph in which the ΔC / ΔV signal obtained by SCM observation of Example Sample 3 was fitted with a Gaussian function.

[0039] Fig. 20B This is a graph showing the fitting of the ΔC / ΔV signal obtained by SCM observation of Example Sample 3 using a complementary error function.

[0040] Fig. 20C This is a graph showing the ΔC / ΔV signal obtained by SCM observation of Example Sample 3 fitted by the Lorentz function. DETAILED DESCRIPTION

[0041] Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings. The following disclosure is only an example. The configuration that can be easily thought of by those skilled in the art by appropriately changing the configuration of the embodiment while maintaining the gist of the invention is of course included in the scope of the present invention. With respect to the accompanying drawings, in order to make the description clearer, the width, thickness, shape, etc. of each part are sometimes schematically indicated compared to the actual method. However, the shape shown in the figure is only an example and does not limit the interpretation of the present invention. In this specification and each figure, the same figure mark is marked for the same elements as those described in the figures that have appeared, and the detailed description is sometimes appropriately omitted.

[0042] In this specification, the direction from the substrate toward the oxide semiconductor layer is referred to as up or above. Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as down or below. Thus, for ease of explanation, the phrases such as above or below are used for explanation, but, for example, the up-and-down relationship between the substrate and the oxide semiconductor layer may be configured in a manner opposite to that shown in the figure. In the following description, for example, the expression "oxide semiconductor layer on the substrate" is only used to illustrate the up-and-down relationship between the substrate and the oxide semiconductor layer as described above, and other components may be configured between the substrate and the oxide semiconductor layer. Above or below means the stacking order in a structure having multiple layers stacked, and in the case of a pixel electrode described as above the transistor, it may also be a positional relationship in which the transistor and the pixel electrode do not overlap when viewed from above. On the other hand, in the case of a pixel electrode described as vertically above the transistor, it means a positional relationship in which the transistor and the pixel electrode overlap when viewed from above.

[0043] In this specification, the term "film" and the term "layer" can be interchanged according to circumstances.

[0044] The so-called "display device" refers to a structure that uses an electro-optical layer to display an image. For example, the term display device sometimes refers to a display panel including an electro-optical layer, or sometimes refers to a structure that is equipped with other optical components (such as polarization components, backlight sources, touch panels, etc.) relative to the display unit. As long as there is no technical contradiction, the "electro-optical layer" may include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer. Therefore, with respect to the embodiments described below, a liquid crystal display device including a liquid crystal layer and an organic EL display device including an organic EL layer are exemplified as display devices for explanation, but the structure in this embodiment can be applied to a display device including the above-mentioned other electro-optical layers.

[0045] In this specification, unless otherwise specified, expressions such as “α includes A, B, or C”, “α includes any one of A, B, and C”, and “α includes one selected from the group consisting of A, B, and C” do not exclude the case where α includes a combination of multiple elements of A to C. In addition, the above expressions do not exclude the case where α includes other elements.

[0046] It should be noted that the following embodiments can be combined with each other as long as no technical contradiction occurs.

[0047] <First embodiment>

[0048] Reference Figures 1 to 13 A thin film transistor 10 according to one embodiment of the present invention will be described. The thin film transistor 10 can be used in, for example, a display device, an integrated circuit (IC) such as a microprocessor (Micro-Processing Unit: MPU), or a memory circuit.

[0049] [1. Configuration of Thin Film Transistor 10]

[0050] Reference Figure 1 and Figure 2 The structure of the thin film transistor 10 according to one embodiment of the present invention will be described. Figure 1 It is a schematic cross-sectional view showing the structure of a thin film transistor 10 according to one embodiment of the present invention. Figure 2 1 is a schematic top view showing the structure of a thin film transistor according to one embodiment of the present invention. Specifically, Figure 1 It is along Figure 2 The cross-sectional view is obtained by cutting along the A-A' line.

[0051] like Figure 1As shown, the thin film transistor 10 includes a substrate 100, a light shielding layer 105, a first insulating layer 110, a second insulating layer 120, an oxide semiconductor layer 140, a gate insulating layer 150, a gate electrode 160, a third insulating layer 170, a fourth insulating layer 180, a source electrode 201 and a drain electrode 203. The light shielding layer 105 is disposed on the substrate 100. The first insulating layer 110 covers the upper surface and end surface of the light shielding layer 105 and is disposed on the substrate 100. The second insulating layer 120 is disposed on the first insulating layer 110. The oxide semiconductor layer 140 is disposed on the second insulating layer 120. The gate insulating layer 150 covers the upper surface and end surface of the oxide semiconductor layer 140 and is disposed on the second insulating layer 120. The gate electrode 160 overlaps with the oxide semiconductor layer 140 and is disposed on the gate insulating layer 150. The third insulating layer 170 covers the upper surface and end surface of the gate electrode 160 and is disposed on the gate insulating layer 150. The fourth insulating layer 180 is provided on the third insulating layer 170. The gate insulating layer 150, the third insulating layer 170, and the fourth insulating layer 180 are provided with openings 171 and 173 that expose a portion of the upper surface of the oxide semiconductor layer 140. The source electrode 201 is provided on the fourth insulating layer 180 and inside the opening 171, and is in contact with the oxide semiconductor layer 140. Similarly, the drain electrode 203 is provided on the fourth insulating layer 180 and inside the opening 173, and is in contact with the oxide semiconductor layer 140. It should be noted that, hereinafter, when the source electrode 201 and the drain electrode 203 are not particularly distinguished, they are sometimes collectively referred to as the source / drain electrode 200.

[0052] The oxide semiconductor layer 140 is divided into a source region S, a drain region D, and a channel region CH based on the gate electrode 160. That is, the oxide semiconductor layer 140 includes a channel region CH overlapping with the gate electrode 160, and a source region S and a drain region D not overlapping with the gate electrode 160. In the film thickness direction of the oxide semiconductor layer 140, the end of the channel region CH coincides with the end of the gate electrode 160. The channel region CH has the properties of a semiconductor. The source region S and the drain region D each have the properties of a conductor. Therefore, the conductivity of the source region S and the drain region D is greater than the conductivity of the channel region CH. The source electrode 201 and the drain electrode 203 are respectively connected to the source region S and the drain region D, and are electrically connected to the oxide semiconductor layer 140. In addition, the oxide semiconductor layer 140 can be a single-layer structure or a stacked structure.

[0053] like Figure 2As shown, the light shielding layer 105 and the gate electrode 160 each have a certain width in the D1 direction, and extend along the D2 direction orthogonal to the D1 direction. In the D1 direction, the width of the light shielding layer 105 is greater than the width of the gate electrode 160. The channel region CH completely overlaps with the light shielding layer 105. In the thin film transistor 10, the D1 direction corresponds to the direction in which the current flows from the source electrode 201 to the drain electrode 203 via the oxide semiconductor layer 140. Therefore, the length of the channel region CH in the D1 direction is the channel length L, and the width of the channel region CH in the D2 direction is the channel width W.

[0054] The substrate 100 can support each layer constituting the thin film transistor 10. As the substrate 100, for example, a glass substrate, a quartz substrate, a sapphire substrate or other light-transmitting rigid substrate can be used. In addition, as the substrate, a silicon substrate or other non-light-transmitting rigid substrate can be used. In addition, as the substrate, a polyimide resin substrate, an acrylic resin substrate, a siloxane resin substrate or a fluororesin substrate or other light-transmitting flexible substrate can be used. In order to improve the heat resistance of the substrate 100, impurities can also be introduced into the above-mentioned resin substrate. It should be noted that a substrate having a silicon oxide film or a silicon nitride film formed on the above-mentioned rigid substrate or flexible substrate can also be used as the substrate 100.

[0055] The light shielding layer 105 can reflect or absorb external light. As described above, since the light shielding layer 105 is arranged in a manner having an area larger than that of the channel region CH of the oxide semiconductor layer 140, it is possible to block external light incident on the channel region CH. As the light shielding layer 105, for example, aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo) or tungsten (W) or their alloys or compounds can be used. In addition, as the light shielding layer 105, it is not necessarily necessary to contain a metal when conductivity is not required. For example, as the light shielding layer 105, a black matrix formed by a black resin can also be used. In addition, the light shielding layer 105 can be a single-layer structure or a stacked structure. For example, the light shielding layer 105 can be a stacked structure of a red filter, a green filter and a blue filter.

[0056] The first insulating layer 110, the second insulating layer 120, the third insulating layer 170, and the fourth insulating layer 180 can prevent impurities from diffusing into the oxide semiconductor layer 140. Specifically, the first insulating layer 110 and the second insulating layer 120 can prevent the diffusion of impurities contained in the substrate 100, and the third insulating layer 170 and the fourth insulating layer 180 can prevent the diffusion of impurities (such as water) intruding from the outside. As each of the first insulating layer 110, the second insulating layer 120, the third insulating layer 170, and the fourth insulating layer 180, for example, silicon oxide (SiO x ), silicon oxide nitride (SiO x Ny ), Silicon Nitride (SiN x ), silicon oxide nitride (SiN x O y ), aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y ), aluminum nitride (AlN x O y ), aluminum nitride (AlN x ) etc. Here, silicon nitride oxide (SiO x N y ) and aluminum oxide nitride (AlO x N y ) are silicon compounds and aluminum compounds containing nitrogen (N) at a ratio (x>y) less than oxygen (O). x O y ) and aluminum nitride (AlN x O y ) is a silicon compound or an aluminum compound containing oxygen at a ratio less than nitrogen (x>y). In addition, the first insulating layer 110, the second insulating layer 120, the third insulating layer 170, and the fourth insulating layer 180 may each have a single layer structure or a stacked structure.

[0057] In addition, each of the first insulating layer 110, the second insulating layer 120, the third insulating layer 170, and the fourth insulating layer 180 may have a planarization function or a function of releasing oxygen by heat treatment. For example, when the second insulating layer 120 has a function of releasing oxygen by heat treatment, oxygen can be released from the second insulating layer 120 by heat treatment performed in the manufacturing process of the thin film transistor 10, and the released oxygen can be supplied to the oxide semiconductor layer 140.

[0058] The gate electrode 160, the source electrode 201, and the drain electrode 203 are conductive. For example, copper (Cu), aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), or bismuth (Bi), or alloys thereof or compounds thereof can be used as the gate electrode 160, the source electrode 201, and the drain electrode 203. Each of the gate electrode 160, the source electrode 201, and the drain electrode 203 may have a single-layer structure or a stacked structure.

[0059] The gate insulating layer 150 includes an oxide having insulating properties. Specifically, silicon oxide (SiO x ), silicon oxide nitride (SiO x N y ), aluminum oxide (AlOx ), aluminum oxide nitride (AlO x N y ) etc. The gate insulating layer 150 preferably has a composition close to a stoichiometric ratio. In addition, the gate insulating layer 150 preferably has few defects. For example, as the gate insulating layer 150, an oxide in which no defects are observed when evaluated by an electron spin resonance method (ESR) may also be used.

[0060] The oxide semiconductor layer 140 has a polycrystalline structure including a plurality of crystal grains. The oxide semiconductor layer 140 having a polycrystalline structure can be formed by using the Poly-OS (Poly-crystalline Oxide Semiconductor) technology, and the details are described later. The composition of the oxide semiconductor layer 140 is described below, and the oxide semiconductor having a polycrystalline structure is sometimes referred to as Poly-OS.

[0061] [2. Configuration of Oxide Semiconductor Layer 140]

[0062] [2-1. Composition Ratio of Oxide Semiconductor Layer 140]

[0063] As the oxide semiconductor layer 140, an oxide semiconductor containing an indium (In) element and a metal (M) element other than the indium element is used. In terms of the composition ratio of the oxide semiconductor layer 140, it is preferred that the atomic ratio of the indium element to the metal element other than the indium element satisfies the formula (1). In other words, the ratio of the indium element to all the metal elements in the oxide semiconductor layer 140 is preferably 50% or more.

[0064] [Mathematical formula 1]

[0065]

[0066] It should be noted that the metal elements other than the indium element are not limited to one metal element. Elements other than the indium element (hereinafter referred to as "other metal elements") may also include multiple metal elements. The detailed manufacturing method of the oxide semiconductor layer 140 is described later, and the oxide semiconductor layer 140 can be formed using a sputtering method. The composition of the oxide semiconductor layer 140 formed by sputtering depends on the composition of the sputtering target. In the sputtering target having the above composition, an oxide semiconductor layer 140 without a composition deviation of the metal elements can be formed by sputtering. Therefore, the composition of the metal elements (for example, indium and other metal elements) of the oxide semiconductor layer 140 may also be equivalent to the composition of the metal elements of the sputtering target. For example, the composition of the metal elements of the oxide semiconductor layer 140 can be determined based on the composition of the metal elements of the sputtering target. It should be noted that since the oxygen element contained in the oxide semiconductor layer 140 changes according to the process conditions of the sputtering, etc., it is not limited to this.

[0067] In addition, the composition of the metal elements of the oxide semiconductor layer 140 can also be determined using fluorescent X-ray analysis or electron probe microanalyzer analysis (Electron Probe Micro Analyzer: EPMA), etc. In addition, the composition of the metal elements of the oxide semiconductor layer 140 can also be determined based on the crystal structure and lattice constant of the oxide semiconductor layer 140 using an X-ray diffraction (XRD) method.

[0068] [2-2. Crystal Structure of Oxide Semiconductor Layer 140]

[0069] The oxide semiconductor layer 140 includes Poly-OS. The crystal grain size of the crystal grains contained in the Poly-OS observed from the upper surface of the oxide semiconductor layer 140 (or in the film thickness direction of the oxide semiconductor layer 140) is 0.1 μm or more, preferably 0.3 μm or more, and more preferably 0.5 μm or more. The crystal grain size of the crystal grain can be obtained, for example, using cross-sectional SEM observation, cross-sectional TEM observation, or electron backscatter diffraction (EBSD) method.

[0070] The crystal grains contained in the oxide semiconductor layer 140 may be composed of a plurality of microcrystals. The microcrystal grain size (Japanese: crystal size) is not particularly limited, but is preferably 1 nm or more, more preferably 10 nm or more, and further preferably 10 nm or more. The microcrystal grain size can be obtained using an electron beam diffraction method or an XRD method.

[0071] In Poly-OS, a plurality of crystal grains may have one crystal structure or multiple crystal structures. The crystal structure of Poly-OS can be determined using electron beam diffraction or XRD. That is, the crystal structure of the oxide semiconductor layer 140 can be determined using electron beam diffraction or XRD.

[0072] The crystal structure of the oxide semiconductor layer 140 is not particularly limited, but preferably has a bixbyite structure. As described above, by increasing the ratio of the indium element, the crystal structure of each of the plurality of crystal grains can be controlled, and the oxide semiconductor layer 140 having the bixbyite structure can be formed.

[0073] [2-3. Carrier Concentration of Oxide Semiconductor Layer 140]

[0074] Figure 3 1 is a schematic diagram for explaining the carrier concentration in the oxide semiconductor layer 140 of the thin film transistor 10 according to one embodiment of the present invention.

[0075] The oxide semiconductor layer 140 is divided into a source region S, a drain region D, and a channel region CH as described above. The source region S and the drain region D are so-called n+ regions containing, for example, argon (Ar), phosphorus (P), or boron (B) as impurities. Therefore, the carrier concentration of the source region S and the drain region D is greater than the carrier concentration of the channel region CH. The first region 141 included in the channel region CH has a first carrier concentration n1. The second region 142 included in the source region S and the drain region D each has a second carrier concentration n2 greater than the first carrier concentration n1. In the oxide semiconductor layer 140, the change from the second carrier concentration n2 of the second region 142 to the first carrier concentration n1 of the first region 141 is not discontinuous, and there is a third region 143 having a gradient of carrier concentration between the second region 142 and the first region 141. That is, the third region 143 has a carrier concentration that decreases from the second carrier concentration n2 toward the first carrier concentration n1 (or increases from the first carrier concentration n1 toward the second carrier concentration n2).

[0076] The third region 143 is included in the channel region CH, and one end of the third region 143 is substantially consistent with the end of the channel region CH. That is, in the film thickness direction of the oxide semiconductor layer 140, one end of the third region 143 is substantially consistent with the end of the gate electrode 160. However, since the third region 143 has a greater carrier concentration than the first region 141, the properties of the third region 143 are closer to a conductor than a semiconductor. Therefore, if the third region 143 exists, the area that functions as a channel in the channel region CH becomes smaller, and the actual channel length (hereinafter referred to as the "effective channel length L eff ”) is smaller than the channel length L defined as the length of the channel region CH. If the length of the third region 143 in the channel length direction (hereinafter referred to as “intrusion length”) is ΔL, the effective channel length L eff It is expressed by formula (2).

[0077] [Mathematical formula 2]

[0078] L eff =L-2ΔL…(2)

[0079] According to formula (2), when the invasion length ΔL increases, the effective channel length L effBecomes smaller, and the oxide semiconductor layer 140 no longer functions as a channel. In addition, even if the channel length L is reduced in design, the intrusion length ΔL hardly changes. Therefore, in the thin film transistor 10 having a small channel length L, it is very important that the intrusion length ΔL is small. In the thin film transistor 10, the intrusion length ΔL is small compared to existing thin film transistors. The intrusion length ΔL in the thin film transistor 10 is greater than 0.00 μm and less than 0.60 μm, preferably greater than 0.00 μm and less than 0.50 μm, further preferably greater than 0.00 μm and less than 0.40 μm, and particularly preferably greater than 0.00 μm and less than 0.30 μm. For example, in the thin film transistor 10 having a channel length L of 2 μm, if the intrusion length ΔL is less than 0.60 μm, an effective channel length L greater than the intrusion length ΔL can be ensured. eff .

[0080] The third region 143 is formed by diffusion of hydrogen from the second region 142. Therefore, the intrusion length ΔL of the third region 143 depends on the diffusion coefficient of hydrogen in the oxide semiconductor layer 140. The diffusion coefficient of hydrogen is small for the Poly-OS contained in the oxide semiconductor layer 140, and the diffusion of hydrogen can be suppressed. Therefore, in the thin film transistor 10, the intrusion length ΔL of the third region 143 can be controlled within the above range.

[0081] The third region 143 is a region where the carrier concentration decreases in the channel length direction from the second region 142 toward the first region 141. Therefore, the intrusion length ΔL of the third region 143 can be obtained by measuring the change in the carrier concentration in the oxide semiconductor layer 140. The carrier concentration in the oxide semiconductor layer 140 can be measured using a scanning spreading resistance microscope (SSRM) or a scanning capacitance microscope (SCM). Figure 4 Let's explain SCM observation.

[0082] Figure 4 It is a schematic diagram for explaining SCM observation of the thin film transistor 10 according to one embodiment of the present invention.

[0083] In the SCM observation of the thin film transistor 10, a sample obtained by thinning the cross section of the thin film transistor 10 is used. In addition, a conductive film such as platinum (Pt) is formed on the first surface of the sample. The device structure of the SCM observation is basically the same as the device structure of the atomic force microscope (AFM) observation. Therefore, not only SCM observation but also AFM observation can be performed. In the SCM observation, a conductive probe 5001 is brought into contact with the second surface of the sample opposite to the first surface. At this time, since a tiny capacitor is formed between the probe 5001 and the sample, a modulated voltage (AC voltage) ΔV is applied to the conductive film on the first surface of the sample, and the electrostatic capacitance change ΔC is detected by the UHF capacitance sensor 5002 connected to the probe. Therefore, by scanning the probe 5001 on the second surface of the sample, a ΔC / ΔV signal in the scanning direction can be obtained.

[0084] The frequency of the modulation voltage ΔV is, for example, 100 kHz, and the frequency of the UHF capacitance sensor is, for example, 1 GHz. In addition, a DC bias voltage V may be applied to the modulation voltage ΔV. bias .

[0085] If the carrier concentration of the oxide semiconductor layer 140 is large, the absolute value of the electrostatic capacitance of the microcapacitor decreases, and if the carrier concentration of the oxide semiconductor layer 140 is small, the absolute value of the electrostatic capacitance of the microcapacitor increases. That is, the change in the carrier concentration in the oxide semiconductor layer 140 corresponds to the change in the ΔC / ΔV signal. Therefore, in the SCM observation of the thin film transistor 10, by scanning the probe 5001 along the channel length direction on the oxide semiconductor layer 140, the change in the carrier concentration of the oxide semiconductor layer 140 can be detected according to the ΔC / ΔV signal, thereby determining the third region 143. The intrusion length ΔL is calculated based on the determined third region 143.

[0086] It should be noted that in AFM observation, the end of the gate electrode 160 can be detected by scanning the probe 5001 along the channel length direction in a manner that passes through the end of the gate electrode 160. Therefore, by performing AFM observation together with SCM observation, the end of the channel region CH can be detected. In this case, the third region 143 can also be determined by assuming that the end of the third region 143 on the second region 142 side is roughly consistent with the end of the gate electrode 160, thereby calculating the intrusion length ΔL.

[0087] The intrusion length ΔL of the third region 143 can also be calculated using a fitting function. As described above, the third region 143 is formed by the diffusion of hydrogen. Since the diffusion of hydrogen in the third region 143 is considered to be Gaussian distributed, the curve f(x) of the ΔC / ΔV signal can be fitted using a Gaussian function (Formula (3)) or a complementary error function (Formula (4)).

[0088] [Mathematical formula 3]

[0089]

[0090] [Formula 4]

[0091]

[0092] In equations (3) and (4), value A is the amplitude of the change in the ΔC / ΔV signal, value b is the offset value, and value c is the scale parameter. The intrusion length ΔL can be calculated based on value c. For example, when using a Gaussian function, the distance over which the ΔC / ΔV signal changes by about 99.7% can be expressed as 3c. That is, in the fitting using a Gaussian function, by using ΔL=3c, most of the intrusion length ΔL of the third region 143 can be covered. The same is true for the complementary error function. Therefore, when using a fitting function, the intrusion length ΔL of the third region 143 can be calculated by setting it to ΔL=3c.

[0093] The formation of the third region 143 in the channel region CH may also be caused by reasons other than hydrogen diffusion (e.g., oxygen defects, etc.). Therefore, the fitting function of the ΔC / ΔV signal is not limited to the Gaussian function and the complementary error function. For example, the Lorentz function (Formula (5)) may also be used as the fitting function.

[0094] [Formula 5]

[0095]

[0096] In the equation (5), A is the amplitude of the change in the ΔC / ΔV signal, b is the offset value, and c is the half-width at half maximum. In this case, the intrusion length ΔL of the third region 143 can also be calculated by setting ΔL=3c.

[0097] The structure of the thin film transistor 10 is described above, but the thin film transistor 10 described above is a so-called top-gate transistor. The thin film transistor 10 can be deformed in various ways. For example, when the light shielding layer 105 is conductive, the thin film transistor 10 can also be a structure in which the light shielding layer 105 functions as a gate electrode and the first insulating layer 110 and the second insulating layer 120 function as gate insulating layers. In this case, the thin film transistor 10 is a so-called dual-gate transistor. In addition, when the light shielding layer 105 is conductive, the light shielding layer 105 can be a floating electrode or can be connected to the source electrode 201. In addition, the thin film transistor 10 can also be a so-called bottom-gate transistor in which the light shielding layer 105 functions as the main gate electrode.

[0098] The above-described structure of the thin film transistor 10 is merely one embodiment, and the present invention is not limited to the above-described structure. Hereinafter, a structure of a thin film transistor 10A as a modification of the thin film transistor 10 will be described.

[0099] <Modification>

[0100] Figure 5 It is a schematic cross-sectional view showing the structure of a thin film transistor 10A according to an embodiment of the present invention. When the structure of the thin film transistor 10A is the same as that of the thin film transistor 10 , the description of the structure of the thin film transistor 10A may be omitted.

[0101] like Figure 5 As shown, the thin film transistor 10A includes a substrate 100, a light shielding layer 105, a first insulating layer 110, a second insulating layer 120, an oxide semiconductor layer 140, a gate insulating layer 150A, a gate electrode 160, a third insulating layer 170A, a fourth insulating layer 180, a source electrode 201 and a drain electrode 203.

[0102] The gate insulating layer 150A is provided on the oxide semiconductor layer 140, but a portion of the oxide semiconductor layer 140 is exposed from the gate insulating layer 150A. The gate insulating layer 150A overlaps with the gate electrode 160, and the end of the gate insulating layer 150A is substantially consistent with the end of the gate electrode 160. The third insulating layer 170A covers the upper surface and end surface of the gate electrode 160, the end surface of the gate insulating layer 150A, and the upper surface and end surface of the oxide semiconductor layer 140, and is provided on the second insulating layer 120. The third insulating layer 170A and the fourth insulating layer 180 are provided with openings 171A and 173A that expose a portion of the upper surface of the oxide semiconductor layer 140. The source electrode 201 is provided on the fourth insulating layer 180 and inside the opening 171A, and is in contact with the oxide semiconductor layer 140. Similarly, the drain electrode 203 is provided on the fourth insulating layer 180 and inside the opening 173A, and is in contact with the oxide semiconductor layer 140.

[0103] In the thin film transistor 10A, the oxide semiconductor layer 140 also includes Poly-OS. Therefore, since the diffusion of hydrogen in the oxide semiconductor layer 140 is suppressed, the intrusion length ΔL of the third region 143 can be reduced.

[0104] [3. Method for Manufacturing Thin Film Transistor 10]

[0105] Reference Figure 6 to Figure 13 A method for manufacturing the thin film transistor 10 according to one embodiment of the present invention will be described. Figure 6 1 is a flowchart showing a method for manufacturing the thin film transistor 10 according to one embodiment of the present invention. Figure 7 to Figure 13 It is a schematic cross-sectional view showing a method for manufacturing the thin film transistor 10 according to one embodiment of the present invention.

[0106] like Figure 6 As shown, the method for manufacturing the thin film transistor 10 includes steps S1010 to S1110. Steps S1010 to S1110 are described in sequence below, but the order of the steps may be changed in the method for manufacturing the thin film transistor 10. In addition, the method for manufacturing the thin film transistor 10 may include further steps.

[0107] In step S1010, a light shielding layer 105 having a predetermined pattern is formed on the substrate 100. The light shielding layer 105 is patterned using photolithography. In addition, a first insulating layer 110 and a second insulating layer 120 are formed on the light shielding layer 105 (see Figure 7). The first insulating layer 110 and the second insulating layer 120 are formed by a CVD method. For example, silicon nitride and silicon oxide are formed as the first insulating layer 110 and the second insulating layer 120, respectively. When silicon nitride is used as the first insulating layer 110, the first insulating layer 110 can block impurities diffused from the substrate 100 side to the oxide semiconductor layer 140. When silicon oxide is used as the second insulating layer 120, the second insulating layer 120 can release oxygen by heat treatment.

[0108] In step S1020, an oxide semiconductor film 145 is formed over the second insulating layer 120 (see Figure 8 The oxide semiconductor film 145 is formed by a sputtering method. The thickness of the oxide semiconductor film 145 is, for example, not less than 10 nm and not more than 100 nm, preferably not less than 15 nm and not more than 70 nm, and more preferably not less than 20 nm and not more than 40 nm.

[0109] The oxide semiconductor film 145 in step S1020 is amorphous. In the Poly-OS technology, in order to make the oxide semiconductor layer 140 have a uniform polycrystalline structure within the substrate surface, the oxide semiconductor film 145 is preferably amorphous after film formation and before heat treatment. Therefore, it is preferred that the film formation conditions of the oxide semiconductor film 145 are conditions in which the oxide semiconductor layer 140 immediately after film formation does not crystallize as much as possible. In the case of forming the oxide semiconductor film 145 by sputtering, the oxide semiconductor film 145 is formed while the temperature of the object to be film-formed (the substrate 100 and the layer formed thereon) is controlled to be below 100°C. In addition, the oxide semiconductor film 145 is formed under conditions of low oxygen partial pressure. The oxygen partial pressure is greater than 2% and less than 20%, preferably greater than 3% and less than 15%, and more preferably greater than 3% and less than 10%.

[0110] In step S1030, the oxide semiconductor film 145 is patterned (see Fig. 9 ). The patterning of the oxide semiconductor film 145 is performed using photolithography. As the etching of the oxide semiconductor film 145, wet etching can be used, or dry etching can be used. In wet etching, an acidic etchant can be used for etching. As an etchant, for example, oxalic acid, PAN, sulfuric acid, hydrogen peroxide, or hydrofluoric acid can be used.

[0111] In step S1040, the oxide semiconductor film 145 is heat treated. Hereinafter, the heat treatment performed in step S1040 is referred to as "OS annealing". In OS annealing, the oxide semiconductor film 145 is maintained at a specified arrival temperature for a specified time. The specified arrival temperature is greater than 300°C and less than 500°C, preferably greater than 350°C and less than 450°C. In addition, the holding time at the arrival temperature is greater than 15 minutes and less than 120 minutes, preferably greater than 30 minutes and less than 60 minutes. Through OS annealing, the oxide semiconductor film 145 is crystallized to form an oxide semiconductor layer 140 having a polycrystalline structure.

[0112] In step S1050, a gate insulating layer 150 is formed on the oxide semiconductor layer 140 (see Fig.10 ). The gate insulating layer 150 is formed by a CVD method. For example, silicon oxide is formed as the gate insulating layer 150. In order to reduce defects in the gate insulating layer 150, the gate insulating layer 150 may be formed at a film forming temperature of 350° C. or higher. The thickness of the gate insulating layer 150 is greater than 50 nm and less than 300 nm, preferably greater than 60 nm and less than 200 nm, and more preferably greater than 70 nm and less than 150 nm. After the gate insulating layer 150 is formed, a process of introducing oxygen into a portion of the gate insulating layer 150 may be performed.

[0113] In step S1060, the oxide semiconductor layer 140 is heat treated. Hereinafter, the heat treatment performed in step S1060 is referred to as "oxidation annealing". When the gate insulating layer 150 is formed on the oxide semiconductor layer 140, a large number of oxygen defects are generated on the upper surface and side surfaces of the oxide semiconductor layer 140. If oxidation annealing is performed, oxygen is supplied from the second insulating layer 120 and the gate insulating layer 150 to the oxide semiconductor layer 140 to repair the oxygen defects.

[0114] In step S1070, a gate electrode 160 having a predetermined pattern is formed on the gate insulating layer 150 (see Fig.11 ). The gate electrode 160 is formed by sputtering or atomic layer deposition, and the gate electrode 160 is patterned using photolithography.

[0115] In step S1080, a source region S and a drain region D are formed in the oxide semiconductor layer 140 (see Fig.11). The source region S and the drain region D are formed by ion implantation. Specifically, the gate electrode 160 is used as a mask to implant impurities into the oxide semiconductor layer 140 via the gate insulating layer 150. As the implanted impurities, for example, argon (Ar), phosphorus (P) or boron (B) is used. In the source region S and the drain region D that do not overlap with the gate electrode 160, oxygen vacancies are generated due to the ion implantation, so the resistance of the source region S and the drain region D is reduced. On the other hand, in the channel region overlapping with the gate electrode 160, since no impurities are implanted, the resistance of the channel region CH does not decrease. In addition, due to the oxygen vacancies formed in the source region S and the drain region D, hydrogen is captured in the source region S and the drain region D. In addition, the diffusion coefficient of hydrogen of the Poly-OS contained in the oxide semiconductor layer 140 is small. Therefore, the diffusion of hydrogen from the source region S or the drain region D to the end of the channel region CH is suppressed. Thus, the intrusion length ΔL of the third region 143 can be reduced.

[0116] It should be noted that in the thin film transistor 10 , impurities are injected into the oxide semiconductor layer 140 through the gate insulating layer 150 , and thus the gate insulating layer 150 may contain impurities such as argon (Ar), phosphorus (P), or boron (B).

[0117] In step S1090, a third insulating layer 170 and a fourth insulating layer 180 are formed on the gate insulating layer 150 and the gate electrode 160 (see Fig.12 ). The third insulating layer 170 and the fourth insulating layer 180 are formed by CVD. For example, silicon oxide and silicon nitride are formed as the third insulating layer 170 and the fourth insulating layer 180, respectively. The thickness of the third insulating layer 170 is greater than 50 nm and less than 500 nm. The thickness of the fourth insulating layer 180 is also greater than 50 nm and less than 500 nm.

[0118] In step S1100, openings 171 and 173 are formed in the gate insulating layer 150, the third insulating layer, and the fourth insulating layer 180 (see Fig.13 ). By forming the openings 171 and 173 , the source region S and the drain region D of the oxide semiconductor layer 140 are exposed.

[0119] In step S1110, the source electrode 201 is formed on the fourth insulating layer 180 and inside the opening 171, and the drain electrode 203 is formed on the fourth insulating layer 180 and inside the opening 173. The source electrode 201 and the drain electrode 203 are formed in the same layer. Specifically, the source electrode 201 and the drain electrode 203 are formed by patterning a conductive film formed. Through the above steps, a Figure 1 The thin film transistor 10 is shown.

[0120] The above describes the manufacturing method of the thin film transistor 10, but various manufacturing methods can be used according to the structure of the thin film transistor 10. For example, in the thin film transistor 10A described as a modified example of the thin film transistor 10, the gate electrode 160 can also be used as a mask to pattern the gate insulating layer 150A in such a way that the upper surface and the end surface of the oxide semiconductor layer 140 are exposed. Next, the exposed oxide semiconductor layer 140 is plasma-treated using argon, helium, nitrogen or fluorine-based gases, thereby forming a source region S and a drain region D with low resistance. Thereafter, a third insulating layer 170A is formed in a manner covering the source region S and the drain region D. In this case, the oxygen defects in the source region S and the drain region D also capture hydrogen. In addition, the oxide semiconductor layer 140 includes Poly-OS. Therefore, it is possible to suppress the diffusion of hydrogen from the source region S or the drain region D to the end of the channel region CH, thereby reducing the intrusion length ΔL of the third region 143.

[0121] According to the thin film transistor 10 of this embodiment, since the oxide semiconductor layer 140 includes Poly-OS, diffusion of hydrogen from the source region S and the drain region D can be suppressed, thereby reducing the intrusion length ΔL in the channel region CH. As a result, the effective channel length L can be increased. eff , so the offset and deviation of the threshold voltage relative to the channel length L in the thin film transistor 10 can be suppressed. For example, even in the case of the thin film transistor 10 with a channel length L of 2 μm, excellent electrical characteristics can be obtained. Therefore, the channel length of the thin film transistor 10 has a high degree of freedom in design, and can be applied to various electronic devices or electrical devices.

[0122] <Second embodiment>

[0123] Reference Fig.14 An electronic device according to an embodiment of the present invention will be described.

[0124] Fig.14 1 is a schematic diagram showing an electronic device 1000 according to an embodiment of the present invention. Fig.14 , a smartphone is shown as an example of the electronic device 1000. The electronic device 1000 includes a display device 1100 with curved sides. The display device 1100 includes a plurality of pixels for displaying an image, and the plurality of pixels are controlled by a pixel circuit and a driving circuit. The pixel circuit and the driving circuit include the thin film transistor 10 described in the first embodiment. Since the thin film transistor 10 has a high field effect mobility, the responsiveness of the pixel circuit and the driving circuit can be improved, and as a result, the performance of the electronic device 1000 can be improved.

[0125] It should be noted that the electronic device 1000 involved in this embodiment is not limited to a smartphone. The electronic device 1000 also includes electronic devices with a display device, such as a clock, a tablet computer, a laptop computer, a car navigation system, or a television. In addition, the thin film transistor 10 described in the first embodiment can be applied to all electronic devices, regardless of whether they have a display device or not.

[0126] Example

[0127] The thin film transistor 10 will be described in further detail based on the produced sample. It should be noted that the embodiment to be described below is an embodiment of the thin film transistor 10, and the configuration of the thin film transistor 10 is not limited to the configuration of the embodiment to be described below.

[0128] [1. Difference in Crystallinity of Oxide Semiconductor Layer]

[0129] [1-1. Preparation of samples for electrical properties]

[0130] As a sample of the embodiment (hereinafter referred to as "Example Sample 1"), a thin film transistor 10 using the manufacturing method described in the first embodiment was produced. In Example Sample 1, an oxide semiconductor containing an indium element of 70% or more in atomic ratio relative to all metal elements was used as a sputtering target for forming an oxide semiconductor layer 140. The oxide semiconductor layer 140 in Example Sample 1 has an amorphous structure before OS annealing, but is crystallized by OS annealing and has a polycrystalline structure. That is, Example Sample 1 is a thin film transistor 10 containing Poly-OS.

[0131] As a sample of the comparative example (hereinafter referred to as "Comparative Example Sample 1"), a thin film transistor was produced in which an oxide semiconductor layer used indium gallium zinc oxide (IGZO) with an indium element ratio of less than 50%. The oxide semiconductor layer in Comparative Example Sample 1 had an amorphous structure before and after OS annealing. It should be noted that Comparative Example Sample 1 had the same structure as Example Sample 1 except for the oxide semiconductor layer.

[0132] [1-2. Electrical characteristics]

[0133] Fig.15 Graph showing the electrical characteristics of Example Sample 1 and Comparative Example Sample 1. Fig.15 The electrical characteristics of multiple thin film transistors having a channel width W of 7.5 μm and a channel length L of 2 μm, 3 μm, and 4 μm in each of Example Sample 1 and Comparative Example Sample 1 are shown in FIG. The drain current Id is shown on the vertical axis of each graph, and the gate voltage Vg is shown on the horizontal axis. The measurement conditions of the electrical characteristics are shown in Table 1. In addition, the electrical characteristics obtained by measuring 18 thin film transistors (i.e., N number = 18) are overlapped in each graph.

[0134] [Table 1]

[0135] Source-drain voltage 0.1V (dashed line), 10V (solid line) Gate voltage -15V~+15V Measurement environment room temperature, dark room

[0136] In Example Sample 1, good electrical characteristics were obtained in the thin film transistors 10 having a channel length L of 2 μm, 3 μm, and 4 μm. That is, in Example Sample 1, a result was obtained in which the shift and deviation of the threshold voltage relative to the channel length L were small. On the other hand, in Comparative Example Sample 1, as the channel length L became smaller, the threshold voltage shifted in the negative direction, and the deviation of the threshold voltage became very large in terms of the electrical characteristics of the thin film transistor having a channel length L of 2 μm.

[0137] According to the results of the electrical characteristics of Example Sample 1 and Comparative Example Sample 1, it is believed that the oxide semiconductor layer 140 includes Poly-OS, thereby suppressing the diffusion of hydrogen from the source region S and the drain region D to the channel region CH. Therefore, in order to study the difference in the diffusion coefficient of hydrogen between Poly-OS and amorphous IGZO, TDS measurement was performed. The TDS measurement is described below.

[0138] [1-3. Preparation of samples for TDS measurement]

[0139] As a sample for TDS measurement of the embodiment (hereinafter referred to as "Example Sample 2"), a sample having Poly-OS (film thickness 50 nm) formed on a silicon substrate was prepared. In addition, as a sample for TDS measurement of the comparative example (hereinafter referred to as "Comparative Example Sample 2"), a sample having amorphous IGZO (film thickness 50 nm) formed on a silicon substrate was prepared.

[0140] [1-4. TDS measurement]

[0141] Fig.16 : is a graph showing the results of TDS measurement of Example Sample 2 and Comparative Example Sample 2. Fig.16 Graph 1 shows the temperature distribution of the molecular weight 18 at a heating rate of 10° C. / min. It should be noted that the temperature T on the horizontal axis of the graph is the temperature of the mounting table.

[0142] like Fig.16 As shown, in Example Sample 2 ( Fig.16 In the solid line in Figure 2), a peak is observed at around 530°C. On the other hand, in Comparative Example Sample 2 ( Fig.16 The peak is observed near 310°C in the dashed line in the figure. Since the molecular weight of 18 is equivalent to water (H2O), it is considered that Fig.16The temperature distribution shown is caused by water detached from Poly-OS or amorphous IGZO. Here, the water detected by TDS measurement includes not only water adsorbed in Poly-OS or amorphous IGZO, but also water generated by the diffusion of hydrogen contained in Poly-OS or amorphous IGZO and the reaction with oxygen. It is difficult to distinguish whether the peak detected in the temperature distribution is caused by the former or the latter. However, it is believed that in the case where hydrogen is difficult to diffuse, it is difficult to react with oxygen, so the generation of water in the latter is suppressed.

[0143] The peak temperature of Example Sample 2 is higher than the peak temperature of Comparative Example Sample 2. This means that, in the Poly-OS of Example Sample 2, since hydrogen is difficult to diffuse, a higher temperature is required to diffuse hydrogen. That is, it is believed that since hydrogen is difficult to diffuse in Poly-OS compared to amorphous IGZO, in Example Sample 2, the peak temperature is shifted to the high temperature side compared to Comparative Example Sample 2. Therefore, it can be said that the oxide semiconductor with a polycrystalline structure such as the Poly-OS of Example Sample 2 has a smaller diffusion coefficient of hydrogen than the oxide semiconductor with an amorphous structure such as the amorphous IGZO of Comparative Example Sample 2.

[0144] As described above, based on the results of the electrical characteristics and TDS measurement, it can be considered that the diffusion of hydrogen is suppressed in the oxide semiconductor layer 140 having a polycrystalline structure compared to the oxide semiconductor layer having an amorphous structure. Therefore, in Example Sample 1, the diffusion of hydrogen from the source region S or the drain region D to the channel region CH is suppressed. As a result, in Example Sample 1, good electrical characteristics can be obtained even in a thin film transistor with a small channel length.

[0145] [2. Differences caused by manufacturing process conditions]

[0146] [2-1. Preparation of samples for SCM observation]

[0147] As a sample for SCM observation of the embodiment, Example Sample 1 was used. In addition, as a sample for SCM observation of the embodiment with different manufacturing process conditions (hereinafter referred to as "Example Sample 3"), a thin film transistor 10A described as a modified example of the first embodiment was produced. The oxide semiconductor layer 140 of the thin film transistor 10A also includes Poly-OS. Among them, in Example Sample 1, ion implantation is performed on the oxide semiconductor layer 140 through the gate insulating layer 150 to form the source region S and the drain region D. In contrast, in Example Sample 3, the oxide semiconductor layer 140 exposed from the gate insulating layer 150A is directly plasma treated to form the source region S and the drain region D.

[0148] [2-2.SCM observation]

[0149] Fig.17 and Fig.19 The following are graphs showing the results of SCM observation of Example Sample 1 and Example Sample 3, respectively. Fig.17 and Fig.19 In FIG. 2 , not only the ΔC / ΔV signal obtained by SCM observation but also the distribution (arbitrary unit) in AFM observation are shown. The apparatus and conditions for SCM observation are shown in Table 2.

[0150] [Table 2]

[0151] Device Bruker Dimension 3100 SCM Probe Ptlr coated silicon cantilever Modulation voltage 2.0V DC bias voltage 0V

[0152] like Fig.17 and Fig.19 As shown, it can be seen that the end of the gate electrode 160 observed by AFM is substantially consistent with the end of the channel region CH observed by SCM.

[0153] Fig.18A , Fig.18B and 17 C is a graph in which the ΔC / ΔV signal obtained by SCM observation of Example Sample 1 is fitted using a Gaussian function, a complementary error function, and a Lorentzian function. Fig. 20A , Fig. 20B and Fig. 20C This is a graph showing the ΔC / ΔV signal obtained by SCM observation of Example Sample 3 using a Gaussian function, a complementary error function, and a Lorentz function. Figures 18A to 18C and Figure 20A to Figure 20C In FIG. 1 , the ΔC / ΔV signal and the fitting function obtained by SCM observation are indicated by dashed lines and solid lines, respectively. In addition, when fitting, the distance is corrected so that the end of the gate electrode 160 becomes the origin. The positive direction of the distance is the direction overlapping with the gate electrode 160, and the negative direction of the distance is the direction not overlapping with the gate electrode 160.

[0154] Table 3 shows the values ​​c calculated by fitting the ΔC / ΔV signal using the fitting functions. Table 4 shows the intrusion length ΔL converted from the calculated value c based on ΔL=3c.

[0155] [Table 3]

[0156]

[0157] [Table 4]

[0158]

[0159] As shown in Table 4, using any fitting function, the intrusion length ΔL of Example Sample 1 is about 0.20 μm, and the intrusion length ΔL of Example Sample 3 is about 0.50 μm. According to this result, in the oxide semiconductor layer 140 including Poly-OS, the intrusion length ΔL can be controlled to be 0.60 μm or less. In particular, in Example Sample 1, when using any fitting function, the intrusion length ΔL can be controlled to be 0.30 μm or less.

[0160] As described above, according to the results of SCM observation, even if the oxide semiconductor layer 140 has a polycrystalline structure, the intrusion length ΔL of the third region 143 varies depending on the conditions of the process for forming the source region S and the drain region D of the thin film transistor 10. In particular, in the thin film transistor 10 including Poly-OS, as shown in the first embodiment, Figure 6 As described in the flowchart of , it can be seen that if ion implantation of the oxide semiconductor layer 140 through the gate insulating layer 150 is performed to form the source region S and the drain region D, the intrusion length ΔL of the third region 143 becomes smaller. Therefore, the manufacturing method of the thin film transistor 10 based on ion implantation of the oxide semiconductor layer 140 through the gate insulating layer 150 is an effective method for controlling in Poly-OS in a manner that further suppresses the diffusion of hydrogen from the source region S and the drain region D. As a result, for the thin film transistor 10, even in the case of a thin film transistor 10 with a channel length L of 2μm, excellent electrical characteristics can be obtained. Therefore, the channel length of the thin film transistor 10 has a high degree of freedom in design, and can be applied to various electronic devices or electrical devices.

[0161] The various embodiments described above as embodiments of the present invention can be appropriately combined and implemented as long as they do not contradict each other. In addition, solutions obtained by adding, deleting or designing components or adding, omitting or changing conditions of processes based on the various embodiments by those skilled in the art are also included in the scope of the present invention as long as they have the gist of the present invention.

[0162] Even if there are other effects different from the effects brought about by the schemes of the above-mentioned embodiments, if they are clearly known from the description of this specification or can be easily predicted by those skilled in the art, they are of course understood to be the effects brought about by the present invention.

[0163] Description of Reference Numerals

[0164] 10: thin film transistor, 100: substrate, 105: light shielding layer, 110: first insulating layer, 120: second insulating layer, 140: oxide semiconductor layer, 141: first region, 142: second region, 143: third region, 145: oxide semiconductor film, 150: gate insulating layer, 160: gate electrode, 170: third insulating layer, 171: opening, 173: opening, 180: fourth insulating layer, 200: source / drain electrode, 201: source electrode, 203: drain electrode, 1000: electronic device, 1100: display device, 5001: probe, 5002: UHF capacitive sensor, CH: channel region, S: source region, D: drain region

Claims

1. A thin film transistor, comprising: an oxide semiconductor layer having a polycrystalline structure disposed on a substrate; a gate electrode disposed on the oxide semiconductor layer; and A gate insulating layer provided between the oxide semiconductor layer and the gate electrode, The oxide semiconductor layer includes: a first region overlapping the gate electrode and having a first carrier concentration; a second region not overlapping the gate electrode and having a second carrier concentration; and a third region overlapping the gate electrode and located between the first region and the second region, The second carrier concentration is greater than the first carrier concentration, The carrier concentration of the third region decreases in the channel length direction from the second region toward the first region, The length of the third region in the channel length direction is 0.60 μm or less.

2. The thin film transistor according to claim 1, wherein: The length of the third region is less than or equal to 0.50 μm.

3. The thin film transistor according to claim 1, wherein: The length of the third region is less than or equal to 0.40 μm.

4. The thin film transistor according to claim 1, wherein: The length of the third region is three times the scale parameter calculated by fitting a ΔC / ΔV signal (where ΔC is the change in electrostatic capacitance and ΔV is the AC voltage) obtained by scanning capacitance microscopy using a Gaussian function.

5. The thin film transistor according to claim 1, wherein: The length of the third region is three times the scale parameter calculated by fitting the ΔC / ΔV signal (where ΔC is the change in electrostatic capacitance and ΔV is the AC voltage) obtained by scanning capacitance microscopy using a complementary error function.

6. The thin film transistor according to claim 1, wherein: The length of the third region is three times the half-width at half maximum calculated by fitting a ΔC / ΔV signal (where ΔC is the change in electrostatic capacitance and ΔV is the AC voltage) obtained by scanning capacitance microscopy using a Lorentz function.

7. The thin film transistor according to claim 1, wherein: The second region includes at least one of boron, phosphorus, and argon.

8. The thin film transistor according to claim 1, wherein: An end portion of the oxide semiconductor layer is covered by the gate insulating layer.

9. The thin film transistor according to claim 8, wherein: The gate insulating layer includes at least one of boron, phosphorus and argon.

10. The thin film transistor according to claim 1, wherein: The oxide semiconductor layer contains indium and at least one metal element. The ratio of the indium element to the indium element and the at least one metal element is 50% or more.

11. The thin film transistor according to claim 1, wherein: The crystal structure of the oxide semiconductor layer is a bixbyite structure.

12. An electronic device comprising the thin film transistor according to any one of claims 1 to 11.

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