Three-dimensional memory devices including trench bridges and methods of forming same

Abstract

A three-dimensional memory device includes layer stacks, each of the layer stacks including a first layer alternating stack of first insulating layers and first conductive layers and a second layer alternating stack of second insulating layers and second conductive layers, the first layer alternating stack and the second layer alternating stack being separated by a backside trench. A memory opening fill structure extends vertically through a respective layer stack and includes a respective vertical stack of memory elements and a respective vertical semiconductor channel. In one embodiment, a bridge structure spans the entire width of the backside trench such that a top surface of the bridge structure is below a top surface of the second layer alternating stack and a bottom surface of the bridge structure is above a bottom surface of the first layer alternating stack. In another embodiment, the perforated bridge structure includes a plurality of vertically extending openings.

Description

[0001] Related Applications

[0002] This application claims the benefit of priority to U.S. Non-Provisional Patent Application No. 17 / 819,081 filed on August 11, 2022 and U.S. Non-Provisional Patent Application No. 17 / 819,097 filed on August 11, 2022, the entire contents of which are hereby incorporated by reference for all purposes. Technical Field

[0003] The present disclosure relates generally to the field of semiconductor devices, and in particular to three-dimensional memory devices and methods of forming the same including bridges that provide enhanced structural support for preventing stack collapse during a replacement process. Background Art

[0004] A three-dimensional memory device including three-dimensional vertical NAND strings with one bit per cell is disclosed in an article by T. Endom et al. entitled “Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell,” IEDM Proc. (2001) 33-36. Summary of the invention

[0005] According to one aspect of the present disclosure, a three-dimensional memory device includes: a pair of layer stacks extending laterally along a first horizontal direction and laterally spaced apart from each other by backside trenches along a second horizontal direction, wherein each layer stack in the layer stacks includes a first layer alternating stack of a first insulating layer and a first conductive layer, a first insulating cap layer located above the first layer alternating stack, and a second layer alternating stack of a second insulating layer and a second conductive layer located above the first insulating cap layer; a memory opening extending vertically through the pair of layer stacks; a memory opening filling structure located in a corresponding memory opening and including a corresponding vertical stack of memory elements and a corresponding vertical semiconductor channel; and a bridge structure spanning the entire width of the backside trench along the second horizontal direction. A top surface of the bridge structure is located below a top surface of the second layer alternating stack, and a bottom surface of the bridge structure is located above a bottom surface of the first layer alternating stack.

[0006] According to another aspect of the present disclosure, a method for forming a semiconductor structure includes: forming a first layer stack extending laterally along a first horizontal direction and laterally spaced apart from each other along a second horizontal direction by a first layer back side groove, and wherein each first layer stack in the first layer stack includes a first layer alternating stack of a first insulating layer and a first sacrificial material layer and a first insulating cap layer covering the first layer alternating stack; forming a filling material stack including a sacrificial trench filling structure and a bridge material matrix in each first layer back side groove in the first layer back side groove; forming a second layer stack above the first layer alternating stack, wherein the second layer stack extends laterally along the first horizontal direction and laterally spaced apart from each other along the second horizontal direction by a second layer back side groove, and wherein each second layer stack in the second layer stack includes a second layer alternating stack of a second insulating layer and a second sacrificial material layer; patterning each bridge material matrix in the bridge material matrix into a corresponding plurality of bridge structures laterally spaced apart along the first horizontal direction; removing the sacrificial trench filling structure from under the plurality of bridge structures; and replacing the first sacrificial material layer and the second sacrificial material layer with a first conductive layer and a second conductive layer, respectively.

[0007] According to another aspect of the present disclosure, a three-dimensional memory device includes: a pair of layer stacks, which extend laterally along a first horizontal direction and are laterally spaced apart from each other along a second horizontal direction by backside trenches, wherein each layer stack in the pair of layer stacks includes a first layer alternating stack of a first insulating layer and a first conductive layer and a second layer alternating stack of a second insulating layer and a second conductive layer; a memory opening, which extends vertically through the pair of layer stacks; a memory opening filling structure, which is located in the corresponding memory opening and includes a corresponding vertical stack of memory elements and a corresponding vertical semiconductor channel; and a perforated bridge structure, which includes a plurality of vertically extending openings located in the backside trenches.

[0008] According to another aspect of the present disclosure, a method for forming a semiconductor structure includes: forming a first vertical alternating sequence of a first continuous insulating layer and a first continuous sacrificial material layer; dividing the first vertical alternating sequence into a first layer alternating stack of a first insulating layer and a first sacrificial material layer by forming a first layer back side trench, wherein the first layer alternating stacks extend laterally along a first horizontal direction and are laterally spaced apart from each other by the first layer back side trenches along a second horizontal direction; forming a filling material stack including a sacrificial trench filling structure and a bridge material matrix in each first layer back side trench in the first layer back side trench; forming a first layer alternating stack of a first insulating layer and a first sacrificial material layer above the first layer alternating stack and the filling material stack; a second vertical alternating sequence of a second continuous insulating layer and a second continuous sacrificial material layer; forming a plurality of rows of discrete backside openings through the second vertical alternating sequence and through the bridge material matrix, wherein each of the bridge material matrices is converted into a corresponding perforated bridge structure, and a corresponding plurality of openings vertically extend through the corresponding perforated bridge structure; dividing the second vertical alternating sequence into a second layer alternating stack of second insulating layers and second sacrificial material layers by laterally extending the discrete backside openings, wherein the discrete backside openings in each of these rows merge with each other to form a second layer of backside grooves; and replacing the first sacrificial material layer and the second sacrificial material layer with the first conductive layer and the second conductive layer, respectively. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a vertical cross-sectional view of a first exemplary structure after forming an optional semiconductor device, an optional lower level dielectric layer, an optional lower metal interconnect structure, a semiconductor material layer, and a first vertical alternating sequence of a first continuous insulating layer and a first continuous sacrificial material layer according to the first embodiment of the present disclosure.

[0010] Figure 2 is a vertical cross-sectional view of the first exemplary structure after forming a first stepped surface and a first layer of rearwardly stepped dielectric material portion according to the first embodiment of the present disclosure.

[0011] Figure 3A is a vertical cross-sectional view of a first exemplary structure after forming a first layer opening according to the first embodiment of the present disclosure.

[0012] Figure 3B yes Figure 3A A top view of the first exemplary structure. The vertical plane A-A' is Figure 3A A plane of a vertical section.

[0013] Figure 3C It is along Figure 3B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'.

[0014] Figure 3D It is along Figure 3B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane DD'.

[0015] Figure 4A is a vertical cross-sectional view of the first exemplary structure after forming a sacrificial dielectric liner layer, a sacrificial semiconductor liner layer, and a sacrificial fill material layer according to the first embodiment of the present disclosure.

[0016] Figure 4B yes Figure 4A A top view of the first exemplary structure. The vertical plane A-A' is Figure 4A A plane of a vertical section.

[0017] Figure 4C It is along Figure 4B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'.

[0018] Figure 4D It is along Figure 4B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane DD'.

[0019] Figure 5A is a vertical cross-sectional view of the first exemplary structure after forming a sacrificial first layer opening filling structure and a sacrificial stop material layer according to the first embodiment of the present disclosure.

[0020] Figure 5B yes Figure 5A A top view of the first exemplary structure. The vertical plane A-A' is Figure 5A A plane of a vertical section.

[0021] Figure 5C It is along Figure 5B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'.

[0022] Figure 5D It is along Figure 5B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane DD'.

[0023] Fig. 6A is a vertical cross-sectional view of the first exemplary structure after forming a first layer of backside trenches according to the first embodiment of the present disclosure.

[0024] Figure 6B yes Fig. 6A A top view of the first exemplary structure. The vertical plane A-A' is Fig. 6A A plane of a vertical section.

[0025] Figure 6C It is along Figure 6BA vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'.

[0026] Fig.6D It is along Figure 6B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane DD'.

[0027] Fig. 7A is a vertical cross-sectional view of the first exemplary structure after forming a sacrificial trench fill structure according to the first embodiment of the present disclosure.

[0028] Figure 7B yes Fig. 7A A top view of the first exemplary structure. The vertical plane A-A' is Fig. 7A A plane of a vertical section.

[0029] Figure 7C It is along Figure 7B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'.

[0030] Fig.7D It is along Figure 7B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane DD'.

[0031] Fig. 8A is a vertical cross-sectional view of the first exemplary structure after forming a matrix of bridge material and removing a layer of sacrificial stop material according to the first embodiment of the present disclosure.

[0032] Figure 8B yes Fig. 8A A top view of the first exemplary structure. The vertical plane A-A' is Fig. 8A A plane of a vertical section.

[0033] Figure 8C It is along Figure 8B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'.

[0034] Fig.8D It is along Figure 8B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane DD'.

[0035] Fig. 8E is a top view of an alternative embodiment of the first exemplary structure according to the first embodiment of the present disclosure.

[0036] Fig. 9A is a vertical cross-sectional view of the first exemplary structure after forming a second vertical alternating sequence of a second continuous insulating layer and a second continuous sacrificial material layer, a second stepped surface, and a second layer of backward stepped dielectric material portion according to the first embodiment of the present disclosure.

[0037] Fig. 9B yes Fig. 9A A top view of the first exemplary structure. The vertical plane A-A' is Fig. 9A A plane of a vertical section.

[0038] Fig. 9C It is along Fig. 9B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'.

[0039] Fig.9D It is along Fig. 9B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane DD'.

[0040] Fig. 10A is a vertical cross-sectional view of the first exemplary structure after forming the second layer opening according to the first embodiment of the present disclosure.

[0041] Fig. 10B yes Fig. 10A A top view of the first exemplary structure. The vertical plane A-A' is Fig. 10A A plane of a vertical section.

[0042] Fig. 10C It is along Fig. 10B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'.

[0043] Fig. 10D It is along Fig. 10B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane DD'.

[0044] Fig.11A is a vertical cross-sectional view of the first exemplary structure after forming an inter-layer memory opening and an inter-layer support opening according to the first embodiment of the present disclosure.

[0045] Fig. 11B yes Fig.11A A top view of the first exemplary structure. The vertical plane A-A' is Fig.11A A plane of a vertical section.

[0046] Fig. 11C It is along Fig. 11B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'.

[0047] Fig.11D It is along Fig. 11B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane DD'.

[0048] FIG. 12A to FIG. 12DSequential vertical cross-sectional views of a memory opening during formation of a memory opening filling structure according to a first embodiment of the present disclosure are shown.

[0049] Fig.13A is a vertical cross-sectional view of the first exemplary structure after forming a memory opening filling structure and a support pillar structure according to the first embodiment of the present disclosure.

[0050] Fig. 13B yes Fig.13A A top view of the first exemplary structure. The vertical plane A-A' is Fig.13A A plane of a vertical section.

[0051] Fig. 13C It is along Fig. 13B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'.

[0052] Fig.13D It is along Fig. 13B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane DD'.

[0053] Fig.14A is a vertical cross-sectional view of the first exemplary structure after forming a second layer backside trench according to the first embodiment of the present disclosure.

[0054] Fig. 14B yes Fig.14A A top view of the first exemplary structure. The vertical plane A-A' is Fig.14A A plane of a vertical section.

[0055] Fig. 14C It is along Fig. 14B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'.

[0056] Fig.14D It is along Fig. 14B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane DD'.

[0057] Fig.15A is a vertical cross-sectional view of the first exemplary structure after forming a patterned photoresist layer according to the first embodiment of the present disclosure.

[0058] Fig. 15B yes Fig.15A A top view of the first exemplary structure. The vertical plane A-A' is Fig.15A A plane of a vertical section.

[0059] Fig. 15C It is along Fig. 15B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'.

[0060] Fig.15D It is along Fig. 15B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane DD'.

[0061] Fig.16A is a vertical cross-sectional view of the first exemplary structure after patterning a bridge material matrix into bridge structures and removing sacrificial trench fill structures according to the first embodiment of the present disclosure.

[0062] Fig. 16B yes Fig.16A A top view of the first exemplary structure. The vertical plane A-A' is Fig.16A A plane of a vertical section.

[0063] Fig. 16C It is along Fig. 16B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'.

[0064] Fig.16D It is along Fig. 16B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane DD'.

[0065] Fig.17 is a vertical cross-sectional view of a first exemplary structure after forming a backside recess according to the first embodiment of the present disclosure.

[0066] Fig.18 is a vertical cross-sectional view of a first exemplary structure after forming a conductive layer according to the first embodiment of the present disclosure.

[0067] Fig.19A is a vertical cross-sectional view of the first exemplary structure after forming a source region and a backside trench fill structure according to the first embodiment of the present disclosure.

[0068] Fig.19B yes Fig.19A A top view of the first exemplary structure. The vertical plane A-A' is Fig.19A A plane of a vertical section.

[0069] Fig.19C It is along Fig.19B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'.

[0070] Fig. 20 is a vertical cross-sectional view of the first exemplary structure after forming various contact via structures according to the first embodiment of the present disclosure.

[0071] Fig.21Ais a vertical cross-sectional view of a second exemplary structure after forming a first layer of openings including a first layer of backside openings according to the second embodiment of the present disclosure.

[0072] Fig.21B yes Fig.21A A top view of the second exemplary structure of FIG. The vertical plane AA' is Fig.21A A plane of a vertical section.

[0073] Fig. 21C It is along Fig.21B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane CC'.

[0074] Fig.22A is a vertical cross-sectional view of a second exemplary structure after forming a sacrificial dielectric liner layer, a sacrificial semiconductor liner layer, and a sacrificial fill material layer according to the second embodiment of the present disclosure.

[0075] Fig. 22B yes Fig.22A A top view of the second exemplary structure of FIG. The vertical plane AA' is Fig.22A A plane of a vertical section.

[0076] Fig. 22C It is along Fig. 22B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane CC'.

[0077] Fig.23A is a vertical cross-sectional view of a second exemplary structure after forming and patterning a first sacrificial capping layer and removing a sacrificial backside opening fill structure according to the second embodiment of the present disclosure.

[0078] Fig. 23B yes Fig.23A A top view of the second exemplary structure of FIG. The vertical plane AA' is Fig.23A A plane of a vertical section.

[0079] Fig.23C It is along Fig. 23B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane CC'.

[0080] Fig.24A is a vertical cross-sectional view of a second exemplary structure after forming a first layer backside trench according to a second embodiment of the present disclosure.

[0081] Fig. 24B yes Fig.24A A top view of the second exemplary structure of FIG. The vertical plane AA' is Fig.24A A plane of a vertical section.

[0082] Fig.24C It is along Fig. 24B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane CC'.

[0083] Fig.25A is a vertical cross-sectional view of a second exemplary structure after forming a sacrificial trench fill structure according to the second embodiment of the present disclosure.

[0084] Fig.25B yes Fig.25A A top view of the second exemplary structure of FIG. The vertical plane AA' is Fig.25A A plane of a vertical section.

[0085] Fig.25C It is along Fig.25B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane CC'.

[0086] Fig.26A is a vertical cross-sectional view of a second exemplary structure after forming a bridge material matrix and removing a first sacrificial capping layer according to a second embodiment of the present disclosure.

[0087] Fig.26B yes Fig.26A A top view of the second exemplary structure of FIG. The vertical plane A-A' is Fig.26A A plane of a vertical section.

[0088] Fig.26C It is along Fig.26B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane CC'.

[0089] Fig.26D is a top view of an alternative embodiment of the second exemplary structure

[0090] Fig.27A is a vertical cross-sectional view of a second exemplary structure after forming a second vertical alternating sequence of a second continuous insulating layer and a second continuous sacrificial material layer, a second stepped surface, and a second layer of backward stepped dielectric material portion according to a second embodiment of the present disclosure.

[0091] Fig.27B yes Fig.27A A top view of the second exemplary structure of FIG. The vertical plane AA' is Fig.27A A plane of a vertical section.

[0092] Fig.27C It is along Fig.27B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane CC'.

[0093] Fig.28Ais a vertical cross-sectional view of a second exemplary structure after forming second layer openings including second layer backside openings and after patterning a bridge material matrix into a perforated bridge structure according to the second embodiment of the present disclosure.

[0094] Fig.28B yes Fig.28A A top view of the second exemplary structure of FIG. The vertical plane AA' is Fig.28A A plane of a vertical section.

[0095] Fig.28C It is along Fig.28B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane CC'.

[0096] Fig.29A is a vertical cross-sectional view of a second exemplary structure after forming a second layer of sacrificial opening filling structure according to the second embodiment of the present disclosure.

[0097] Fig.29B yes Fig.29A A top view of the second exemplary structure of FIG. The vertical plane AA' is Fig.29A A plane of a vertical section.

[0098] Fig.29C It is along Fig.29B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane CC'.

[0099] Fig. 30A is a vertical cross-sectional view of a second exemplary structure after forming a second sacrificial capping layer and a patterned photoresist layer and patterning the second sacrificial capping layer according to the second embodiment of the present disclosure.

[0100] Fig. 30B yes Fig. 30A A top view of the second exemplary structure of FIG. The vertical plane AA' is Fig. 30A A plane of a vertical section.

[0101] Fig. 30C It is along Fig. 30B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane CC'.

[0102] Fig.31A is a vertical cross-sectional view of a second exemplary structure after forming a memory opening filling structure and a support pillar structure according to the second embodiment of the present disclosure.

[0103] Fig.31B yes Fig.31A A top view of the second exemplary structure of FIG. The vertical plane AA' is Fig.31A A plane of a vertical section.

[0104] Fig.31C It is along Fig.31B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane CC'.

[0105] Fig.32A is a vertical cross-sectional view of a second exemplary structure after depositing and patterning a contact level dielectric layer according to the second embodiment of the present disclosure.

[0106] Fig.32B yes Fig.32A A top view of the second exemplary structure of FIG. The vertical plane AA' is Fig.32A A plane of a vertical section.

[0107] Fig.32C It is along Fig.32B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane CC'.

[0108] Fig.33A is a vertical cross-sectional view of a second exemplary structure after removal of a second layer of backside opening filling structure according to the second embodiment of the present disclosure.

[0109] Fig.33B yes Fig.33A A top view of the second exemplary structure of FIG. The vertical plane AA' is Fig.33A A plane of a vertical section.

[0110] Fig.33C It is along Fig.33B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane CC'.

[0111] Fig.34A is a vertical cross-sectional view of a second exemplary structure after forming a second layer backside trench according to a second embodiment of the present disclosure.

[0112] Fig.34B yes Fig.34A A top view of the second exemplary structure of FIG. The vertical plane AA' is Fig.34A A plane of a vertical section.

[0113] Fig.34C It is along Fig.34B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane CC'.

[0114] Fig.35A is a vertical cross-sectional view of the second exemplary structure after removal of the first layer of sacrificial backside trench fill structure according to the second embodiment of the present disclosure.

[0115] Fig.35B yes Fig.35AA top view of the second exemplary structure of FIG. The vertical plane AA' is Fig.35A A plane of a vertical section.

[0116] Fig.35C It is along Fig.35B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane CC'.

[0117] Fig.36A is a vertical cross-sectional view of a second exemplary structure after replacing the sacrificial material layer with a conductive layer according to the second embodiment of the present disclosure.

[0118] Fig.36B yes Fig.36A A top view of the second exemplary structure of FIG. The vertical plane AA' is Fig.36A A plane of a vertical section.

[0119] Fig.36C It is along Fig.36B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane CC'.

[0120] Fig.36D It is along Fig.36A A horizontal cross-sectional view of the second exemplary structure taken along a horizontal plane DD'.

[0121] Fig.37A is a vertical cross-sectional view of a second exemplary structure after forming a source region and a backside trench fill structure according to the second embodiment of the present disclosure.

[0122] Fig.37B yes Fig.37A A top view of the second exemplary structure of FIG. The vertical plane AA' is Fig.37A A plane of a vertical section.

[0123] Fig.37C It is along Fig.37B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane CC'.

[0124] Fig.37D It is along Fig.37A A horizontal cross-sectional view of the second exemplary structure taken along a horizontal plane DD'.

[0125] Fig.37E It is along Fig.37A A horizontal cross-sectional view of the second exemplary structure taken along a horizontal plane EE'.

[0126] Fig.37F It is along Fig.37A A vertical cross-sectional view of the second exemplary structure taken along a vertical plane FF'.

[0127] Figure 37G is along the line corresponding to Fig.37A A horizontal cross-sectional view of an alternative embodiment of a second exemplary structure taken along a horizontal plane DD'.

[0128] Fig.38 is a vertical cross-sectional view of a second exemplary structure after forming various contact via structures according to the second embodiment of the present disclosure. DETAILED DESCRIPTION

[0129] As described above, embodiments of the present disclosure relate to three-dimensional memory devices and methods of forming the same including bridges that provide enhanced structural support for preventing stack collapse during a replacement process, and various aspects thereof are now described in detail.

[0130] The drawings are not drawn to scale. Multiple instances of an element may be repeated where a single instance of an element is shown, unless explicitly described or otherwise clearly indicated that there is no repetition of an element. Serial numbers such as "first," "second," and "third" are used only to identify similar elements, and different serial numbers may be used throughout the specification and claims of this disclosure. The term "at least one" element refers to all possibilities including the possibility of a single element and the possibility of multiple elements.

[0131] The same reference numerals represent the same element or similar element. Unless otherwise specified, elements with the same reference numerals are assumed to have the same composition and the same function. Unless otherwise specified, "contact" between elements refers to direct contact between elements providing an edge or surface shared by the elements. If two or more elements are not in direct contact with each other, the two elements are "separated" from each other. As used herein, a first element positioned "on" a second element can be positioned on the outer side of the surface of the second element or on the inner side of the second element. As used herein, if there is physical contact between the surface of the first element and the surface of the second element, the first element is "directly" positioned on the second element. As used herein, if there is a conductive path composed of at least one conductive material between the first element and the second element, the first element is "electrically connected to" the second element. As used herein, a "prototype" structure or a "process" structure refers to a transient structure that is subsequently modified in the shape or composition of at least one of the components.

[0132] As used herein, "layer" refers to a portion of a material including a region having a thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have an extent that is less than the extent of an underlying or overlying structure. In addition, a layer may be a region of a uniform or non-uniform continuous structure having a thickness that is less than the thickness of a first continuous structure. For example, a layer may be located between the top and bottom surfaces of a first continuous structure or between any pair of horizontal planes at the top and bottom surfaces of the first continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layers thereon, above, and / or below.

[0133] As used herein, a first surface and a second surface "vertically coincide" with each other if the second surface is above or below the first surface and if there is a vertical plane or a substantially vertical plane that includes the first surface and the second surface. A substantially vertical plane is a plane that extends straight along a direction that deviates from the vertical direction at an angle of less than 5 degrees. A vertical plane or a substantially vertical plane is straight along the vertical direction or a substantially vertical direction and may or may not include curvature along a direction perpendicular to the vertical direction or the substantially vertical direction.

[0134] As used herein, a "memory level" or "memory array level" refers to a level corresponding to the general area between a first horizontal plane (i.e., a plane parallel to the top surface of the substrate) including the topmost surface of the array of memory elements and a second horizontal plane including the bottommost surface of the array of memory elements. As used herein, a "through-stack" element refers to an element that extends vertically through a memory level.

[0135] As used herein, "semiconductor material" refers to a material having an electrical conductivity in the range of 1.0×10-5S / m to 1.0×105S / m. As used herein, "semiconductor material" refers to a material having an electrical conductivity in the range of 1.0×10-5S / m to 1.0S / m in the absence of an electrical dopant, and is capable of producing a doped material having an electrical conductivity in the range of 1.0S / m to 1.0×107S / m when appropriately doped with an electrical dopant. As used herein, "electrical dopant" refers to a p-type dopant that adds holes to the valence band within the energy band structure, or an n-type dopant that adds electrons to the conduction band within the energy band structure. As used herein, "conductive material" refers to a material having an electrical conductivity greater than 1.0×105S / m. As used herein, "insulator material" or "dielectric material" refers to a material having an electrical conductivity less than 1.0×10-5S / m. As used herein, "heavily doped semiconductor material" refers to a semiconductor material doped with an electrical dopant at a sufficiently high atomic concentration to become a conductive material (i.e., having a conductivity greater than 1.0×105S / m) when formed into a crystalline material or converted into a crystalline material by an annealing process (e.g., starting from an initial amorphous state). "Doped semiconductor material" may be a heavily doped semiconductor material, or may be a semiconductor material including an electrical dopant (i.e., a p-type dopant and / or an n-type dopant) at a concentration providing a conductivity in the range of 1.0×10-5S / m to 1.0×107S / m. "Intrinsic semiconductor material" refers to a semiconductor material that is not doped with an electrical dopant. Thus, a semiconductor material may be semiconducting or conductive, and may be an intrinsic semiconductor material or a doped semiconductor material. A doped semiconductor material may be semiconducting or conductive, depending on the atomic concentration of the electrical dopant therein. As used herein, "metallic material" refers to a conductive material including at least one metal element therein. All conductivity measurements are performed under standard conditions.

[0136] A monolithic three-dimensional memory array is a memory array in which multiple memory levels are formed above a single substrate (such as a semiconductor wafer) without an intervening substrate. The term "monolithic" refers to the layers of each level of the array being deposited directly on the layers of each lower level of the array. In contrast, a two-dimensional array can be formed separately and then packaged together to form a non-monolithic memory device. For example, as described in U.S. Patent No. 5,915,167, entitled "Three-dimensional Structure Memory", a non-monolithic stacked memory is constructed by forming memory levels on separate substrates and vertically stacking the memory levels. The substrate may be thinned or removed from the memory levels before bonding, but since the memory levels are initially formed above separate substrates, such memories are not true monolithic three-dimensional memory arrays. The substrate may include integrated circuits manufactured thereon, such as driver circuits for memory devices.

[0137] Various three-dimensional memory devices disclosed herein include single three-dimensional NAND string memory devices and can be manufactured using various embodiments described herein. Single three-dimensional NAND strings are positioned in a single three-dimensional NAND string array located above a substrate. At least one memory cell in a first device level of the three-dimensional NAND string array is located above another memory cell in a second device level of the three-dimensional NAND string array.

[0138] Generally speaking, a semiconductor package (or "package") refers to a unit semiconductor device that can be attached to a circuit board by a set of pins or solder balls. A semiconductor package may include one or more semiconductor chips (or "chips") that are bonded through, for example, by flip chip bonding or another chip-to-chip bonding. A package or chip may include a single semiconductor die (or "die") or multiple semiconductor dies. A die is the smallest unit that can independently execute external commands or report status. Typically, a package or chip with multiple dies is capable of simultaneously executing as many external commands as the total number of dies therein. Each die includes one or more planes. The same concurrent operation can be performed in each plane within the same die, but there may be some restrictions. In the case where the die is a memory die (i.e., a die including a memory element), concurrent read operations, concurrent write operations, or concurrent erase operations can be performed in each plane within the same memory die. In a memory die, each plane contains multiple storage blocks (or "blocks"), which are the smallest units that can be erased by a single erase operation. Each memory block contains multiple pages, which are the smallest units that can be selected for programming. A page is also the smallest unit that can be selected for a read operation.

[0139] refer to Figure 1, a first exemplary structure for forming an exemplary semiconductor die is illustrated in a vertical cross-sectional view. The first exemplary structure may include a memory array region 100, in which a three-dimensional memory array is subsequently formed, and a step region 200, in which a stepped surface of alternating stacks of insulating layers and conductive layers is subsequently formed.

[0140] Semiconductor device 720 may be formed on substrate semiconductor layer 9 disposed at least within an upper portion of substrate 8. A lower level dielectric layer 760 may be formed over substrate semiconductor layer 9 embedding a lower level metal interconnect structure 780 (schematically represented by a dashed area).

[0141] The substrate semiconductor layer 9 may include a top portion (e.g., a doped well) of a substrate 8 (such as a silicon wafer) or a semiconductor layer positioned above a substrate (such as a silicon-on-insulator substrate or a semiconductor substrate). The semiconductor device 720 may include a field effect transistor formed above the top surface of the substrate 8. The lower level dielectric layer 760 may be an interconnect level dielectric material layer embedded in the lower level metal interconnect structure 780.

[0142] In an alternative embodiment, semiconductor device 720, lower level dielectric layer 760, and subsequently lower level metal interconnect structure 780 are omitted or formed outside the memory array region. If they are omitted, they can be formed on a separate substrate and then bonded to the memory device to be formed in memory array region 100 during a subsequent step.

[0143] A first vertical alternating sequence of semiconductor material layers 110 and first continuous insulating layers 132L and first continuous sacrificial material layers 142L may be formed over substrate 8 (and over semiconductor device 720, if present). First continuous insulating layer 132L may be referred to as a first insulating layer or insulating layer. First continuous sacrificial material layer 142L may be referred to as a first sacrificial material layer or sacrificial material layer. First continuous insulating capping layer 170L may be formed over the first vertical alternating sequence. As used herein, a vertical alternating sequence refers to a sequence of multiple instances of a first element and multiple instances of a second element, the sequence being arranged such that an instance of the second element is positioned between each vertically adjacent pair of instances of the first element, and an instance of the first element is positioned between each vertically adjacent pair of instances of the second element.

[0144] The first continuous insulating layer 132L may be composed of a first material, and the first continuous sacrificial material layer 142L may be composed of a second material different from the first material. Each of the first continuous insulating layers 132L is an insulating layer that extends continuously over the entire area of ​​the substrate 8, and may have a uniform thickness as a whole. Each of the first sacrificial material layers 142L includes a sacrificial material layer that includes a dielectric material and extends continuously over the entire area of ​​the substrate 8, and may have a uniform thickness as a whole. Insulating materials that can be used for the first continuous insulating layer 132L include, but are not limited to, silicon oxide (including doped silicate glass or undoped silicate glass), silicon nitride, silicon oxynitride, organic silicate glass (OSG), spin-on dielectric materials, dielectric metal oxides (e.g., aluminum oxide, hafnium oxide, etc.) commonly referred to as high dielectric constant (high-k) dielectric oxides and their silicates, dielectric metal oxynitrides and their silicates, and organic insulating materials. In one embodiment, the first material of the first continuous insulating layer 132L may be silicon oxide.

[0145] The second material of the first continuous sacrificial material layer 142L is a dielectric material that is a sacrificial material that is selectively removable with respect to the first material of the first continuous insulating material layer 132L. As used herein, removal of the first material is "selective with respect to" the second material if the removal process removes the first material at a rate at least twice the removal rate of the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the "selectivity" of the removal process of the first material relative to the second material. The second material of the first continuous sacrificial material layer 142L may then be replaced with a conductive electrode, which may be used, for example, as a control gate electrode of a vertical NAND device. In one embodiment, the first continuous sacrificial material layer 142L may be a material layer comprising silicon nitride.

[0146] The first continuous insulating capping layer 170L includes a dielectric material different from the material of the first continuous sacrificial material layer 142L. For example, the first continuous insulating capping layer 170L may include silicon oxide. The thickness of the first continuous insulating capping layer 170L may be in the range of 30 nm to 600 nm, such as 60 nm to 300 nm, although lesser and greater thicknesses may also be used.

[0147] refer to Figure 2, the first continuous insulating cap layer 170L may be patterned so that the first continuous insulating cap layer 170L remains in the memory array area 100 and is removed outside the memory array area 100 (e.g., in the step area 200). A fine-tunable mask layer (not shown) may be applied above the first vertical alternating sequence. The fine-tunable mask layer may include a fine-tunable photoresist layer that can be controllably fine-tuned by a timed ashing process. The fine-tunable mask layer may be patterned with an initial pattern so that the section of each rectangular opening in the hard mask layer closest to the memory array area 100 is not masked by the fine-tunable mask layer, while the remainder of each rectangular opening is covered by the fine-tunable mask layer. For example, the fine-tunable mask layer may have a rectangular shape having straight edges perpendicular to the first horizontal direction and parallel to the second horizontal direction.

[0148] The first stepped surface may be formed by repeatedly performing a set of layer patterning process steps, the number of which is the total number of first continuous sacrificial material layers 142L in the first vertical alternating sequence minus 1. The set of layer patterning process steps includes: an anisotropic etching process that etches unmasked portions of a pair of first continuous insulating layers 132L and first continuous sacrificial material layers 142L; and a mask trimming process in which a trimmable mask layer is isotropically trimmed to provide shifted sidewalls that are shifted toward the memory array region 100. A final anisotropic etching process may be performed after the last mask trimming process, and the trimmable mask layer may be removed, for example, by ashing. The first stepped cavity is located above the first stepped surface of the first vertical alternating sequence (132L, 142L).

[0149] A first dielectric filling material, such as undoped silicate glass (i.e., silicon oxide) or doped silicate glass, may be deposited in the first stepped cavity. The first dielectric filling material may be planarized to remove excess portions of the first dielectric filling material above a horizontal plane including the top surface of the first continuous insulating cap layer 170L. The remaining portion of the first dielectric filling material filling the first stepped cavity constitutes a first layer of backward stepped dielectric material portion 165.

[0150] refer to FIG. 3A to FIG. 3D , various first layer openings may be formed through the first continuous insulating capping layer 170 and the first vertical alternating sequence (132L, 142L) and into the semiconductor material layer 110. A photoresist layer (not shown) may be applied over the first vertical alternating sequence (132L, 142L), and the photoresist layer may be photolithographically patterned to form various openings therethrough. The pattern of the openings in the photoresist layer may be transferred through the first vertical alternating sequence (132L, 142L) into the semiconductor material layer 110 by a first anisotropic etching process to simultaneously form various first layer openings.

[0151] The various first layer openings may include first layer memory openings 149 formed in the memory array region 100 and first layer support openings 129 formed in the stepped region 200. Each cluster of the first layer memory openings 149 may be formed as a two-dimensional array of the first layer memory openings 149. The first layer support openings 129 are openings formed in the stepped region 200 and are subsequently used to form a support post structure. A subset of the first layer support openings 129 may be formed through a corresponding horizontal surface of the first stepped surface.

[0152] In one embodiment, the first layer memory openings 149 and the first layer support openings 129 may have corresponding circular or elliptical horizontal cross-sectional shapes. The lateral dimensions (such as diameter or long axis) of each of the first layer memory openings 149 and the first layer support openings 129 may be in the range of 30 nm to 300 nm, such as 60 nm to 150 nm, but smaller and larger dimensions may also be used. In one embodiment, the first layer memory openings 149 and / or the first layer support openings 129 may be formed in corresponding rows extending laterally along a first horizontal direction (e.g., word line direction) hd1. The rows may be laterally spaced apart from each other along a second horizontal direction (e.g., bit line direction) hd2. In one embodiment, the first layer memory openings 149 and the first layer support openings 129 may be formed as opening clusters that are laterally spaced apart along the second horizontal direction hd2 by strip-shaped areas without the first layer memory openings 149 and the first layer support openings 129. In this case, the strip-shaped areas may extend laterally along the first horizontal direction hd1.

[0153] refer to 4A to 4D, a sacrificial first layer filling material is simultaneously deposited in each of the first layer openings (149, 129). For example, an optional sacrificial dielectric liner layer 121L, an optional sacrificial semiconductor liner layer 122L, and a sacrificial filling material layer 124L may be deposited in sequence. The sacrificial filling material layer 124L includes a material that can be selectively removed from the material of the sacrificial semiconductor liner layer 122L. The sacrificial semiconductor liner layer 122L includes a material that can be selectively removed from the material of the sacrificial dielectric liner layer 121L. In an illustrative example, the sacrificial dielectric liner layer 121L may include silicon oxide or silicon nitride, the sacrificial semiconductor liner layer 122L may include silicon or a silicon germanium alloy (e.g., amorphous silicon) in an amorphous or polycrystalline form, and the sacrificial filling material layer 124L may include a carbon-based material, such as amorphous carbon or diamond-like carbon (DLC). If the sacrificial filling material layer 124L includes a carbon-based material, the sacrificial semiconductor liner layer 122L and / or the sacrificial dielectric liner layer 121L may be omitted. In one embodiment, the sacrificial filling material layer 124L may include a material that can be subsequently removed by ashing (i.e., volatilization by oxidation). In another embodiment, the sacrificial filling material layer 124L may include a semiconductor material such as amorphous silicon. In this case, the dielectric liner layer 121L may exist as an etch stop layer during the selective removal of the material of the sacrificial dielectric liner layer 121L by the sacrificial filling material layer 124L in subsequent processing steps. In general, the presence or absence and material selection of each of the sacrificial dielectric liner layer 121L and the sacrificial semiconductor liner layer 122L may be optimized based on the material composition of the sacrificial filling material layer 124L. The thickness of the sacrificial dielectric liner layer 121L may be in the range of 2nm to 20nm, but smaller and larger thicknesses may also be used. The thickness of the sacrificial semiconductor liner layer 122L may be in the range of 4nm to 40nm, but smaller and larger thicknesses may also be used. The sacrificial filling material layer 124L may fill the remaining unfilled volumes of the first-layer memory openings 149 and the first-layer support openings 129 .

[0154] refer to Figure 5A and Figure 5D, a planarization process may be performed to remove portions of the sacrificial dielectric liner layer 121L, the sacrificial semiconductor liner layer 122L, and the sacrificial filling material layer 124L from above a horizontal plane including the top surface of the first continuous insulating cap layer 170L. The planarization process may employ a chemical mechanical polishing (CMP) process and / or at least one recessed etch-back process. Each remaining portion of the sacrificial dielectric liner layer 121L that remains in the first layer opening (149, 129) is referred to herein as a sacrificial dielectric liner 121. Each remaining portion of the sacrificial semiconductor liner layer 122L that remains in the first layer opening (149, 129) is referred to herein as a sacrificial semiconductor liner 122. Each remaining portion of the sacrificial filling material layer 124L that remains in the first layer opening (149, 129) is referred to herein as a sacrificial filling material portion 124. Each combination of the optional sacrificial dielectric liner 121, the optional sacrificial semiconductor liner 122, and the sacrificial filling material portion 124 filling the first layer memory opening 149 constitutes a sacrificial first layer memory opening filling structure 140. Each combination of the optional sacrificial dielectric liner 121, the optional sacrificial semiconductor liner 122, and the sacrificial filling material portion 124 filling the first layer support opening 129 constitutes a sacrificial first layer support opening filling structure 120.

[0155] A sacrificial stop material layer (e.g., a sacrificial etch stop layer) 126 may be formed on the top surface of the first continuous insulating cap layer 170L, the sacrificial first layer memory opening filling structure 140, and the sacrificial first layer support opening filling structure 120. The sacrificial stop material layer 126 includes a material that can be used as an etch stop material during a subsequent planarization (e.g., etch back) process. In addition, the sacrificial stop material layer 126 may include a material that can be selectively removed from the material of the first continuous insulating cap layer 170L. In one embodiment, the sacrificial stop material layer 126 may include silicon nitride. The thickness of the sacrificial stop material layer 126 may be in the range of 20nm to 100nm, but smaller and larger thicknesses may also be used.

[0156] See also Fig. 6A and Fig.6D A photoresist layer (not shown) may be applied over the sacrificial stop material layer 126, and the photoresist layer may be photolithographically patterned to form an elongated opening extending laterally along the first horizontal direction hd1. The elongated opening may have a corresponding uniform width along the second horizontal direction hd2. In one embodiment, the elongated opening in the photoresist layer may cover the corresponding strip-shaped area without the first layer memory opening 149 and the first layer support opening 129.

[0157] An anisotropic etching process may be performed to etch portions of the first continuous insulating capping layer 170L and the first vertical alternating sequence (132L, 142L). First layer backside trenches 179 are formed in the volume from which the material of the first continuous insulating capping layer 170L and the first vertical alternating sequence (132L, 142L) is removed. The bottom surface of the semiconductor material layer 110 may be physically exposed under each of the first layer backside trenches 179. The patterned photoresist layer may then be removed, for example, by ashing.

[0158] The sacrificial stop material layer 126 may be divided into a plurality of portions located between a corresponding adjacent pair of first layer backside grooves 179. The first continuous insulating capping layer 170L may be divided into a plurality of first insulating capping layers 170 by the first layer backside grooves 179. The first vertical alternating sequence (132L, 142L) may be divided into a plurality of first layer alternating stacks (132, 142) of first insulating layers 132 and first sacrificial material layers 142. Each first insulating layer 132 is a patterned portion of a corresponding first continuous insulating layer 132L. Each first sacrificial material layer 142 is a patterned portion of a corresponding first continuous sacrificial material layer 142L. In one embodiment, each of the first layer backside grooves 179 may have a corresponding pair of longitudinal sidewalls extending laterally along a first horizontal direction hd1. In one embodiment. Each of the first layer backside grooves may have a uniform width along a second horizontal direction hd2. Each successive combination of the first layer alternating stack (132, 142) and the first insulating capping layer 170 constitutes a first layer stack (132, 142, 170).

[0159] In general, first layer backside trenches 179 may be formed through the first continuous insulating capping layer 170L and the first vertical alternating sequence (132L, 142L). The first layer stack (132, 142, 170) includes the first continuous insulating capping layer 170L and the patterned portion of the first vertical alternating sequence (132L, 142L). The first layer stack (132, 142, 170) may be formed above the semiconductor material layer 110. The first layer stack (132, 142, 170) extends laterally along a first horizontal direction hd1 and is laterally spaced apart from each other along a second horizontal direction hd2 by the first layer backside trenches 179. Each of the first layer stacks (132, 142, 170) includes a first layer alternating stack (132, 142) of first insulating layers 132 and first sacrificial material layers 142, and includes a first insulating capping layer 170 covering the first layer alternating stack (132, 142). Each of the first layer backside trenches 179 has a corresponding pair of longitudinal sidewalls perpendicular to the second horizontal direction hd2.

[0160] refer to 7A to 7D, an optional sacrificial trench liner material and a sacrificial trench filling material may be deposited in the first layer backside trench 179. The sacrificial trench liner material (if used) may include silicon oxide with a thickness in the range of 1 nm to 6 nm. The sacrificial trench filling material may include and / or may be substantially composed of amorphous carbon, diamond-like carbon, silicon-germanium alloy, borosilicate glass, or organosilicate glass. In one embodiment, the sacrificial trench filling material may include and / or may be substantially composed of amorphous carbon or diamond-like carbon. The optional sacrificial trench liner material and the sacrificial trench filling material may be removed by performing a planarization process to cover the portion of the horizontal plane above the top surface of the sacrificial stop material layer 126. The planarization process may use a chemical mechanical polishing process and / or at least one recess etching process. Each remaining portion of the sacrificial trench liner material remaining in the first layer backside trench 179 constitutes a sacrificial trench liner 171. Each remaining portion of the sacrificial trench filling material remaining in the first layer backside trench 179 constitutes a sacrificial trench filling structure 174.

[0161] refer to FIG. 8A to FIG. 8D , the sacrificial trench filling structure 174 may be vertically recessed by performing a recess etching process. The duration of the recess etching process may be selected so that the top surface of the sacrificial trench filling structure 174 is formed below a horizontal plane including the top surface of the first insulating capping layer 170. Subsequently, the physically exposed portion of the sacrificial trench liner 171 may be removed so that the sidewall section of the first insulating capping layer 170 is physically exposed. A linear recess may be formed above each recessed top surface of the sacrificial trench filling structure 174.

[0162] A bridge material for subsequently forming a bridge structure may be deposited in a linear recess overlying the sacrificial trench fill structure 174. In one embodiment, the bridge material includes a material that provides high etching resistance to a wet etching chemical that is subsequently used to remove the cylindrical bottom portion of the memory film and the first sacrificial material layer 142. For example, in the case where the first sacrificial material layer 142 includes silicon nitride, the bridge material may include a material that provides high etching resistance to hot phosphoric acid, which may be subsequently used to remove silicon nitride in a wet etching process. In the case where the memory film 50 includes a silicon oxide layer, the bridge material may include a material that provides high etching resistance to dilute hydrofluoric acid, which may be subsequently used to remove silicon oxide in the memory film 50. In one embodiment, the bridge material includes a material having a Young's modulus higher than that of the material of the first insulating layer 132 and the first insulating cap layer 170. For example, the bridge material may include a semiconductor material or a conductive material (such as a metal or a metal alloy), and / or may be substantially composed thereof. In one embodiment, the bridge material includes amorphous silicon or polycrystalline silicon. The bridge material may be doped to change the etch resistance to subsequently employed etching chemicals. For example, in the case where the sacrificial fill material layer 124L comprises amorphous silicon, the bridge material may comprise boron-doped amorphous silicon that provides high etch resistance in a wet etching process using trimethyl-2-hydroxyethylammonium hydroxide (TMY) or tetramethylammonium hydroxide (TMAH), which etches undoped amorphous silicon at a high etching rate. In one embodiment, the bridge material may be deposited to fill the entire volume of the linear recess, and the sacrificial stop material layer 126 may be selectively vertically recessed so that the top surface of the remaining portion of the bridge material is formed at or near a horizontal plane including the top surface of the first insulating cap layer 170. The recessing may be performed by CMP and / or back etching. Each portion of the bridge material formed in the upper region of the corresponding first layer backside trench 179 is referred to herein as a bridge material matrix 176. The sacrificial stop material layer 126 may be removed during the recessing process or during a separate selective etching step after the bridge matrix 176 is formed.

[0163] Although embodiments are described above in which the vertical recess distance is the same over the entire sacrificial trench filling structure 174, alternative embodiments are expressly contemplated herein in which an etch mask layer and an additional etching process are employed to increase the vertical recess distance of the sacrificial trench filling structure 174 in the step region 200 without increasing the vertical recess distance in the memory array region 100. In this case, each bridge material matrix 176 may be formed with a thinner portion having a first thickness located in the memory array region 100 and a thicker portion having a second thickness located in the step region 200. The second thickness is 10% to 500% greater than the first thickness. Thus, each bridge material matrix 176 may have a first thickness similar to the thickness of the layer 170 in the memory array region 100 and a larger second thickness in the step region 200. In another alternative embodiment, the bridge material matrix 176 is formed only in the step region 200 and is omitted in the memory array region 100.

[0164] A filling material stack (171, 174, 176) including an optional sacrificial trench liner 171, a sacrificial trench fill structure 174, and a bridge material matrix 176 may be formed in each of the first layer backside trenches 179. In one embodiment, a trim chemical mechanical polishing process may be performed such that a top surface of the filling material stack (171, 174, 176) is formed within a horizontal plane including a top surface of the first insulating capping layer 170. In one embodiment, each of the bridge material matrices 176 may have a respective pair of bottom edges adjacent to sidewalls of a respective one of the first insulating capping layers 170.

[0165] Generally, the bridge material matrix 176 can be formed by depositing a bridge material over the sacrificial trench fill structure 174 and by removing portions of the bridge material from above a horizontal plane that includes the top surface of the first insulating capping layer 170. In one embodiment, the top surface of the bridge material matrix 176 is formed within a horizontal plane that includes the top surface of the first insulating capping layer 170. In one embodiment, the bridge material matrix 176 includes and / or consists essentially of a semiconductor material or a conductive material. For example, the bridge material matrix 176 includes amorphous silicon or polycrystalline silicon.

[0166] refer to Fig. 8E By forming a patterned photoresist layer over the sacrificial trench fill structure 174, 7A to 7DThe illustrated first exemplary structure leads to an alternative embodiment of the first exemplary structure. The patterned photoresist layer includes multiple rows of openings therethrough. Each row of openings overlies a corresponding one of the sacrificial trench filling structures 174. A recess etching process may be performed to vertically recess the material of the sacrificial trench filling structures 174 selectively to the material of the sacrificial stop material layer 126. A row of discrete recesses may be formed in an upper region of each sacrificial trench filling structure 174. The patterned photoresist layer may then be removed, for example, by ashing. Bridge material may be deposited in the multiple rows of discrete recesses, and excess portions of the bridge material may be removed from above a horizontal plane including the top surface of the sacrificial stop material layer 126 by a planarization process. The bridge material may be FIG. 8A to FIG. 8D The remaining portion of the bridge material filling each row of discrete recesses constitutes a row of bridge structures 178. The top surfaces of the bridge structures 178 may lie in the same horizontal plane as the physically exposed top surfaces of the sacrificial trench fill structures 174.

[0167] Although embodiments are described above in which the vertical recess distance is the same across all recessed regions of the sacrificial trench fill structures 174 and all bridge structures 178 are formed with the same thickness, alternative embodiments are expressly contemplated herein in which an etch mask layer and an additional etch process are employed to increase the vertical recess distance of the sacrificial trench fill structures 174 in the step region 200 without increasing the vertical recess distance in the memory array region 100. In this case, a first subset of bridge structures 178 having a first thickness may be formed in the memory array region 100, and a second subset of bridge structures 178 having a second thickness may be formed in the step region 200, which second thickness may be greater than the first thickness (such as 10% to 500% greater). Thus, each bridge structure 178 may have a first thickness similar to the thickness of the layer 170 in the memory array region 100 and a larger second thickness in the step region 200. In another alternative embodiment, the bridge structures 178 are formed only in the step region 200 and are omitted in the memory array region 100.

[0168] refer to 9A to 9D, a second vertical alternating sequence of a second continuous insulating layer 232L and a second continuous sacrificial material layer 242L may be formed. Each of the second continuous insulating layers 232L is an insulating layer that extends continuously over the entire area of ​​the substrate 8, and may have a uniform thickness as a whole. Each of the second continuous sacrificial material layers 242L includes a sacrificial material layer that includes a dielectric material and extends continuously over the entire area of ​​the substrate 8, and may have a uniform thickness as a whole. The second continuous insulating layer 232L may be referred to as a second insulating layer or insulating layer. The second continuous sacrificial material layer 242L may be referred to as a second sacrificial material layer or sacrificial material layer. The second continuous insulating layer 232L may have the same material composition and the same thickness as the first continuous insulating layer 132L. The second continuous sacrificial material layer 242L may have the same material composition and the same thickness as the first sacrificial material layer 142L. A second continuous insulating cap layer 270L may be formed over the second vertical alternating sequence (232L, 242L). In one embodiment, the second continuous insulating capping layer 270L may include the same material as the second continuous insulating layer 232L.

[0169] A second stepped surface may be formed within the stepped region 200. The area of ​​the second stepped surface is laterally offset from the first stepped surface along the first horizontal direction hd1. In one embodiment, the first stepped surface of the first layer alternating stack (132, 142) may be located in an area not covered by the patterned portion of the second vertical alternating sequence (232L, 242L). In general, the method for forming the first stepped surface of the first vertical alternating sequence (132L, 142L) may be performed with any desired changes to form the second stepped surface.

[0170] A second stepped cavity may be formed above the second stepped cavity. A second dielectric filling material, such as undoped silicate glass or doped silicate glass, may be deposited in the second stepped cavity. The second dielectric filling material may be planarized to remove excess portions of the second dielectric filling material from above a horizontal plane including the top surface of the second continuous insulating cap layer 270L. The remaining portion of the second dielectric filling material that fills the second stepped cavity constitutes a second layer of backward stepped dielectric material portion 265. Thus, the second layer of backward stepped dielectric material portion 265 is formed on the second vertical alternating sequence (232L, 242L).

[0171] refer to FIG. 10A to FIG. 10D, various second layer openings may be formed through the second vertical alternating sequence (232L, 242L). A photoresist layer (not shown) may be applied over the second vertical alternating sequence (232L, 242L), and the photoresist layer may be photolithographically patterned to form various openings therethrough. The pattern of the openings in the photoresist layer may be the same as the pattern of the first layer openings (149, 129). The pattern of the openings in the photoresist layer may be transferred through the second vertical alternating sequence (232L, 242L) by a second anisotropic etching process to simultaneously form various second layer openings (249, 229).

[0172] The various second-layer openings (249, 229) may include second-layer memory openings 249 in the memory array region 100 formed on a corresponding one of the sacrificial first-layer memory opening filling structures 140 and second-layer support openings 229 in the stepped region 200 formed on a corresponding one of the sacrificial second-layer support opening filling structures 120. Each cluster of the second-layer memory openings 249 may be formed as a two-dimensional array of the second-layer memory openings 249. The second-layer support openings 229 include openings formed in the stepped region 200 and are subsequently used to form a support post structure. A subset of the second-layer support openings 229 may be formed through a corresponding horizontal surface of the second stepped surface.

[0173] refer to FIG. 11A to FIG. 11D , the sacrificial first layer memory opening filling structure 140 and the sacrificial first layer support opening filling structure 120 can be removed from under the second layer memory opening 249 and the second layer support opening 149 by performing a series of etching processes. For example, the sacrificial filling material portion 124 within the sacrificial first layer memory opening filling structure 140 and the sacrificial first layer support opening filling structure 120 can be removed by a first etching process, which can include an anisotropic etching process or an isotropic etching process. The first etching process can be selective to the material of the optional sacrificial semiconductor liner 122 (if present). If the sacrificial semiconductor liner 122 is present, a second etching process can be performed to remove the sacrificial semiconductor liner 122. For example, the second etching process can include an isotropic etching process, which isotropic etching process etches the semiconductor material of the sacrificial semiconductor liner 122 selectively to the material of the optional sacrificial dielectric liner 121 (if present). If the sacrificial dielectric liner 121 is present, a third etching process (such as an isotropic etching process) can be performed to remove the sacrificial dielectric liner 121.

[0174] Each continuous combination of the volume of the second layer memory opening 249 and the underlying first layer memory opening 149 constitutes an inter-layer memory opening, which is also referred to as a memory opening 49. Each continuous combination of the volume of the second layer support opening 229 and the underlying first layer support opening 129 constitutes an inter-layer support opening, which is also referred to as a support opening 19. In general, memory openings 49 and support openings 19 may be formed through the second vertical alternating sequence (232L, 242L) and through the first layer stack (132, 142, 170).

[0175] FIG. 12A to FIG. 12D Sequential vertical cross-sectional views of a memory opening during formation of a memory opening filling structure according to a first embodiment of the present disclosure are shown.

[0176] refer to Fig. 12A , illustrating an interlayer memory opening (ie, memory opening 49 ) extending through the second vertical alternating sequence ( 232L, 242L) and the first vertical alternating sequence ( 132L, 142L) and into the semiconductor material layer 110 .

[0177] refer to Fig. 12B , a layer stack including a blocking dielectric layer 52, a memory material layer 54, and an optional dielectric material liner 56 may be sequentially deposited in the memory opening 49. The blocking dielectric layer 52 may include a single dielectric material layer or a stack of multiple dielectric material layers. In one embodiment, the blocking dielectric layer may include a dielectric metal oxide layer, which is substantially composed of a dielectric metal oxide. As used herein, a dielectric metal oxide refers to a dielectric material including at least one metal element and at least oxygen. The dielectric metal oxide may be substantially composed of at least one metal element and oxygen, or may be substantially composed of at least one metal element, oxygen, and at least one non-metallic element such as nitrogen. In one embodiment, the blocking dielectric layer 52 may include a dielectric metal oxide having a dielectric constant greater than 7.9 (i.e., having a dielectric constant greater than the dielectric constant of silicon nitride). The thickness of the dielectric metal oxide layer may be in the range of 1nm to 20nm, but smaller and larger thicknesses may also be used. Subsequently, the dielectric metal oxide layer may be used as a dielectric material portion that blocks the stored charge from leaking to the control gate electrode. In one embodiment, the blocking dielectric layer 52 includes aluminum oxide.Alternatively or additionally, the blocking dielectric layer 52 can include a dielectric semiconductor compound such as silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof.

[0178] Subsequently, a memory material layer 54 may be formed. In general, the memory material layer may include any memory material, such as a charge storage material, a ferroelectric material, a phase change material, or any material that can store a data bit in the form of the presence or absence of charge, ferroelectric polarization direction, resistivity, or another measurable physical parameter. In one embodiment, the memory material layer 54 may be a continuous layer or patterned discrete portions of a charge trapping material including a dielectric charge trapping material (e.g., which may be silicon nitride). Alternatively, the memory material layer 54 may include a continuous layer or patterned discrete portions of a conductive material (such as doped polysilicon or a metallic material) that is patterned into a plurality of electrically isolated portions (e.g., floating gates), for example, by being formed as a sacrificial material layer (142, 242L) within a lateral recess. In one embodiment, the memory material layer 54 includes a silicon nitride layer. In one embodiment, the sacrificial material layer 42 and the insulating layer 32 may have vertically overlapping sidewalls, and the memory material layer 54 may be formed as a single continuous layer. Generally, the memory material layer 54 may include a vertical stack of memory elements at the level of the sacrificial material layer (142, 242L).

[0179] The optional dielectric material liner 56, if present, comprises a dielectric material. In one embodiment, the dielectric material liner 56 may include a tunneling dielectric layer through which charge tunneling may be performed under suitable electrical bias conditions. Charge tunneling may be performed by hot carrier injection or by Fowler-Nordheim tunneling induced charge transfer, depending on the operating mode of the single three-dimensional NAND string memory device to be formed. The dielectric material liner 56 may include silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal oxynitride, dielectric metal silicates, alloys thereof, and / or combinations thereof. In one embodiment, the dielectric material liner 56 may include a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, which stack is generally referred to as an ONO stack. In one embodiment, the dielectric material liner 56 may include a substantially carbon-free silicon oxide layer or a substantially carbon-free silicon oxynitride layer. The thickness of the dielectric material liner 56 may be in the range of 2 nm to 20 nm, but smaller and larger thicknesses may also be used. The stack of blocking dielectric layer 52, memory material layer 54, and dielectric material liner 56 constitutes memory film 50 that stores memory bits.

[0180] An anisotropic etching process may be performed to remove horizontal portions of dielectric material liner 56, memory material layer 54, and blocking dielectric layer 52. A surface of semiconductor material layer 110 may be physically exposed at the bottom of each cavity within each memory opening 49.

[0181] A semiconductor channel material layer 60L may then be deposited. The semiconductor channel material layer 60L includes a p-doped semiconductor material, such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the semiconductor channel material layer 60L may have uniform doping. In one embodiment, the semiconductor channel material layer 60L has a p-type doping, wherein the p-type dopant (such as boron atoms) is present at an atomic concentration in the range of 1.0×1012 / cm3 to 1.0×1018 / cm3, such as 1.0×1014 / cm3 to 1.0×1017 / cm3. In one embodiment, the semiconductor channel material layer 60L includes boron-doped amorphous silicon or boron-doped polycrystalline silicon and / or is substantially composed of boron-doped amorphous silicon or boron-doped polycrystalline silicon. In another embodiment, the semiconductor channel material layer 60L has an n-type doping, wherein an n-type dopant (such as phosphorus atoms or arsenic atoms) is present at an atomic concentration in the range of 1.0×1012 / cm3 to 1.0×1018 / cm3, such as 1.0×1014 / cm3 to 1.0×1017 / cm3. The semiconductor channel material layer 60L may be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the semiconductor channel material layer 60L may be in the range of 2nm to 10nm, but smaller and larger thicknesses may also be used. The cavity 49' may exist in the volume of each interlayer memory opening 49 that is not filled with the deposited material layer (52, 54, 56, 60L).

[0182] refer to Fig. 12C , in the case where the cavity 49' in each memory opening is not completely filled with the semiconductor channel material layer 60L, a dielectric core layer can be deposited in the cavity 49' to fill any remaining portion of the cavity 49' within each memory opening. The dielectric core layer includes a dielectric material, such as silicon oxide or organic silicate glass. The dielectric core layer can be deposited by a conformal deposition method (such as low pressure chemical vapor deposition (LPCVD)), or deposited by a self-planarization deposition process (such as spin coating). The horizontal portion of the dielectric core layer covering the second continuous insulating cap layer 270L can be removed, for example, by recess etching. The recess etching continues until the top surface of the remaining portion of the dielectric core layer is recessed to a height between the top surface and the bottom surface of the second continuous insulating cap layer 270L. Each remaining portion of the dielectric core layer constitutes a dielectric core 62.

[0183] refer to Fig.12D and FIG. 13A to FIG. 13D, a doped semiconductor material having a second conductivity type of doping may be deposited in the cavity covering the dielectric core 62. The second conductivity type is opposite to the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The deposited doped semiconductor material and the portion of the semiconductor channel material layer 60L that covers the horizontal plane including the top surface of the second continuous insulating cap layer 270L may be removed by a planarization process such as a chemical mechanical planarization (CMP) process.

[0184] Each remaining portion of the second conductivity type doped semiconductor material constitutes a drain region 63. The dopant concentration of the drain region 63 may be in the range of 5.0×1018 / cm3 to 2.0×1021 / cm3, although smaller and larger dopant concentrations may also be used. The doped semiconductor material may be, for example, doped polysilicon.

[0185] Each remaining portion of the semiconductor channel material layer 60L constitutes a vertical semiconductor channel 60, through which current can flow when the vertical NAND device including the vertical semiconductor channel 60 is turned on. The dielectric material liner 56 is surrounded by the memory material layer 54 and laterally surrounds the vertical semiconductor channel 60. Each adjacent group of the blocking dielectric layer 52, the memory material layer 54, and the optional dielectric material liner 56 together constitutes a memory film 50, which can store information in a data bit at a macroscopic retention time. In some embodiments, the blocking dielectric layer 52 may not be present in the memory film 50 at this step, and the blocking dielectric layer may be subsequently formed after forming the backside recess. As used herein, the macroscopic retention time refers to a retention time suitable for the operation of a memory device as a permanent memory device, such as a retention time of more than 24 hours.

[0186] Each combination of the memory film 50 and the vertical semiconductor channel 60 within the interlayer memory opening 49 constitutes a memory stack structure 55. The memory stack structure 55 is a combination of the vertical semiconductor channel 60, the dielectric material liner 56, a plurality of memory elements including a portion of the memory material layer 54, and an optional blocking dielectric layer 52. The memory stack structure 55 can be formed through the memory array region 100 of the first vertical alternating sequence and the second vertical alternating sequence, wherein all layers of the first vertical alternating sequence and the second vertical alternating sequence are present. Each combination of the memory stack structure 55, the dielectric core 62, and the drain region 63 within the interlayer memory opening 49 constitutes a memory opening filling structure 58. Generally speaking, the memory opening filling structure 58 is formed within the memory opening 49. Each of the memory opening filling structures 58 includes a corresponding memory film 50 and a corresponding vertical semiconductor channel 60.

[0187] In general, memory opening filling structures 58 may be formed in memory openings 49. Each of the memory opening filling structures 58 includes a respective vertical stack of memory elements (e.g., portions of layer 54) and a respective vertical semiconductor channel 60. Support pillar structures 20 may be formed in each support opening 19 simultaneously with the formation of the memory opening filling structures 58. In one embodiment, the support pillar structures 20 may include the same set of structural elements as the memory opening filling structures 58. In one embodiment, the top surfaces of the memory opening filling structures 58 and the top surfaces of the support pillar structures 20 may be formed in a horizontal plane including the top surface of the second continuous insulating cap layer 270L.

[0188] refer to Fig.14A and Fig.14D , a contact level dielectric layer 280 may be deposited over the second insulating cap layer 270, the second backward stepped dielectric material portion 265, the memory opening filling structure 58, and the support pillar structure 20. A photoresist layer (not shown) may be applied over the contact level dielectric layer 280, and the photoresist layer may be photolithographically patterned to form an elongated opening extending laterally along the first horizontal direction hd1. The elongated opening may have the same area as the first layer backside trench 179, i.e., the same area as the filling material stack (171, 174, 176) filling the first layer backside trench 179.

[0189] An anisotropic etching process may be performed to etch unmasked portions of the contact level dielectric layer 280, the second continuous insulating capping layer 270L, and the second vertical alternating sequence (232L, 242L). The second layer backside trenches 279 are formed in the volume from which the material of the contact level dielectric layer 280L, the second continuous insulating capping layer 270L, and the second vertical alternating sequence (232L, 242L) is removed. The top surface of the bridge material matrix 176 may be physically exposed under each of the second layer backside trenches 279. The bridge material matrix 176 acts as an etch stop during the etching process. The patterned photoresist layer may then be removed, for example, by ashing.

[0190] The contact level dielectric layer 280 may be divided into a plurality of portions located between a corresponding adjacent pair of second layer backside grooves 279. The second continuous insulating cap layer 270L may be divided into a plurality of second insulating cap layers 270 by the second layer backside grooves 279. The second vertical alternating sequence (232L, 242L) may be divided into a plurality of second layer alternating stacks (232, 242) of second insulating layers 232 and second sacrificial material layers 242. Each second insulating layer 232 is a patterned portion of a corresponding second continuous insulating layer 232L. Each second sacrificial material layer 242 is a patterned portion of a corresponding second continuous sacrificial material layer 242L. In one embodiment, each of the second layer backside grooves 279 may have a corresponding pair of longitudinal sidewalls extending laterally along the first horizontal direction hd1. In one embodiment. Each of the second layer backside grooves may have a uniform width along the second horizontal direction hd2. Each successive combination of the second alternating layer stack (232, 242) and the second insulating capping layer 270 constitutes a second layer stack (232, 242, 270).

[0191] A second layer backside groove 279 may be formed through the second continuous insulating capping layer 270L and the second vertical alternating sequence (232L, 242L). The second layer stack (232, 242, 270) includes a patterned portion of the second continuous insulating capping layer 270L and the second vertical alternating sequence (232L, 242L). The second layer stack (232, 242, 270) may be formed above the first layer stack (132, 142, 270). The second layer stacks (232, 242, 270) extend laterally along the first horizontal direction hd1 and are laterally spaced apart from each other along the second horizontal direction hd2 by the second layer backside groove 179. Each of the second layer stacks (232, 242, 270) includes a second layer alternating stack (232, 242) of second insulating layers 232 and second sacrificial material layers 234, and includes a second insulating capping layer 270 covering the second layer alternating stack (232, 242). Each of the second layer backside trenches 279 has a corresponding pair of longitudinal sidewalls perpendicular to the second horizontal direction hd2.

[0192] In general, a second layer backside groove 279 may be formed through the second vertical alternating sequence (232L, 242L). The second layer stack (232, 242, 270) includes a patterned portion of the second vertical alternating sequence (232L, 242L). Each of the second layer backside grooves 279 has a corresponding second uniform width along the second horizontal direction hd2 and has a corresponding pair of longitudinal sidewalls perpendicular to the second horizontal direction hd2. The second layer stacks (232, 242, 270) extend laterally along the first horizontal direction hd1 and are laterally spaced apart from each other by the second layer backside grooves 279 along the second horizontal direction hd2. Each of the second layer stacks (232, 242, 270) includes a second layer alternating stack (232, 242) of a second insulating layer 232 and a second sacrificial material layer 242.

[0193] A plurality of layer stacks (132, 142, 170, 180, 232, 242, 270, 280) may be formed over the semiconductor material layer 110. The layer stacks (132, 142, 170, 180, 232, 242, 270, 280) extend laterally along a first horizontal direction hd1 and are laterally spaced apart from each other along a second horizontal direction hd2 by the filling material stacks (171, 174, 176) and the second layer backside trenches 279. Each of the layer stacks (132, 142, 170, 180, 232, 242, 270, 280) includes a first layer alternating stack (132, 142) of first insulating layers 132 and first conductive layers 142, a first insulating capping layer 170, an interlayer dielectric layer 180, a second layer alternating stack (232, 242) of second insulating layers 232 and second conductive layers 242, a second insulating capping layer 270, and a contact level dielectric layer 280. Each interlevel dielectric layer 180 may contact a top surface of a corresponding first layer back stepped dielectric material portion 165, a top surface of a corresponding first insulating capping layer 170, a bottom surface of a corresponding second layer back stepped dielectric material portion 265, and a bottom surface of a corresponding second layer alternating stack (232, 242).

[0194] In one embodiment, each memory opening 49 extends vertically through a corresponding first layer alternating stack (132, 142), a corresponding first insulating capping layer 170, a corresponding second layer alternating stack (232, 242), and a corresponding second insulating capping layer 270. A memory opening filling structure 58 may be formed in the memory opening 49. Each memory opening filling structure in the memory opening filling structure 58 includes a corresponding vertical stack of memory elements and a corresponding vertical semiconductor channel 60. Each first layer backward stepped dielectric material portion 165 may contact a stepped surface of a corresponding one of the first layer alternating stacks (132, 142). Each second layer backward stepped dielectric material portion 265 may contact a stepped surface of a corresponding one of the second layer alternating stacks (232, 242). In one embodiment, each top surface of the first layer backward stepped dielectric material portion 165 may be located in a horizontal plane including a top surface of the first insulating capping layer 170.

[0195] refer to FIG. 15A to FIG. 15D A photoresist layer may be applied over the second layer alternating stack (232, 246) and in the second layer backside trenches 279, and the photoresist layer may be photolithographically patterned to form a patterned photoresist layer 287. In one embodiment, the patterned photoresist layer 287 may include a plurality of photoresist material strips extending laterally along the second horizontal direction hd2 and laterally spaced apart along the first horizontal direction hd1. The percentage of the area of ​​the top surface of the filling material stack (171, 174, 176) covered by the patterned photoresist layer 287 relative to the total area of ​​the top surface of the filling material stack (171, 174, 176) may be in the range of 1% to 50%, such as 2% to 30% and / or 4% to 20%, although smaller and larger percentages may also be employed. The width of each stripe of photoresist material along the first horizontal direction hd1 may be in the range of 50 nm to 2,000 nm, such as 100 nm to 1,000 nm and / or 200 nm to 500 nm, although smaller and larger widths may also be employed.

[0196] refer to FIG. 16A to FIG. 16D, an etching process may be performed to remove portions of the bridge material matrix 176 that are not covered by the patterned photoresist layer 287. The etching process may include an anisotropic etching process or an isotropic etching process. Each bridge material matrix 176 may be divided into a plurality of discrete material portions including a bridge material. The remaining portion of the bridge material matrix 176 is referred to herein as a bridge structure 178. A row of bridge structures 178 arranged along the first horizontal direction hd1 may be formed within the upper portion of each first layer backside groove 179. Generally speaking, each bridge material matrix in the bridge material matrix 176 may be patterned into a corresponding plurality of bridge structures 178 spaced laterally apart along the first horizontal direction hd1. In one embodiment, a one-dimensional periodic array of bridge structures 178 may be formed within each first layer backside groove 179.

[0197] Subsequently, the sacrificial trench filling structure 174 may be removed. In one embodiment, the sacrificial trench filling structure 174 includes a carbon-based material, such as amorphous carbon. In this case, the sacrificial trench filling structure 174 may be removed by performing an ashing process. Alternatively, the sacrificial trench filling structure 174 may be removed by selective etching, such as isotropic etching. For example, if the sacrificial trench filling structure 174 includes amorphous silicon, a wet etching process using TMAH or TMY may be used to remove the sacrificial trench filling structure 174. Subsequently, the sacrificial trench liner 171 (if present) may be removed by performing an isotropic etching process. Each continuous union of the volume of the second layer backside trench 279 and the volume of the corresponding underlying first layer backside trench 179 is referred to herein as a backside trench 79, which is also referred to as an interlayer backside trench 79. A row of bridge structures 178 may be formed in each backside trench 79. The bridge structure 178 spans the width of each respective backside groove 79 along the second horizontal direction hd2 and is freely suspended above the bottom of the respective backside groove 79 (ie, not supported from below), as shown in FIG. Fig. 16C shown.

[0198] In one embodiment, each of the bridge structures 178 may have a corresponding top surface located within a horizontal plane including a top surface of the first insulating capping layer 170. In one embodiment, each of the bridge structures 178 may have a corresponding pair of first sidewalls that contact a corresponding pair of sidewalls of the first insulating capping layer 170 and extend laterally along a first horizontal direction. The first sidewalls of the bridge structures 178 may be vertical or substantially vertical. In one embodiment, each of the bridge structures 178 may have a corresponding pair of second sidewalls that are physically exposed in a void within a corresponding backside trench 79 and parallel to a second horizontal direction hd2. In one embodiment, the bridge structures 178 may be patterned from the bridge material matrix 176 using an anisotropic etching process, and the second sidewalls of the bridge structures 178 may be perpendicular to the first horizontal direction hd1. In one embodiment, each of the first sidewalls of the plurality of bridge structures 178 has a corresponding bottom edge that is adjacent to a sidewall of a corresponding one of the first insulating capping layers 170. In one embodiment, each bridge structure in the plurality of bridge structures 178 includes a semiconductor material (eg, amorphous silicon or polycrystalline silicon) or a conductive material.

[0199] In adopting Fig. 8E An alternative embodiment of the illustrated first exemplary structure replaces FIG. 8A to FIG. 8D In the case of the first exemplary structure illustrated, it is possible to FIG. 14A to FIG. 14D After forming the second layer backside trench 279 at the processing step of removing the portion of the sacrificial trench filling structure 174. In this case, by performing FIG. 16A to FIG. 16D The sacrificial trench fill structure 174 is selectively removed from the bridge structure 178 to provide FIG. 16A to FIG. 16D In other words, the structure shown in the example can be omitted. FIG. 15A to FIG. 15D The processing steps.

[0200] refer to Fig.17 , an isotropic etching process may be used to selectively remove the sacrificial material layer (142, 242) from the insulating layer (132, 232), the outermost layer of the support pillar structure 20, the outermost layer of the memory stack structure 58 (such as the blocking dielectric layer 52), and the semiconductor material layer 110. In one embodiment, an etchant that selectively etches the material of the sacrificial material layer (142, 242) relative to the material of the insulating layer (132, 232), the blocking dielectric layer 52, and the semiconductor material layer 110 may be introduced into the backside trench 79 during the isotropic etching process. For example, the sacrificial material layer (142, 242) may include silicon nitride, the material of the insulating layer (132, 232) and the blocking dielectric layer 52 may include a silicon oxide material, and the isotropic etching process may use hot phosphoric acid.

[0201] A backside recess (143, 243) is formed in the volume from which the sacrificial material layer (142, 242) is removed. The backside recess (143, 243) includes a first backside recess 143 formed in the volume from which the first sacrificial material layer 142 is removed and a second backside recess 243 formed in the volume from which the second sacrificial material layer 242 is removed. Each of the backside recesses (143, 243) can be a laterally extending cavity having a lateral dimension that is greater than the vertical extent of the cavity. In other words, the lateral dimension of each of the backside recesses (143, 243) can be greater than the height of the corresponding backside recess. Multiple backside recesses (143, 243) can be formed in the volume from which the material of the sacrificial material layer (142, 242) is removed. Each of the backside recesses (143, 243) may extend substantially parallel to the top surface of the semiconductor material layer 110. The backside recesses (143, 243) may be vertically bounded by the top surface of the underlying insulating layer (132, 232) and the bottom surface of the overlying insulating layer (132, 232). In one embodiment, each of the backside recesses (143, 243) may have a uniform height throughout.

[0202] After the isotropic etching process, the support post structure 20 is physically exposed to the backside recess (143, 243). The support post structure 20 vertically supports the insulating layer (132, 232). The bridge structure 178 laterally supports the insulating layer (132, 232) and prevents or reduces the insulating layer (132, 232) from tipping or tilting into the backside trench 79 while the backside recess (143, 243) exists in the first exemplary structure.

[0203] refer to Fig.18 A backside blocking dielectric layer (not shown) may be optionally deposited in the peripheral portion of the backside recess (143, 243) by a conformal deposition process. In one embodiment, the backside blocking dielectric layer comprises a dielectric metal oxide, such as aluminum oxide.

[0204] At least one conductive material may be deposited in the back recess (143, 243) by performing at least one conformal deposition process. In one embodiment, the at least one conductive material may include at least one metallic material, i.e., a conductive material including at least one metallic element. Non-limiting exemplary metallic materials that may be deposited in the back recess (143, 243) include tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, cobalt, and ruthenium. For example, the at least one conductive material may include a conductive metal nitride liner comprising a conductive metal nitride material such as TiN, TaN, WN, MoN, or a combination thereof, and a conductive filling material such as W, Co, Ru, Mo, Cu, or a combination thereof. In one embodiment, the at least one conductive material used to fill the back recess (143, 243) may be a combination of a titanium nitride layer and a tungsten filling material.

[0205] The conductive layer (146, 246) may be formed by depositing at least one conductive material in the backside recess (143, 243). A plurality of first conductive layers 146 may be formed in a plurality of first backside recesses 143, a plurality of second conductive layers 246 may be formed in a plurality of second backside recesses 243, and a continuous metal material layer (not shown) may be formed on the sidewall of each backside trench 79. Each of the first conductive layer 146 and the second conductive layer 246 may include a corresponding conductive metal nitride liner and a corresponding conductive filling material. Therefore, the first sacrificial material layer (142) and the second sacrificial material layer (242) may be replaced with the first conductive layer (146) and the second conductive layer (246), respectively. Specifically, each first sacrificial material layer 142 may be replaced with an optional portion of the backside blocking dielectric layer and the first conductive layer 146, and each second sacrificial material layer 242 may be replaced with an optional portion of the backside blocking dielectric layer and the second conductive layer 246. A backside cavity exists within the portion of each backside trench 79 that is not filled with the continuous layer of metal material.

[0206] The residual conductive material can be removed from inside the backside trench 79 and from above the contact level dielectric layer by an anisotropic process and / or an isotropic etching process. Each remaining portion of the deposited metal material in the first backside recess constitutes the first conductive layer 146. Each remaining portion of the deposited metal material in the second backside recess constitutes the second conductive layer 246.

[0207] A subset of the conductive layers (146, 246) may include word lines for memory elements. One or more of the topmost conductive layer and the bottommost conductive layer may include select gate electrodes. The semiconductor device 720, if present, may include driver circuit transistors (such as word line switch devices configured to control voltages to corresponding word lines) and / or bit line driver devices (such as sense amplifiers configured to control voltages to bit lines to be formed above the memory opening fill structure 58).

[0208] refer to FIG. 19A to FIG. 1 9D, an optional ion implantation process may be performed to implant a second conductivity type dopant into a portion of the semiconductor material layer 110 that is not masked by the overlying structure. The surface portion of the semiconductor material layer 110 that is located below the backside trench 79 and is not masked by the corresponding overlying bridge structure 178 may be converted into a source region 61 doped with the second conductivity type. The surface portion of the semiconductor material layer 110 that is located between the source region 61 and the vertical semiconductor channel 60 of the memory opening filling structure 58 constitutes a horizontal semiconductor channel.

[0209] The insulating material may be conformally deposited, for example, by a chemical vapor deposition process, and may subsequently be anisotropically etched to remove horizontally extending portions of the deposited insulating material that are not masked by the overlying structure. The thickness of the deposited insulating material may be less than half the width of each backside trench 79, and may be in the range of 1% to 30% of the width of each backside trench 79. In one embodiment, the insulating material may include a silicon oxide-based material, such as undoped silicate glass or doped silicate glass. Each remaining portion of the deposited insulating material that remains in the corresponding backside trench 79 constitutes an insulating spacer 74.

[0210] exist Fig.19C In one embodiment shown, each insulating spacer 74 includes a plurality of upper insulating bridge portions 74U that contact the bottom surface of a corresponding one of the plurality of bridge structures 178. In one embodiment, the plurality of upper insulating bridge portions 74U have the same width along the first horizontal direction hd1 as a corresponding overlying one of the plurality of bridge structures 178, and have the same vertical thickness as the lateral thickness of the vertically extending portion of the insulating spacer 74. In one embodiment, the insulating spacer 74 includes a plurality of lower insulating bridge portions 74L that contact corresponding top surface segments of the semiconductor material layer 110.

[0211] At least one conductive material may be conformally deposited in the unfilled volume of the backside trench 79. The at least one conductive material may include a metal liner material (such as a conductive metal nitride material) and at least one metal fill material. Excess portions of the at least one conductive material may be removed from above a horizontal plane including the top surface of the contact-level dielectric layer 280 by a planarization process, which may employ a chemical mechanical polishing process or a recess etching process. Each remaining portion of the at least one conductive material in the respective backside trench 79 constitutes a backside contact via structure 76. The one or more materials that fill the space of the backside trench 79 after forming the bridge structure 178 are referred to herein as backside trench fill structures (74, 76).

[0212] Alternatively, at least one dielectric material such as silicon oxide may be conformally deposited in the backside trench 79 by a conformal deposition process. Each portion of the deposited dielectric material that fills the backside trench 79 constitutes a backside trench fill structure. In this case, each backside trench fill structure may fill the entire volume of the backside trench 79 and may consist essentially of at least one dielectric material. In this alternative embodiment, the source region 61 may be omitted, and a horizontal source line (e.g., a direct stripe contact) may contact one side of the lower portion of the semiconductor channel 60.

[0213] Each backside trench fill structure (74, 76) may optionally include a backside contact via structure 76 embedded with a plurality of bridge structures 178. Each backside trench fill structure (74, 76) further includes an insulating spacer 74 that contacts longitudinal sidewalls of a pair of layer stacks (132, 146, 170, 180, 232, 246, 270, 280) and laterally surrounds a corresponding backside contact via structure 76 (if present). Each of the plurality of bridge structures 178 includes a corresponding pair of first sidewalls that contact a first insulating capping layer 170 within the plurality of layer stacks (132, 146, 170, 180, 232, 246, 270, 280) and includes a corresponding top surface within a horizontal plane that includes a top surface of the first insulating capping layer 170.

[0214] In one embodiment, each backside contact via structure 76 contacts a plurality of source regions 61 embedded within the semiconductor material layer 110. In one embodiment, the plurality of source regions 61 may be laterally spaced apart from one another by portions of the semiconductor material layer 110 that are located below and in contact with a plurality of lower insulating bridge portions of the insulating spacers 74. In one embodiment, each backside contact via structure 76 extends vertically from a first horizontal plane including a top surface of the semiconductor material layer 110 to a second horizontal plane including a top surface of the contact-level dielectric layer 280 of the layer stack (132, 146, 170, 180, 232, 246, 270, 280). In one embodiment, each of the plurality of bridge structures 178 includes a respective pair of second sidewalls that are perpendicular to the first horizontal direction hd1 and contact a respective sidewall surface segment of the backside contact via structure 76. In one embodiment, each of the top surfaces of the plurality of bridge structures 178 contact a respective bottom surface segment of the backside contact via structure 76.

[0215] refer to Fig. 20, various additional contact via structures (88, 86) may be formed. The additional contact via structures (88, 86) may include a drain contact via structure 88 formed through the contact level dielectric layer 280 directly on the top surface of a corresponding one of the drain regions 63 in the memory opening filling structure 58. In addition, the additional contact via structures (88, 86) may include a layer contact via structure 86 formed through the contact level dielectric layer 280 and the second backward stepped dielectric material portion 265 and optionally through the first backward stepped dielectric material portion 165 and directly on the top surface of the corresponding conductive layer (146, 246). In one embodiment, a subset of the conductive layers (146, 246) may be used as word lines, and a subset of the layer contact via structures 86 contacting the word lines may be word line contact via structures. Additional dielectric material layers (also referred to as upper level dielectric material layers) and additional metal interconnect structures (eg, bit lines that are in electrical contact with the drain contact via structure 88 ) may be formed over the contact level dielectric material layer 280 .

[0216] refer to FIG. 21A to FIG. 21C , can be formed by performing additional openings through the first vertical alternating sequence (132L, 142L) while forming the first layer memory openings 149 and the first layer support openings 129 Figures 3A to 3D The illustrated first exemplary structure leads to a second exemplary structure according to the second embodiment of the present disclosure. FIG. 3A to FIG. 3C In the illustrated first exemplary structure, the additional opening is formed in a strip-shaped region without the first layer opening (149, 249). The additional opening formed in the second exemplary structure is referred to herein as the first layer backside opening 377. In an alternative embodiment, the first layer backside opening 377 may be formed before or after forming the first layer memory opening 149 and the first layer support opening 129. In this case, a combination of an additional photolithography patterning process and an additional anisotropic etching process may be performed to form the first layer backside opening 377 before or after forming the first layer memory opening 149 and the first layer support opening 129.

[0217] The first layer backside openings 377 may be formed as a plurality of rows of first layer backside openings 377 arranged along the first horizontal direction hd1. Each row of first layer backside openings 377 may be formed in a corresponding strip area located between adjacent clusters of memory openings 149 and between adjacent clusters of support openings 129. The lateral dimension (such as diameter) of each of the first layer backside openings 377 may be in the range of 50% to 200%, such as 80% to 125%, of the lateral dimension (such as diameter) of each of the first layer memory openings 149. The lateral spacing between adjacent pairs of first layer backside openings 377 in each row of first layer backside openings 377 may be in the range of 5% to 100%, such as 10% to 60% and / or 20% to 40%, of the lateral dimension of each of the first layer backside openings 377.

[0218] In one embodiment, for example, first layer memory openings 149, first layer support openings 129, and first layer backside openings 377 may be simultaneously formed by applying and patterning a photoresist layer over first continuous insulating capping layer 170L to form discrete openings therein, and by performing a first anisotropic etching process to transfer the pattern of the openings in the photoresist layer through first continuous insulating capping layer 170L and first vertical alternating sequence (132L, 142L). Multiple rows of discrete first layer backside openings 377, multiple rows of first layer memory openings 149, and multiple rows of first layer support openings 129 may be formed through first vertical alternating sequence (132L, 142L) by performing a first anisotropic etching process.

[0219] refer to FIG. 22A to FIG. 22C, a sacrificial first layer filling material is simultaneously deposited in each of the first layer openings (149, 129, 377). For example, an optional sacrificial dielectric liner layer 121L, an optional sacrificial semiconductor liner layer 122L, and a sacrificial filling material layer 124L may be deposited in sequence. The sacrificial filling material layer 124L includes a material that can be selectively removed from the material of the sacrificial semiconductor liner layer 122L. The sacrificial semiconductor liner layer 122L includes a material that can be selectively removed from the material of the sacrificial dielectric liner layer 121L. In an exemplary example, the sacrificial dielectric liner layer 121L may include silicon oxide, the sacrificial semiconductor liner layer 122L may include silicon or a silicon-germanium alloy in an amorphous or polycrystalline form, and the sacrificial filling material layer 124L may include a carbon-based material, such as amorphous silicon or diamond-like carbon (DLC). In one embodiment, the sacrificial filling material layer 124L may include a material that can be subsequently removed by ashing (i.e., volatilization by oxidation). The thickness of the sacrificial dielectric liner layer 121L may be in the range of 2 nm to 20 nm, although lesser and greater thicknesses may also be employed. The thickness of the sacrificial semiconductor liner layer 122L may be in the range of 4 nm to 40 nm, although lesser and greater thicknesses may also be employed. The sacrificial fill material layer 124L may fill the remaining unfilled volume of the first layer memory opening 149, the first layer support opening 129, and the first layer backside opening 377.

[0220] refer to Fig.23A and Fig.23C, a planarization process may be performed to remove portions of the sacrificial dielectric liner layer 121L, the sacrificial semiconductor liner layer 122L, and the sacrificial filling material layer 124L from above a horizontal plane including the top surface of the first continuous insulating cap layer 170L. The planarization process may employ a chemical mechanical polishing (CMP) process and / or at least one recess etching (i.e., etch back) process. Each remaining portion of the sacrificial dielectric liner layer 121L that remains in the first layer opening (149, 129, 377) is referred to herein as a sacrificial dielectric liner 121. Each remaining portion of the sacrificial semiconductor liner layer 122L that remains in the first layer opening (149, 129, 377) is referred to herein as a sacrificial semiconductor liner 122. Each remaining portion of the sacrificial filling material layer 124L that remains in the first layer opening (149, 129, 377) is referred to herein as a sacrificial filling material portion 124. Each combination of the optional sacrificial dielectric liner 121, the optional sacrificial semiconductor liner 122, and the sacrificial filling material portion 124 filling the first layer memory opening 149 constitutes a sacrificial first layer memory opening filling structure 140. Each combination of the optional sacrificial dielectric liner 121, the optional sacrificial semiconductor liner 122, and the sacrificial filling material portion 124 filling the first layer support opening 129 constitutes a sacrificial first layer support opening filling structure 120. Each combination of the optional sacrificial dielectric liner 121, the optional sacrificial semiconductor liner 122, and the sacrificial filling material portion 124 filling the first layer memory opening 149 constitutes a sacrificial first layer backside opening filling structure.

[0221] A first sacrificial capping layer 172 may be deposited over the first continuous insulating capping layer 170L and the first layer of rear stepped dielectric material portion 165. The first sacrificial capping layer 172 may include a dielectric material such as silicon oxide and may have a thickness in the range of 100 nm to 500 nm, although lesser and greater thicknesses may also be employed. In one embodiment, the first sacrificial capping layer 172 may include the same material as the first continuous insulating layer 132L or the first continuous sacrificial material layer 142L. For example, the first sacrificial capping layer 172 may include a double layer of silicon oxide, silicon nitride, or a silicon nitride etch stop layer and a silicon oxide capping layer. Generally speaking, the thickness of the first sacrificial capping layer 172 may be greater than half of the lateral spacing between adjacent pairs of sacrificial first layer backside opening fill structures.

[0222] A photoresist layer 387 may be applied over the first sacrificial capping layer 172 and may be photolithographically patterned to form an elongated opening overlying a corresponding row of sacrificial first layer backside opening filling structures. In one embodiment, the elongated opening in the photoresist layer 387 may have a uniform width along the second horizontal direction hd2 that is greater than the lateral dimension of the underlying sacrificial first layer backside opening filling structures along the second horizontal direction hd2. An anisotropic etching process may be performed to remove portions of the first sacrificial capping layer 172 that are not masked by the patterned photoresist layer 187. The first sacrificial capping layer 172 may be divided into a plurality of first sacrificial capping layers 172 that are laterally spaced apart from each other by line grooves 279. Each of the line grooves 279 may overlying a corresponding row of sacrificial first layer backside opening filling structures.

[0223] Subsequently, the sacrificial first layer backside opening filling structure can be removed from under the line trench 279 between the first sacrificial capping layer by performing a series of etching processes. For example, the sacrificial filling material portion 124 within the sacrificial first layer backside opening filling structure can be removed by a first etching process, which can include an anisotropic etching process or an isotropic etching process. The first etching process can be selective to the material of the optional sacrificial semiconductor liner 122 (if present). If the sacrificial semiconductor liner 122 is present, a second etching process can be performed to remove the sacrificial semiconductor liner 122. For example, the second etching process can include an isotropic etching process, which isotropic etching process selectively etches the semiconductor material of the sacrificial semiconductor liner 122 to the material of the optional sacrificial dielectric liner 121 (if present). If the sacrificial dielectric liner 121 is present, a third etching process (such as an isotropic etching process) can be performed to remove the sacrificial dielectric liner 121. A void is formed in each of the first layer backside openings 377 in the first layer backside openings. A row of first layer backside openings 377 is located beneath each line trench between adjacent pairs of first sacrificial capping layers 172. The photoresist layer 387 may then be removed, for example, by ashing.

[0224] refer to FIG. 24A to FIG. 24C, a series of isotropic etching steps may be performed to laterally recess portions of the first vertical alternating sequence (132L, 142L) proximate to the first layer backside opening 377. For example, a first isotropic etching step may be performed to laterally recess physically exposed sidewalls of the first continuous insulating layer 132L and the first continuous insulating capping layer 170L from around the first layer backside opening 377, and a second isotropic etching step may be performed to laterally recess physically exposed sidewalls of the first continuous sacrificial material layer 142L. In an illustrative example, the first continuous insulating layer 132L includes silicon oxide, and the first continuous sacrificial material layer 142L includes silicon nitride. In this case, the first isotropic etching step may be a wet etching step using dilute hydrofluoric acid, and the second isotropic etching step may be a wet etching step using hot phosphoric acid. The duration of the first isotropic etching step and the duration of the second isotropic etching step may be selected so that adjacent pairs of first layer backside openings 377 merge within each row of first layer backside openings 377 to form corresponding first layer backside trenches 379. The first sacrificial capping layer 172 may be recessed during the first isotropic etching step and / or in parallel during the second isotropic etching step.

[0225] In general, the first layer backside openings 377 may be laterally expanded by at least one isotropic etching step. The discrete first layer backside openings 377 in each row merge with each other to form first layer backside trenches 379. The first vertical alternating sequence (132L, 142L) may be divided into first layer alternating stacks (132, 142) of first insulating layers 132 and first sacrificial material layers 142 by forming first layer backside trenches 379. The first layer alternating stacks (132, 146) extend laterally along a first horizontal direction hd1 and are laterally spaced apart from each other along a second horizontal direction hd2 by first layer backside trenches 379. The first continuous insulating capping layer 170L may be divided into a plurality of first insulating capping layers 170 covering a corresponding one of the first layer alternating stacks (132, 146). Each first level backside trench 379 may include a pair of laterally undulating sidewalls extending generally along a first horizontal direction hd1 and including a corresponding set of vertically straight sidewall segments and laterally convex sidewall segments adjacent to each other. As used herein, a "laterally undulating" element refers to an element whose lateral extent has a modulation when translated along a length direction perpendicular to the lateral extent. In one embodiment, a dopant of the second conductivity may be implanted into a physically exposed surface portion of the semiconductor material layer 110 located below the first level backside opening 379 to form an optional source region 61.

[0226] refer to FIG. 25A to FIG. 25C, an optional sacrificial trench liner material (not shown) and a sacrificial trench filling material may be deposited in the first layer backside trench 379. If a sacrificial trench liner material is used, the sacrificial trench liner material may include silicon oxide having a thickness in the range of 1 nm to 6 nm. The sacrificial trench filling material may include amorphous silicon, silicon germanium alloy, borosilicate glass, or organosilicate glass. In one embodiment, the sacrificial trench filling material includes and / or is substantially composed of undoped amorphous silicon. The optional sacrificial trench liner material and the sacrificial trench filling material covering the portion above the horizontal plane including the top surface of the first sacrificial capping layer 172 may be removed by performing a planarization process. The planarization process may use a chemical mechanical polishing process and / or at least one recess etching process. In the case of using a sacrificial trench liner material, each remaining portion of the sacrificial trench liner material remaining in the first layer backside trench 379 constitutes a sacrificial trench liner (not shown). Each remaining portion of the sacrificial trench filling material remaining in the first layer backside trench 379 constitutes a sacrificial trench filling structure 374.

[0227] The sacrificial trench filling structure 374 may be vertically recessed by performing a recess etching process. The duration of the recess etching process may be selected so that the top surface of the sacrificial trench filling structure 374 is formed below a horizontal plane including the top surface of the first insulating capping layer 170 and above a horizontal plane including the bottom surface of the first insulating capping layer 170. An elongated recess 379R having a laterally undulating width may be formed above each recessed top surface of the sacrificial trench filling structure 374.

[0228] refer to FIG. 26A to FIG. 26C, a bridge material for subsequently forming a bridge structure may be deposited in a linear recess 379R overlying the sacrificial trench filling structure 374. In one embodiment, the bridge material includes a material that provides high etching resistance to a wet etching chemical that is subsequently used to remove the cylindrical bottom portion of the memory film and the first sacrificial material layer 142. For example, in the case where the first sacrificial material layer 142 includes silicon nitride, the bridge material may include a material that provides high etching resistance to hot phosphoric acid, which may be subsequently used to remove silicon nitride in a wet etching process. In the case where the memory film 50 includes a silicon oxide layer, the bridge material may include a material that provides high etching resistance to dilute hydrofluoric acid, which may be subsequently used to remove silicon oxide in the memory film 50. In one embodiment, the bridge material may include a material having a higher Young's modulus than the material of the first insulating layer 132 and the first insulating cap layer 170. For example, the bridge material may include a semiconductor material or a conductive material (such as a metal material), and / or may be substantially composed thereof. In one embodiment, the bridge material includes a heavily doped silicon material, such as boron-doped amorphous silicon. The bridge material may be doped to change the etch resistance to subsequently employed etching chemicals. For example, where the sacrificial fill material layer 124L comprises amorphous silicon, the bridge material may comprise boron-doped amorphous silicon that provides high etch resistance in a wet etching process employing trimethyl-2-hydroxyethylammonium hydroxide (TMY) or tetramethylammonium hydroxide (TMAH), which etches undoped amorphous silicon at a high etch rate. In one embodiment, the bridge material may be deposited to fill the entire volume of the linear recess 379R, and the first sacrificial capping layer 172 may be selectively vertically recessed so that the top surface of the remaining portion of the bridge material is formed at or near a horizontal plane including the top surface of the first insulating capping layer 170. Each portion of the bridge material formed in the upper region 379R of the corresponding first layer backside trench 379 is referred to herein as a bridge material matrix 376. The first sacrificial capping layer 172 may then be removed, for example, by selective etching.

[0229] Although embodiments are described above in which the vertical recess distance is the same over the entire sacrificial trench filling structure 374, embodiments are expressly contemplated herein in which an etch mask layer and an additional etching process are employed to increase the vertical recess distance of the sacrificial trench filling structure 374 in the step region 200 without increasing the vertical recess distance in the memory array region 100. In this case, each bridge material matrix 376 may be formed with a thinner portion having a first thickness in the memory array region 100 and a thicker portion having a second thickness in the step region 200. The second thickness is greater than the first thickness (e.g., 10% to 500% greater). Thus, each bridge material matrix 376 may have a first thickness similar to the thickness of the layer 170 in the memory array region 100 and a larger second thickness in the step region 200. In another alternative embodiment, the bridge material matrix 376 is formed only in the step region 200 and is omitted in the memory array region 100.

[0230] A filling material stack (374, 376) including an optional sacrificial trench liner (not shown), a sacrificial trench filling structure 374, and a bridge material matrix 376 may be formed in each of the first layer backside trenches 379. In one embodiment, a trim chemical mechanical polishing process may be performed such that a top surface of the filling material stack (374, 376) is formed within a horizontal plane including a top surface of the first insulating capping layer 170. In one embodiment, each of the bridge material matrices 376 may have a corresponding pair of laterally undulating sidewalls extending generally along a first horizontal direction hd1 and including a plurality of vertically straight sidewall segments and laterally convex sidewall segments adjacent to each other. The laterally undulating sidewalls of the bridge material matrix 376 may contact the laterally undulating sidewalls of the corresponding first insulating capping layer 170, which include a corresponding plurality of vertically straight surface segments and laterally concave surface segments adjacent to each other. In one embodiment, each bridge material matrix in the bridge material matrix 376 may have a corresponding pair of bottom edges, which are adjacent to the side walls of a corresponding one of the first insulating capping layers 170 and extend laterally generally along the first horizontal direction hd1 and have lateral undulations along the second horizontal direction hd2.

[0231] In general, the bridge material matrix 376 can be formed by depositing a bridge material over the sacrificial trench fill structures 374 and by removing portions of the bridge material from above a horizontal plane that includes the top surface of the first insulating capping layer 170. In one embodiment, the top surface of the bridge material matrix 376 is formed within a horizontal plane that includes the top surface of the first insulating capping layer 170. In one embodiment, the bridge material matrix 376 includes and / or consists essentially of a semiconductor material or a metallic material. Each sacrificial trench fill structure 374 includes a pair of laterally undulating sidewalls that include a corresponding set of vertically straight sidewall segments and laterally convex sidewall segments that are adjacent to each other and vertically coincident with the corresponding laterally undulating sidewalls of the corresponding overlying bridge material matrix 376.

[0232] refer to Fig.26D By forming a plurality of rows of vertical recesses in the upper portion of each of the sacrificial trench filling structures 374, FIG. 25A to FIG. 25C The illustrated second exemplary structure leads to an alternative embodiment of the second exemplary structure. FIG. 26A to FIG. 26C The described bridge material may be deposited in the plurality of rows of vertical recesses, and excess portions of the bridge material may be removed by performing a planarization process from above a horizontal plane including the top surface of the first insulating capping layer 170. In this case, a plurality of bridge material matrices 376 laterally spaced apart along the first horizontal direction hd1 may be formed in an upper portion of each of the sacrificial trench filling structures 374.

[0233] Although embodiments are described above in which the vertical recess distance is the same across all recessed regions of the sacrificial trench fill structures 374 and all bridge material matrices 376 are formed with the same thickness, alternative embodiments are expressly contemplated herein in which an etch mask layer and an additional etch process are employed to increase the vertical recess distance of the sacrificial trench fill structures 374 in the step region 200 without increasing the vertical recess distance in the memory array region 100. In this case, a first subset of bridge material matrices 376 having a first thickness may be formed in the memory array region 100, and a second subset of bridge material matrices 376 having a second thickness may be formed in the step region 200, which second thickness may be greater than the first thickness (e.g., 10% to 500% greater). Thus, each bridge material matrix 376 may have a first thickness similar to the thickness of the layer 170 in the memory array region 100 and a larger second thickness in the step region 200. In another alternative embodiment, the bridge material matrix 376 is formed only in the step region 200 and is omitted in the memory array region 100.

[0234] refer to FIG. 27A to FIG. 27C, a second vertical alternating sequence of a second continuous insulating layer 232L and a second continuous sacrificial material layer 242L may be formed. Each of the second continuous insulating layers 232L is an insulating layer that extends continuously over the entire area of ​​the substrate 8, and may have a uniform thickness as a whole. Each of the second continuous sacrificial material layers 242L includes a sacrificial material layer that includes a dielectric material and extends continuously over the entire area of ​​the substrate 8, and may have a uniform thickness as a whole. The second continuous insulating layer 232L may be referred to as a second insulating layer or insulating layer. The second continuous sacrificial material layer 242L may be referred to as a second sacrificial material layer or sacrificial material layer. The second continuous insulating layer 232L may have the same material composition and the same thickness as the first continuous insulating layer 132L. The second continuous sacrificial material layer 242L may have the same material composition and the same thickness as the first sacrificial material layer 142L. A second continuous insulating cap layer 270L may be formed over the second vertical alternating sequence (232L, 242L). In one embodiment, the second continuous insulating capping layer 270L may include the same material as the second continuous insulating layer 232L.

[0235] A second stepped surface may be formed within the stepped region 200. The area of ​​the second stepped surface is laterally offset from the first stepped surface along the first horizontal direction hd1. In one embodiment, the first stepped surface of the first layer alternating stack (132, 142) may be formed in an area not covered by the patterned portion of the second vertical alternating sequence (232L, 242L). In general, the method for forming the first stepped surface of the first vertical alternating sequence (132L, 142L) may be performed with any desired changes to form the second stepped surface.

[0236] A second stepped cavity may be formed above the second stepped cavity. A second dielectric filling material, such as undoped silicate glass or doped silicate glass, may be deposited in the second stepped cavity. The second dielectric filling material may be planarized to remove excess portions of the second dielectric filling material from above a horizontal plane including the top surface of the second continuous insulating cap layer 270L. The remaining portion of the second dielectric filling material that fills the second stepped cavity constitutes a second layer of backward stepped dielectric material portion 265. Thus, the second layer of backward stepped dielectric material portion 265 is formed on the second vertical alternating sequence (232L, 242L).

[0237] refer to FIG. 28A to FIG. 28C, various second layer openings may be formed through the second vertical alternating sequence (232L, 242L). A photoresist layer (not shown) may be applied over the second vertical alternating sequence (232L, 242L), and the photoresist layer may be photolithographically patterned to form various openings therethrough. The pattern of the openings in the photoresist layer may be the same as the pattern of the first layer openings (149, 129, 377). The pattern of the openings in the photoresist layer may be transferred through the second vertical alternating sequence (232L, 242L) by a second anisotropic etching process to simultaneously form various second layer openings (249, 229, 477).

[0238] The various second-layer openings may include second-layer memory openings in the memory array region 100 formed on a corresponding one of the sacrificial first-layer memory opening filling structures 140, second-layer support openings in the stepped region 200 formed on a corresponding one of the sacrificial second-layer support opening filling structures 120, and second-layer backside openings 477 formed in the same region as the corresponding first-layer backside openings 377. Each cluster of second-layer memory openings may be formed as a two-dimensional array of second-layer memory openings. The second-layer support openings include openings formed in the stepped region 200 and are subsequently used to form a support post structure. A subset of the second-layer support openings may be formed through a corresponding horizontal surface of the second stepped surface.

[0239] Each of the second layer backside openings 477 can be formed through a corresponding bridge material matrix 376 and into a corresponding sacrificial trench filling structure 374. For example, the second anisotropic etching process can include an etching step of etching the material of the second vertical alternating sequence (232L, 242L) and an additional etching step of etching the material of the bridge material matrix 376. As described above, the pattern of the first layer backside openings 377 includes a plurality of rows of discrete openings arranged along the first horizontal direction hd1. Therefore, a row of discrete openings can be formed through each bridge material matrix 376, and each bridge material matrix 376 can be converted into a perforated structure, which is hereinafter referred to as a perforated bridge structure 378. The perforated bridge structure 378 includes a plurality of vertically extending openings 478 therethrough. Each vertically extending opening 478 is a portion of the opening 477 at the level of the perforated bridge structure 378.

[0240] Subsequently, the sacrificial first layer memory opening filling structure 140 and the sacrificial first layer support opening filling structure 120 can be removed from under the second layer memory opening and the second layer support opening by performing a series of etching processes. For example, the sacrificial first layer memory opening filling structure 140 and the sacrificial filling material portion 124 within the sacrificial first layer support opening filling structure 120 can be removed by a first etching process, which can include an anisotropic etching process or an isotropic etching process. The first etching process can be selective to the material of the optional sacrificial semiconductor liner 122 (if present). If the sacrificial semiconductor liner 122 is present, a second etching process can be performed to remove the sacrificial semiconductor liner 122. For example, the second etching process can include an isotropic etching process, which isotropic etching process etches the semiconductor material of the sacrificial semiconductor liner 122 selectively to the material of the optional sacrificial dielectric liner 121 (if present). If the sacrificial dielectric liner 121 is present, a third etching process (such as an isotropic etching process) can be performed to remove the sacrificial dielectric liner 121. During the removal of the sacrificial first layer memory opening filling structure 140 and the sacrificial first layer support opening filling structure 120 , the second layer backside opening 477 may be expanded in parallel under the via bridge structure 378 .

[0241] Each continuous combination of the volume of the second layer memory openings and the underlying first layer memory openings 149 constitutes an interlayer memory opening 49, which is also referred to as a memory opening 49. Each continuous combination of the volume of the second layer support openings and the underlying first layer support openings 129 constitutes an interlayer support opening 19, which is also referred to as a support opening 19. In general, memory openings 49 and support openings 19 may be formed through the second vertical alternating sequence (232L, 242L) and through the first layer stack (132, 142, 170).

[0242] Generally, multiple rows of discrete backside openings 477 may be formed through the second vertical alternating sequence (232L, 242L) and through the bridge material matrix 376. Each of the bridge material matrices 376 may be transformed into a respective perforated bridge structure 378 through which a respective plurality of openings extend vertically. The second level memory openings and the second level support openings may be formed during the formation of the multiple rows of discrete backside openings 477 over the region of the first level memory openings and the first level support openings (i.e., during the second anisotropic etching process).

[0243] refer to FIG. 29A to FIG. 29C, at least one sacrificial filling material may be deposited in the interlayer memory opening 49, the interlayer support opening 19, and the second layer backside opening 477. In an illustrative example, the at least one sacrificial filling material may include a carbon-based material, such as a material substantially composed of carbon, such as amorphous carbon or diamond-like carbon (DLC). Excess portions of the at least one sacrificial filling material may be removed from above a horizontal plane including the top surface of the second continuous insulating cap layer 270L by performing a planarization process such as a recess etching process. Each remaining portion of the at least one sacrificial filling material filling the corresponding interlayer memory opening 49 constitutes a sacrificial memory opening filling structure 47. Each remaining portion of the at least one sacrificial filling material filling the corresponding interlayer support opening 19 constitutes a sacrificial support opening filling structure 17. Each remaining portion of the at least one sacrificial filling material filling the corresponding second layer backside opening 477 constitutes a sacrificial backside opening filling structure 471.

[0244] refer to FIG. 30A to FIG. 30C , a second sacrificial capping layer 281 may be deposited over the second continuous insulating capping layer 270L and the various sacrificial fill structures (47, 17, 471). The second sacrificial capping layer 281 may include a dielectric material such as silicon oxide and may have a thickness in the range of 20 nm to 200 nm, although lesser and greater thicknesses may also be employed.

[0245] A photoresist layer may be applied over the second sacrificial capping layer 281 and may be photolithographically patterned to form a patterned photoresist layer 487. The patterned photoresist layer 487 may cover the sacrificial backside opening filling structure 471 without covering the sacrificial memory opening filling structure 47 or the sacrificial support opening filling structure 17. An etching process may be performed to etch the unmasked portion of the second sacrificial capping layer 281. Thus, the top surface of the sacrificial memory opening filling structure 47 or the sacrificial support opening filling structure 17 may be physically exposed, while the sacrificial backside opening filling structure 471 is covered by the second sacrificial capping layer 281. The patterned photoresist layer 487 may then be removed, for example, by ashing.

[0246] refer to FIG. 31A to FIG. 31CThe sacrificial filling material of the sacrificial memory opening filling structure 47 and the sacrificial support opening filling structure 17 may be selectively removed from the materials of the second vertical alternating sequence (232L, 242L), the first layer alternating stack (132, 142), the backward stepped dielectric material portion (165, 265), the first insulating capping layer 170, the interlayer insulating layer 180, the second continuous insulating capping layer 270L, and the semiconductor material layer 110. For example, if the sacrificial memory opening filling structure 47 and the sacrificial support opening filling structure 17 include amorphous carbon or diamond-like carbon, an ashing process may be performed to remove the sacrificial filling material of the sacrificial memory opening filling structure 47 or the sacrificial support opening filling structure 17. Voids are formed in the interlayer memory opening 49 and in the interlayer support opening 19. During the removal of the sacrificial memory opening filling structure 47 and the sacrificial support opening filling structure 17, the second sacrificial capping layer 281 protects the sacrificial backside opening filling structure 471.

[0247] Then, you can execute FIG. 12B to FIG. 12D The processing steps are performed to form the memory opening filling structure 58 in the inter-layer memory opening 49 and the support pillar structure 20 in the inter-layer support opening 19. The second sacrificial capping layer 281 may be removed during a planarization process performed to remove excess portions of the deposited doped semiconductor material (i.e., the material of the drain region 63) and the semiconductor channel material layer 60L overlying a horizontal plane including the top surface of the second continuous insulating capping layer 270L.

[0248] In general, memory opening filling structures 58 may be formed within each successive combination of the volume of the first level memory openings and the volume of the second level memory openings. Each of memory opening filling structures 58 includes a respective vertical stack of memory elements (e.g., portions of memory material layer 54) and a respective vertical semiconductor channel 60.

[0249] refer to FIG. 32A to FIG. 32C , a contact level dielectric layer 280 may be deposited over the second continuous insulating cap layer 270L, the second backward stepped dielectric material portion 265, the memory opening filling structure 58, and the support pillar structure 20. A photoresist layer 285 may be applied over the contact level dielectric layer 280, and the photoresist layer may be photolithographically patterned to form an elongated opening extending laterally along the first horizontal direction hd1. The elongated opening may be formed over a rectangular area including an area of ​​a corresponding row of sacrificial backside opening filling structures 471.

[0250] An anisotropic etching process may be performed to etch unmasked portions of the contact-level dielectric layer 280. Line trenches 469 are formed over multiple rows of sacrificial backside opening-filling structures 471 between a corresponding pair of patterned portions of the contact-level dielectric layer 280. A top surface of a row of sacrificial backside opening-filling structures 471 may be physically exposed under each line trench 469. The photoresist layer 285 may then be removed, for example, by ashing.

[0251] refer to FIG. 33A to FIG. 33C , the sacrificial backside opening filling structure 471 may be selectively removed through the line trench 469 without removing the sacrificial trench filling structure 374. For example, the sacrificial trench filling structure 374 may include undoped amorphous silicon, borosilicate glass, or organosilicate glass, the perforated bridge structure 378 may include boron-doped silicon or a metal material, and the sacrificial backside opening filling structure 471 may include amorphous carbon or diamond-like carbon. In this case, the sacrificial backside opening filling structure 471 may be removed by ashing without removing the sacrificial trench filling structure 374 or the perforated bridge structure 378. All sidewalls of the first layer backside trench may be covered by a corresponding combination of the sacrificial trench filling structure 374 and the perforated bridge structure 378.

[0252] refer to FIG. 34A to FIG. 34C , a series of isotropic etching steps may be performed to laterally recess a portion of the second vertical alternating sequence (232L, 242L) adjacent to the second layer backside opening 477. For example, a first isotropic etching step may be performed to laterally recess physically exposed sidewalls of the second continuous insulating layer 232L and the second continuous insulating capping layer 270L from around the second layer backside opening 477, and a second isotropic etching process may be performed to laterally recess physically exposed sidewalls of the second continuous sacrificial material layer 242L. In an illustrative example, the second continuous insulating layer 232L includes silicon oxide, and the second continuous sacrificial material layer 242L includes silicon nitride. In this case, the first isotropic etching step may be a wet etching step using dilute hydrofluoric acid, and the second isotropic etching step may be a wet etching step using hot phosphoric acid. The duration of the first isotropic etching step and the duration of the second isotropic etching step may be selected so that adjacent pairs of second layer backside openings 477 merge within each row of second layer backside openings 477 to form respective second layer backside trenches 479. The contact-level dielectric layer 280 may be recessed during the first isotropic etching step and / or in parallel during the second isotropic etching step.

[0253] In general, the second layer backside openings 477 may be laterally expanded by at least one isotropic etching process. The discrete second layer backside openings 477 in each row merge with each other to form second layer backside grooves 479. The second vertical alternating sequence (232L, 242L) may be divided into second layer alternating stacks (232, 242) of second insulating layers 232 and second sacrificial material layers 242 by forming second layer backside grooves 479. The second layer alternating stacks (232, 242) extend laterally along the first horizontal direction hd1 and are laterally spaced apart from each other along the second horizontal direction hd2 by the second layer backside grooves 479. The second continuous insulating capping layer 270L may be divided into a plurality of second insulating capping layers 270 covering a corresponding one of the second layer alternating stacks (232, 242). Each second layer backside trench 479 may include a pair of laterally undulating sidewalls extending generally along the first horizontal direction hd1 and including a respective set of vertical straight sidewall segments and laterally convex sidewall segments adjacent to each other.

[0254] A plurality of layer stacks (132, 142, 170, 180, 232, 242, 270, 280) may be formed over the semiconductor material layer 110. The layer stacks (132, 142, 170, 180, 232, 242, 270, 280) extend laterally along a first horizontal direction hd1 and are laterally spaced apart from each other along a second horizontal direction hd2 by filler material stacks (374, 378) and second layer backside trenches 479. Each of the layer stacks (132, 142, 170, 180, 232, 242, 270, 280) includes a first layer alternating stack (132, 142) of first insulating layers 132 and first sacrificial material layers 142, a first insulating capping layer 170, an interlayer dielectric layer 180, a second layer alternating stack (232, 242) of second insulating layers 232 and second sacrificial material layers 242, a second insulating capping layer 270, and a contact level dielectric layer 280. Each interlevel dielectric layer 180 may contact a top surface of a corresponding first layer back stepped dielectric material portion 165, a top surface of a corresponding first insulating capping layer 170, a bottom surface of a corresponding second layer back stepped dielectric material portion 265, and a bottom surface of a corresponding second layer alternating stack (232, 242).

[0255] In one embodiment, each memory opening 49 extends vertically through a corresponding first layer alternating stack (132, 142), a corresponding first insulating capping layer 170, a corresponding second layer alternating stack (232, 242), and a corresponding second insulating capping layer 270. A memory opening filling structure 58 may be formed in the memory opening 49. Each memory opening filling structure in the memory opening filling structure 58 includes a corresponding vertical stack of memory elements and a corresponding vertical semiconductor channel 60. Each first layer backward stepped dielectric material portion 165 may contact a stepped surface of a corresponding one of the first layer alternating stacks (132, 142). Each second layer backward stepped dielectric material portion 265 may contact a stepped surface of a corresponding one of the second layer alternating stacks (232, 242). In one embodiment, each top surface of the first layer backward stepped dielectric material portion 165 may be located in a horizontal plane including a top surface of the first insulating capping layer 170.

[0256] In one embodiment, the top surface of each perforated bridge structure 378 may be located in a horizontal plane including the top surface of the first insulating capping layer 170. In one embodiment, the perforated bridge structure 378 contacts the sidewalls of a corresponding pair of first insulating capping layers 170 and includes a semiconductor material or a metal material. In one embodiment, each perforated bridge structure 378 includes a pair of laterally undulating outer sidewalls including a corresponding set of vertical straight sidewall segments and laterally convex sidewall segments adjacent to each other.

[0257] refer to FIG. 35A to FIG. 35C , the sacrificial trench filling structure 374 may be selectively removed from the materials of the first layer alternating stack (132, 142), the second layer alternating stack (232, 242), the perforated bridge structure 378, and the semiconductor material layer 110. In one embodiment, the sacrificial trench filling structure 374 may include undoped amorphous silicon, and the perforated bridge structure 378 may include heavily boron-doped silicon including boron atoms at an atomic concentration greater than 1.0×1018 / cm3, such as 1.0×1019 / cm3 to 1.0×1021 / cm3. In this case, a wet etching process using tetramethylammonium hydroxide (TMAH) or trimethyl-2-hydroxyethylammonium hydroxide (TMY) may be performed to selectively remove the sacrificial trench filling structure 374 from the perforated bridge structure 378. Generally speaking, an isotropic etching process that provides an etching chemistry that selectively etches the material of the sacrificial trench filling structure 374 from the material of the perforated bridge structure 378 may be used for the selective removal of the sacrificial trench filling structure 374.

[0258] Each combination of the volume of the second layer backside grooves 479 and the volume of the first layer backside grooves 379 constitutes a backside groove 79, which is also referred to as an interlayer backside groove 79. A perforated bridge structure 378 may be disposed within each backside groove 79. Generally, a backside groove 79 extending vertically through the first layer alternating stack (132, 142) and the second layer alternating stack (232, 242) may be formed by removing the sacrificial trench filling structure 374 after forming the second layer backside grooves 479. In one embodiment, the bottom portion of each backside groove 79 located below the corresponding perforated bridge structure 378 includes a pair of laterally undulating sidewalls, the pair of laterally undulating sidewalls including a corresponding set of vertically straight sidewall segments and laterally convex sidewall segments adjacent to each other. In one embodiment, the pair of laterally undulating sidewalls of the bottom portion of each backside groove 79 may vertically coincide with a pair of laterally undulating outer sidewalls of the corresponding overlying perforated bridge structure 378.

[0259] refer to FIG. 36A to FIG. 36D , the first sacrificial material layer 142 and the second sacrificial material layer 242 may be replaced with the first conductive layer 146 and the second conductive layer 246. For example, Fig.17 and Fig.18 The processing steps are to replace the first sacrificial material layer 142 and the second sacrificial material layer 242 with the first conductive layer 146 and the second conductive layer 246, respectively.

[0260] refer to FIG. 37A to FIG. 37F , the insulating material may be conformally deposited, for example, by a chemical vapor deposition process, and may subsequently be anisotropically etched to remove horizontally extending portions of the deposited insulating material that are not masked by the overlying structure. The thickness of the deposited insulating material may be less than half of the minimum width of each backside trench 79 along the second horizontal direction hd2, and may be in the range of 1% to 30% of the minimum width of each backside trench 79 along the second horizontal direction hd2. In one embodiment, the insulating material may include a silicon oxide-based material, such as undoped silicate glass or doped silicate glass. Each remaining portion of the deposited insulating material that remains in the corresponding backside trench 79 constitutes a corresponding insulating spacer (74A, 74B, 74C).

[0261] The insulating spacers (74A, 74B, 74C) may include a first insulating spacer 74A formed below a horizontal plane including the top surface of the perforated bridge structure 378. Each first insulating spacer 74A may contact the entire bottom surface of the corresponding perforated bridge structure 378, and may contact at least the lower portion of each inner sidewall of the corresponding perforated bridge structure 378 (i.e., the lower portion of each vertically extending opening 478 within the corresponding perforated bridge structure 378). In one embodiment, each first insulating spacer 74A includes a pair of laterally undulating outer sidewalls, which include a corresponding set of vertical straight sidewall segments and a laterally convex sidewall segment adjacent to each other. In one embodiment, each first insulating spacer 74A may include a tubular portion that contacts the sidewalls of multiple vertically extending openings 478 in the corresponding perforated bridge structure 378.

[0262] The insulating spacers (74A, 74B, 74C) may also include a second insulating spacer 74B formed above a horizontal plane including the top surface of the perforated bridge structure 378 and formed below a horizontal plane including the bottom surface of the contact-level dielectric layer 280. Each second insulating spacer 74B may contact a peripheral region of the top surface of the corresponding underlying perforated bridge structure 378. In one embodiment, each second insulating spacer 74B includes a pair of laterally undulating outer sidewalls including a corresponding set of vertical straight sidewall segments and laterally convex sidewall segments adjacent to each other. In one embodiment, the second insulating spacer 74B and the first insulating spacer 74A within each backside trench 79 are two discrete insulating structures that include the same material, have the same lateral thickness, and are not in direct contact with each other.

[0263] The insulating spacers (74A, 74B, 74C) may further include a third insulating spacer 74C formed in the line trench 469 and located above a horizontal plane including the bottom surface of the contact-level dielectric layer 280. In one embodiment, each third insulating spacer 74C includes a pair of laterally straight outer sidewalls extending laterally along the first horizontal direction hd1.

[0264] Optionally, at least one conductive material may be conformally deposited in the unfilled volume of the backside trench 79. The at least one conductive material may include a metal liner material (such as a conductive metal nitride material) and at least one metal fill material. Excess portions of the at least one conductive material may be removed from above a horizontal plane including the top surface of the contact-level dielectric layer 280 by a planarization process, which may employ a chemical mechanical polishing process or a recess etching process. Each remaining portion of the at least one conductive material in the respective backside trench 79 constitutes an optional backside contact via structure 76. The combination of all material portions that fill the backside trenches 79, except for the perforated bridge structure 378, is referred to herein as a backside trench fill structure (74A, 74B, 74C, 76).

[0265] In one embodiment, a backside trench fill structure (74A, 74B, 74C, 76) is located in each backside trench 79. The backside trench fill structure (74A, 74B, 74C, 76) includes an optional backside contact via structure 76. The perforated bridge structure 378 may include a plurality of vertically extending openings 478 through which the cylindrical connecting portions of the backside contact via structures 76 extend vertically.

[0266] exist Fig.37C In one embodiment shown, the backside contact via structure 76 includes a lower backside contact via portion 76L located between a first layer alternating stack (132, 146) of a pair of layer stacks (132, 146, 170, 180, 232, 246, 270, 280) and an upper backside contact via portion 76U located between a second layer alternating stack (232, 246) of the pair of layer stacks (132, 146, 170, 180, 232, 246, 270, 280). In one embodiment, the lower backside contact via portion 76L is adjacent to the bottom perimeter of the sidewall of the cylindrical connecting portion 76C of the backside contact via structure 76, and the upper backside contact via portion 76U is adjacent to the top perimeter of the sidewall of the cylindrical connecting portion 76C of the backside contact via structure 76.

[0267] In one embodiment, the lower backside contact via structures 76L are embedded in a corresponding row of encapsulated cylindrical cavities (i.e., air gaps) 473 without any solid material. Alternatively, the air gaps in the lower backside contact via portion 76L can be omitted. In one embodiment, there are no encapsulated cavities (i.e., air gaps) in the upper backside contact via portion 76U. In one embodiment, each backside trench fill structure (74A, 74B, 74C, 76) includes a first insulating spacer 74A that laterally surrounds the lower backside contact via portion 76L of the backside contact via structure 76 and contacts the entire bottom surface of the through-hole bridge structure 378. In one embodiment, the first insulating spacer 74A includes a tubular portion that contacts the sidewalls of the plurality of vertically extending openings 478 in the through-hole bridge structure 378.

[0268] In one embodiment, each backside trench filling structure (74A, 74B, 74C, 76) further includes a second insulating spacer 74B that laterally surrounds a lower portion of an upper backside contact via portion 76U of the backside contact via structure 76 and contacts a peripheral region of a top surface of the through-hole bridge structure 378. In one embodiment, the second insulating spacer 74B and the first insulating spacer 74A are two discrete insulating structures that include the same material, have the same lateral thickness, and are not in direct contact with each other.

[0269] In one embodiment, each backside trench filling structure (74A, 74B, 74C, 76) further includes a third insulating spacer 74C that overlies the second insulating spacer 74B and laterally surrounds an upper portion of the upper backside contact via portion 76U. In one embodiment, the second insulating spacer 74B includes a pair of laterally undulating outer sidewalls that include a corresponding set of vertical straight sidewall segments and laterally convex sidewall segments that are adjacent to each other, and the third insulating spacer 74C includes a pair of laterally straight outer sidewalls that extend laterally along the first horizontal direction hd1.

[0270] Although embodiments in which the perforated bridge structures 378 have the same thickness throughout are described above, embodiments in which an etch mask layer and an additional etch process are employed to increase the vertical recess distance of the sacrificial trench fill structure 174 in the step region 200 without increasing the vertical recess distance in the memory array region 100 are expressly contemplated herein. In this case, one or more of the perforated bridge structures 378 may be formed with a thinner portion having a first thickness in the memory array region 100 and a thicker portion having a second thickness in the step region 200. The second thickness is greater than the first thickness (e.g., 10% to 500%). Thus, each perforated bridge structure 378 may have a first thickness similar to the thickness of the layer 170 in the memory array region 100 and a larger second thickness in the step region 200. In another alternative embodiment, the perforated bridge structure 378 is formed only in the step region 200 and is omitted in the memory array region 100.

[0271] refer to Figure 37G , illustrates an alternative embodiment of the second exemplary structure, which can be performed by executing reference Fig.26D The processing steps described replace the reference FIG. 26A to FIG. 26C In this case, a plurality of through-hole bridge structures 378 may be formed in each back-side trench. The first insulating spacer 74A may contact the sidewalls of the plurality of through-hole bridge structures 378.

[0272] refer to Fig.38 , various additional contact via structures (88, 86) may be formed. The additional contact via structures (88, 86) may include a drain contact via structure 88 formed through the contact level dielectric layer 280 directly on the top surface of a corresponding one of the drain regions 63 in the memory opening filling structure 58. In addition, the additional contact via structures (88, 86) may include a layer contact via structure 86 formed through the contact level dielectric layer 280 and the second backward stepped dielectric material portion 265 and optionally through the first backward stepped dielectric material portion 165 and directly on the top surface of the corresponding conductive layer (146, 246). In one embodiment, a subset of the conductive layers (146, 246) may be used as word lines, and a subset of the layer contact via structures 86 contacting the word lines may be word line contact via structures. Additional dielectric material layers (also referred to as upper level dielectric material layers) and additional metal interconnect structures (eg, bit lines) may be formed over the contact level dielectric material layer 280 .

[0273] Referring to the first embodiment and Figures 1 to 20The three-dimensional memory device comprises: a pair of layer stacks (132, 146, 170, 232, 246) extending laterally along a first horizontal direction hd1 and being laterally spaced apart from each other along a second horizontal direction hd2 by backside trenches 79, wherein each of the layer stacks (132, 146, 170, 232, 246) comprises a first layer alternating stack (132, 146) of a first insulating layer 132 and a first conductive layer 146, a first insulating capping layer 170 located above the first layer alternating stack, and a first insulating capping layer 270 located above the first insulating capping layer 270. A second layer alternating stack (232, 246) of two insulating layers 232 and a second conductive layer 246; a memory opening 49 extending vertically through a pair of layer stacks (132, 146, 170, 232, 246); a memory opening filling structure 58 located in a corresponding memory opening 49 and including a corresponding vertical stack of memory elements (e.g., a portion of a memory material layer 54) and a corresponding vertical semiconductor channel 60; and a bridge structure 178 spanning the entire width of the backside trench 79 along a second horizontal direction hd2. The top surface of the bridge structure 178 is located below the top surface of the second layer alternating stack (232, 246), and the bottom surface of the bridge structure 178 is located above the bottom surface of the first layer alternating stack (132, 246).

[0274] In one embodiment, backside trench fill structures (74, 76) are also located in the backside trenches and embedded in bridge structure 178. In one embodiment, bridge structure 178 includes a respective pair of first sidewalls contacting first insulating capping layer 178 within a pair of layer stacks (132, 146, 170, 232, 246) and includes respective top surfaces within a horizontal plane including a top surface of first insulating capping layer 170.

[0275] In one embodiment, the device includes a plurality of bridge structures 178 in the backside trench 79. Each of the plurality of bridge structures 178 also includes a corresponding pair of second sidewalls perpendicular to the first horizontal direction hd1 and contacting a corresponding sidewall surface segment of the backside trench filling structure (74, 76). In one embodiment, each of the top surfaces of the plurality of bridge structures 178 contacts a corresponding bottom surface segment of the backside trench filling structure (74, 76).

[0276] In one embodiment, the backside trench fill structure ( 74 , 76 ) includes an insulating spacer 74 that contacts longitudinal sidewalls of a pair of layer stacks ( 132 , 146 , 170 , 232 , 246 ) and laterally surrounds the backside contact via structure 76 .

[0277] exist Fig.19CIn one embodiment shown, the insulating spacer 74 includes a plurality of upper insulating bridge portions 74U that contact the bottom surface of a corresponding one of the plurality of bridge structures 178. In one embodiment, the plurality of upper insulating bridge portions 74U have the same width as a corresponding one of the plurality of bridge structures 178 along the first horizontal direction hd1, and have the same vertical thickness as the lateral thickness of the vertically extending portion of the insulating spacer 74. In one embodiment, the insulating spacer 74 includes a plurality of lower insulating bridge portions 74L that contact corresponding top surface segments of the semiconductor material layer 110 below the backside trench 79.

[0278] In one embodiment, the backside contact via structure 76 contacts a plurality of source regions 61 embedded within the semiconductor material layer 110. The plurality of source regions 61 are laterally spaced apart from each other by portions of the semiconductor material layer 110 beneath the plurality of lower insulating bridge portions 74L of the insulating spacers 74.

[0279] In one embodiment, the pair of layer stacks also include a second insulating cap layer 270 and a contact level dielectric layer 280 covering the second layer alternating stack (232, 246); and the back side contact via structure 76 extends vertically from a first horizontal plane including the top surface of the semiconductor material layer 110 to a second horizontal plane including the top surface of the contact level dielectric layer 280 of the layer stack (132, 146, 170, 232, 246, 270, 280).

[0280] In one embodiment, the three-dimensional memory device also includes: a first layer backward stepped dielectric material portion 165, which contacts the stepped surface of a corresponding one of the first layer alternating stacks (132, 146); and a second layer backward stepped dielectric material portion 265, which contacts the stepped surface of a corresponding one of the second layer alternating stacks (232, 246), wherein the top surface of the first layer backward stepped dielectric material portion 165 is located in a horizontal plane including the top surface of the first insulating cap layer 170.

[0281] In one embodiment, each layer stack in a pair of layer stacks (132, 146, 170, 180, 232, 246, 270, 280) also includes an inter-level dielectric layer 180, which contacts the top surface of the corresponding first layer backward stepped dielectric material portion 165, the top surface of the corresponding first insulating cap layer 170, the bottom surface of the corresponding second layer backward stepped dielectric material portion 265 and the bottom surface of the corresponding second layer alternating stack (232, 246).

[0282] In one embodiment, each of the first sidewalls of the plurality of bridge structures 178 has a respective bottom edge that is adjacent to a sidewall of a respective one of the first insulating capping layers 170. In one embodiment, each of the plurality of bridge structures 178 includes a semiconductor material.

[0283] Referring to the second embodiment and FIG. 21A to FIG. 38 , a three-dimensional memory device includes: a pair of layer stacks (132, 146, 232, 246), which extend laterally along a first horizontal direction hd1 and are laterally spaced from each other along a second horizontal direction hd2 by a backside trench 79, wherein each layer stack in the pair of layer stacks (132, 146, 232, 246) includes a first layer alternating stack (132, 146) of a first insulating layer 132 and a first conductive layer 146 and a second layer alternating stack (232, 246) of a second insulating layer 232 and a second conductive layer 246; a memory opening 49, which vertically extends through the pair of layer stacks; a memory opening filling structure 58, which is located in the corresponding memory opening 49 and includes a corresponding vertical stack of memory elements (for example, a portion of the memory layer 54) and a corresponding vertical semiconductor channel 60; and a perforated bridge structure 378, which includes a plurality of vertically extending openings 478 located in the backside trench 79.

[0284] The backside trench fill structure (74, 76) is located in the backside trench 79. The backside trench fill structure includes a backside contact via structure 76 including a cylindrical connecting portion 76C that vertically extends through a vertically extending opening 478 in the perforated bridge structure 378. In one embodiment, the backside contact via structure 76 includes: a lower backside contact via portion 76L that is located between the first layer alternating stack (132, 146) of the pair of layer stacks; and an upper backside contact via portion 76U that is located between the second layer alternating stack (232, 246) of the pair of layer stacks. In one embodiment, the lower back side contact via portion 76L is adjacent to the bottom perimeter of the sidewall of the cylindrical connecting portion 76C of the back side contact via structure 76, and the upper back side contact via portion 76U is adjacent to the top perimeter of the sidewall of the cylindrical connecting portion 76C of the back side contact via structure 76.

[0285] In one embodiment, the lower backside contact via structures 76L are embedded in a corresponding row of air gaps 473. In one embodiment, the upper backside contact via portion 75U is free of any air gaps.

[0286] In one embodiment, the backside trench fill structure (74, 76) further includes a first insulating spacer 74A that laterally surrounds the lower backside contact via portion 76L and contacts the entire bottom surface of the through-via bridge structure 378. In one embodiment, the first insulating spacer 74A includes a tubular portion that contacts the sidewalls of the plurality of vertically extending openings 478 in the through-via bridge structure 378.

[0287] In one embodiment, the backside trench fill structure (74, 76) further includes a second insulating spacer 74B that laterally surrounds a lower portion of the upper backside contact via portion 76U and contacts a peripheral region of a top surface of the through-hole bridge structure 378. In one embodiment, the second insulating spacer 74B and the first insulating spacer 74A are two discrete insulating structures that include the same material, have the same lateral thickness, and are not in direct contact with each other.

[0288] In one embodiment, the backside trench filling structure (74, 76) further includes a third insulating spacer 74C, which overlies the second insulating layer and laterally surrounds the upper portion of the upper backside contact via portion 76U. The second insulating spacer 74B includes a pair of laterally undulating outer sidewalls, the pair of laterally undulating outer sidewalls including a corresponding set of vertical straight sidewall segments and laterally convex sidewall segments adjacent to each other, and the third insulating spacer 74C includes a pair of laterally straight outer sidewalls extending laterally along the first horizontal direction hd1.

[0289] In one embodiment, the top surface of the perforated bridge structure 378 is located below the top surface of the second layer alternating stack (232, 246), and the bottom surface of the perforated bridge structure 378 is located above the bottom surface of the first layer alternating stack (132, 146). In one embodiment, each layer stack in the pair of layer stacks further includes a first insulating capping layer 170 located between the respective first layer alternating stack (132, 146) and the respective second layer alternating stack (232, 246), and the top surface of the perforated bridge structure 378 is located within a horizontal plane including the top surface of the first insulating capping layer 170. In one embodiment, the perforated bridge structure 378 contacts the sidewalls of the first insulating capping layer 170 and includes a doped semiconductor material.

[0290] In one embodiment, the perforated bridge structure 378 includes a pair of laterally undulating outer sidewalls, which include a corresponding set of vertical straight sidewall segments and a laterally convex sidewall segment adjacent to each other. In one embodiment, the bottom portion of the back groove 79 located below the perforated bridge structure 378 includes a pair of laterally undulating sidewalls, which include a corresponding set of vertical straight sidewall segments and a laterally convex sidewall segment adjacent to each other; and the pair of laterally undulating sidewalls of the bottom portion of the back groove 79 vertically coincide with the pair of laterally undulating outer sidewalls of the perforated bridge structure 378.

[0291] Various embodiments of the present disclosure may be used to form a bridge structure (178, 378) that provides lateral structural support for the insulating layer (132, 232) during replacement of the sacrificial material layer (142, 242) with the conductive layer (146, 246). During the replacement process of forming the conductive layer (146, 246), lateral movement of the insulating layer (132, 232) at the middle and bottom of the backside trench 79 may be limited and / or controlled due to the presence of the bridge structure at the middle vertical level between the lower alternating stack and the upper alternating stack.

[0292] Although specific embodiments are mentioned above, it should be understood that the present disclosure is not limited thereto. It will be appreciated by those of ordinary skill in the art that various modifications may be made to the disclosed embodiments, and such modifications are intended to fall within the scope of the present disclosure. Compatibility is assumed in all embodiments that are not alternatives to each other. Unless otherwise expressly stated, the words "comprising" or "including" contemplate all embodiments in which the words "consisting essentially of..." or the words "consisting of..." replace the words "comprising" or "including". Embodiments using specific structures and / or configurations are shown in the present disclosure, and it should be understood that the present disclosure can be practiced with any other compatible structures and / or configurations that are functionally equivalent, provided that such substitutions are not explicitly prohibited or otherwise considered impossible by those of ordinary skill in the art. All publications, patent applications, and patents cited herein are incorporated herein by reference in their entirety.

Claims

1. A three-dimensional memory device, comprising: a pair of layer stacks extending laterally along a first horizontal direction and laterally spaced apart from each other along a second horizontal direction by backside trenches, wherein each of the layer stacks comprises a first layer alternating stack of first insulating layers and first conductive layers, a first insulating capping layer over the first layer alternating stack, and a second layer alternating stack of second insulating layers and second conductive layers over the first insulating capping layer; a memory opening extending vertically through the pair of layer stacks; a memory opening filling structure located in a respective memory opening and comprising a respective vertical stack of memory elements and a respective vertical semiconductor channel; and A bridge structure spans the entire width of the backside trench along the second horizontal direction, wherein a top surface of the bridge structure is below a top surface of the second layer of alternating stacks and a bottom surface of the bridge structure is above a bottom surface of the first layer of alternating stacks. 2 . The three-dimensional memory device according to claim 1 , further comprising a backside trench filling structure located in the backside trench and embedded in the bridge structure.

3. The three-dimensional memory device of claim 2 , wherein the bridge structure comprises a corresponding pair of first sidewalls contacting the first insulating capping layer within the pair of layer stacks and comprises corresponding top surfaces within a horizontal plane including a top surface of the first insulating capping layer.

4. The three-dimensional memory device according to claim 3 further comprises a plurality of the bridge structures located in the backside trench, and each of the plurality of bridge structures comprises a corresponding pair of second sidewalls perpendicular to the first horizontal direction and contacting corresponding sidewall surface sections of the backside trench filling structure. 5 . The three-dimensional memory device of claim 4 , wherein each of the top surfaces of the plurality of bridge structures contacts a corresponding bottom surface segment of the backside trench fill structure. 6 . The three-dimensional memory device of claim 4 , wherein the backside trench filling structure comprises an insulating spacer contacting longitudinal sidewalls of the pair of layer stacks and laterally surrounding a backside contact via structure.

7. The three-dimensional memory device according to claim 6, wherein: the insulating spacer comprising a plurality of upper insulating bridge portions contacting a bottom surface of a corresponding one of the plurality of bridge structures; The plurality of upper insulating bridge portions have the same width along the first horizontal direction as a corresponding one of the plurality of bridge structures and have the same vertical thickness as a lateral thickness of a vertically extending portion of the insulating spacer; and The insulating spacer includes a plurality of lower insulating bridge portions contacting respective top surface segments of a semiconductor material layer underlying the backside trench.

8. The three-dimensional memory device according to claim 7, wherein: The backside contact via structure contacts a plurality of source regions embedded in the semiconductor material layer; and The plurality of source regions are laterally spaced apart from one another by portions of the semiconductor material layer underlying the plurality of lower insulating bridge portions of the insulating spacers.

9. The three-dimensional memory device according to claim 7, wherein: The pair of layer stacks further includes a second insulating capping layer and a contact level dielectric layer overlying the second layer alternating stack; and The backside contact via structure extends vertically from a first horizontal plane including a top surface of the semiconductor material layer to a second horizontal plane including a top surface of the contact-level dielectric layer of the pair of layer stacks.

10. The three-dimensional memory device according to claim 9, further comprising: a first layer of rearwardly stepped dielectric material portion, the first layer of rearwardly stepped dielectric material portion contacting a stepped surface of a corresponding one of the first layer of alternating stacks; and a second layer back stepped dielectric material portion, the second layer back stepped dielectric material portion contacting a stepped surface of a corresponding one of the second layer alternating stacks, The top surface of the first layer of backward stepped dielectric material portion is located in the horizontal plane including the top surface of the first insulating capping layer.

11. The three-dimensional memory device of claim 10 , wherein each of the pair of layer stacks comprises an inter-level dielectric layer contacting a top surface of a corresponding first layer backward stepped dielectric material portion, a top surface of a corresponding first insulating cap layer, a bottom surface of a corresponding second layer backward stepped dielectric material portion, and a bottom surface of a corresponding second layer alternating stack. 12 . The three-dimensional memory device of claim 3 , wherein each of the first sidewalls of the plurality of bridge structures has a respective bottom edge adjacent to a sidewall of a respective one of the first insulating capping layers.

13. The three-dimensional memory device of claim 1, wherein the bridge structure comprises a semiconductor material.

14. A method of forming a semiconductor structure, the method comprising: forming first layer stacks extending laterally along a first horizontal direction and laterally spaced apart from each other along a second horizontal direction by first layer backside trenches, and wherein each of the first layer stacks comprises a first layer alternating stack of first insulating layers and first sacrificial material layers and a first insulating capping layer overlying the first layer alternating stack; forming a fill material stack including a sacrificial trench fill structure and a bridge material matrix in each of the first layer backside trenches; forming a second layer stack over the first layer alternating stack, wherein the second layer stacks extend laterally along the first horizontal direction and are laterally spaced apart from each other along the second horizontal direction by second layer backside trenches, and wherein each of the second layer stacks comprises a second layer alternating stack of a second insulating layer and a second sacrificial material layer; patterning each of the bridge material matrices into a plurality of bridge structures laterally spaced apart along the first horizontal direction; removing the sacrificial trench fill structure from beneath the plurality of bridge structures; as well as The first sacrificial material layer and the second sacrificial material layer are replaced with a first conductive layer and a second conductive layer, respectively.

15. The method according to claim 14, wherein: The sacrificial trench fill structure is formed by depositing a sacrificial trench fill material in the first layer backside trench and recessing the sacrificial trench fill material; and The bridge material matrix is ​​formed by depositing a bridge material over the sacrificial trench fill structure and removing portions of the bridge material above a horizontal plane including a top surface of the first insulating capping layer.

16. The method of claim 15, wherein: A top surface of the bridge material matrix is ​​formed within a horizontal plane including the top surface of the first insulating capping layer; and The bridge material matrix includes a semiconductor material.

17. The method according to claim 14, further comprising: applying a photoresist layer over the second layer alternating stack and in the second layer backside trenches; patterning the photoresist layer into a plurality of strips of photoresist material extending laterally along the second horizontal direction and laterally spaced apart along the first horizontal direction; as well as Portions of the matrix of bridge material not masked by the plurality of strips of photoresist material are etched, wherein a remaining portion of the matrix of bridge material comprises the bridge structure.

18. The method of claim 14, wherein: Each of the first layer backside grooves has a corresponding pair of first longitudinal sidewalls perpendicular to the second horizontal direction; and Each of the second layer backside grooves has a corresponding pair of second longitudinal sidewalls perpendicular to the second horizontal direction.

19. The method according to claim 14, further comprising: forming a first vertical alternating sequence of a first continuous insulating layer and a first continuous sacrificial material layer; forming a first continuous insulating cap layer over the first vertical alternating sequence; forming the first layer backside trench through the first continuous insulating capping layer and the first vertical alternating sequence, wherein the first layer stack includes the first continuous insulating capping layer and the patterned portion of the first vertical alternating sequence; forming a second vertical alternating sequence of a second continuous insulating layer and a second continuous sacrificial material layer over the first layer stack and the fill material stack; as well as The second layer backside trench is formed through the second vertical alternating sequence, wherein the second layer stack includes a patterned portion of the second vertical alternating sequence.

20. The method according to claim 19, further comprising: forming a memory opening through the second vertical alternating sequence and through the first layer stack; as well as Memory opening filling structures are formed in the memory openings, wherein each of the memory opening filling structures includes a respective vertical stack of memory elements and a respective vertical semiconductor channel.

21. A three-dimensional memory device, comprising: a pair of layer stacks extending laterally along a first horizontal direction and laterally spaced apart from each other by backside trenches along a second horizontal direction, wherein each layer stack in the pair of layer stacks comprises a first layer alternating stack of first insulating layers and first conductive layers and a second layer alternating stack of second insulating layers and second conductive layers, a memory opening extending vertically through the pair of layer stacks; a memory opening filling structure located in a respective memory opening and comprising a respective vertical stack of memory elements and a respective vertical semiconductor channel; and A perforated bridge structure includes a plurality of vertically extending openings located in the back side groove.

22. The three-dimensional memory device of claim 21 , further comprising a backside trench filling structure in the backside trench, wherein the backside trench filling structure comprises a backside contact via structure comprising a cylindrical connecting portion extending vertically through the vertically extending opening in the perforated bridge structure.

23. The three-dimensional memory device of claim 22, wherein the backside contact via structure comprises: a lower backside contact via portion, the lower backside contact via portion being located between the first layer alternating stacks of the pair of layer stacks; and An upper backside contact via portion is located between the second layer alternating stacks of the pair of layer stacks.

24. The three-dimensional memory device according to claim 23, wherein: The lower back contact via portion is adjacent to a bottom periphery of a sidewall of the cylindrical connecting portion of the back contact via structure; and The upper backside contact via portion is adjacent to a top perimeter of the sidewall of the cylindrical connecting portion of the backside contact via structure.

25. The three-dimensional memory device of claim 23, wherein the lower backside contact via portion is embedded in a corresponding row of air gaps, and the upper backside contact via portion is free of any air gaps. 26 . The three-dimensional memory device of claim 23 , wherein the backside contact via structure further comprises a first insulating spacer laterally surrounding the lower backside contact via portion and contacting an entire bottom surface of the through-via bridge structure. 27 . The three-dimensional memory device of claim 26 , wherein the first insulating spacer comprises a tubular portion contacting sidewalls of the plurality of vertically extending openings in the through-hole bridge structure.

28. The three-dimensional memory device of claim 26, wherein the backside contact via structure further comprises a second insulating spacer laterally surrounding a lower portion of the upper backside contact via portion and contacting a peripheral region of a top surface of the through-hole bridge structure.

29. The three-dimensional memory device of claim 28, wherein the second insulating spacer and the first insulating spacer are two discrete insulating structures comprising the same material, having the same lateral thickness and not in direct contact with each other.

30. The three-dimensional memory device of claim 28, wherein the backside contact via structure further comprises a third insulating spacer overlying the second insulating layer and laterally surrounding an upper portion of the upper backside contact via portion, wherein: the second insulating spacer comprising a pair of laterally undulating outer sidewalls comprising a respective set of vertically straight sidewall segments and laterally convex sidewall segments adjacent to one another; and The third insulating spacer includes a pair of laterally straight outer sidewalls extending laterally along the first horizontal direction.

31. The three-dimensional memory device of claim 21, wherein a top surface of the perforated bridge structure is below a top surface of the second layer of alternating stacks, and a bottom surface of the perforated bridge structure is above a bottom surface of the first layer of alternating stacks.

32. The three-dimensional memory device of claim 31 , wherein Each layer stack of the pair of layer stacks includes a first insulating capping layer located between a corresponding first layer alternating stack and a corresponding second layer alternating stack; The top surface of the perforated bridge structure is located in a horizontal plane including the top surface of the first insulating cap layer; and The through-hole bridge structure contacts a sidewall of the first insulating capping layer and includes a doped semiconductor material.

33. The three-dimensional memory device of claim 21, wherein the perforated bridge structure comprises a pair of laterally undulating outer sidewalls, the pair of laterally undulating outer sidewalls comprising a respective set of vertical straight sidewall segments and laterally convex sidewall segments adjacent to each other.

34. The three-dimensional memory device of claim 33, wherein: A bottom portion of the backside groove below the perforated bridge structure includes a pair of laterally undulating sidewalls including a respective set of vertical straight sidewall segments and laterally convex sidewall segments adjacent to each other; and The pair of laterally undulating side walls of the bottom portion of the backside groove vertically coincide with the pair of laterally undulating outer side walls of the perforated bridge structure.

35. A method of forming a semiconductor structure, the method comprising: forming a first vertical alternating sequence of a first continuous insulating layer and a first continuous sacrificial material layer; dividing the first vertical alternating sequence into first layer alternating stacks of first insulating layers and first sacrificial material layers by forming first layer backside trenches, wherein the first layer alternating stacks extend laterally along a first horizontal direction and are laterally spaced apart from each other along a second horizontal direction by the first layer backside trenches; forming a fill material stack including a sacrificial trench fill structure and a bridge material matrix in each of the first layer backside trenches; forming a second vertical alternating sequence of a second continuous insulating layer and a second continuous sacrificial material layer over the first alternating layer stack and the fill material stack; forming a plurality of rows of discrete backside openings through the second vertical alternating sequence and through the bridge material matrices, wherein each of the bridge material matrices is converted into a respective perforated bridge structure, a respective plurality of openings extending vertically through the respective perforated bridge structure; dividing the second vertical alternating sequence into a second layer alternating stack of a second insulating layer and a second sacrificial material layer by laterally expanding the discrete backside openings, wherein the discrete backside openings in each of the rows merge with one another to form a second layer of backside trenches; as well as The first sacrificial material layer and the second sacrificial material layer are replaced with a first conductive layer and a second conductive layer, respectively.

36. The method of claim 35, further comprising: forming a first continuous insulating cap layer over the first vertical alternating sequence; as well as The first continuous insulating capping layer is divided into a plurality of first insulating capping layers covering a corresponding one of the first layer alternating stacks in the first layer alternating stacks, wherein: The sacrificial trench fill structure is formed by depositing a sacrificial trench fill material in the first layer backside trench and recessing the sacrificial trench fill material; and The bridge material matrix is ​​formed by depositing a bridge material over the sacrificial trench fill structure and removing portions of the bridge material above a horizontal plane including a top surface of the first insulating capping layer.

37. The method of claim 35, wherein the first layer backside trench is formed by: forming a plurality of rows of discrete first layer backside openings through said first vertical alternating sequence; and The first layer backside openings are laterally expanded, wherein the discrete first layer backside openings in each of the rows merge with each other to form the first layer backside trenches.

38. The method of claim 37, further comprising: forming first-level memory openings during the formation of the plurality of rows of discrete first-level backside openings by performing a first anisotropic etching process; forming a second level of memory openings during formation of the plurality of rows of discrete backside openings over a region of the first level of memory openings by performing a second anisotropic etching process; as well as A memory opening filling structure is formed within each successive combination of the volume of the first layer of memory openings and the volume of the second layer of memory openings.

39. The method of claim 38, wherein each of the memory opening filling structures comprises a respective vertical stack of memory elements and a respective vertical semiconductor channel.

40. The method of claim 35, further comprising: removing the sacrificial trench fill structure after forming the second layer backside trench to form the backside trench extending vertically through the first layer alternating stack and the second layer alternating stack; as well as A backside contact via structure is formed in the backside trench.

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