A semiconductor silicon epitaxial wafer material and a preparation method thereof

Abstract

The present invention discloses a semiconductor silicon epitaxial wafer material and a preparation method thereof, relating to the field of semiconductor material technology. The method comprises the following steps: step S1, pre-treating a substrate; step S2, growing a prefabricated layer; step S3, growing a first epitaxial layer; and step S4, growing a second epitaxial layer. The semiconductor silicon epitaxial wafer material disclosed in the present invention has high flatness, good uniformity, and strong gettering capability.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor materials, and in particular to a semiconductor silicon epitaxial wafer material and a preparation method thereof. Background Art

[0002] With the rapid development of the domestic electronic information industry, the demand for electronic components is increasing, and the research on electronic component materials and their preparation technology is becoming more and more important. Epitaxial layer process materials were originally used for bipolar integrated circuits and high-voltage devices, and are mainly used to improve circuit performance in MOS integrated circuits. With the development of the semiconductor industry, the demand for semiconductor silicon epitaxial wafers has greatly increased, and the requirements for their performance and quality are also getting higher and higher.

[0003] At present, in the preparation process of semiconductor silicon epitaxial wafer materials, when the epitaxial layer is grown by chemical vapor deposition, the impurities contained in the epitaxial layer come not only from the doping source, but also from impurities in the heavily doped substrate. The phenomenon that the impurities in the heavily doped substrate evaporate and enter the epitaxial layer due to the high temperature during the epitaxial growth process is usually called autodoping. The impurities in the heavily doped substrate mainly enter the epitaxial layer through gas phase transport and solid phase diffusion during the epitaxial growth process, thereby affecting the product yield of the epitaxial silicon wafer. In addition, the semiconductor silicon epitaxial wafer materials on the market still have more or less defects, crystal dislocations, stacking faults, insufficient flatness, low uniformity and other technical problems.

[0004] To address the above issues, Chinese invention patent publication number CN105026624B discloses an epitaxial silicon wafer with a diameter of 300 mm or greater cut from a silicon single crystal grown using the Czochralski method. The epitaxial silicon wafer is characterized by a cooling time of less than 450 minutes for each portion of the silicon single crystal from 800°C to 600°C during growth, and an interstitial oxygen concentration of 1.5×10 18 -2.2×10 18 atoms / cm 3 (old ASTM), the entire surface of the silicon wafer cut out above is composed of COP area, and the BMD density of the body of the epitaxial wafer after heat treatment at 1000℃×16 hours is 1×10 4 / cm 2 Even if the thermal process in the semiconductor device manufacturing process is a low-temperature thermal process, the epitaxial silicon wafer can obtain sufficient impurity gettering ability and will not produce epitaxial defects. However, the flatness of the epitaxial silicon wafer still needs to be further improved.

[0005] It can be seen that the development of a semiconductor silicon epitaxial wafer material with high flatness, good uniformity and strong impurity absorption ability and its preparation method meets market demand, has high market value and application prospects, and is of great significance to promoting the development of the silicon epitaxial wafer material field. Summary of the Invention

[0006] In order to overcome the defects in the prior art, the present invention provides a semiconductor silicon epitaxial wafer material with high flatness, good uniformity and strong impurity gettering ability and a preparation method thereof.

[0007] The technical solution adopted by the present invention to solve the technical problem is: a method for preparing a semiconductor silicon epitaxial wafer material, comprising the following steps:

[0008] Step S1, pretreatment of the substrate: polishing and cleaning the selected silicon substrate before epitaxy, then baking it with hydrogen, and then performing back sealing treatment on the substrate to obtain a pretreated silicon substrate;

[0009] Step S2, growth of a prefabricated layer: growing a prefabricated layer on the substrate surface using a molecular beam epitaxy process;

[0010] Step S3, growth of the first epitaxial layer: Under normal pressure, a single-wafer epitaxial growth system is used, a high-purity graphite base is used as a silicon wafer carrier, and ultra-high-purity H2 is used as a protective gas; the first epitaxial layer is grown on the surface of the prefabricated layer;

[0011] Step S4, growth of the second epitaxial layer: under a low pressure of 18-20KPa, a single-wafer epitaxial growth system is used, a high-purity graphite base is used as a silicon wafer carrier, and ultra-high-purity H2 is used as a protective gas; the second epitaxial layer is grown on the surface of the prefabricated layer.

[0012] Preferably, the cleaning in step S1 is performed using RCA SC-2 solution, and a multi-energy field assisted treatment is used during the cleaning process for 5-8 minutes.

[0013] Preferably, the multi-energy field is a superposition field of a steady magnetic field and an electromagnetic oscillation field; the magnetic field strength of the steady magnetic field is 5000-13000Gs; the frequency of the electromagnetic oscillation field is 13-33HZ, and the medium and low duty cycle is 18-32%.

[0014] Preferably, the baking temperature using hydrogen in step S1 is 1100-1200° C., and the constant temperature time is 3-6 minutes.

[0015] Preferably, the back sealing process in step S1 is SiO2+POLY, and the thickness of the SiO2 back seal is

[0016] Preferably, the thickness of the prefabricated layer in step S2 is 0.3-1.1 μm; the silicon source gas used in the production process of the prefabricated layer is at least one of SiH2Cl2 or SiH4; and the silicon source gas flow rate of the prefabricated layer is 10-15 L / min.

[0017] Preferably, the prefabricated layer in step S2 is N-type doped and heavily doped; the N-type doping includes at least one element selected from N, P, As, Sb, and Bi.

[0018] Preferably, the N-type doping atoms are arsenic atoms, and the doping concentration of arsenic atoms is 5×10 15 ~5.5×10 15 atoms / cm 3 .

[0019] Preferably, before the growth of the first epitaxial layer in step S3, the epitaxial growth system is subjected to corrosion and base silicon coating treatment to reduce the influence of system self-doping.

[0020] Preferably, in step S3, the thickness of the first epitaxial layer is 0.5-3 μm.

[0021] Preferably, during the growth of the first epitaxial layer in step S3, the growth temperature is 1080-1150° C., the silicon source flow rate is 3-5 g / min, the growth rate is 0.8-1.2 μm / min, and the ultra-high purity H 2 flow rate is 140-160 slm.

[0022] Preferably, the purity of the ultra-high purity H2 reaches above 99.999999%.

[0023] Preferably, during the growth of the first epitaxial layer in step S3, the silicon source used is a mixture of SiH2Cl2 and SiH4 in a mass ratio of (3-5):1.

[0024] Preferably, in step S4, the thickness of the second epitaxial layer is 5-10 μm.

[0025] Preferably, during the growth of the second epitaxial layer in step S4, the growth temperature is 1030-1070° C., the silicon source flow rate is 1-3 g / min, the growth rate is 0.5-0.8 μm / min, and the ultra-high purity H 2 flow rate is 120-140 slm.

[0026] Preferably, during the growth of the second epitaxial layer in step S4, the silicon source used is a mixture of SiH2Cl2 and SiH4 in a mass ratio of (1-3):1.

[0027] Another object of the present invention is to provide a conductive silicon epitaxial wafer material prepared by the above-mentioned method for preparing a semiconductor silicon epitaxial wafer material.

[0028] The beneficial effects of adopting the above technical solution are:

[0029] (1) The method for preparing semiconductor silicon epitaxial wafer materials provided by the present invention has simple process, convenient operation and control, high preparation efficiency and finished product qualification rate, low dependence on equipment, stable industrial production, and high promotion and application value.

[0030] (2) The semiconductor silicon epitaxial wafer material provided by the present invention comprises a substrate, on which a prefabricated layer, a first epitaxial layer, and a second epitaxial layer are sequentially provided; by designing the above-mentioned epitaxial structure, the epitaxial wafer material produced has high flatness, good uniformity, and strong impurity absorption capability; the silicon source gas used in the production process of the prefabricated layer is at least one of SiH2Cl2 and SiH4; in the growth process of the first epitaxial layer in step S3, the silicon source used is a mixture of SiH2Cl2 and SiH4 in a mass ratio of (3-5):1; in the growth process of the second epitaxial layer in step S4, the silicon source used is SiH2Cl2 and SiH4 in a mass ratio of (3-5):1. The silicon source is a mixture of SiH2Cl2 and SiH4 in a mass ratio of (1-3):1; by using different silicon sources for the above-mentioned different epitaxial layers and rationally selecting different epitaxial growth conditions, these growth conditions cooperate with each other to complete the epitaxial growth process at a lower temperature and lower pressure. The epitaxial growth system controls the flow rate of the incoming gas while evacuating the air, so that the pressure impurity molecules and corrosive gases can be quickly discharged with the main gas flow, thereby suppressing the occurrence of defects such as unevenness and unevenness of the epitaxial wafer caused by the diffusion, evaporation, self-doping and other effects of impurities in the substrate and the failure of the gas to be discharged in time.

[0031] (3) The semiconductor silicon epitaxial wafer material provided by the present invention is beneficial to improving the performance of the semiconductor silicon epitaxial wafer material produced through the reasonable selection of epitaxial structure and epitaxial process parameters, can effectively reduce epitaxial defects, improve the quality of the epitaxial layer, and make the epitaxial wafer material produced have high flatness, good uniformity, and strong impurity absorption ability; it effectively reduces the yield loss of the chip produced and further improves the production efficiency. DETAILED DESCRIPTION

[0032] In order to enable those skilled in the art to better understand the technical solution of the present invention and to make the above-mentioned features, purposes and advantages of the present invention more clearly understood, the present invention is further described below in conjunction with examples. The examples are only used to illustrate the present invention and are not intended to limit the scope of the present invention.

[0033] The single wafer epitaxial growth system described in the following embodiments is an ASM E2000 single wafer epitaxial growth system.

[0034] Example 1

[0035] A method for preparing a semiconductor silicon epitaxial wafer material comprises the following steps:

[0036] Step S1, pretreatment of the substrate: polishing and cleaning the selected silicon substrate before epitaxy, then baking it with hydrogen, and then performing back sealing treatment on the substrate to obtain a pretreated silicon substrate;

[0037] Step S2, growth of a prefabricated layer: growing a prefabricated layer on the substrate surface using a molecular beam epitaxy process;

[0038] Step S3, growth of the first epitaxial layer: Under normal pressure, a single-wafer epitaxial growth system is used, a high-purity graphite base is used as a silicon wafer carrier, and ultra-high-purity H2 is used as a protective gas; the first epitaxial layer is grown on the surface of the prefabricated layer;

[0039] Step S4, growth of the second epitaxial layer: under a low pressure of 18KPa, a single-wafer epitaxial growth system is used, a high-purity graphite base is used as a silicon wafer carrier, and the protective gas is ultra-high-purity H2; the second epitaxial layer is grown on the surface of the prefabricated layer.

[0040] The cleaning in step S1 is performed using RCA SC-2 liquid, and a multi-energy field auxiliary treatment is used for 5 minutes during the cleaning process; the multi-energy field is a superposition field of a steady magnetic field and an electromagnetic oscillation field; the magnetic field strength of the steady magnetic field is 5000Gs; the frequency of the electromagnetic oscillation field is 13HZ, and the medium and low duty cycle is 18% at this time; the temperature for baking with hydrogen in step S1 is 1100°C, and the constant temperature time is 3 minutes; the back sealing process of the back sealing treatment in step S1 is SiO2+POLY, and the thickness of the SiO2 back seal is

[0041] The thickness of the prefabricated layer in step S2 is 0.3 μm; the silicon source gas used in the production process of the prefabricated layer is SiH2Cl2; the silicon source gas flow rate of the prefabricated layer is 10 L / min; the prefabricated layer in step S2 is N-type doped and heavily doped; the N-type doping atom is arsenic atom, and the doping concentration of arsenic atom is 5×10 15 atoms / cm 3 .

[0042] Before the growth of the first epitaxial layer in step S3, the epitaxial growth system is corroded and the base is silicon-coated to reduce the influence of system self-doping; the thickness of the first epitaxial layer in step S3 is 0.5 μm; during the growth of the first epitaxial layer in step S3, the growth temperature is 1080°C, the silicon source flow rate is 3 g / min, the growth rate is 0.8 μm / min, and the ultra-high purity H2 flow rate is 140 slm; the purity of the ultra-high purity H2 reaches more than 99.999999%; during the growth of the first epitaxial layer in step S3, the silicon source used is a mixture of SiH2Cl2 and SiH4 in a mass ratio of 3:1.

[0043] The thickness of the second epitaxial layer in step S4 is 5 μm; during the growth of the second epitaxial layer in step S4, the growth temperature is 1030°C, the silicon source flow rate is 1 g / min, the growth rate is 0.5 μm / min, and the ultra-high purity H2 flow rate is 120 slm; during the growth of the second epitaxial layer in step S4, the silicon source used is a mixture of SiH2Cl2 and SiH4 in a mass ratio of 1:1.

[0044] A conductive silicon epitaxial wafer material is prepared by adopting the above-mentioned method for preparing a semiconductor silicon epitaxial wafer material.

[0045] Example 2

[0046] A method for preparing a semiconductor silicon epitaxial wafer material comprises the following steps:

[0047] Step S1, pretreatment of the substrate: polishing and cleaning the selected silicon substrate before epitaxy, then baking it with hydrogen, and then performing back sealing treatment on the substrate to obtain a pretreated silicon substrate;

[0048] Step S2, growth of a prefabricated layer: growing a prefabricated layer on the substrate surface using a molecular beam epitaxy process;

[0049] Step S3, growth of the first epitaxial layer: Under normal pressure, a single-wafer epitaxial growth system is used, a high-purity graphite base is used as a silicon wafer carrier, and ultra-high-purity H2 is used as a protective gas; the first epitaxial layer is grown on the surface of the prefabricated layer;

[0050] Step S4, growth of the second epitaxial layer: under a low pressure of 18.5 KPa, a single-wafer epitaxial growth system is used, a high-purity graphite base is used as a silicon wafer carrier, and the protective gas is ultra-high-purity H2; the second epitaxial layer is grown on the surface of the prefabricated layer.

[0051] The cleaning in step S1 is carried out using RCA SC-2 liquid, and a multi-energy field auxiliary treatment is used for 6 minutes during the cleaning process; the multi-energy field is a superposition field of a steady magnetic field and an electromagnetic oscillation field; the magnetic field strength of the steady magnetic field is 7000Gs; the frequency of the electromagnetic oscillation field is 18HZ, and the medium and low duty cycle is 22% at this time; the temperature for baking with hydrogen in step S1 is 1130℃, and the constant temperature time is 4 minutes; the back sealing process of the back sealing treatment in step S1 is SiO2+POLY, and the thickness of the SiO2 back seal is

[0052] The thickness of the prefabricated layer in step S2 is 0.5 μm; the silicon source gas used in the production process of the prefabricated layer is SiH4; the flow rate of the silicon source gas for the prefabricated layer is 12 L / min; the prefabricated layer in step S2 is N-type doped and heavily doped; the N-type doping atom is arsenic atom, and the doping concentration of arsenic atom is 5.2×10 15atoms / cm 3 .

[0053] Before the growth of the first epitaxial layer in step S3, the epitaxial growth system is corroded and the base is silicon-coated to reduce the influence of system self-doping; the thickness of the first epitaxial layer in step S3 is 1.5μm; during the growth of the first epitaxial layer in step S3, the growth temperature is 1100°C, the silicon source flow rate is 3.5g / min, the growth rate is 0.9μm / min, and the ultra-high purity H2 flow rate is 145slm; the purity of the ultra-high purity H2 reaches more than 99.999999%; during the growth of the first epitaxial layer in step S3, the silicon source used is a mixture of SiH2Cl2 and SiH4 in a mass ratio of 3.5:1.

[0054] The thickness of the second epitaxial layer in step S4 is 6 μm; during the growth of the second epitaxial layer in step S4, the growth temperature is 1040°C, the silicon source flow rate is 1.5 g / min, the growth rate is 0.6 μm / min, and the ultra-high purity H2 flow rate is 125 slm; during the growth of the second epitaxial layer in step S4, the silicon source used is a mixture of SiH2Cl2 and SiH4 in a mass ratio of 1.5:1.

[0055] A conductive silicon epitaxial wafer material is prepared by adopting the above-mentioned method for preparing a semiconductor silicon epitaxial wafer material.

[0056] Example 3

[0057] A method for preparing a semiconductor silicon epitaxial wafer material comprises the following steps:

[0058] Step S1, pretreatment of the substrate: polishing and cleaning the selected silicon substrate before epitaxy, then baking it with hydrogen, and then performing back sealing treatment on the substrate to obtain a pretreated silicon substrate;

[0059] Step S2, growth of a prefabricated layer: growing a prefabricated layer on the substrate surface using a molecular beam epitaxy process;

[0060] Step S3, growth of the first epitaxial layer: Under normal pressure, a single-wafer epitaxial growth system is used, a high-purity graphite base is used as a silicon wafer carrier, and ultra-high-purity H2 is used as a protective gas; the first epitaxial layer is grown on the surface of the prefabricated layer;

[0061] Step S4, growth of the second epitaxial layer: under a low pressure of 19 KPa, a single-wafer epitaxial growth system is used, a high-purity graphite base is used as a silicon wafer carrier, and the protective gas is ultra-high-purity H2; the second epitaxial layer is grown on the surface of the prefabricated layer.

[0062] The cleaning in step S1 is performed using RCA SC-2 liquid, and a multi-energy field auxiliary treatment is used for 6.5 minutes during the cleaning process; the multi-energy field is a superposition field of a steady magnetic field and an electromagnetic oscillation field; the magnetic field strength of the steady magnetic field is 9000Gs; the frequency of the electromagnetic oscillation field is 23HZ, and the medium and low duty cycle is 25% at this time; the temperature for baking with hydrogen in step S1 is 1150°C, and the constant temperature time is 4.5 minutes; the back sealing process of the back sealing treatment in step S1 is SiO2+POLY, and the thickness of the SiO2 back seal is

[0063] The thickness of the prefabricated layer in step S2 is 0.8 μm; the silicon source gas used in the production process of the prefabricated layer is SiH2Cl2; the silicon source gas flow rate of the prefabricated layer is 13 L / min; the prefabricated layer in step S2 is N-type doped and heavily doped; the N-type doping atom is arsenic atom, and the doping concentration of arsenic atom is 5.3×10 15 atoms / cm 3 .

[0064] Before the growth of the first epitaxial layer in step S3, the epitaxial growth system is corroded and the base is silicon-coated to reduce the influence of system self-doping; the thickness of the first epitaxial layer in step S3 is 2μm; during the growth of the first epitaxial layer in step S3, the growth temperature is 1120°C, the silicon source flow rate is 4g / min, the growth rate is 1μm / min, and the ultra-high purity H2 flow rate is 150slm; the purity of the ultra-high purity H2 reaches more than 99.999999%; during the growth of the first epitaxial layer in step S3, the silicon source used is a mixture of SiH2Cl2 and SiH4 in a mass ratio of 4:1.

[0065] The thickness of the second epitaxial layer in step S4 is 8 μm; during the growth of the second epitaxial layer in step S4, the growth temperature is 1050°C, the silicon source flow rate is 2 g / min, the growth rate is 0.65 μm / min, and the ultra-high purity H2 flow rate is 130 slm; during the growth of the second epitaxial layer in step S4, the silicon source used is a mixture of SiH2Cl2 and SiH4 in a mass ratio of 2:1.

[0066] A conductive silicon epitaxial wafer material is prepared by adopting the above-mentioned method for preparing a semiconductor silicon epitaxial wafer material.

[0067] Example 4

[0068] A method for preparing a semiconductor silicon epitaxial wafer material comprises the following steps:

[0069] Step S1, pretreatment of the substrate: polishing and cleaning the selected silicon substrate before epitaxy, then baking it with hydrogen, and then performing back sealing treatment on the substrate to obtain a pretreated silicon substrate;

[0070] Step S2, growth of a prefabricated layer: growing a prefabricated layer on the substrate surface using a molecular beam epitaxy process;

[0071] Step S3, growth of the first epitaxial layer: Under normal pressure, a single-wafer epitaxial growth system is used, a high-purity graphite base is used as a silicon wafer carrier, and ultra-high-purity H2 is used as a protective gas; the first epitaxial layer is grown on the surface of the prefabricated layer;

[0072] Step S4, growth of the second epitaxial layer: under a low pressure of 19.5 KPa, a single-wafer epitaxial growth system is used, a high-purity graphite base is used as a silicon wafer carrier, and the protective gas is ultra-high-purity H2; the second epitaxial layer is grown on the surface of the prefabricated layer.

[0073] Preferably, the cleaning in step S1 is performed using RCA SC-2 liquid, and a multi-energy field auxiliary treatment is used during the cleaning process for 7.5 minutes; the multi-energy field is a superposition field of a steady magnetic field and an electromagnetic oscillation field; the magnetic field strength of the steady magnetic field is 12000Gs; the frequency of the electromagnetic oscillation field is 30HZ, and the medium and low duty cycle is 30% at this time; the temperature for baking with hydrogen in step S1 is 1190°C, and the constant temperature time is 5.5 minutes; the back sealing process of the back sealing treatment in step S1 is SiO2+POLY, and the thickness of the SiO2 back seal is

[0074] The thickness of the prefabricated layer in step S2 is 1 μm; the silicon source gas used in the production process of the prefabricated layer is SiH2Cl2; the flow rate of the silicon source gas for the prefabricated layer is 14 L / min; the prefabricated layer in step S2 is N-type doped and heavily doped; the N-type doping atom is arsenic atom, and the doping concentration of arsenic atom is 5.4×10 15 atoms / cm 3 .

[0075] Before the growth of the first epitaxial layer in step S3, the epitaxial growth system is corroded and the base is silicon-coated to reduce the influence of system self-doping; the thickness of the first epitaxial layer in step S3 is 2.5μm; during the growth of the first epitaxial layer in step S3, the growth temperature is 1140°C, the silicon source flow rate is 4.5g / min, the growth rate is 1.1μm / min, and the ultra-high purity H2 flow rate is 155slm; the purity of the ultra-high purity H2 reaches more than 99.999999%; during the growth of the first epitaxial layer in step S3, the silicon source used is a mixture of SiH2Cl2 and SiH4 in a mass ratio of 4.5:1.

[0076] The thickness of the second epitaxial layer in step S4 is 9 μm; during the growth of the second epitaxial layer in step S4, the growth temperature is 1060°C, the silicon source flow rate is 2.5 g / min, the growth rate is 0.75 μm / min, and the ultra-high purity H2 flow rate is 135 slm; during the growth of the second epitaxial layer in step S4, the silicon source used is a mixture of SiH2Cl2 and SiH4 in a mass ratio of 2.5:1.

[0077] A conductive silicon epitaxial wafer material is prepared by adopting the above-mentioned method for preparing a semiconductor silicon epitaxial wafer material.

[0078] Example 5

[0079] A method for preparing a semiconductor silicon epitaxial wafer material comprises the following steps:

[0080] Step S1, pretreatment of the substrate: polishing and cleaning the selected silicon substrate before epitaxy, then baking it with hydrogen, and then performing back sealing treatment on the substrate to obtain a pretreated silicon substrate;

[0081] Step S2, growth of a prefabricated layer: growing a prefabricated layer on the substrate surface using a molecular beam epitaxy process;

[0082] Step S3, growth of the first epitaxial layer: Under normal pressure, a single-wafer epitaxial growth system is used, a high-purity graphite base is used as a silicon wafer carrier, and ultra-high-purity H2 is used as a protective gas; the first epitaxial layer is grown on the surface of the prefabricated layer;

[0083] Step S4, growth of the second epitaxial layer: under a low pressure of 20 KPa, a single-wafer epitaxial growth system is used, a high-purity graphite base is used as a silicon wafer carrier, and the protective gas is ultra-high-purity H2; the second epitaxial layer is grown on the surface of the prefabricated layer.

[0084] The cleaning in step S1 is performed using RCA SC-2 liquid, and a multi-energy field auxiliary treatment is used for 8 minutes during the cleaning process; the multi-energy field is a superposition field of a steady magnetic field and an electromagnetic oscillation field; the magnetic field strength of the steady magnetic field is 13000Gs; the frequency of the electromagnetic oscillation field is 33HZ, and the medium and low duty cycle is 32% at this time; the temperature for baking with hydrogen in step S1 is 1200℃, and the constant temperature time is 6 minutes; the back sealing process of the back sealing treatment in step S1 is SiO2+POLY, and the thickness of the SiO2 back seal is

[0085] The thickness of the prefabricated layer in step S2 is 1.1 μm; the silicon source gas used in the production process of the prefabricated layer is SiH4; the flow rate of the silicon source gas for the prefabricated layer is 15 L / min; the prefabricated layer in step S2 is N-type doped and heavily doped; the N-type doping atom is arsenic atom, and the doping concentration of arsenic atom is 5.5×1015 atoms / cm 3 .

[0086] Before the growth of the first epitaxial layer in step S3, the epitaxial growth system is corroded and the base is silicon-coated to reduce the influence of system self-doping; the thickness of the first epitaxial layer in step S3 is 3 μm; during the growth of the first epitaxial layer in step S3, the growth temperature is 1150°C, the silicon source flow rate is 5 g / min, the growth rate is 1.2 μm / min, and the ultra-high purity H2 flow rate is 160 slm; the purity of the ultra-high purity H2 reaches more than 99.999999%; during the growth of the first epitaxial layer in step S3, the silicon source used is a mixture of SiH2Cl2 and SiH4 in a mass ratio of 5:1.

[0087] The thickness of the second epitaxial layer in step S4 is 10 μm; during the growth of the second epitaxial layer in step S4, the growth temperature is 1070°C, the silicon source flow rate is 3 g / min, the growth rate is 0.8 μm / min, and the ultra-high purity H2 flow rate is 140 slm; during the growth of the second epitaxial layer in step S4, the silicon source used is a mixture of SiH2Cl2 and SiH4 in a mass ratio of 3:1.

[0088] A conductive silicon epitaxial wafer material is prepared by adopting the above-mentioned method for preparing a semiconductor silicon epitaxial wafer material.

[0089] Comparative Example 1

[0090] A semiconductor silicon epitaxial wafer material and a preparation method thereof are basically the same as those in Example 1, except that the growth of the prefabricated layer adopts a chemical vapor deposition manufacturing process instead of a molecular beam epitaxy process.

[0091] Comparative Example 2

[0092] A semiconductor silicon epitaxial wafer material and a preparation method thereof are basically the same as those in Example 1, except that multi-energy field assisted processing is not used.

[0093] The semiconductor silicon epitaxial wafer material samples described in Examples 1-5 and Comparative Examples 1-2 were subjected to performance tests. The test results are shown in Table 1. The test method is as follows:

[0094] (1) Thermal stress load test: The sample was subjected to five consecutive millisecond annealing cycles with a maximum temperature of 1200°C using a flash lamp annealing furnace. The sample surface was then subjected to Wright etching to visually confirm the presence of dislocation pits on the sample surface. Samples with dislocation pits (bad results of the thermal stress load test) were marked with an "×" and samples without dislocation pits (good results of the thermal stress load test) were marked with an "○".

[0095] (2) Gettering ability evaluation: The back of the sample was intentionally contaminated with Ni to a depth of 1×10 12 / cm 2 The sample was heat treated at 900°C for 10 minutes for diffusion (redistribution (drive-in) heat treatment). A 1 μm thick portion of the sample surface was then removed by Wright etching to confirm the presence of tiny shallow depressions, or shallow pits, on the surface. Samples with shallow pits (low gettering ability) were marked with an "×," while samples without shallow pits (high gettering ability) were marked with an "○."

[0096] (3) Thickness uniformity: Use an infrared film thickness gauge to test the thickness, and calculate the thickness uniformity.

[0097] Table 1

[0098] Test items Example 1 Example 2 Example 3 Example 4 Example 5 Comparative Example 1 Comparative Example 2 Thermal stress load ○ ○ ○ ○ ○ × × Impurity absorption capacity ○ ○ ○ ○ ○ × × Thickness uniformity (%) 0.13 0.1 0.08 0.04 0.03 0.74 0.61

[0099] As can be seen from Table 1, the semiconductor silicon epitaxial wafer material disclosed in the embodiment of the present invention has better thermal stress load test results, stronger impurity gettering ability, and better thickness uniformity than the comparative example; the combined use of molecular beam epitaxy process and multi-energy field assisted treatment is beneficial to improving the above performance.

[0100] The above shows and describes the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The above embodiments and descriptions merely illustrate the principles of the present invention. Various changes and modifications may be made to the present invention without departing from the spirit and scope of the present invention. Such changes and modifications are intended to fall within the scope of the present invention. The scope of protection claimed by the present invention is defined by the appended claims and their equivalents.

Claims

1. A method for preparing semiconductor silicon epitaxial wafer material, characterized in that: The steps include: Step S1, pretreatment of the substrate: polishing and cleaning the selected silicon substrate before epitaxy, then baking it with hydrogen, and then performing back sealing treatment on the substrate to obtain a pretreated silicon substrate; The cleaning is performed using RCA SC-2 liquid, and a multi-energy field is used to assist the cleaning process for 5-8 minutes. The multi-energy field is a superposition field of a steady magnetic field and an electromagnetic oscillation field. The magnetic field strength of the steady magnetic field is 5000-13000 Gs. The frequency of the electromagnetic oscillation field is 13-33 Hz, and the medium and low duty cycle is 18-32%. Step S2, growth of a prefabricated layer: growing a prefabricated layer on the substrate surface by using a molecular beam epitaxy process; the prefabricated layer is N-type doped and heavily doped; the N-type doping is at least one element selected from N, P, As, Sb, and Bi; Step S3, growth of the first epitaxial layer: Under normal pressure, a single-wafer epitaxial growth system is used, a high-purity graphite base is used as a silicon wafer carrier, and the protective gas is ultra-high-purity H2; the first epitaxial layer is grown on the surface of the prefabricated layer; during the growth of the first epitaxial layer, the silicon source used is a mixture of SiH2Cl2 and SiH4 in a mass ratio of (3-5):1; Step S4, growth of the second epitaxial layer: under a low pressure of 18-20KPa, a single-wafer epitaxial growth system is used, a high-purity graphite base is used as a silicon wafer carrier, and the protective gas is ultra-high-purity H2; the second epitaxial layer is grown on the surface of the prefabricated layer; during the growth of the second epitaxial layer, the silicon source used is SiH2Cl2 and SiH4 mixed in a mass ratio of (1-3):

1.

2. The method for preparing a semiconductor silicon epitaxial wafer material according to claim 1, wherein: The temperature for baking using hydrogen in step S1 is 1100-1200°C, and the constant temperature time is 3-6 minutes; the back sealing process of the back sealing treatment in step S1 is SiO2+POLY, and the thickness of the SiO2 back seal is 3800~5200Å.

3. The method for preparing semiconductor silicon epitaxial wafer material according to claim 1, characterized in that: The thickness of the prefabricated layer in step S2 is 0.3-1.1 μm; the silicon source gas used in the production process of the prefabricated layer is at least one of SiH2Cl2 or SiH4; the flow rate of the silicon source gas of the prefabricated layer is 10-15 L / min.

4. The method for preparing semiconductor silicon epitaxial wafer material according to claim 1, characterized in that: The N-type doping atoms are arsenic atoms, and the doping concentration of arsenic atoms is 5×10 15 ~5.5×10 15 atoms / cm 3 .

5. The method for preparing semiconductor silicon epitaxial wafer material according to claim 1, characterized in that: Before the growth of the first epitaxial layer in step S3, the epitaxial growth system is corroded and the base is silicon-coated to reduce the influence of system self-doping; the thickness of the first epitaxial layer in step S3 is 0.5-3μm; during the growth of the first epitaxial layer in step S3, the growth temperature is 1080-1150℃, the silicon source flow rate is 3-5g / min, the growth rate is 0.8-1.2μm / min, and the ultra-high purity H2 flow rate is 140-160slm; the purity of the ultra-high purity H2 reaches above 99.999999%.

6. The method for preparing semiconductor silicon epitaxial wafer material according to claim 1, characterized in that: The thickness of the second epitaxial layer in step S4 is 5-10 μm; during the growth of the second epitaxial layer in step S4, the growth temperature is 1030-1070°C, the silicon source flow rate is 1-3 g / min, the growth rate is 0.5-0.8 μm / min, and the ultra-high purity H2 flow rate is 120-140 slm.