Chip response test circuit
By designing chip response test circuits, including temperature control units and test units, the problem that the existing technology cannot automatically adjust the test ambient temperature and obtain the optimal response time of the chip, and realize automatic testing and optimal response of the chip at different temperatures Getting time.
Patent Information
- Application Number
- CN202411832749.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-13
- Publication Date
- 2025-02-14
- Estimated Expiration
- Not applicable · inactive patent
AI Technical Summary
The existing chip test circuit cannot automatically adjust the test ambient temperature and conduct automatic testing after the temperature is adjusted, and cannot obtain the optimal response time and operating temperature of the chip at different temperatures.
A chip response test circuit is designed, including a temperature control unit and a test unit. The temperature control unit is used to set the temperature range of the chip and adjust the test ambient temperature. The test unit is used to feedback the temperature adjustment signal after the first test of the chip is completed. And obtain its optimal response time and operating temperature based on the chip's response time and temperature curve.
It is realized that after the tester gives the initial test signal, the chip can automatically conduct subsequent tests and obtain the chip's optimal response time and operating temperature within the set temperature range, improving the automation and efficiency of the test.
Smart Images
Figure CN119438871A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of chip testing, and in particular to a chip response testing circuit. Background Art
[0002] The 5G era has brought the development of the electronics industry to a peak. As one of the important parts of scientific and technological electronic equipment, the requirements for chip quality are getting higher and higher. Chip testing is an important link before commercial mass production. Testers will input test signals into the chip to measure the response time of the chip after obtaining the input signal and performing calculations and feeding back the calculation results. High and low temperature environments will affect the response of the chip, and the existing test circuits cannot automatically adjust the test environment temperature of the chip and perform automatic testing after adjustment. Therefore, a chip response test circuit is needed, which can automatically perform subsequent tests on the chip after the tester gives the initial test signal, and obtain the optimal response time and operating temperature within the set temperature range based on the chip's response time and temperature curve during the test. Summary of the invention
[0003] In view of the above technical problems, the purpose of the present invention is to provide a chip response test circuit, including a temperature control unit and a test unit, characterized in that the temperature control unit and the test unit are connected, the temperature control unit is used to set the highest / lowest temperature range of the chip's extreme working and adjust the test environment temperature of the chip based on the signal feedback of the test unit, and the test unit is used to feedback the temperature adjustment signal of the temperature control unit after the first test of the chip is completed, and to obtain the optimal response time and operating temperature of the chip based on the response time and temperature curve of the chip during the test and feed back to the terminal.
[0004] Further, the test unit includes a first resistor R1, a third resistor R3, a seventh resistor R7, a thirtieth resistor R30, a thirty-first resistor R31, an eighth operational amplifier U8, a first MOS tube Q1, a second MOS tube Q2, a first capacitor C1, and a first connector P1. One end of the third resistor R3 and one end of the thirtieth resistor R30 are connected to the power supply, the other end of the third resistor R3 is connected to one end of the first resistor R1 and the inverting end of the eighth operational amplifier U8, the drain of the first MOS tube Q1 is connected to the other end of the thirtieth resistor R30 and one end of the thirty-first resistor R31, the gate of the first MOS tube Q1 is connected to the gate of the second MOS tube Q2 and the first connector P1, the source of the first MOS tube Q1 and the source of the second MOS tube Q2 are connected to one end of the first capacitor C1, the drain of the second MOS tube Q2 is connected to one end of the seventh resistor R7 and the in-phase end of the eighth operational amplifier U8, and the other end of the first resistor R1, the other end of the seventh resistor R7, the other end of the thirty-first resistor R31, and the other end of the first capacitor C1 are connected to the ground end.
[0005] Furthermore, the test unit also includes a second resistor R2, a fourth resistor R4, a fifteenth resistor R15, a twentieth resistor R20, a second trigger U2, a ninth operational amplifier U9, a fourth MOS tube Q4, a third capacitor C3, a second diode D2, a fourth diode D4, and a second connector P2, wherein the anode of the second diode D2 is connected to the second connector P2, the cathode of the second diode D2 is connected to one end of the second resistor R2, the output end of the eighth operational amplifier U8, and the third pin of the second trigger U2 are connected, the first pin of the second trigger U2 is connected to the power supply, the second pin of the second trigger U2 is connected to the sixth pin of the second trigger U2, and the fourth pin of the second trigger U2 is connected to the fourth resistor R4. The first terminal of the second trigger U2 is connected, the fifth pin of the second trigger U2 and one end of the fifteenth resistor R15 are connected to the in-phase terminal of the ninth operational amplifier U9, the inverting terminal of the ninth operational amplifier U9 is connected to the inverting terminal of the eighth operational amplifier U8, the output terminal of the ninth operational amplifier U9 is connected to one end of the twentieth resistor R20 and the anode of the fourth diode D4, the cathode of the fourth diode D4 is connected to one end of the third capacitor C3 and the drain of the fourth MOS tube Q4, the gate of the fourth MOS tube Q4 is connected to the gate of the second MOS tube Q2, the other end of the second resistor R2, the other end of the fourth resistor R4, the other end of the fifteenth resistor R15, the other end of the twentieth resistor R20, the other end of the third capacitor C3, the source of the fourth MOS tube Q4 and the ground terminal are connected.
[0006] Furthermore, the test unit also includes a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a seventeenth resistor R17, an eighteenth resistor R18, a nineteenth resistor R19, a third operational amplifier U3, and a fourth operational amplifier U4, wherein one end of the ninth resistor R9 is connected to the power supply, the other end of the ninth resistor R9 is connected to one end of the eleventh resistor R11 and one end of the twelfth resistor R12, the other end of the eleventh resistor R11 is connected to one end of the tenth resistor R10 and the in-phase end of the third operational amplifier U3, and the third The output end of the operational amplifier U3 is connected to one end of the seventeenth resistor R17, the other end of the seventeenth resistor R17 is connected to one end of the eighteenth resistor R18 and the inverting end of the third operational amplifier U3, the other end of the eighteenth resistor R18 is connected to one end of the nineteenth resistor R19 and the output end of the fourth operational amplifier U4, the other end of the nineteenth resistor R19 is connected to the inverting end of the fourth operational amplifier U4, the non-inverting end of the fourth operational amplifier U4 is connected to the drain of the fourth MOS tube Q4, and the other end of the tenth resistor R10, the other end of the twelfth resistor R12 and the ground end are connected.
[0007] Furthermore, the test unit also includes a fifth resistor R5, a sixth resistor R6, a thirteenth resistor R13, a fourteenth resistor R14, a sixteenth resistor R16, a first operational amplifier U1, a sixth trigger U6, a third MOS tube Q3, a first diode D1, a third diode D3, and a second capacitor C2, wherein the anode of the first diode D1 is connected to the anode of the second diode D2, the cathode of the first diode D1 is connected to one end of the sixth resistor R6 and the third pin of the sixth trigger U6, the first pin of the sixth trigger U6 is connected to the power supply, the second pin of the sixth trigger U6 is connected to the sixth pin of the sixth trigger U6, the fourth pin of the sixth trigger U6 is connected to one end of the fifth resistor R5, the fifth pin of the sixth trigger U6 is connected to the fourteenth One end of the resistor R14 is connected to the non-inverting end of the first operational amplifier U1, the inverting end of the first operational amplifier U1 is connected to the inverting end of the ninth operational amplifier U9, the output end of the first operational amplifier U1 is connected to one end of the thirteenth resistor R13 and the gate of the third MOS tube Q3, the drain of the third MOS tube Q3 is connected to the output end of the third operational amplifier U3, the source of the third MOS tube Q3 is connected to one end of the sixteenth resistor R16 and the anode of the third diode D3, the cathode of the third diode D3 is connected to one end of the second capacitor C2, and the other end of the fifth resistor R5, the other end of the sixth resistor R6, the other end of the thirteenth resistor R13, the other end of the fourteenth resistor R14, the other end of the sixteenth resistor R16, the other end of the second capacitor C2 and the ground end are connected.
[0008] Further, the test unit also includes a twenty-first resistor R21, a twenty-second resistor R22, a twenty-third resistor R23, a twenty-fourth resistor R24, a twenty-fifth resistor R25, a seventh operational amplifier U7, a fifth MOS tube Q5, and a third connector P3, wherein one end of the twenty-fifth resistor R25 is connected to the gate of the fifth MOS tube Q5 and the third connector P3, the drain of the fifth MOS tube Q5 is connected to one end of the twenty-third resistor R23 and the output end of the seventh operational amplifier U7, the other end of the twenty-third resistor R23 is connected to one end of the twenty-fourth resistor R24 and the inverting end of the seventh operational amplifier U7, the other end of the twenty-fourth resistor R24 is connected to the cathode of the third diode D3, the in-phase end of the seventh operational amplifier U7 is connected to one end of the twenty-first resistor R21 and one end of the twenty-second resistor R22, the other end of the twenty-first resistor R21 is connected to one end of the twelfth resistor R12, the other end of the twenty-second resistor R22, the other end of the twenty-fifth resistor R25, the source of the fifth MOS tube Q5 and the ground end are connected.
[0009] Further, the test unit also includes a twenty-sixth resistor R26, a twenty-eighth resistor R28, a twenty-ninth resistor R29, a fifth operational amplifier U5, a sixth MOS tube Q6, a seventh MOS tube Q7, a fifth diode D5, and a fourth connector P4, one end of the twenty-sixth resistor R26 is connected to the output end of the fifth operational amplifier U5 and the drain of the sixth MOS tube Q6, the source of the sixth MOS tube Q6 is connected to one end of the twenty-eighth resistor R28 and the gate of the seventh MOS tube Q7, the gate of the sixth MOS tube Q6 is connected to the cathode of the fifth diode D5, the anode of the fifth diode D5 is connected to the anode of the first diode D1, the in-phase end of the fifth operational amplifier U5 is connected to the in-phase end of the fourth operational amplifier U4, the inverting end of the fifth operational amplifier U5 is connected to the drain of the fifth MOS tube Q5 and the drain of the seventh MOS tube Q7, the source of the seventh MOS tube Q7 is connected to one end of the twenty-ninth resistor R29 and the fourth connector P4, and the other end of the twenty-sixth resistor R26, the other end of the twenty-eighth resistor R28, and the other end of the twenty-ninth resistor R29 are connected to the ground end.
[0010] Furthermore, the test unit further includes an eighth resistor R8, one end of the eighth resistor R8 is connected to the gate of the fourth MOS tube Q4, and the other end of the eighth resistor R8 is connected to the ground.
[0011] Furthermore, the test unit further includes a twenty-seventh resistor R27, one end of the twenty-seventh resistor R27 is connected to the gate of the sixth MOS transistor Q6, and the other end of the twenty-seventh resistor R27 is connected to the ground.
[0012] The beneficial effects of the present invention compared with the prior art are: The present invention can automatically perform subsequent tests on the chip after the tester gives an initial test signal, and obtain the optimal response time and operating temperature of the chip to the terminal based on the response time and temperature curve of the chip during the test within a set temperature range. BRIEF DESCRIPTION OF THE DRAWINGS
[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the prior art and the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0014] Figure 1 The present invention provides an overall structural diagram.
[0015] Figure 2 This is a schematic diagram of the circuit structure of the test unit provided by the present invention. DETAILED DESCRIPTION
[0016] In order to make the objects and advantages of the present invention more clearly understood, the present invention is specifically described below in conjunction with embodiments. It should be understood that the following text is only used to describe one or several specific implementations of the present invention, and does not strictly limit the scope of protection specifically requested by the present invention.
[0017] The present invention discloses a chip response test circuit, comprising a temperature control unit and a test unit, wherein the temperature control unit and the test unit are connected, the temperature control unit is used to set the highest / lowest temperature range of the chip's extreme operation and adjust the test environment temperature of the chip based on the signal feedback of the test unit, and the test unit is used to feedback the temperature adjustment signal of the temperature control unit after the first test of the chip is completed and obtain the optimal response time and operating temperature of the chip based on the response time and temperature curve of the chip during the test and feed back to the terminal.
[0018] Specifically, the test unit includes a first resistor R1, a third resistor R3, a seventh resistor R7, a thirtieth resistor R30, a thirty-first resistor R31, an eighth operational amplifier U8, a first MOS tube Q1, a second MOS tube Q2, a first capacitor C1, and a first connector P1. One end of the third resistor R3 and one end of the thirtieth resistor R30 are connected to a power supply, the other end of the third resistor R3 is connected to one end of the first resistor R1 and an inverting end of the eighth operational amplifier U8, the drain of the first MOS tube Q1 is connected to the other end of the thirtieth resistor R30 and one end of the thirty-first resistor R31, the gate of the first MOS tube Q1 is connected to the gate of the second MOS tube Q2 and the first connector P1, the source of the first MOS tube Q1 and the source of the second MOS tube Q2 are connected to one end of the first capacitor C1, the drain of the second MOS tube Q2 is connected to one end of the seventh resistor R7 and the in-phase end of the eighth operational amplifier U8, and the other end of the first resistor R1, the other end of the seventh resistor R7, the other end of the thirty-first resistor R31, and the other end of the first capacitor C1 are connected to the ground end.
[0019] Specifically, the test unit also includes a second resistor R2, a fourth resistor R4, a fifteenth resistor R15, a twentieth resistor R20, a second trigger U2, a ninth operational amplifier U9, a fourth MOS tube Q4, a third capacitor C3, a second diode D2, a fourth diode D4, and a second connector P2, wherein the anode of the second diode D2 is connected to the second connector P2, the cathode of the second diode D2 is connected to one end of the second resistor R2, the output end of the eighth operational amplifier U8, and the third pin of the second trigger U2, the first pin of the second trigger U2 is connected to the power supply, the second pin of the second trigger U2 is connected to the sixth pin of the second trigger U2, and the fourth pin of the second trigger U2 is connected to the fourth resistor R4. The first terminal of the second trigger U2 is connected, the fifth pin of the second trigger U2 and one end of the fifteenth resistor R15 are connected to the in-phase terminal of the ninth operational amplifier U9, the inverting terminal of the ninth operational amplifier U9 is connected to the inverting terminal of the eighth operational amplifier U8, the output terminal of the ninth operational amplifier U9 is connected to one end of the twentieth resistor R20 and the anode of the fourth diode D4, the cathode of the fourth diode D4 is connected to one end of the third capacitor C3 and the drain of the fourth MOS tube Q4, the gate of the fourth MOS tube Q4 is connected to the gate of the second MOS tube Q2, the other end of the second resistor R2, the other end of the fourth resistor R4, the other end of the fifteenth resistor R15, the other end of the twentieth resistor R20, the other end of the third capacitor C3, the source of the fourth MOS tube Q4 and the ground terminal are connected.
[0020] Specifically, the test unit also includes a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a seventeenth resistor R17, an eighteenth resistor R18, a nineteenth resistor R19, a third operational amplifier U3, and a fourth operational amplifier U4, wherein one end of the ninth resistor R9 is connected to the power supply, the other end of the ninth resistor R9 is connected to one end of the eleventh resistor R11 and one end of the twelfth resistor R12, the other end of the eleventh resistor R11 is connected to one end of the tenth resistor R10 and the in-phase end of the third operational amplifier U3, and the third operational amplifier U4 is connected to the power supply. The output end of the operational amplifier U3 is connected to one end of the seventeenth resistor R17, the other end of the seventeenth resistor R17 is connected to one end of the eighteenth resistor R18 and the inverting end of the third operational amplifier U3, the other end of the eighteenth resistor R18 is connected to one end of the nineteenth resistor R19 and the output end of the fourth operational amplifier U4, the other end of the nineteenth resistor R19 is connected to the inverting end of the fourth operational amplifier U4, the non-inverting end of the fourth operational amplifier U4 is connected to the drain of the fourth MOS tube Q4, and the other end of the tenth resistor R10, the other end of the twelfth resistor R12 and the ground end are connected.
[0021] Specifically, the test unit also includes a fifth resistor R5, a sixth resistor R6, a thirteenth resistor R13, a fourteenth resistor R14, a sixteenth resistor R16, a first operational amplifier U1, a sixth trigger U6, a third MOS tube Q3, a first diode D1, a third diode D3, and a second capacitor C2, wherein the anode of the first diode D1 is connected to the anode of the second diode D2, the cathode of the first diode D1 is connected to one end of the sixth resistor R6 and the third pin of the sixth trigger U6, the first pin of the sixth trigger U6 is connected to the power supply, the second pin of the sixth trigger U6 is connected to the sixth pin of the sixth trigger U6, the fourth pin of the sixth trigger U6 is connected to one end of the fifth resistor R5, and the fifth pin of the sixth trigger U6 is connected to the fourteenth One end of the resistor R14 is connected to the non-inverting end of the first operational amplifier U1, the inverting end of the first operational amplifier U1 is connected to the inverting end of the ninth operational amplifier U9, the output end of the first operational amplifier U1 is connected to one end of the thirteenth resistor R13 and the gate of the third MOS tube Q3, the drain of the third MOS tube Q3 is connected to the output end of the third operational amplifier U3, the source of the third MOS tube Q3 is connected to one end of the sixteenth resistor R16 and the anode of the third diode D3, the cathode of the third diode D3 is connected to one end of the second capacitor C2, and the other end of the fifth resistor R5, the other end of the sixth resistor R6, the other end of the thirteenth resistor R13, the other end of the fourteenth resistor R14, the other end of the sixteenth resistor R16, the other end of the second capacitor C2 and the ground end are connected.
[0022] Specifically, the test unit also includes a twenty-first resistor R21, a twenty-second resistor R22, a twenty-third resistor R23, a twenty-fourth resistor R24, a twenty-fifth resistor R25, a seventh operational amplifier U7, a fifth MOS tube Q5, and a third connector P3, one end of the twenty-fifth resistor R25 is connected to the gate of the fifth MOS tube Q5 and the third connector P3, the drain of the fifth MOS tube Q5 is connected to one end of the twenty-third resistor R23 and the output end of the seventh operational amplifier U7, the other end of the twenty-third resistor R23 is connected to one end of the twenty-fourth resistor R24 and the inverting end of the seventh operational amplifier U7, the other end of the twenty-fourth resistor R24 is connected to the cathode of the third diode D3, the in-phase end of the seventh operational amplifier U7 is connected to one end of the twenty-first resistor R21 and one end of the twenty-second resistor R22, the other end of the twenty-first resistor R21 is connected to one end of the twelfth resistor R12, the other end of the twenty-second resistor R22, the other end of the twenty-fifth resistor R25, the source of the fifth MOS tube Q5 and the ground end are connected.
[0023] Specifically, the test unit also includes a twenty-sixth resistor R26, a twenty-eighth resistor R28, a twenty-ninth resistor R29, a fifth operational amplifier U5, a sixth MOS tube Q6, a seventh MOS tube Q7, a fifth diode D5, and a fourth connector P4. One end of the twenty-sixth resistor R26 is connected to the output end of the fifth operational amplifier U5 and the drain of the sixth MOS tube Q6. The source of the sixth MOS tube Q6 is connected to one end of the twenty-eighth resistor R28 and the gate of the seventh MOS tube Q7. The gate of the sixth MOS tube Q6 is connected to the cathode of the fifth diode D5. The anode of the fifth diode D5 is connected to the anode of the first diode D1. The in-phase end of the fifth operational amplifier U5 is connected to the in-phase end of the fourth operational amplifier U4. The inverting end of the fifth operational amplifier U5 is connected to the drain of the fifth MOS tube Q5 and the drain of the seventh MOS tube Q7. The source of the seventh MOS tube Q7 is connected to one end of the twenty-ninth resistor R29 and the fourth connector P4. The other end of the twenty-sixth resistor R26, the other end of the twenty-eighth resistor R28, and the other end of the twenty-ninth resistor R29 are connected to the ground end.
[0024] Specifically, the test unit further includes an eighth resistor R8, one end of the eighth resistor R8 is connected to the gate of the fourth MOS tube Q4, and the other end of the eighth resistor R8 is connected to the ground.
[0025] Specifically, the test unit further includes a twenty-seventh resistor R27, one end of the twenty-seventh resistor R27 is connected to the gate of the sixth MOS transistor Q6, and the other end of the twenty-seventh resistor R27 is connected to the ground.
[0026] See attached Figure 1 , Attachment Figure 2In this embodiment, the temperature control unit is connected to the test unit. The temperature control unit is used to set the highest / lowest temperature range for the extreme working of the chip and adjust the test environment temperature of the chip based on the signal feedback of the test unit. The test unit is used to feedback the temperature adjustment signal of the temperature control unit after the first test of the chip is completed and obtain its optimal response time and working temperature based on the response time and temperature curve of the chip during the test and feedback to the terminal. The highest / lowest temperature range for the extreme working of the chip is set on the temperature control unit. Before the test starts, the temperature control unit puts the chip at the highest or lowest working environment temperature. When the chip starts the responsiveness test, the initial test signal is generated by the test unit. According to personnel feedback, the test signal is fed back to the input pin of the chip and the test unit, and the test signal is fed back to the test unit through the first connector P1. When the chip obtains the initial test signal and completes the operation, the output pin of the chip will feedback the operation completion signal, and the completion signal is fed back to the test unit and the temperature control unit through the second connector P2. When the temperature control unit obtains a completion signal feedback, the temperature of the working environment of the chip is adjusted up / down. When the working environment temperature of the chip is adjusted, the temperature control unit feeds back the adjustment completion signal to the first connector P1 on the test unit, so that the test unit can automatically perform subsequent tests after the tester gives the initial test signal.
[0027] See attached Figure 1 , Attachment Figure 2In this embodiment, the test signal is fed back to the gate of the first MOS tube Q1 and the gate of the second MOS tube Q2 through the first connector P1. When the chip input pin obtains signal feedback, the voltage difference between the gate of the first MOS tube Q1 and the source of the first MOS tube Q1 is higher than the conduction threshold, the first MOS tube Q1 is turned on, the power supply signal passes through the 30th resistor R30 and the 31st resistor R31 to the ground end loop, the signal at the end of the 31st resistor R31 passes through the drain of the first MOS tube Q1 and the source of the first MOS tube Q1 and then is fed back to the source of the second MOS tube Q2, and at the same time the potential of the first capacitor C1 rises. When the chip input pin loses signal feedback, the voltage difference between the gate of the second MOS tube Q2 and the source of the second MOS tube Q2 is higher than the conduction threshold, the second MOS tube Q2 is turned on, the signal at the end of the first capacitor C1 passes through the source of the second MOS tube Q2, the drain of the second MOS tube Q2, and the seventh resistor R7 to the ground end loop, and at the same time the signal at the drain end of the second MOS tube Q2 is fed back to the in-phase end of the eighth operational amplifier U8, the power supply signal passes through the third resistor R3 and the first resistor R1 to the ground end loop, the first resistor The signal at the R1 end is fed back to the inverting end of the eighth operational amplifier U8 and output by the eighth operational amplifier U8. The signal at the output end of the eighth operational amplifier U8 is the test start signal of the chip. When the first connector P1 obtains signal feedback, the signal of the first connector P1 is synchronously fed back to the gate of the fourth MOS tube Q4. The eighth resistor R8 is used to discharge the parasitic capacitance of the gates of the first MOS tube Q1, the second MOS tube Q2 and the fourth MOS tube Q4. The voltage difference between the gate of the fourth MOS tube Q4 and the source of the fourth MOS tube Q4 is higher than the conduction threshold, and the fourth MOS tube Q4 is turned on. The signal at the third capacitor C3 end is looped through the drain of the fourth MOS tube Q4 and the source of the fourth MOS tube Q4 to the ground end, so that when the signal feedback is obtained at the first connector P1 end, the signal at the third capacitor C3 end is released. When the chip input pin obtains signal feedback, the recorded amplitude of the chip response time at the last test environment temperature is released. When the chip input pin loses signal feedback, the chip response test is performed on the chip at the current test environment temperature, so that the response time of the chip is tested in the set temperature range.
[0028] See attached Figure 1 , Attachment Figure 2In this embodiment, the power supply signal is fed back to the ground terminal loop through the fourth resistor R4, the signal at the fourth resistor R4 end is fed back to the pin 4 of the second trigger U2, the output terminal signal of the eighth operational amplifier U8 is fed back to the ground terminal loop through the second resistor R2, and the output terminal signal of the eighth operational amplifier U8 is fed back to the pin 3 of the second trigger U2. At this time, the pin 5 of the second trigger U2 is high level, and its signal is fed back to the in-phase terminal of the ninth operational amplifier U9, the signal at the first resistor R1 end is fed back to the inverting terminal of the ninth operational amplifier U9, the fifteenth resistor R15 is the pull-down resistor of the in-phase terminal of the ninth operational amplifier U9, the ninth operational amplifier U9 outputs, the output terminal signal of the ninth operational amplifier U9 is fed back to the ground terminal loop through the twentieth resistor R20, and the output terminal signal of the ninth operational amplifier U9 is fed back to the ground terminal loop through the fourth The diode D4 is fed back to the drain of the fourth MOS tube Q4, and the potential of the third capacitor C3 rises at the same time. The signal amplitude at the end of the third capacitor C3 is the chip response time amplitude of the current test environment temperature. The second connector P2 is used to obtain the completion signal fed back by the output pin of the chip. When the second connector P2 obtains the signal feedback, the signal is fed back to the pin 3 of the second trigger U2 after passing through the second diode D2. At this time, the 5th pin of the second trigger U2 is at a low level, the ninth operational amplifier U9 is cut off, and the potential of the third capacitor C3 stops rising. At the same time, the signal of the second connector P2 is fed back to the temperature control unit. When the temperature control unit obtains a completion signal feedback, the temperature of the working environment of the chip is adjusted up / down, so that when the chip completes a test, the chip test environment temperature is adjusted to perform the next test on it.
[0029] See attached Figure 1 , Attachment Figure 2In this embodiment, the signal at the end of the third capacitor C3 is fed back to the in-phase end of the fourth operational amplifier U4, the inverting end of the fourth operational amplifier U4 is negatively feedback connected to the output end of the fourth operational amplifier U4 through the nineteenth resistor R19, the output end signal of the fourth operational amplifier U4 is fed back to the inverting end of the third operational amplifier U3 after passing through the eighteenth resistor R18, the power supply signal passes through the ninth resistor R9 and the twelfth resistor R12 to the ground end loop, the signal amplitude at the end of the twelfth resistor R12 is any amplitude above the signal amplitude of the longest response time of the chip at the highest / lowest working environment temperature, the signal at the end of the twelfth resistor R12 passes through the eleventh resistor R11 and the tenth resistor R10 to the ground end loop, and the signal at the end of the tenth resistor R10 is fed back to the in-phase end of the third operational amplifier U3, At the same time, the output end of the third operational amplifier U3 is negatively feedback connected to the inverting end of the third operational amplifier U3 through the seventeenth resistor R17, so that the signal amplitude of the output end of the third operational amplifier U3 is the difference between the signal amplitude of the twelfth resistor R12 and the signal amplitude of the chip response time of the current test environment temperature. The power supply signal is looped to the ground end through the fifth resistor R5, and the signal at the fifth resistor R5 end is fed back to the pin 4 of the sixth trigger U6. The signal at the output end of the third operational amplifier U3 is fed back to the drain of the third MOS tube Q3. When the second connector P2 obtains the signal feedback, the signal is looped to the ground end through the first diode D1 and the sixth resistor R6, and the signal at the sixth resistor R6 end is fed back to the pin 3 of the sixth trigger U6. At this time, the pin 5 of the sixth trigger U6 is The first operational amplifier U1 is at a high level, and its signal is fed back to the in-phase terminal of the first operational amplifier U1. The fourteenth resistor R14 is a pull-down resistor at the in-phase terminal of the first operational amplifier U1. When the in-phase terminal of the first operational amplifier U1 obtains signal feedback, the first operational amplifier U1 outputs, and the output terminal signal of the first operational amplifier U1 is fed back to the gate of the third MOS tube Q3. The thirteenth resistor R13 is used to discharge the parasitic capacitance of the gate of the third MOS tube Q3. The voltage difference between the gate of the third MOS tube Q3 and the source of the third MOS tube Q3 is higher than the conduction threshold, and the third MOS tube Q3 is turned on. The output terminal signal of the third operational amplifier U3 causes the potential of the second capacitor C2 to rise after passing through the third diode D3. The signal at the second capacitor C2 is fed back to the seventh operational amplifier U7 through the twenty-fourth resistor R24 to reverse the phase. The output end of the seventh operational amplifier U7 is negatively feedback connected to the inverting end of the seventh operational amplifier U7 through the twenty-third resistor R23, the signal at the end of the twelfth resistor R12 is looped to the ground end through the twenty-first resistor R21 and the twenty-second resistor R22, and the signal at the end of the twenty-second resistor R22 is fed back to the in-phase end of the seventh operational amplifier U7. At this time, the output end signal of the seventh operational amplifier U7 is the response time amplitude during the period when the chip is in the highest / lowest working environment temperature and the chip input pin obtains the test signal and the operation is completed and the completion signal is fed back. When the working environment temperature of the chip is adjusted, the temperature control unit feeds back the adjustment completion signal to the first connector P1 on the test unit. At this time, the signal obtained at the end of the first connector P1 is the second test signal of the chip.When the first connector P1 obtains the test signal again, the ninth operational amplifier U9 outputs, the potential of the third capacitor C3 rises, the signal at the output end of the seventh operational amplifier U7 is fed back to the inverting end of the fifth operational amplifier U5, and the signal at the third capacitor C3 end is fed back to the non-inverting end of the fifth operational amplifier U5. When the working environment temperature of the chip is adjusted up / down from the highest / lowest working environment temperature of its extreme working, the responsiveness of the chip increases accordingly. During the second test, the signal amplitude at the third capacitor C3 end is lower than the signal amplitude at the third capacitor C3 end during the first test. When the chip is repeatedly tested to be in the fastest response time, the temperature control unit adjusts its working environment again. When the chip response time rises again after the test is performed again after the ambient temperature is reached, the fifth operational amplifier U5 outputs the completion signal, and the completion signal is fed back to the grounding loop via the second connector P2, the fifth diode D5, and the twenty-seventh resistor R27. The signal at the end of the twenty-seventh resistor R27 is fed back to the gate of the sixth MOS tube Q6. The voltage difference between the gate of the sixth MOS tube Q6 and the source of the sixth MOS tube Q6 is higher than the conduction threshold, and the sixth MOS tube Q6 is turned on. The signal at the output end of the fifth operational amplifier U5 is fed back to the grounding loop via the drain of the sixth MOS tube Q6, the source of the sixth MOS tube Q6, and the twenty-eighth resistor R28. The signal at the end of the twenty-eighth resistor R28 is fed back to the seventh MOS tube Q6. The voltage difference between the gate of the seventh MOS tube Q7, the gate of the seventh MOS tube Q7 and the source of the seventh MOS tube Q7 is higher than the conduction threshold, the seventh MOS tube Q7 is turned on, and the signal at the output end of the seventh operational amplifier U7 is looped to the ground end via the drain of the seventh MOS tube Q7, the source of the seventh MOS tube Q7, and the twenty-ninth resistor R29. The signal at the end of the twenty-ninth resistor R29 is fed back to the temperature control unit via the fourth connector P4. The signal at the end of the fourth connector P4 is the signal amplitude of the optimal response time of the chip. The signal at the end of the fourth connector P4 is fed back to the temperature control unit and the terminal. When the temperature control unit obtains the signal fed back by the fourth connector P4, it adjusts the temperature once and then feeds back its signal amplitude to Terminal, the reset signal is given by the tester, the reset signal is fed back to the third connector P3 on the test unit, the third connector P3 end signal is fed back to the gate of the fifth MOS tube Q5, the twenty-fifth resistor R25 is used to discharge the parasitic capacitance of the gate of the fifth MOS tube Q5, the voltage difference between the gate of the fifth MOS tube Q5 and the source of the fifth MOS tube Q5 is higher than the conduction threshold, and the output end signal of the seventh operational amplifier U7 is looped through the drain of the fifth MOS tube Q5 and the source of the fifth MOS tube Q5 to the ground end, so as to obtain the optimal response time and operating temperature of the chip based on the response time and temperature curve during the test period within the set temperature range and feedback to the terminal. ,
[0030] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations within the meaning and scope of the equivalent elements of the claims be included in the invention. Any marking in a claim should not be considered as limiting the claim to which it relates.
Claims
1. A chip response test circuit, comprising a temperature control unit and a test unit, characterized in that: The temperature control unit is connected to the test unit. The temperature control unit is used to set the highest / lowest temperature range for the chip's extreme operation and adjust the test environment temperature of the chip based on the signal feedback from the test unit. The test unit is used to feedback the temperature adjustment signal of the temperature control unit after the first test of the chip is completed and to obtain the optimal response time and operating temperature based on the chip's response time and temperature curve during the test and feed back to the terminal.
2. The chip response test circuit according to claim 1, characterized in that: The test unit includes a first resistor, a third resistor, a seventh resistor, a thirtieth resistor, a thirty-first resistor, an eighth operational amplifier, a first MOS tube, a second MOS tube, a first capacitor, and a first connector. One end of the third resistor and one end of the thirtieth resistor are connected to a power supply, the other end of the third resistor is connected to one end of the first resistor and an inverting end of the eighth operational amplifier, the drain of the first MOS tube is connected to the other end of the thirtieth resistor and one end of the thirty-first resistor, the gate of the first MOS tube is connected to the gate of the second MOS tube and the first connector, the source of the first MOS tube and the source of the second MOS tube are connected to one end of the first capacitor, the drain of the second MOS tube is connected to one end of the seventh resistor and the in-phase end of the eighth operational amplifier, and the other end of the first resistor, the other end of the seventh resistor, the other end of the thirty-first resistor, the other end of the first capacitor and the ground are connected.
3. The chip response test circuit according to claim 2, characterized in that: The test unit also includes a second resistor, a fourth resistor, a fifteenth resistor, a twentieth resistor, a second trigger, a ninth operational amplifier, a fourth MOS tube, a third capacitor, a second diode, a fourth diode, and a second connector, wherein the anode of the second diode is connected to the second connector, the cathode of the second diode is connected to one end of the second resistor, the output end of the eighth operational amplifier, and the third pin of the second trigger, the first pin of the second trigger is connected to the power supply, the second pin of the second trigger is connected to the sixth pin of the second trigger, the fourth pin of the second trigger is connected to one end of the fourth resistor, the fifth pin of the second trigger is connected to one end of the fifteenth resistor, the in-phase end of the ninth operational amplifier is connected, the inverting end of the ninth operational amplifier is connected to the inverting end of the eighth operational amplifier, the output end of the ninth operational amplifier is connected to one end of the twentieth resistor, the anode of the fourth diode is connected, the cathode of the fourth diode is connected to one end of the third capacitor, and the drain of the fourth MOS tube is connected, the gate of the fourth MOS tube is connected to the gate of the second MOS tube, and the other end of the second resistor, the other end of the fourth resistor, the other end of the fifteenth resistor, the other end of the twentieth resistor, the other end of the third capacitor, the source of the fourth MOS tube and the ground are connected.
4. The chip response test circuit according to claim 3, characterized in that: The test unit also includes a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, a third operational amplifier, and a fourth operational amplifier. One end of the ninth resistor is connected to a power supply, the other end of the ninth resistor is connected to one end of the eleventh resistor and one end of the twelfth resistor, the other end of the eleventh resistor is connected to one end of the tenth resistor and a non-inverting end of the third operational amplifier, the output end of the third operational amplifier is connected to one end of the seventeenth resistor, the other end of the seventeenth resistor is connected to one end of the eighteenth resistor and an inverting end of the third operational amplifier, the other end of the eighteenth resistor is connected to one end of the nineteenth resistor and the output end of the fourth operational amplifier, the other end of the nineteenth resistor is connected to the inverting end of the fourth operational amplifier, the non-inverting end of the fourth operational amplifier is connected to the drain of the fourth MOS tube, and the other end of the tenth resistor and the other end of the twelfth resistor are connected to the ground end.
5. The chip response test circuit according to claim 3, characterized in that: The test unit also includes a fifth resistor, a sixth resistor, a thirteenth resistor, a fourteenth resistor, a sixteenth resistor, a first operational amplifier, a sixth trigger, a third MOS tube, a first diode, a third diode, and a second capacitor. The anode of the first diode is connected to the anode of the second diode, the cathode of the first diode is connected to one end of the sixth resistor and the third pin of the sixth trigger, the first pin of the sixth trigger is connected to the power supply, the second pin of the sixth trigger is connected to the sixth pin of the sixth trigger, the fourth pin of the sixth trigger is connected to one end of the fifth resistor, the fifth pin of the sixth trigger is connected to one end of the fourteenth resistor and the in-phase end of the first operational amplifier, the inverting end of the first operational amplifier is connected to the inverting end of the ninth operational amplifier, the output end of the first operational amplifier is connected to one end of the thirteenth resistor and the gate of the third MOS tube, the drain of the third MOS tube is connected to the output end of the third operational amplifier, the source of the third MOS tube is connected to one end of the sixteenth resistor and the anode of the third diode, the cathode of the third diode is connected to one end of the second capacitor, and the other end of the fifth resistor, the other end of the sixth resistor, the other end of the thirteenth resistor, the other end of the fourteenth resistor, the other end of the sixteenth resistor, the other end of the second capacitor and the ground end are connected.
6. The chip response test circuit according to claim 4, characterized in that: The test unit also includes a twenty-first resistor, a twenty-second resistor, a twenty-third resistor, a twenty-fourth resistor, a twenty-fifth resistor, a seventh operational amplifier, a fifth MOS tube, and a third connector. One end of the twenty-fifth resistor is connected to the gate of the fifth MOS tube and the third connector, the drain of the fifth MOS tube is connected to one end of the twenty-third resistor and the output end of the seventh operational amplifier, the other end of the twenty-third resistor is connected to one end of the twenty-fourth resistor and the inverting end of the seventh operational amplifier, the other end of the twenty-fourth resistor is connected to the cathode of the third diode, the in-phase end of the seventh operational amplifier is connected to one end of the twenty-first resistor and one end of the twenty-second resistor, the other end of the twenty-first resistor is connected to one end of the twelfth resistor, the other end of the twenty-second resistor, the other end of the twenty-fifth resistor, the source of the fifth MOS tube and the ground end are connected.
7. The chip response test circuit according to claim 5, characterized in that: The test unit also includes a twenty-sixth resistor, a twenty-eighth resistor, a twenty-ninth resistor, a fifth operational amplifier, a sixth MOS tube, a seventh MOS tube, a fifth diode, and a fourth connector. One end of the twenty-sixth resistor is connected to the output end of the fifth operational amplifier and the drain of the sixth MOS tube. The source of the sixth MOS tube is connected to one end of the twenty-eighth resistor and the gate of the seventh MOS tube. The gate of the sixth MOS tube is connected to the cathode of the fifth diode. The anode of the fifth diode is connected to the anode of the first diode. The in-phase end of the fifth operational amplifier is connected to the in-phase end of the fourth operational amplifier. The inverting end of the fifth operational amplifier is connected to the drain of the fifth MOS tube and the drain of the seventh MOS tube. The source of the seventh MOS tube is connected to one end of the twenty-ninth resistor and the fourth connector. The other ends of the twenty-sixth resistor, the twenty-eighth resistor, and the twenty-ninth resistor are connected to the ground.
8. The chip response test circuit according to claim 3, characterized in that: The test unit further includes an eighth resistor, one end of the eighth resistor is connected to the gate of the fourth MOS tube, and the other end of the eighth resistor is connected to the ground end.
9. The chip response test circuit according to claim 7, characterized in that: The test unit also includes a twenty-seventh resistor, one end of the twenty-seventh resistor is connected to the gate of the sixth MOS tube, and the other end of the twenty-seventh resistor is connected to the ground end.