A multi-phase energy storage inverter parallel system and grid-side wiring detection method thereof

Abstract

The present invention discloses a multi-phase energy storage inverter parallel system and a grid-side wiring detection method thereof, wherein the system comprises a plurality of multi-phase energy storage inverters, one of which is a host and the rest are slaves; the grid-side wiring detection method comprises: the host and each slave respectively count the corresponding counters, and the host and each slave respectively detect the grid voltage of each phase; when the slave receives the detection signal sent by the host, it checks whether the value of the counter of its corresponding phase is within a preset range, if so, the wiring of the phase is correct; otherwise, the wiring of the phase is wrong; after the slave completes the wiring detection of all phases and the wiring is correct, the slave outputs a feedback signal; after the host receives the feedback signals of all slaves, it determines whether the effective value of the current grid voltage is within a normal range, and if so, controls the host and all slaves to be parallel and grid-connected. The present invention can accurately identify grid wiring errors when multiple multi-phase energy storage inverters are applied in parallel, and improve the safety of the energy storage system.

Description

Technical Field

[0001] The present invention relates to the technical field of energy storage systems, and in particular to a multi-phase energy storage inverter parallel system and a grid-side connection detection method thereof. Background Art

[0002] Split-phase energy storage systems and three-phase energy storage systems are common energy storage models; split-phase energy storage systems are often found in some foreign regions. They have two live wires (L1 and L2) and one neutral wire (N), and can provide two voltage levels (such as 120V and 240V). They are mainly used in residential and small commercial applications; three-phase energy storage systems are complete three-phase systems, including three live wires (L1, L2 and L3) and one neutral wire (N). The phase difference between each live wire is 120 degrees, which provides more stable and efficient power transmission and is suitable for industrial and large commercial facilities.

[0003] In order to meet the market demand for flexible expansion of energy storage inverters, the parallel connection technology of inverters came into being. In building an inverter parallel system, it is very important to ensure the correct grid connection sequence between the inverters, and it must strictly follow the principle of phase consistency. Take two split-phase energy storage inverters as an example: the L1 phases of the two inverters need to be connected to each other, and the same should be true for the L2 phase and the N line; any violation of this rule, such as mistakenly connecting the L1 phase of one inverter to the L2 phase of another inverter, when the system switches from off-grid mode to grid-connected operation, is equivalent to connecting the L1 phase and L2 phase of the grid together, which may cause a short circuit between the live wires of the grid, which will not only damage the equipment, but also endanger personal safety.

[0004] In the prior art, in order to avoid such incidents, a common method is to make clear restrictions on wiring in the user manual, including the color of the wire selection, etc., and to confirm with a multimeter or other measuring equipment after wiring. This method can well avoid the occurrence of mixed wiring of the power grid to a certain extent; however, in actual installation operations, due to differences in the actual installation conditions at the user end and the professional skills of the installation electrician, the problem of mixed wiring of the power grid cannot be completely eliminated. At the same time, the restrictions on wire color and the introduction of professional testing equipment also cause an increase in installation costs.

[0005] The disclosure of the above background technology content is only used to assist in understanding the concept and technical solution of the present invention. It does not necessarily belong to the prior art of this patent application. In the absence of clear evidence that the above content has been disclosed on the filing date of this patent application, the above background technology should not be used to evaluate the novelty and creativity of the present application. Summary of the invention

[0006] To solve the above technical problems, the present invention proposes a multi-phase energy storage inverter parallel system and a grid-side wiring detection method thereof, which can accurately identify grid wiring errors when multiple multi-phase energy storage inverters are used in parallel in a low-cost manner, thereby improving the safety of the energy storage system.

[0007] In order to achieve the above object, the present invention adopts the following technical solutions:

[0008] In a first aspect, the present invention discloses a grid-side wiring detection method for a multi-phase energy storage inverter parallel system, the system comprising a plurality of multi-phase energy storage inverters, one of which is a host and the rest are slaves; the host and the AC side of each of the slaves are connected in parallel to a power grid, and the host and each of the slaves are provided with a counter corresponding to each; each of the slaves is respectively connected to the host through a group of signal ports, the host provides each of the slaves with N output ports corresponding to each and 1 input port, and each of the slaves has N input ports corresponding to each and 1 output port, wherein N is the total number of phases; the grid-side wiring detection method comprises the following steps:

[0009] Step S1: the host and the corresponding counters in each of the slaves count respectively. When each counting cycle is reached, the value of the counter is incremented once. The host and the slaves detect the grid voltage of each phase respectively. When the grid voltage of any phase reaches a preset condition, the value of the corresponding counter is cleared;

[0010] Step S2: When the value of a phase counter of the host is reset to zero, a wiring detection is triggered, and a detection signal is sent to each of the slaves through the output port of the corresponding phase;

[0011] Step S3: When the slave receives the detection signal sent by the master, it checks whether the value of the counter of its corresponding phase is within a preset range. If yes, it means that the wiring of the phase is correct; if no, it means that the wiring of the phase is wrong;

[0012] Step S4: After the slave completes the wiring detection of all phases and the wiring is correct, the output port of the slave outputs a feedback signal;

[0013] Step S5: After receiving the feedback signals from all the slaves, the host determines whether the effective value of the current grid voltage is within a normal range. If so, all the hosts and slaves are controlled to operate in parallel and in grid connection.

[0014] Preferably, the preset condition in step S1 is that the grid voltage passes through zero.

[0015] Preferably, in step S1, the counting of the corresponding counters in the host and each slave respectively includes: when the value of each phase counter exceeds a first threshold, the value of the corresponding phase counter is cleared; the first threshold is within the range of 1.5 to 3 times the theoretical value of each phase counter, and the theoretical value of each phase counter is equal to the grid voltage period divided by the counting period.

[0016] Preferably, the signal ports of the host and each of the slaves are GPIO ports.

[0017] Preferably, sending a detection signal to each slave through the output port of the corresponding phase in step S2 includes: sending a detection signal to each slave through the output port of the corresponding phase adjusted to a high level; outputting a feedback signal from the output port of the slave in step S4 includes: adjusting the output port of the slave to a high level to output a feedback signal.

[0018] Preferably, before step S1, it also includes: judging in turn whether the corresponding output ports in the host and the output ports of each slave satisfy the high level for a counting cycles, if so, adjusting the corresponding output ports in the host and the output ports of each slave to a low level, and continuing to execute step S1; if not, directly continuing to execute step S1, where a takes the value of 2 or 3.

[0019] Preferably, the preset range in step S3 includes a value less than the second threshold or greater than the difference between the theoretical value of each phase counter and the second threshold, wherein the second threshold is greater than or equal to 3 and less than or equal to 10, and the theoretical value of each phase counter is equal to the grid voltage period divided by the counting period.

[0020] In a second aspect, the present invention discloses a multi-phase energy storage inverter parallel system, comprising a plurality of multi-phase energy storage inverters, one of which is a host and the rest are slaves; the host and the AC side of each of the slaves are connected in parallel to a power grid, and the host and each of the slaves are provided with a corresponding counter; each of the slaves is respectively connected to the host through a group of signal ports, and the host provides each of the slaves with N corresponding output ports and 1 input port, and each of the slaves has N corresponding input ports and 1 output port, wherein N is the total number of phases; wherein the host and each of the slaves are detected using the grid-side wiring detection method of the multi-phase energy storage inverter parallel system described in the first aspect.

[0021] Preferably, the signal ports of the host and each of the slaves are GPIO ports.

[0022] Preferably, the multi-phase energy storage inverter is a split-phase energy storage inverter.

[0023] Compared with the prior art, the present invention has the following beneficial effects:

[0024] According to the requirement that the phases of multiple multi-phase inverters must be consistent when they are connected in parallel and grid-connected, the present invention sets corresponding counters in each inverter and counts them respectively. Once the grid voltage reaches a preset condition, the value of the counter is cleared and the wiring detection is triggered at the same time. After receiving the detection signal of a certain phase sent by the host, the slave determines whether the value of the counter of the corresponding phase of the local machine matches the value of the counter of the corresponding phase of the host. If they match, it means that the wiring is correct.

[0025] By setting corresponding counters in each inverter and monitoring the grid voltage in real time, when the preset conditions are met, the counter value of the corresponding phase is cleared to ensure the timeliness and accuracy of monitoring; when the counter value of a phase of the host is cleared, the wiring detection is triggered immediately, and the detection signal is sent to the slave through a dedicated interface. This design realizes the automation of wiring detection and reduces the need for manual intervention; after receiving the detection signal, the slave automatically determines whether the counter value of the corresponding phase of the machine matches the counter value of the host. This method not only improves the detection accuracy, but also enhances the reliability of the system. Through the above technical means, it is only necessary to set the counter of each phase in each inverter and use a universal port for communication, so as to accurately identify wiring errors in parallel applications in a simple and low-cost way, thereby greatly improving the safety of the energy storage system. Compared with traditional methods, it does not need to rely on manual wire checking or special requirements such as wire color, which significantly reduces the installation cost and complexity. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 This is a flow chart of a grid-side connection detection method for a multi-phase energy storage inverter parallel system according to Embodiment 1 of the present invention;

[0027] Figure 2 It is a connection diagram of a multi-phase energy storage inverter parallel system in a specific example of the present invention. DETAILED DESCRIPTION

[0028] The following is a detailed description of the embodiments of the present invention. It should be emphasized that the following description is only exemplary and is not intended to limit the scope and application of the present invention.

[0029] It should be noted that when a component is referred to as being "fixed to" or "disposed on" another component, it can be directly on the other component or indirectly on the other component. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element. In addition, connection can be used for both fixing and circuit / signal communication.

[0030] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0031] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0032] Embodiment 1 of the present invention discloses a grid-side wiring detection method for a multi-phase energy storage inverter parallel system, wherein the system comprises a plurality of multi-phase energy storage inverters, one of which is a host and the rest are slaves; the AC side of the host and each slave is connected in parallel to a power grid, and the host and each slave are provided with a counter corresponding to each; each slave is respectively connected to the host through a group of signal ports, wherein the signal ports of the host and each slave are GPIO ports; the host provides each slave with N output ports corresponding to each and 1 input port, wherein each slave has N input ports corresponding to each and 1 output port, wherein N is the total number of phases; Figure 1 As shown, the grid-side wiring detection method includes the following steps:

[0033] Step S1: The corresponding counters in the host and each slave respectively count. When each counting cycle is reached, the value of the counter is incremented once. The host and each slave respectively detect the grid voltage of each phase. When the grid voltage of any phase reaches the preset condition, the value of the corresponding counter is cleared;

[0034] Before step S1, it also includes: judging in turn whether the corresponding output ports in the host and the output ports of the slaves meet the first preset level (such as a high level) for a counting cycle; if so, adjusting the corresponding output ports in the host and the output ports of the slaves to a second preset level (such as a low level), and continuing to execute step S1; if not, directly continuing to execute step S1, where a takes the value of 2 or 3.

[0035] In step S1, the corresponding counters in the host and each slave respectively count, including: when the value of each phase counter exceeds the first threshold, the value of the corresponding phase counter is cleared; the first threshold is within the range of 1.5 to 3 times the theoretical value of each phase counter, and the theoretical value of each phase counter is equal to the grid voltage period divided by the counting period. The preset conditions include grid voltage zero crossing, grid voltage peak value, etc., preferably grid voltage zero crossing.

[0036] Step S2: When the value of a phase counter of the host is reset to zero, the wiring detection is triggered, and a detection signal is sent to each slave through the output port of the corresponding phase;

[0037] Wherein, sending the detection signal to each slave through the output port of the corresponding phase includes: sending the detection signal to each slave through the output port of the corresponding phase adjusted to a first preset level (such as a high level);

[0038] Step S3: When the slave receives the detection signal sent by the master, it checks whether the value of the counter of its corresponding phase is within the preset range. If yes, it means that the wiring of the phase is correct; if no, it means that the wiring of the phase is wrong;

[0039] Theoretically, when the host and each slave are correctly connected to the grid, the grid voltage detected by the host and each slave should be synchronized for the same phase. However, taking into account communication delays and other possible errors, the preset range in this step S3 includes a value less than the second threshold or greater than the difference between the theoretical value of each phase counter and the second threshold, wherein the second threshold is greater than or equal to 3 and less than or equal to 10, and the theoretical value of each phase counter is equal to the grid voltage period divided by the counting period.

[0040] Step S4: After the slave completes the wiring detection of all phases and the wiring is correct, the output port of the slave outputs a feedback signal;

[0041] The output port of the slave machine outputs the feedback signal, which includes: the output port of the slave machine is adjusted to a first preset level (such as a high level) to output the feedback signal.

[0042] Step S5: After receiving the feedback signals from all slaves, the host determines whether the effective value of the current grid voltage is within the normal range. If so, the host is controlled to operate in parallel with all slaves and in parallel with the grid.

[0043] Embodiment 2 of the present invention discloses a multi-phase energy storage inverter parallel system, including multiple multi-phase energy storage inverters, one of which is a host and the rest are slaves; the AC side of the host and each slave is connected to the power grid in parallel, and the host and each slave are provided with a counter corresponding to each; each slave is connected to the host through a set of signal ports, and the host provides each slave with N output ports corresponding to each and 1 input port, and each slave has N input ports corresponding to each and 1 output port, where N is the total number of phases; wherein the host and each slave adopt the grid-side wiring detection method of the multi-phase energy storage inverter parallel system in embodiment 1 for detection. wherein the signal ports of the host and each slave are GPIO ports, and by using the GPIO port as the detection trigger signal of the multi-phase energy storage inverter and the algorithm for returning the result, compared with the communication circuit method, the implementation is simple and the cost is low.

[0044] In one embodiment, the multi-phase energy storage inverter is a split-phase energy storage inverter, and the number of the split-phase energy storage inverters is 2; in another embodiment, the multi-phase energy storage inverter is a three-phase energy storage inverter, and the number of the three-phase energy storage inverters is 2 or 3.

[0045] The following further describes the grid-side connection detection method of the multi-phase energy storage inverter parallel system in the first embodiment of the present invention and the multi-phase energy storage inverter parallel system in the second embodiment in combination with specific examples.

[0046] like Figure 2As shown, the energy storage system in this example includes two split-phase energy storage inverters ESS_1 and ESS_2, wherein the two split-phase energy storage inverters ESS_1 and ESS_2 are connected to the power grid respectively, a relay RY1 is provided between the split-phase energy storage inverter ESS_1 and the L1 phase Grid_L1 of the power grid, a relay RY2 is provided between the split-phase energy storage inverter ESS_1 and the N-end Grid_N of the power grid, and a relay RY3 is provided between the split-phase energy storage inverter ESS_1 and the L2 phase Grid_L2 of the power grid; a relay RY6 is provided between the split-phase energy storage inverter ESS_2 and the L1 phase Grid_L1 of the power grid, a relay RY5 is provided between the split-phase energy storage inverter ESS_2 and the N-end Grid_N of the power grid, and a relay RY4 is provided between the split-phase energy storage inverter ESS_2 and the L2 phase Grid_L2 of the power grid. Before the system has determined whether the grid-side wiring of each phase of each energy storage inverter is correct, the relays of each phase of each energy storage inverter are in a disconnected state. There is a master-slave relationship between the two split-phase energy storage inverters ESS_1 and ESS_2. In this example, the split-phase energy storage inverter ESS_1 is the master and the split-phase energy storage inverter ESS_2 is the slave. There are many principles for the allocation of the master and slave, such as the unique serial number SN code set when the energy storage inverter is produced. The two split-phase energy storage inverters ESS_1 and ESS_2 are both equipped with three GPIO ports. After the master and slave are allocated, the IO signals of the three GPIO ports of the master are Out1, Out2 and In3, respectively, and the IO signals of the three GPIO ports of the slave are In1, In2 and Out3, respectively, wherein In1 is connected to Out1 of the master, In2 is connected to Out2 of the host, and Out3 is connected to In3 of the host. The user load 10 is connected to the master, the slave and the power grid respectively.

[0047] The following specific example is to detect the grid-side connection of the first multi-phase energy storage inverter (master) and the second multi-phase energy storage inverter (slave) in the above energy storage system, including the following steps:

[0048] A1: Determine whether the counting period has been reached. If so, execute step A2; if not, do not call this algorithm step. For example, in one example, the counting period is 100 μs.

[0049] A2: The host determines whether the GPIO port with IO signal Out1 satisfies the high level for 3 counting cycles. If so, the GPIO port with IO signal Out1 in the host is controlled to be low level and continue to execute step A3. If not, directly execute step A3;

[0050] A3: The host determines whether the GPIO port with IO signal Out2 satisfies the high level for 3 counting cycles. If so, the GPIO port with IO signal Out2 in the host is controlled to be low level and continue to execute step A4. If not, directly execute step A4;

[0051] A4: The slave determines whether the GPIO port with IO signal Out3 satisfies the high level for 3 counting cycles. If so, the GPIO port with IO signal Out3 in the slave is controlled to be low level and continues to execute step A5. If not, directly execute step A5;

[0052] It should be noted that the detection of each signal output port of each inverter in steps A2 to A4 can be implemented synchronously, and there is no order of precedence; through the judgment and corresponding control in steps A2 to A4, sufficient time can be given to identify the high level in the subsequent step of detecting the zero crossing of the grid voltage, and by reading the signal, the recognition accuracy of the zero crossing detection of the grid voltage can be improved. In other embodiments, steps A2 to A4 can also be controlled to be "high level" at the beginning, and after the detection is triggered, the host sending port is set to "low level". Regardless of whether the host is set to a high level or a low level after the detection is triggered, the slave will receive a corresponding signal.

[0053] A5: The value of the L1 phase (L1-N) counter of the master or slave increases, where the value of the L1 phase (L1-N) counter increases by 1 each time starting from 0; it should be noted that this example limits the value of the L1 phase (L1-N) counter, and the limit value of one example is 400. When the value of the L1 phase (L1-N) counter is greater than 400, the value of the L1 phase (L1-N) counter is cleared. The next step is to execute step A6;

[0054] The limit value of the value taken in this example is determined based on the theoretical value of the L1-N counter. The theoretical value of the L1-N counter is equal to the grid voltage cycle divided by the counting cycle. In this example, the host frequency is 50Hz, the grid voltage cycle is 1 / 50Hz, and the counting cycle is 100μs. It can be calculated that the theoretical value of the L1-N counter is equal to 200. It is more appropriate to take the limit value as 1.5-3 times the theoretical value of the L1-N counter. In this example, the limit value is 2 times the theoretical value of the L1-N counter.

[0055] By processing the value of the L1-N counter as a limit value, the problem of data crossing the boundary caused by the unlimited increment of the value of the L1-N counter is avoided.

[0056] A6: The host or slave determines whether the L1-N grid voltage is zero-crossing. If yes, execute step A7; if no, execute step A8;

[0057] Among them, in some instances, determining whether the L1-N grid voltage is zero-crossing includes: determining whether the L1-N grid voltage is positively zero-crossing, or determining whether the L1-N grid voltage is negatively zero-crossing. In some embodiments, determining whether the L1-N grid voltage is zero-crossing specifically includes: collecting the L1-N grid voltage signal, determining whether the L1-N grid voltage sampling value satisfies that the previous counting cycle is positive and the current sampling value is negative, if so, the L1-N grid voltage is negatively zero-crossing, otherwise the L1-N grid voltage does not negatively zero-crossing. In other instances, determining whether the L1-N grid voltage is zero-crossing specifically includes: collecting the L1-N grid voltage signal, determining whether the L1-N grid voltage sampling value satisfies that the previous counting cycle is negative and the current sampling value is positive, if so, the L1-N grid voltage is positively zero-crossing, otherwise the L1-N grid voltage does not positively zero-crossing.

[0058] A7: The value of the L1-N counter of the master or slave is cleared. In addition, when the value of the L1-N counter of the master is cleared, the master sets the "slave L1-N wiring detection flag" and the next step is to execute step A8.

[0059] Among them, the host sets the "slave L1-N wiring detection flag", which means that the L1-N wiring detection step is triggered, and the detection can be started later.

[0060] A8: The value of the L2 phase (L2-N) counter of the master or slave increases, where the value of the L2 phase (L2-N) counter increases by 1 each time starting from 0; it should be noted that this example limits the value of the L2 phase (L2-N) counter, and the limit value of one example is 400. When the value of the L2 phase (L2-N) counter is greater than 400, the value of the L2 phase (L2-N) counter is cleared. The next step is to execute step A9;

[0061] The limit value of the value taken in this example is determined based on the theoretical value of the L2-N counter. The theoretical value of the L2-N counter is equal to the grid voltage cycle divided by the counting cycle. In this example, the host frequency is 50Hz, the grid voltage cycle is 1 / 50Hz, and the counting cycle is 100μs. It can be calculated that the theoretical value of the L2-N counter is equal to 200. It is more appropriate to take the limit value as 1.5-3 times the theoretical value of the L2-N counter. In this example, the limit value is 2 times the theoretical value of the L2-N counter.

[0062] By processing the value of the L2-N counter as a limit value, the problem of data crossing the boundary caused by the wireless increment of the value of the L2-N counter is avoided.

[0063] A9: The host or slave determines whether the L2-N grid voltage is zero-crossing. If yes, execute step A10; if no, execute step A11;

[0064] Wherein, in some instances, determining whether the L2-N grid voltage is zero-crossing specifically includes: determining whether the L2-N grid voltage is positively zero-crossing, or determining whether the L2-N grid voltage is negatively zero-crossing. In some embodiments, determining whether the L2-N grid voltage is zero-crossing specifically includes: collecting the L2-N grid voltage signal, determining whether the L2-N grid voltage sampling value satisfies that the previous counting cycle is positive and the current sampling value is negative, if so, the L2-N grid voltage is positively zero-crossing, otherwise the L2-N grid voltage does not have a positive zero-crossing. In other instances, determining whether the L2-N grid voltage is zero-crossing specifically includes: collecting the L2-N grid voltage signal, determining whether the L2-N grid voltage sampling value satisfies that the previous counting cycle is negative and the current sampling value is positive, if so, the L2-N grid voltage is negatively zero-crossing, otherwise the L2-N grid voltage does not have a negative zero-crossing. Compared with negative zero-crossing, positive zero-crossing is more preferred.

[0065] A10: The value of the L2-N counter of the master or slave is cleared. In addition, when the value of the L2-N counter of the master is cleared, the master sets the "slave L2-N wiring detection flag" and the next step is to execute step A11.

[0066] Among them, the host sets the "slave L2-N wiring detection flag", which means that the L2-N wiring detection step is triggered, and the detection can be started later.

[0067] Among them, the above steps A5 to A7 are for counting the counter of the L1 phase (L1-N) of each energy storage inverter and determining whether to trigger the L1-N wiring detection, and steps A8 to A10 are for counting the counter of the L2 phase (L2-N) of each energy storage inverter and determining whether to trigger the L2-N wiring detection. It should be noted that the process steps of steps A5 to A7 and the process steps of steps A8 to A10 are implemented simultaneously, and there is no order of precedence.

[0068] A11: Determine whether the current host is the host. If so, execute step A12; if not, execute step A16.

[0069] The function of this step is to assign different tasks to the master and the slave respectively. The master executes the subsequent steps A12 to A15, and the slave executes the subsequent steps A16 to A24.

[0070] A12: Determine whether the "slave L1-N wiring detection flag" is set. If so, execute step A13; if not, execute step A14.

[0071] A13: Control the GPIO port of the IO signal Out1 in the host to be high level, and clear the "slave L1-N wiring detection flag", and then execute step A14.

[0072] A14: Determine whether the "slave L2-N wiring detection flag" is set. If so, execute step A15; if not, execute step A16.

[0073] A15: Control the GPIO port of the IO signal Out2 in the host to be high level, and clear the "slave L2-N wiring detection flag", and then execute step A16.

[0074] Among them, the above steps A12 to A13 are the host's adjustment steps for the GPIO port with IO signal Out1, and the above steps A14 to A15 are the host's adjustment steps for the GPIO port with IO signal Out2. Similarly, steps A12 to A13 and steps A14 to A15 can be implemented simultaneously.

[0075] A16: Determine whether the GPIO port whose IO signal is In1 in the slave is at a high level. If yes, execute step A17; if not, execute step A20.

[0076] A17: Calculate the "theoretical value of the L1-N counter" within a grid voltage cycle, specifically "theoretical value of the L1-N counter" = grid voltage cycle / counting cycle = 1 / (f_Master * 100μs), "theoretical value of the L1-N counter" is recorded as T_CheckCnt, f_Master is the host frequency. Among them, in one example, f_Master is 50Hz, then T_CheckCnt is 200. In other examples, the value of f_Master will vary depending on the model. For example, the United States defaults to 60Hz, and Japan can send it to each energy storage system through mobile phone APP and other methods according to regional differences. The next step is to execute step A18.

[0077] A18: Determine whether the slave L1-N counter satisfies less than b or greater than T_CheckCnt - b, where the value of b is related to the IO effectiveness rate and the counting cycle, for example, the value of b is [3, 10], and the value of b in this example is 5; if yes, execute step A19; if no, execute step A20.

[0078] A19: Set the "slave L1-N detection completion flag" and execute step A20.

[0079] Among them, the host sets the "slave L1-N detection completion flag", which means that the detection shows that the L1 phase wiring is correct.

[0080] A20: Determine whether the GPIO port whose IO signal is In2 ​​in the slave is at a high level. If yes, execute step A21; if not, execute step A24.

[0081] A21: Calculate the "theoretical value of the L2-N counter" within a grid voltage cycle, specifically "theoretical value of the L2-N counter" = grid voltage cycle / counting cycle = 1 / (f_Master * 100μs), "theoretical value of the L2-N counter" is recorded as T_CheckCnt, f_Master is the host frequency. Among them, in one example, f_Master is 50Hz, then T_CheckCnt is 200. In other examples, the value of f_Master will vary depending on the model. For example, the United States defaults to 60Hz, and Japan can send it to each energy storage system through mobile phone APP and other methods according to regional differences. The next step is to execute step A22.

[0082] A22: Determine whether the slave L2-N connection counter satisfies less than b or greater than T_CheckCnt - b, where the value of b is related to the IO effectiveness rate and the counting cycle, for example, the value of b is [3, 10], and the value of b in this example is 5; if yes, execute step A23; if no, execute step A24.

[0083] A23: Set the "slave L2-N detection completion flag" and execute step A24.

[0084] Among them, the host sets the "slave L2-N detection completion flag", which means that the detection shows that the L2 phase wiring is correct.

[0085] Among them, the above steps A16 to A19 are steps for judging whether the L1 phase connection is correct, and steps A20 to A23 are steps for judging whether the L2 phase connection is correct. Similarly, steps A16 to A19 and steps A20 to A23 can be implemented simultaneously.

[0086] A24: Determine whether the "slave L1-N detection completion flag" and the "slave L2-N detection completion flag" are both set. If yes, execute step A25. If not, it indicates that the wiring does not meet the parallel wiring requirements of the two systems, and the invention algorithm step ends this call.

[0087] A25: Control the GPIO port of the slave machine whose IO signal is Out3 to be high level, and clear the "slave machine L1-N detection completion flag" and "slave machine L2-N detection completion flag" at the same time, and then execute step A26.

[0088] A26: Determine whether the current grid voltage effective value is within the normal range. If yes, execute step A27; if not, it indicates that the system grid connection requirements are not met, and the inventive algorithm step ends this call.

[0089] Among them, the standard for judging whether the current grid voltage is normal can be based on the overvoltage and undervoltage standards used in the national grid connection certification.

[0090] A27: Determine whether the GPIO port whose IO signal is In3 in the host is at a high level. If yes, execute step A28; if not, execute step A29.

[0091] A28: Execute normal grid-connected logic.

[0092] A29: If the GPIO port with IO signal In3 in the host is at a low level and lasts for 5 seconds, the grid wiring error is set, the parallel system is not allowed to run in parallel, and it is displayed externally through the APP.

[0093] From the above detailed description of the present invention, it can be seen that the present invention can accurately identify the grid connection problem of the split-phase energy storage system when it is connected in parallel; for example, when L1 of the energy storage inverter as the host is connected to L2 of the energy storage inverter as the slave, the present invention is applied. When the grid voltage sampling zero-crossing signal is detected at the host, the slave is notified by outputting an IO signal. At this time, the value of the slave L1-N connection detection counter is around 100 (taking the grid cycle of 50Hz and the counting cycle of 100μs as an example), which does not meet the condition of being less than 5 or greater than (T_CheckCnt-5), and the connection abnormality is accurately identified, thereby avoiding the occurrence of safety accidents.

[0094] In the above examples, the energy storage system includes two split-phase energy storage inverters as an example to illustrate the first and second embodiments. In other examples, the energy storage system of the second embodiment includes two three-phase energy storage inverters. Correspondingly, at this time, the host and the slave have four GPIO ports respectively. The four IO signal ports of the host are Out1, Out2, Out3 and In4 respectively. The four IO signal ports of the slave are In1 connected to the host Out1, In2 connected to the host Out2, In3 connected to the host Out3, and Out4 connected to the host In4. The first embodiment can also be applied to the grid-side wiring detection of two three-phase energy storage inverters. It only needs to perform one more corresponding step each time. Those skilled in the art will not repeat them here.

[0095] The multi-phase energy storage inverter parallel system and the grid-side wiring detection method thereof proposed in the present invention can accurately identify grid wiring errors when multiple multi-phase energy storage inverters are used in parallel, thereby improving the safety of the multi-phase energy storage inverter parallel system. Moreover, the process steps of the present invention realize automatic detection of grid-side wiring, eliminating manual wire checking and special requirements for wire color, etc., thereby improving intelligence and reducing installation costs. In addition, the GPIO port is used as the detection trigger signal of the multi-phase energy storage inverter and the algorithm for returning the results is simple to implement and low in cost compared to the communication circuit method.

[0096] Embodiment 3 of the present invention discloses a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to be executable by a processor to execute the steps of the grid-side connection detection method of the multi-phase energy storage inverter parallel system in the above-mentioned embodiment 1.

[0097] Optionally, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0098] The background section of the present invention may contain background information about the problem or environment of the present invention, rather than describing the prior art by others. Therefore, the content contained in the background section is not an admission by the applicant that the prior art is available.

[0099] The above content is a further detailed description of the present invention in combination with specific / preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, without departing from the concept of the present invention, it can also make several substitutions or modifications to these described embodiments, and these substitutions or modifications should be regarded as belonging to the protection scope of the present invention. In the description of this specification, the description of reference terms "an embodiment", "some embodiments", "preferred embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in combination with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily target the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, in the absence of mutual contradiction, the technical personnel in this field can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples. Although the embodiments of the present invention and their advantages have been described in detail, it should be understood that various changes, substitutions and modifications can be made herein without departing from the scope defined by the attached claims.

Claims

1. A grid-side connection detection method for a multi-phase energy storage inverter parallel system, characterized in that: The system includes a plurality of multi-phase energy storage inverters, one of which is a host and the rest are slaves; the AC side of the host and each of the slaves is connected to the power grid in parallel, and the host and each of the slaves are provided with a counter corresponding to each; each of the slaves is connected to the host through a group of signal ports respectively, and the signal ports of the host and each of the slaves are GPIO ports, and the host provides each of the slaves with N output ports corresponding to each and 1 input port, and each of the slaves has N input ports corresponding to each and 1 output port, wherein N is the total number of phases; the grid-side wiring detection method includes the following steps: Step S1: the host and the corresponding counters in each of the slaves count respectively. When each counting cycle is reached, the value of the counter is incremented once. The host and the slaves detect the grid voltage of each phase respectively. When the grid voltage of any phase reaches a preset condition, the value of the corresponding counter is cleared; Step S2: When the value of a phase counter of the host is reset to zero, a wiring detection is triggered, and a detection signal is sent to each of the slaves through the output port of the corresponding phase; Step S3: When the slave receives the detection signal sent by the master, it checks whether the value of the counter of its corresponding phase is within a preset range. If yes, it means that the wiring of the phase is correct; if no, it means that the wiring of the phase is wrong; Step S4: After the slave completes the wiring detection of all phases and the wiring is correct, the output port of the slave outputs a feedback signal; Step S5: After receiving the feedback signals from all the slaves, the host determines whether the effective value of the current grid voltage is within a normal range. If so, the host is controlled to operate in parallel with all the slaves.

2. The method according to claim 1, characterized in that The preset condition in step S1 is that the grid voltage passes through zero.

3. The method according to claim 1, characterized in that In the step S1, the host and each of the slaves respectively count the corresponding counters, including: when the value of each phase counter exceeds a first threshold, the value of the corresponding phase counter is cleared; the first threshold is within the range of 1.5 to 3 times the theoretical value of each phase counter, and the theoretical value of each phase counter is equal to the grid voltage period divided by the counting period.

4. The method according to claim 1, characterized in that: In the step S2, sending a detection signal to each of the slaves through the output port of the corresponding phase includes: sending a detection signal to each slave through the output port of the corresponding phase adjusted to a high level; in the step S4, the output port of the slave outputs a feedback signal, including: the output port of the slave is adjusted to a high level to output a feedback signal.

5. The method according to claim 4, characterized in that Before step S1, the method further includes: Determine in turn whether the corresponding output ports in the host and the output ports of each slave satisfy the high level for a counting cycles. If so, adjust the corresponding output ports in the host and the output ports of the slave to a low level and continue to execute step S1; if not, directly continue to execute step S1, where a is 2 or 3.

6. The method according to claim 1, characterized in that The preset range in step S3 includes a value less than the second threshold or greater than the difference between the theoretical value of each phase counter and the second threshold, wherein the second threshold is greater than or equal to 3 and less than or equal to 10, and the theoretical value of each phase counter is equal to the grid voltage period divided by the counting period.

7. A multi-phase energy storage inverter parallel system, characterized in that: It comprises a plurality of multi-phase energy storage inverters, one of which is a host and the rest are slaves; the AC sides of the host and each of the slaves are connected in parallel to a power grid, and the host and each of the slaves are provided with corresponding counters; each of the slaves is respectively connected to the host through a group of signal ports, and the signal ports of the host and each of the slaves are GPIO ports, and the host provides each of the slaves with N corresponding output ports and 1 input port, and each of the slaves has N corresponding input ports and 1 output port, wherein N is the total number of phases; wherein the host and each of the slaves are detected by using the grid-side wiring detection method of the multi-phase energy storage inverter parallel system according to any one of claims 1 to 6.

8. The system according to claim 7, characterized in that The multi-phase energy storage inverter is a split-phase energy storage inverter.

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