A prefetch instruction conversion optimization method based on memory access mode virtualization

Abstract

The present invention discloses a prefetch instruction conversion optimization method based on memory access mode virtualization. When an executable file is executed in a dynamic instruction conversion mode, the address memory access mode of the prefetch instruction of the x86 architecture is obtained, and the operand and offset calculation method of the prefetch instruction are analyzed. According to the address memory access mode, the operand and the offset calculation method, an instruction or instruction sequence of the ARM architecture capable of completing the memory address calculation and prefetching functions is constructed. The prefetch instruction of the x86 architecture is replaced with a corresponding ARM instruction or instruction sequence to complete the dynamic conversion of the instruction, thereby realizing the conversion of the prefetch instruction of the complex address mode under the x86 architecture and improving the reliability of the execution of the executable file in the dynamic instruction conversion mode.

Description

Technical Field

[0001] The invention belongs to the technical field of computer software development, and in particular relates to a prefetch instruction conversion optimization method based on memory access mode virtualization. Background Art

[0002] In order to solve the problem of delay in reading or writing data from memory to register, existing processors provide a data prefetch mechanism, which can load data from memory to cache in advance, so that it can be retrieved faster when the data is actually used later, thus reducing waiting time. The x86 architecture provides the following prefetch instructions, such as PREFETCHT0, PREFETCHT1, PREFETCHT2, PREFETCHNTA, etc. These instructions are mainly prefetch instructions related to data reading, rather than write prefetch instructions. The ARM architecture provides both data prefetch instructions and write prefetch instructions.

[0003] The prefetch instructions provided by the existing x86 architecture can support multiple address access modes, while the prefetch instructions provided by the ARM architecture can only support the address access mode of the simple address mode, that is, the operand of the prefetch instruction is the memory address of the memory area to be prefetched. For the address access mode that determines the final memory address through different calculation methods, that is, the complex address mode includes indirect address mode, index address mode, base address mode and relative address mode, the prefetch instructions provided by the ARM architecture cannot support it. Therefore, when executing x86 architecture software on the ARM platform, the problem of some instructions not being able to be converted will occur when performing dynamic instruction conversion on the prefetch instructions. Summary of the invention

[0004] In view of this, the present invention provides a prefetch instruction conversion optimization method based on memory access mode virtualization, which determines the corresponding ARM architecture instruction or instruction sequence by analyzing the address memory access mode, operand and offset calculation method of the prefetch instruction of the x86 architecture, and realizes the conversion of complex address mode prefetch instructions under the x86 architecture.

[0005] The present invention provides a prefetch instruction conversion optimization method based on memory access mode virtualization, which specifically includes the following steps:

[0006] Step 1, load and execute the executable file through dynamic instruction conversion, if the current instruction to be converted is a prefetch instruction of the x86 architecture, execute step 2, otherwise, convert the current instruction to be converted into an ARM instruction and then execute step 7;

[0007] Step 2, reverse the current instruction to be converted to obtain the address access mode it adopts, if the address access mode is a simple address mode, execute step 3, if the address access mode is a base address index mode, execute step 4, if the address access mode is a composite address mode, execute step 5, if the address access mode is a segment register related mode, execute step 6;

[0008] Step 3, record the register in the operand as the first register, select a register in the ARM that stores the memory address in the first register as the first ARM register, construct a first ARM prefetch instruction with the first ARM register as the operand, convert the current instruction to be converted into the first ARM prefetch instruction, and execute step 7;

[0009] Step 4, obtaining the base address register, the offset register and the offset calculation method in the operand, recording the register storing the base address as the first ARM register in ARM, recording the register storing the offset as the second ARM register, recording the register storing the memory address as the third ARM register, determining the logical operator according to the offset calculation method, constructing a first ARM load instruction to load the sum of the result processed by the second ARM register through the logical operator and the first ARM register into the third ARM register, constructing a first ARM prefetch instruction with the third ARM register as the operand; converting the current instruction to be converted into an instruction sequence formed by the first ARM load instruction and the first ARM prefetch instruction, and executing step 7;

[0010] Step 5, obtain N registers, M constants and offset calculation methods in the operands, assign one-to-one corresponding ARM registers to the N registers, and record the register that stores the memory address as the target ARM register; determine the corresponding calculation instruction and logical operator according to the offset calculation method, construct an address calculation instruction sequence composed of multiple calculation instructions, logical operators and immediate numbers to calculate the memory address, save the memory address to the target ARM register, and construct a first ARM prefetch instruction with the target ARM register as the operand; convert the current instruction to be converted into an instruction sequence formed by the address calculation instruction sequence and the first ARM prefetch instruction, and execute step 7;

[0011] Step 6, delineate the simulation segment memory area in the ARM architecture, establish a first mapping relationship between the simulation segment memory area and the segment register of the x86 architecture; obtain the current segment register and the offset register in the operand, determine the simulation segment memory area corresponding to the current segment register according to the first mapping relationship, obtain the segment base address of the simulation segment memory area, record the register storing the segment base address as the first ARM register; record the register storing the offset as the second ARM register, record the register storing the memory address as the target ARM register, construct an addition instruction that stores the sum of the addresses in the first ARM register and the second ARM register in the target ARM register, and construct a first ARM prefetch instruction with the target ARM register as the operand; convert the current instruction to be converted into an instruction sequence formed by the addition instruction and the first ARM prefetch instruction, and execute step 7;

[0012] Step 7: If the executable file has not been executed, select the next instruction to execute step 2; otherwise, complete the execution of the executable file and end this process.

[0013] Furthermore, the method for determining the prefetch instruction of the x86 architecture in step 1 is: determining according to the operation code of the prefetch instruction of the x86 architecture.

[0014] Furthermore, the method of reversing the current instruction to be converted in step 2 to obtain the address access mode it adopts is: reversely analyze the current instruction to be converted to obtain the data structure of the operand, if the operand contains only one register, the address access mode is determined to be a simple address mode, if the operand contains two registers, the address access mode is determined to be a base address displacement mode, if the operand contains a register and a constant, the address access mode is determined to be a compound address mode, and if the operand contains a segment register, it is determined to be a segment register related mode.

[0015] Furthermore, the method of defining the simulation segment memory area in the ARM architecture in step 6 is: using software-defined definition.

[0016] Furthermore, before step 2, the current instruction to be converted is forward reverse analyzed by a set number of instructions to form a first instruction set. If there is a write operation on a memory address related to the current instruction to be converted in the first instruction set, the prefetch instruction in the first ARM prefetch instruction is a write prefetch instruction; otherwise, the prefetch instruction in the first ARM prefetch instruction is a read prefetch instruction.

[0017] Further, the write prefetch instruction is a PLDW instruction, and the read prefetch instruction is a PLD instruction.

[0018] Furthermore, the segment register is a code segment register CS, a data segment register DS or an additional segment register ES.

[0019] Furthermore, the first mapping relationship in step 6 is established by using a register mapping algorithm.

[0020] Furthermore, the register mapping algorithm includes a Tomasulo algorithm and a fully associative mapping algorithm.

[0021] Furthermore, the register mapping algorithm is a direct mapping algorithm. Beneficial Effects

[0022] When executing an executable file in a dynamic instruction conversion mode, the present invention obtains the address memory access mode of the prefetch instruction of the x86 architecture, and parses the operand and offset calculation method of the prefetch instruction, constructs an instruction or instruction sequence of the ARM architecture that can complete the memory address calculation and prefetch functions according to the address memory access mode, the operand and the offset calculation method, replaces the prefetch instruction of the x86 architecture with the corresponding ARM instruction or instruction sequence to complete the dynamic conversion of the instruction, realizes the conversion of the prefetch instruction of the complex address mode under the x86 architecture, and improves the reliability of the execution of the executable file in the dynamic instruction conversion mode. DETAILED DESCRIPTION

[0023] The present invention is described in detail with reference to the following embodiments.

[0024] The present invention provides a prefetch instruction conversion optimization method based on memory access mode virtualization, the core idea of ​​which is: when executing an executable file in a dynamic instruction conversion mode, the address memory access mode of the prefetch instruction of the x86 architecture is obtained, and the operand and offset calculation method of the prefetch instruction are parsed, and an instruction or instruction sequence of the ARM architecture that can complete the memory address calculation and prefetching functions is constructed according to the address memory access mode, the operand and the offset calculation method, and the prefetch instruction of the x86 architecture is replaced by the corresponding ARM instruction or instruction sequence to complete the dynamic conversion of instructions.

[0025] The present invention provides a prefetch instruction conversion optimization method based on memory access mode virtualization, which specifically includes the following steps:

[0026] Step 1: Load and execute the executable file through dynamic instruction conversion. If the current instruction to be converted is a prefetch instruction of the x86 architecture, execute step 2; otherwise, convert the current instruction to be converted into an ARM instruction and then execute step 7.

[0027] The method for determining whether the current instruction to be converted is a prefetch instruction of the x86 architecture is to determine according to the opcode of the prefetch instruction of the x86 architecture, for example, the opcode of PREFETCHT0 is 0x08, the opcode of PREFETCHT1 is 0x09, and so on.

[0028] Step 2: Reverse the current instruction to be converted to obtain the address access mode it adopts. If the address access mode is a simple address mode, execute step 3; if the address access mode is a base address displacement mode, execute step 4; if the address access mode is a compound address mode, execute step 5; if the address access mode is a segment register related mode, execute step 6.

[0029] Among them, the method of reversing the current instruction to be converted to obtain the address access mode it adopts is: reversely analyze the current instruction to be converted to obtain the data structure of the operand, if the operand contains only one register, the address access mode is determined to be a simple address mode, if the operand contains two registers, the address access mode is determined to be a base address displacement mode, if the operand contains registers and constants, the address access mode is determined to be a compound address mode, if the operand contains a segment register, it is determined to be a segment register related mode.

[0030] Step 3: record the register in the operand as the first register, record the memory address saved in the first register as the first memory address, select a register in ARM that can save the first memory address, record it as the first ARM register, save the first memory address in the first ARM register, construct a first ARM prefetch instruction with the first ARM register as the operand, convert the current instruction to be converted into the first ARM prefetch instruction, and execute step 7.

[0031] Step 4, obtain the base address register, offset register and offset calculation method in the operand, in ARM, select a register that can save the base address as the first ARM register, select a register that can save the offset as the second ARM register, select a register that can save the memory address as the third ARM register, determine the logical operator according to the offset calculation method, construct a first ARM load instruction to load the result of the second ARM register processed by the logical operator and the sum of the first ARM register into the third ARM register, construct a first ARM prefetch instruction with the third ARM register as the operand; convert the current instruction to be converted into an instruction sequence formed by the first ARM load instruction and the first ARM prefetch instruction, and execute step 7.

[0032] Step 5, obtain N registers, M constants and offset calculation methods in the operands, select an ARM register corresponding to each register, select a register that can save the memory address as the target ARM register; determine the corresponding calculation instructions and logical operators according to the offset calculation method, construct an address calculation instruction sequence composed of multiple calculation instructions, logical operators and immediate numbers, simulate the calculation of N registers and M constants by the address calculation instruction sequence to obtain the memory address, and save the memory address to the target ARM register, and construct a first ARM prefetch instruction with the target ARM register as the operand; convert the current instruction to be converted into an instruction sequence formed by the address calculation instruction sequence and the first ARM prefetch instruction, and execute step 7.

[0033] Step 6. Use software definition to delineate multiple simulation segment memory areas in the ARM architecture, and establish a first mapping relationship between the simulation segment memory area and the segment register of the x86 architecture; obtain the current segment register and the offset register in the operand, determine the corresponding simulation segment memory area according to the first mapping relationship, obtain the segment base address of the simulation segment memory area, select a register that can save the segment base address as the first ARM register; select a register that can save the offset as the second ARM register, select a register that can save the memory address as the target ARM register, construct an addition instruction that saves the sum of the addresses in the first ARM register and the second ARM register to the target ARM register, and construct a first ARM prefetch instruction with the target ARM register as the operand; convert the current instruction to be converted into an instruction sequence formed by the addition instruction and the first ARM prefetch instruction, and execute step 7.

[0034] Step 7: If the executable file has not been executed, select the next instruction to execute step 2; otherwise, complete the execution of the executable file and end this process.

[0035] In order to further optimize the efficiency of instruction conversion, the present invention forward reversely analyzes a set number of instructions of the prefetch instruction of the x86 architecture, and forms a first instruction set from these instructions. If there is a write operation to the memory address related to the prefetch instruction in the first instruction set, the prefetch instruction is converted into a write prefetch instruction of ARM; otherwise, the prefetch instruction is converted into a read prefetch instruction of ARM. Example

[0036] In this embodiment, a prefetch instruction conversion optimization method based on memory access mode virtualization provided by the present invention is used to realize the conversion of the prefetch instruction of the x86 architecture to the prefetch instruction of the ARM architecture, including the following steps:

[0037] S1. In the process of executing an executable file in a dynamic instruction conversion mode, the following method is used to determine whether the current instruction to be converted is a prefetch instruction of the x86 architecture, specifically: if the opcode of the current instruction to be converted is 0x08, it is a PREFETCHT0 instruction; if the opcode of the current instruction to be converted is 0x09, it is a PREFETCHT1 instruction; if the opcode of the current instruction to be converted is 0x0A, it is a PREFETCHT2 instruction; if the opcode of the current instruction to be converted is 0x0B, it is a PREFETCHNTA instruction, etc.

[0038] S2. For the pre-fetch instructions of the x86 architecture, a set number of instructions are forward and reversed. If there is a write operation to the memory address related to the pre-fetch instruction among these instructions, then S4 is executed; otherwise, S3 is executed.

[0039] S3. Analyze the address access mode of the prefetch instruction of the x86 architecture, and execute different instruction conversion strategies according to the address access mode. The specific steps are as follows:

[0040] S3.1. When the address access mode is the simple address mode, that is, the PREFETCHT0 [esi] instruction of the x86 architecture, where esi is a 32-bit general register of the x86 architecture, also known as the source index register, it is converted into the PLD [r0] instruction of the ARM architecture, where r0 is a register of the ARM architecture.

[0041] Specifically, at this time, when the operand of the prefetch instruction of the x86 architecture is the memory address pointed to by the register, and there is a corresponding register in the ARM architecture that can save the memory address, the above method is directly used for conversion, including the following steps: assigning the memory address of the prefetch instruction of the x86 architecture to the register of the ARM architecture. In addition, the register used by the ARM architecture prefetch instruction can be determined by an existing more efficient register mapping algorithm, wherein the register mapping algorithm is such as the Tomasulo algorithm, fully associative mapping, etc. Furthermore, since the ARM processor has far more registers than the x86 registers, a simpler and more efficient direct mapping algorithm can also be used for determination.

[0042] S3.2. When the address access mode is the base-indexed mode, take the following x86 loop code as an example:

[0043] mov esi, offset array / / Assume array is the starting address of an array

[0044] mov ecx, count / / count is the number of array elements

[0045] loop_start:

[0046] PREFETCHT0 [esi + 4*ecx]

[0047] / / Other loop code

[0048] loop loop_start

[0049] In ARM this can be converted to:

[0050] ldr r0, =array / / Load the array starting address to r0

[0051] mov r1, #count

[0052] loop_start_ARM:

[0053] ldr r2, [r0, r1, lsl #2]

[0054] PLD [r2]

[0055] / / Other loop code

[0056] b loop_start_ARM

[0057] Among them, for the prefetch instruction in the loop, it is necessary to analyze the relationship between the loop variable and the prefetch memory address. In the above sample code, the prefetched memory address is [esi + 4*ecx], register esi is the base address register, and ecx is the offset register.

[0058] In the process of converting to ARM instructions, the array start address is first loaded into register r0, the loop variable count is loaded into register r1, the pre-fetched memory address is calculated through ldr r2, [r0, r1, lsl #2] and stored in register r2, and then PLD [r2] is used for pre-fetching. The key is to correctly calculate the memory address corresponding to the pre-fetch instruction and pass the memory address to the PLD instruction of the ARM architecture.

[0059] S3.3. When the address access mode is the composite address mode, the prefetch instruction of the x86 architecture is: PREFETCHT0[eax + ebx*4 + 10h]. First, the address calculation method of the x86 architecture is simulated in the ARM architecture. The following instruction sequence can be used to complete a similar calculation, as follows:

[0060] mov r2, r1, lsl #2 / / Shift the value of r1 (corresponding to ebx) to the left by 2 bits, which is equivalent to multiplying by 4, and store the result in r2, simulating ebx*4

[0061] add r2, r2, r0 / / Add r2 (the result of ebx*4) and r0 (corresponding to eax), at this time the value of r2 is eax +ebx*4

[0062] add r2, r2, #0x10 / / Add the immediate value 0x10 (corresponding to 10h) to r2. Now r2 stores the memory address calculated by eax + ebx*4 + 10h.

[0063] By generating the above instructions, the memory address calculation process in the composite address mode of the x86 architecture can be reproduced in the ARM architecture, and then the calculated memory address is stored in register r2.

[0064] Then, the prefetch instruction of the ARM architecture is generated: after the correct memory address is stored in register r2, the PLD instruction of the ARM architecture can be used to prefetch data, the instruction is: PLD [r2]. This instruction implements the prefetch operation of the data corresponding to the memory address previously obtained through complex calculations, and loads the data into the cache in advance to improve the performance of subsequent access to the data, thereby completing the conversion from the prefetch instruction of the x86 composite address mode to the ARM data prefetch instruction.

[0065] Since the PLD instruction of the ARM architecture requires a relatively simple memory address operand, the present invention first calculates the actual memory address obtained by the complex addressing calculation by generating an additional instruction sequence, temporarily stores it in an adapted register, and then uses the register as the operand of the PLD instruction to implement prefetching, which is equivalent to separating the complex memory address calculation process and the prefetching operation. In actual applications, it may also be necessary to perform appropriate adjustments and optimizations according to the specific program context, register usage, etc.

[0066] S3.4, when the address access mode is the segment register related mode, the prefetch instruction of the x86 architecture is: PREFETCHT0 [cs:eax]. First, the ARM architecture is divided into different memory areas through software definition to simulate the segment registers in the x86 architecture. For example, the area from memory address 0x10000 to 0x1FFFF is used to simulate the code segment corresponding to the code segment register CS of the x86 architecture, assuming that the segment base address of the code segment is 0x10000.

[0067] Then, get the offset address and perform address conversion calculation. In the generated ARM code, assuming that the value of register eax has been correctly transferred to register r0, the memory address of the final prefetched data is calculated through the following instructions:

[0068] ldr r1, =0x10000 / / Assume that the base address of the code segment is 0x10000, stored in register r1

[0069] add r2, r1, r0 / / Add the code segment base address (r1) and the offset address (r0), and store the result in register r2 to get the final memory address

[0070] Through the above calculation, the process of determining the memory address through the code segment register CS and the offset register eax in the x86 architecture is simulated, and the obtained memory address is saved in the register r2.

[0071] Finally, the prefetch instruction of the ARM architecture is generated, and the PLD instruction of the ARM architecture is used to perform data prefetching. The instruction is: PLD [r2], which implements the prefetch operation on the data corresponding to the memory address determined by the simulated segmented memory management, and loads the data into the cache in advance.

[0072] In addition, for other different segment registers, such as data segment register DS, additional segment register ES, etc., a similar method is used to define the corresponding simulation segment memory area in ARM, and then the segment base address of the corresponding simulation segment memory area is selected according to the specific segment register to participate in the address calculation, and then the PLD instruction is executed to prefetch data.

[0073] For example, for the x86 architecture prefetch instruction PREFETCHT0 [ds:ebx], assuming that the segment base address has been stored in register r3 and the value of register ebx has been transferred to register r4, then:

[0074] add r5, r3, r4 / / Calculate the final memory address and store it in register r5

[0075] PLD [r5]

[0076] In the x86 architecture, segmented memory management determines the physical memory address through segment registers, such as code segment register CS, data segment register DS, and additional segment register ES, in combination with the offset address. For example, instruction PREFETCHT0 [cs:eax] refers to determining the memory address of prefetched data based on the base address of the code segment plus the offset represented by register eax. However, the ARM architecture itself does not have a segmented memory management mechanism that completely corresponds to it, making it difficult to achieve direct conversion. Therefore, the present invention simulates the logic of segmented memory management at the software level, constructs a similar address mapping mechanism in the ARM architecture, and equivalently implements the functions corresponding to the segment registers through specific memory area division and address calculation rules, thereby completing the conversion of prefetch instructions involving segmented memory management.

[0077] S4. Analyze the address access mode of the prefetch instruction of the x86 architecture, and execute different instruction conversion strategies according to the address access mode. The specific steps are as follows:

[0078] S4.1. When the address access mode is the simple address mode, that is, the PREFETCHT0 [esi] instruction of the x86 architecture, where esi is a 32-bit general register of the x86 architecture, also known as the source index register, it is converted into the PLDW [r0] instruction of the ARM architecture, where r0 is a register of the ARM architecture.

[0079] Specifically, at this time, when the operand of the prefetch instruction of the x86 architecture is the memory address pointed to by the register, and there is a corresponding register in the ARM architecture that can save the memory address, the above method is directly used for conversion, including the following steps: assigning the memory address of the prefetch instruction of the x86 architecture to the register of the ARM architecture. In addition, the register used by the ARM architecture prefetch instruction can be determined by an existing more efficient register mapping algorithm, wherein the register mapping algorithm is such as the Tomasulo algorithm, the fully associative mapping algorithm, etc. Furthermore, since the ARM processor has far more registers than the x86 registers, a simpler and more efficient direct mapping algorithm can also be used for determination.

[0080] S4.2. When the address access mode is the base address index mode, take the following x86 loop code as an example:

[0081] mov esi, offset array / / Assume array is the starting address of an array

[0082] mov ecx, count / / count is the number of array elements

[0083] loop_start:

[0084] PREFETCHT0 [esi + 4*ecx]

[0085] / / Other loop code

[0086] loop loop_start

[0087] In ARM this can be converted to:

[0088] ldr r0, =array / / Load the array starting address to r0

[0089] mov r1, #count

[0090] loop_start_ARM:

[0091] ldr r2, [r0, r1, lsl #2]

[0092] PLDW [r2]

[0093] / / Other loop code

[0094] b loop_start_ARM

[0095] Among them, for the prefetch instruction in the loop, it is necessary to analyze the relationship between the loop variable and the prefetch memory address. In the above sample code, the prefetched memory address is [esi + 4*ecx], register esi is the base address register, and ecx is the offset register.

[0096] In the process of converting to ARM instructions, the array start address is first loaded into register r0, the loop variable count is loaded into register r1, the pre-fetched memory address is calculated through ldr r2, [r0, r1, lsl #2] and stored in register r2, and then PLDW [r2] is used for pre-fetching. The key is to correctly calculate the memory address corresponding to the pre-fetch instruction and pass the memory address to the PLDW instruction of the ARM architecture.

[0097] S4.3. When the address access mode is the composite address mode, the prefetch instruction of the x86 architecture is: PREFETCHT0[eax + ebx*4 + 10h]. First, the address calculation method of the x86 architecture is simulated in the ARM architecture. The following instruction sequence can be used to complete a similar calculation, as follows:

[0098] mov r2, r1, lsl #2 / / Shift the value of r1 (corresponding to ebx) to the left by 2 bits, which is equivalent to multiplying by 4, and store the result in r2, simulating ebx*4

[0099] add r2, r2, r0 / / Add r2 (the result of ebx*4) and r0 (corresponding to eax), at this time the value of r2 is eax +ebx*4

[0100] add r2, r2, #0x10 / / Add the immediate value 0x10 (corresponding to 10h) to r2. Now r2 stores the memory address calculated by eax + ebx*4 + 10h.

[0101] By generating the above instructions, the memory address calculation process in the composite address mode of the x86 architecture can be reproduced in the ARM architecture, and then the calculated memory address is stored in register r2.

[0102] Then, the prefetch instruction of the ARM architecture is generated: after the correct memory address is stored in register r2, the PLDW instruction of the ARM architecture can be used to prefetch data, the instruction is: PLDW[r2]. This instruction implements the prefetch operation of the data corresponding to the memory address previously obtained through complex calculations, and loads the data into the cache in advance to improve the performance of subsequent access to the data, thus completing the conversion from the prefetch instruction of the x86 composite address mode to the ARM data prefetch instruction.

[0103] Since the PLDW instruction of the ARM architecture requires a relatively simple memory address operand, the present invention generates an additional instruction sequence to first calculate the actual memory address obtained by the complex addressing calculation, temporarily stores it in an adapted register, and then uses the register as the operand of the PLDW instruction to implement prefetching, which is equivalent to separating the complex memory address calculation process from the prefetching operation. In actual applications, appropriate adjustments and optimizations may also be required based on specific program contexts, register usage, etc.

[0104] S4.4, when the address access mode is the segment register related mode, the prefetch instruction of the x86 architecture is: PREFETCHT0 [cs:eax]. First, the ARM architecture is divided into different memory areas through software definition to simulate the segment registers in the x86 architecture. For example, the area from memory address 0x10000 to 0x1FFFF is used to simulate the code segment corresponding to the code segment register CS of the x86 architecture, assuming that the segment base address of the code segment is 0x10000.

[0105] Then, get the offset address and perform address conversion calculation. In the generated ARM code, assuming that the value of register eax has been correctly transferred to register r0, the memory address of the final prefetched data is calculated through the following instructions:

[0106] ldr r1, =0x10000 / / Assume that the base address of the code segment is 0x10000, stored in register r1

[0107] add r2, r1, r0 / / Add the code segment base address (r1) and the offset address (r0), and store the result in register r2 to get the final memory address

[0108] Through the above calculation, the process of determining the memory address through the code segment register CS and the offset register eax in the x86 architecture is simulated, and the obtained memory address is saved in the register r2.

[0109] Finally, the prefetch instruction of the ARM architecture is generated, and the PLDW instruction of the ARM architecture is used to perform data prefetching. The instruction is: PLDW [r2], which implements the prefetch operation on the data corresponding to the memory address determined by the simulated segmented memory management, and loads the data into the cache in advance.

[0110] In addition, for other different segment registers, such as data segment register DS, additional segment register ES, etc., a similar method is used to define the corresponding simulation segment memory area in ARM, and then the segment base address of the corresponding simulation segment memory area is selected according to the specific segment register to participate in the address calculation, and then the PLDW instruction is executed to prefetch data.

[0111] For example, for the x86 architecture prefetch instruction PREFETCHT0 [ds:ebx], assuming that the segment base address has been stored in register r3 and the value of register ebx has been transferred to register r4, then:

[0112] add r5, r3, r4 / / Calculate the final memory address and store it in register r5

[0113] PLDW [r5]

[0114] In the x86 architecture, segmented memory management determines the physical memory address through segment registers, such as code segment register CS, data segment register DS, and additional segment register ES, in combination with the offset address. For example, instruction PREFETCHT0 [cs:eax] refers to determining the memory address of prefetched data based on the base address of the code segment plus the offset represented by register eax. However, the ARM architecture itself does not have a segmented memory management mechanism that completely corresponds to it, making it difficult to achieve direct conversion. Therefore, the present invention simulates the logic of segmented memory management at the software level, constructs a similar address mapping mechanism in the ARM architecture, and equivalently implements the functions corresponding to the segment registers through specific memory area division and address calculation rules, thereby completing the conversion of prefetch instructions involving segmented memory management.

[0115] In summary, the above are only preferred embodiments of the present invention and are not intended to limit the protection scope of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A prefetch instruction conversion optimization method based on memory access mode virtualization, characterized in that: The specific steps include: Step 1, load and execute the executable file through dynamic instruction conversion, if the current instruction to be converted is a prefetch instruction of the x86 architecture, execute step 2, otherwise, convert the current instruction to be converted into an ARM instruction and then execute step 7; Step 2, reverse the current instruction to be converted to obtain the address access mode it adopts, if the address access mode is a simple address mode, execute step 3, if the address access mode is a base address index mode, execute step 4, if the address access mode is a composite address mode, execute step 5, if the address access mode is a segment register related mode, execute step 6; Step 3, record the register in the operand as the first register, select a register in the ARM that stores the memory address in the first register as the first ARM register, construct a first ARM prefetch instruction with the first ARM register as the operand, convert the current instruction to be converted into the first ARM prefetch instruction, and execute step 7; Step 4, obtaining the base address register, the offset register and the offset calculation method in the operand, recording the register storing the base address as the first ARM register in ARM, recording the register storing the offset as the second ARM register, recording the register storing the memory address as the third ARM register, determining the logical operator according to the offset calculation method, constructing a first ARM load instruction to load the sum of the result processed by the second ARM register through the logical operator and the first ARM register into the third ARM register, constructing a first ARM prefetch instruction with the third ARM register as the operand; converting the current instruction to be converted into an instruction sequence formed by the first ARM load instruction and the first ARM prefetch instruction, and executing step 7; Step 5, obtain N registers, M constants and offset calculation methods in the operands, assign one-to-one corresponding ARM registers to the N registers, and record the register that stores the memory address as the target ARM register; determine the corresponding calculation instructions and logical operators according to the offset calculation method, construct an address calculation instruction sequence composed of multiple calculation instructions, logical operators and immediate numbers to calculate the memory address, save the memory address to the target ARM register, and construct the first ARM prefetch instruction with the target ARM register as the operand; Convert the current instruction to be converted into an instruction sequence formed by an address calculation instruction sequence and a first ARM prefetch instruction, and execute step 7; Step 6, delineate the simulation segment memory area in the ARM architecture, establish a first mapping relationship between the simulation segment memory area and the segment register of the x86 architecture; obtain the current segment register and the offset register in the operand, determine the simulation segment memory area corresponding to the current segment register according to the first mapping relationship, obtain the segment base address of the simulation segment memory area, record the register storing the segment base address as the first ARM register; record the register storing the offset as the second ARM register, record the register storing the memory address as the target ARM register, construct an addition instruction that stores the sum of the addresses in the first ARM register and the second ARM register in the target ARM register, and construct a first ARM prefetch instruction with the target ARM register as the operand; convert the current instruction to be converted into an instruction sequence formed by the addition instruction and the first ARM prefetch instruction, and execute step 7; Step 7: If the executable file has not been executed, select the next instruction to execute step 2; otherwise, complete the execution of the executable file and end this process; The method of reversing the current instruction to be converted in step 2 to obtain the address access mode it adopts is: reversely analyze the current instruction to be converted to obtain the data structure of the operand, if the operand contains only one register, the address access mode is determined to be a simple address mode, if the operand contains two registers, the address access mode is determined to be a base address displacement mode, if the operand contains a register and a constant, the address access mode is determined to be a compound address mode, and if the operand contains a segment register, it is determined to be a segment register related mode.

2. The prefetch instruction conversion optimization method according to claim 1, characterized in that: The method for determining the prefetch instruction of the x86 architecture in step 1 is: determining according to the operation code of the prefetch instruction of the x86 architecture.

3. The prefetch instruction conversion optimization method according to claim 1, characterized in that: The method of defining the simulation segment memory area in the ARM architecture in step 6 is: using software-defined definition.

4. The prefetch instruction conversion optimization method according to claim 1, characterized in that: Before step 2, the current instruction to be converted is forward reverse analyzed to form a set number of instructions to form a first instruction set. If there is a write operation on the memory address related to the current instruction to be converted in the first instruction set, the prefetch instruction in the first ARM prefetch instruction is a write prefetch instruction; otherwise, the prefetch instruction in the first ARM prefetch instruction is a read prefetch instruction.

5. The prefetch instruction conversion optimization method according to claim 4, characterized in that: The write prefetch instruction is a PLDW instruction, and the read prefetch instruction is a PLD instruction.

6. The prefetch instruction conversion optimization method according to claim 1, characterized in that: The segment register is a code segment register CS, a data segment register DS or an additional segment register ES.

7. The prefetch instruction conversion optimization method according to claim 1, characterized in that: The first mapping relationship in step 6 is established by using a register mapping algorithm.

8. The prefetch instruction conversion optimization method according to claim 7, characterized in that: The register mapping algorithm includes the Tomasulo algorithm and the fully associative mapping algorithm.

9. The prefetch instruction conversion optimization method according to claim 7, characterized in that: The register mapping algorithm is a direct mapping algorithm.