Instruction acquisition method, device, computer equipment and storage medium

Abstract

The embodiments of the present application provide an instruction acquisition method, apparatus, computer device and storage medium, the method comprising: reading a target instruction for the first time according to a target instruction address, generating a first re-execution signal; performing error detection on the target instruction according to the first re-execution signal; generating a first clear signal when an error occurs in the target instruction; generating a second clear signal according to the first clear signal; generating a second re-execution signal according to the second clear signal, and reading the target instruction for the second time according to the target instruction address; performing error detection on the target instruction according to the second re-execution signal, generating instruction error information or controlling an error correction module to correct the target instruction, and by means of first discovery and second confirmation, a circuit error detection module, an error correction module and a combinational logic with a long delay are executed separately, so as to achieve the purpose of timing optimization.

Description

Technical Field

[0001] The present application relates to the technical field of central processing units, and in particular, to an instruction acquisition method, apparatus, computer equipment and storage medium. Background Art

[0002] In related technologies, such as Figure 1 As shown, when the instruction fetch unit reads instructions, it accesses the storage unit ILM (Information Lifecycle Management) or I-Cache (a memory used to cache instructions) through the ICB (custom bus protocol) bus. After accessing the ILM or I-Cache, the read data or address may need to be pre-processed, such as ECC (Error Checking and Correcting) check, to check whether the data is wrong. After that, the checked data will be uploaded to the subsequent branch prediction and partial decoding parts for processing.

[0003] See also Figure 2 In the above process, the data reading of the storage unit is usually regarded as a clock cycle. After the data is read, preprocessing is performed, and branch prediction and partial decoding are performed as a clock cycle. In the case of an error found in the ECC check, the memory unit is checked to detect whether an error really occurs and whether the error can be corrected, which will block the pipeline. That is, after reading the data, preprocessing such as ECC error detection is performed to check the accuracy of the data in the memory unit. At this time, two signals are generated, one is the data signal and the other is the data valid signal. The data signal represents the data obtained from the SRAM (Static Random-Access Memory), and the data valid signal indicates that the data is valid after the ECC check. After the data signal is read from the SRAM, it is beat by the pipeline register e2, and then passes through the combinational logic 1 and is connected to the input of the pipeline register e3. The delay of the combinational logic 1 can be controlled relatively well, so the timing path of the data signal will not be the critical path. However, the data valid signal is generated after the data signal of the pipeline register e2 needs to be processed by ECC error detection. Therefore, there is a difference between the timing of the data valid signal and the data signal. The data valid signal needs to be processed by the pre-processing ECC module and the subsequent combinational logic 2 before it can reach the pipeline register e3. Since the timing of ECC error detection and ECC error correction is relatively poor, and the subsequent combinational logic 2 also has a certain degree of delay, ECC error detection and ECC error correction and combinational logic 2 are connected in series, resulting in a very tight path timing corresponding to the data valid signal, which becomes a critical path. Summary of the invention

[0004] The embodiments of the present application provide an instruction acquisition method, apparatus, computer device and storage medium.

[0005] According to a first aspect of an embodiment of the present application, an instruction acquisition method is provided, which is applied to an instruction acquisition device, wherein the instruction acquisition device includes an instruction fetch control module, a register connected to the instruction fetch control module, a re-execution control module connected to the register, an error detection module and an error correction module, and a clear generation module downstream of the re-execution control module, wherein the error detection module and the error correction module are both connected to the re-execution control module, and the method includes:

[0006] Using the instruction fetch control module to read the target instruction for the first time according to the target instruction address, generating a first re-execution signal, sending the first re-execution signal and the target instruction to the re-execution control module via the register, and sending the target instruction address to the clear generation module via the register and the re-execution control module;

[0007] Using the re-execution control module to generate a data valid signal, and controlling the error detection module to perform error detection on the target instruction according to the first re-execution signal;

[0008] When the target instruction fails, the error detection module generates a first clear signal, and sends the first clear signal to the clear generation module;

[0009] Generate a target instruction address re-fetch request and a second clear signal using a clear generation module according to a data valid signal, a target instruction address and a first clear signal;

[0010] Generate a second re-execution signal according to the second clear signal by using the instruction fetch control module, and read the target instruction for the second time according to the target instruction address in the re-fetch request;

[0011] The re-execution control module is used to control the error detection module to perform error detection on the target instruction according to the second re-execution signal, and instruction error information is generated according to the bit value of the target instruction error, or the error correction module is controlled to perform error correction on the target instruction.

[0012] In an optional embodiment of the present application, generating instruction error information according to the bit value of the target instruction error or controlling the error correction module to correct the target instruction includes:

[0013] When the bit value of the target instruction error is 1 bit, the control error correction module corrects the target instruction. When the bit value of the target instruction error exceeds 1 bit, the control module is re-executed to generate instruction error information.

[0014] In an optional embodiment of the present application, controlling the error correction module to correct the target instruction includes:

[0015] The error-corrected instruction is written into the memory storing the target instruction to replace the target instruction, and the error-corrected instruction is sent downstream.

[0016] In an optional embodiment of the present application, the instruction fetch control module generates a second re-execution signal according to the second clear signal, and reads the target instruction for the second time according to the target instruction address in the re-fetch request of the target instruction address, including:

[0017] The current instruction address in the instruction fetch control module is cleared, and the current instruction address is updated to the target instruction address in the target instruction address re-fetch request in the next beat, and a second re-execution signal is generated at the same time.

[0018] In an optional embodiment of the present application, after using the re-execution control module to control the error detection module to perform error detection on the target instruction according to the first re-execution signal or the second re-execution signal, the method further includes:

[0019] Using the error detection module, when there is no error in the target instruction, sending a request to the re-execution control module to send the target instruction to the downstream;

[0020] Utilize the re-execution control module to send the target instruction downstream.

[0021] In an optional embodiment of the present application, the register includes a first register and a second register, and sending the first re-execution signal and the target instruction to the re-execution control module via the register includes:

[0022] Using the instruction fetch control module, sending the first re-execution signal to the re-execution control module via the first register and the second register;

[0023] The instruction fetch control module is used to send the target instruction to the re-execution control module via the second register.

[0024] In an optional embodiment of the present application, generating a data valid signal by re-executing the control module includes:

[0025] The re-execution control module is used to generate a data valid signal after the target instruction passing through the second register is error-checked by the error-checking module.

[0026] According to a second aspect of the embodiment of the present application, an instruction acquisition device is provided, comprising an instruction fetch control module, a register connected to the instruction fetch control module, a re-execution control module connected to the register, an error detection module and an error correction module, and a clear generation module downstream of the re-execution control module, wherein the error detection module and the error correction module are both connected to the re-execution control module.

[0027] The instruction fetch control module is used to read the target instruction for the first time according to the target instruction address, generate a first re-execution signal, send the first re-execution signal and the target instruction to the re-execution control module via the register, and send the target instruction address to the clear generation module via the register and the re-execution control module; and is also used to generate a second re-execution signal according to the second clear signal, and read the target instruction for the second time according to the target instruction address in the instruction re-fetch request;

[0028] A re-execution control module is used to generate a data valid signal, and control the error detection module to perform error detection on the target instruction according to the first re-execution signal; and is also used to control the error detection module to perform error detection on the target instruction according to the second re-execution signal, and generate instruction error information according to the bit value of the target instruction error or control the error correction module to perform error correction on the target instruction;

[0029] An error detection module, used for generating a first clear signal when an error occurs in the target instruction, and sending the first clear signal to the clear generation module;

[0030] The clear generation module is used to generate a target instruction address re-fetch request and a second clear signal according to the data valid signal, the target instruction address and the first clear signal.

[0031] According to a third aspect of an embodiment of the present application, a computer device is provided, including: a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of any of the above instruction acquisition methods when executing the computer program.

[0032] A fourth aspect of an embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program implements the steps of any of the above instruction acquisition methods when executed by a processor.

[0033] The above technical solution provided by the embodiment of the present application has at least some or all of the following advantages compared with the prior art:

[0034] The instruction acquisition method described in the embodiment of the present application uses an instruction fetch control module to read the target instruction for the first time according to the target instruction address, generates a first re-execution signal, sends the first re-execution signal and the target instruction to the re-execution control module via a register, and sends the target instruction address to the clear generation module via the register and the re-execution control module; uses the re-execution control module to generate a data valid signal, controls the error detection module to perform error detection on the target instruction according to the first re-execution signal; uses the error detection module to generate a first clear signal when the target instruction fails, and sends it to the clear generation module; uses the clear generation module to generate a clear signal according to the data valid signal, the target instruction address and the first clear signal A target instruction address re-fetch request and a second clear signal; using the instruction fetch control module to generate a second re-execution signal according to the second clear signal, and reading the target instruction for the second time according to the target instruction address in the target instruction address re-fetch request; using the re-execution control module to control the error detection module to perform error detection on the target instruction according to the second re-execution signal, and generate instruction error information according to the bit value of the target instruction error or control the error correction module to correct the target instruction. By introducing the re-execution mechanism and utilizing the depth of the processor pipeline, the error detection module, error correction module and combinational logic of the circuit with a long delay are executed separately through the first discovery and second confirmation method, so as to achieve the purpose of timing optimization. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0036] Figure 1 A flowchart of an instruction fetch unit performing instruction reading provided in the related art;

[0037] Figure 2 A flowchart of the processing after the instruction fetch unit reads the data provided by the related technology;

[0038] Figure 3 A flowchart of an instruction acquisition method provided by an embodiment of the present application;

[0039] Figure 4 A flowchart of an instruction acquisition method provided by another embodiment of the present application;

[0040] Figure 5 A schematic diagram of the structure of an instruction acquisition device provided in one embodiment of the present application;

[0041] Figure 6 A schematic diagram of the computer device structure provided for one embodiment of the present application. DETAILED DESCRIPTION

[0042] In the process of implementing the present application, the inventors found that the current ECC error detection and ECC error correction as well as the combinational logic 2 are connected in series, resulting in poor path timing corresponding to the data valid signal.

[0043] In response to the above problems, an instruction acquisition method, apparatus, computer device and storage medium are provided in the embodiments of the present application, so that the circuit error detection module, error correction module and combinational logic with a long delay are executed separately to achieve the purpose of timing optimization.

[0044] The solutions in the embodiments of the present application can be implemented using various computer languages, for example, the object-oriented programming language Java and the interpreted scripting language JavaScript.

[0045] In order to make the technical solutions and advantages in the embodiments of the present application more clearly understood, the exemplary embodiments of the present application are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0046] See also Figure 3 The instruction acquisition method provided in the embodiment of the present application is applied to an instruction acquisition device, wherein the instruction acquisition device includes an instruction fetch control module, a register connected to the instruction fetch control module, a re-execution control module connected to the register, an error detection module and an error correction module, and a clear generation module downstream of the re-execution control module, wherein the error detection module and the error correction module are both connected to the re-execution control module, and the method includes the following steps 100 to 600:

[0047] Step 100: using the instruction fetch control module to read the target instruction for the first time according to the target instruction address, generating a first re-execution signal, sending the first re-execution signal and the target instruction to the re-execution control module via the register, and sending the target instruction address to the clear generation module via the register and the re-execution control module;

[0048] Step 200: Generate a data valid signal using the re-execution control module, and control the error detection module to perform error detection on the target instruction according to the first re-execution signal;

[0049] Step 300: When an error occurs in the target instruction, the error detection module generates a first clear signal and sends the signal to the clear generation module;

[0050] Step 400, using a clear generation module to generate a target instruction address re-fetch request and a second clear signal according to a data valid signal, a target instruction address and a first clear signal;

[0051] Step 500: Generate a second re-execution signal according to the second clear signal by using the instruction fetch control module, and read the target instruction for the second time according to the target instruction address in the re-fetch request;

[0052] Step 600: Use the re-execution control module to control the error detection module to perform error detection on the target instruction according to the second re-execution signal, generate instruction error information according to the bit value of the target instruction error, or control the error correction module to perform error correction on the target instruction.

[0053] In an optional embodiment of the present application, the error in the target instruction may be an ECC error, that is, a memory error.

[0054] In an optional embodiment of the present application, in step 100, the register includes a first register and a second register, and sending the first re-execution signal and the target instruction to the re-execution control module via the register includes:

[0055] Using the instruction fetch control module, sending the first re-execution signal to the re-execution control module via the first register and the second register;

[0056] The instruction fetch control module is used to send the target instruction to the re-execution control module via the second register.

[0057] In an optional embodiment of the present application, in step 200, generating a data valid signal by re-executing the control module includes:

[0058] The re-execution control module is used to generate a data valid signal after the target instruction passing through the second register is error-checked by the error-checking module.

[0059] In an optional embodiment of the present application, in step 500, the instruction fetch control module generates a second re-execution signal according to the second clear signal, and reads the target instruction for the second time according to the target instruction address in the re-fetch request of the target instruction address, including:

[0060] The current instruction address in the instruction fetch control module is cleared, and the current instruction address is updated to the target instruction address in the target instruction address re-fetch request in the next beat, and a second re-execution signal is generated at the same time.

[0061] In an optional embodiment of the present application, after using the re-execution control module to control the error detection module to perform error detection on the target instruction according to the first re-execution signal or the second re-execution signal, the method further includes:

[0062] Using the error detection module, when there is no error in the target instruction, sending a request to the re-execution control module to send the target instruction to the downstream;

[0063] Utilize the re-execution control module to send the target instruction downstream.

[0064] See also Figure 4 , replay signal is the re-execution signal, flush generation module is the clear generation module, en_ecc_flush is the first clear signal, ecc_flush_req is the target instruction address re-fetch request, ecc_flush_pc is the target instruction address, PC is the instruction address, e0_pc is the current instruction address, e0_replay is the current re-execution signal, e0, e1, e2 and e3 are registers, such as Figure 4As shown, the instruction fetch control module is used to control the generation of instruction fetch and replay signals. If the flush generation module of the pipeline en output stage generates ecc_flush_req (including ecc_flush_pc) due to en_ecc_flush and sends it to the instruction fetch control module, the instruction fetch control module will respond to ecc_flush_req, clear the PC of the current instruction fetch, and update the e0_pc of the instruction fetch to ecc_flush_pc in the next beat, and pull the e0_replay signal high in the next beat. If the flush generation module does not generate ecc_flush_req, the instruction fetch control module will generate a new e0_pc in the next beat after sending the current e0's instruction fetch signal to pipeline e1 (that is, e0 completes the pipeline handshake). The new e0_pc is the PC value generated according to the normal instruction fetch logic (such as PC value +2 or +4), and will pull e0_replay low in the next beat (if the current e0_replay is 1, then the next beat e0_replay will be cleared to 0, if the current e0_replay is 0, then the next beat e0_replay will continue to remain 0). The e0_replay signal is generated in the instruction fetch control module (e0_replay is pulled high) in the next beat of ecc_flush_req. After the handshake is completed for the instruction fetch with e0_replay pulled high, e0_replay will be cleared, that is, e0 will and will only mark the access that needs to be re-fetched due to the occurrence of ecc_flush (that is, by pulling e0_replay high to mark); e0_replay will be passed to e1 (e1_replay) and e2 (e2_replay) through the pipeline handshake. The replay mark (ex_replay) on the pipeline is used to indicate that the instruction fetch of the current PC address had an ecc error during the last instruction fetch, and this instruction fetch needs to be handled with care. Therefore, when the instruction fetch control module finds ecc_flush_req, it will re-fetch instructions from the PC (ecc_flush_pc) where ecc_flush appears, and mark this instruction fetch as e0_replay (that is, e0_replay is pulled high) for use in subsequent pipelines; if ecc_flush_req does not appear, instruction fetching is carried out in the normal way, and e0_replay is pulled low.

[0065] In an optional embodiment of the present application, in step 600, generating instruction error information according to the bit value of the target instruction error or controlling the error correction module to correct the target instruction includes:

[0066] When the bit value of the target instruction error is 1 bit, the control error correction module corrects the target instruction. When the bit value of the target instruction error exceeds 1 bit, the control module is re-executed to generate instruction error information.

[0067] In an optional embodiment of the present application, controlling the error correction module to correct the target instruction includes:

[0068] The error-corrected instruction is written into the memory storing the target instruction to replace the target instruction, and the error-corrected instruction is sent downstream.

[0069] exist Figure 4 In the re-execution control module, if e2_replay is pulled high, it means that the PC of this instruction fetch of e2 has an ecc error in the last instruction fetch. This instruction fetch will be carefully processed through multiple beats. The processing flow is as follows:

[0070] S1, the replay control module controls the ECC error detection module to perform error detection and records the error detection results;

[0071] S2, the replay control module determines the error detection result. If a 1-bit error is found, the ECC error correction module is controlled to perform error correction, and the corrected value is saved as corr_data, and the process jumps to S3; if no error is found or the error is greater than 1 bit, the process jumps to S4;

[0072] S3, triggers SRAM update backfill, waits for the corrected corr_data to be written into SRAM, pauses for one beat, and jumps to S5; the data valid signal is generated by the signal of pipeline register e2 via the replay control module;

[0073] S4, judge the error detection result again. If it is a 1-bit error, the value of e2_data is selected as corr_data, otherwise, the value of e2_data is selected as e2_data_pre; e2_data_vld is pulled high; and e2_ecc_flush is pulled low.

[0074] S5, wait for the instruction of e2 to complete the handshake and enter pipeline e3, including e2_data, e2_ecc_flush, e2_pc, etc.

[0075] However, if e2_replay is low, the replay control module will only control the ECC error detection module to perform error detection, and the error detection result will be transmitted to e3 through e2_ecc_flush. At the same time, the result of e2_data_pre will be assigned to ec_data, and e2_data_vld will be pulled high so that the handshake can be completed in the beat and the instruction fetch result of e2 can be transmitted to e3.

[0076] Therefore, in the absence of an ECC error, the instruction fetch efficiency of the instruction fetch unit will not be affected by the replay mechanism and is the same as the instruction fetch efficiency of the prior art.

[0077] like Figure 4 As shown, when e2_ecc_flush and e2_replay are low and an ecc error (including 1 bit and above) occurs, e2_ecc_flush will be pulled high during the e2 handshake, that is, the ecc_flush signal is generated, and then passed to e3 through the pipeline; e3_ecc_flush of pipeline e3 will be passed along the pipeline to pipeline en, and en_ecc_flush is obtained. In the flush generation module, en_ecc_flush is pulled high to indicate that an ecc error has occurred in the instruction fetch of pipeline en, and a flush needs to be initiated to fetch again, which will generate ecc_flush_req, and at the same time, the PC of pipeline en, i.e. en_pc, will be sent to the instruction fetch control module as ecc_flush_pc.

[0078] In the instruction acquisition of the present application, from the timing point of view, the timing will be improved due to the introduction of the replay mechanism. On the one hand, when an ECC error occurs and replay is performed, e2_replay is pulled high, and e2_replay is a register output signal with good timing. Then, the replay control module can be used to control ECC detection, ECC error correction, writing the error correction result back to SRAM, and controlling the transmission of the e2 result to e3 in steps of multiple clock cycles, so as to ensure that the timing is good during replay; on the other hand, when e2_replay is pulled low, the ECC error detection result is directly sent to the downstream pipeline e3; therefore, the present application will not have such a situation. Figure 2 The structure shown is that two circuits with very long delays (ECC error detection module and combinational logic 2) are connected in series, so the timing of the application is improved.

[0079] In the instruction acquisition of the present application, from the performance point of view, the introduction of the replay mechanism will not affect the performance. On the one hand, when no ecc error occurs, the instruction fetch efficiency of the present application is as high as that of the prior art. Since ecc error is a low-probability event, even if an ecc error occurs, the impact on performance can be ignored. Therefore, the introduction of the replay mechanism of the present application will not affect the normal instruction fetch performance.

[0080] It should be understood that, although the various steps in the flow chart are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the figure may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these sub-steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0081] See also Figure 5 An embodiment of the present application provides an instruction acquisition device 500, comprising an instruction fetch control module 510, a register 520 connected to the instruction fetch control module, a re-execution control module 530 connected to the register, an error detection module 540 and an error correction module 550, and a clear generation module 560 downstream of the re-execution control module, wherein the error detection module and the error correction module are both connected to the re-execution control module,

[0082] The instruction fetch control module is used to read the target instruction for the first time according to the target instruction address, generate a first re-execution signal, send the first re-execution signal and the target instruction to the re-execution control module via the register, and send the target instruction address to the clear generation module via the register and the re-execution control module; and is also used to generate a second re-execution signal according to the second clear signal, and read the target instruction for the second time according to the target instruction address in the instruction re-fetch request;

[0083] A re-execution control module is used to generate a data valid signal, and control the error detection module to perform error detection on the target instruction according to the first re-execution signal; and is also used to control the error detection module to perform error detection on the target instruction according to the second re-execution signal, and generate instruction error information according to the bit value of the target instruction error or control the error correction module to perform error correction on the target instruction;

[0084] An error detection module, used for generating a first clear signal when an error occurs in the target instruction, and sending the first clear signal to the clear generation module;

[0085] The clear generation module is used to generate a target instruction address re-fetch request and a second clear signal according to the data valid signal, the target instruction address and the first clear signal.

[0086] For the specific definition of the above-mentioned device 500, please refer to the definition of the instruction acquisition generation method above, which will not be repeated here. Each module in the above-mentioned device 500 can be implemented in whole or in part by software, hardware and a combination thereof. The above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory of the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

[0087] In one embodiment, a computer device is provided, the internal structure diagram of which can be as follows: Figure 6 As shown. The computer device includes a processor, a memory, a network interface and a database connected via a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store data. The network interface of the computer device is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, an instruction acquisition generation method as described above is implemented. It includes: a memory and a processor, the memory stores a computer program, and when the processor executes the computer program, any step in the instruction acquisition generation method as described above is implemented.

[0088] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, any step in the above instruction acquisition generation method can be implemented.

[0089] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0090] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0091] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0092] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0093] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0094] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A method for obtaining an instruction, characterized in that: The invention is applied to an instruction acquisition device, wherein the instruction acquisition device comprises an instruction fetch control module, a register connected to the instruction fetch control module, a re-execution control module connected to the register, an error detection module and an error correction module, and a clear generation module downstream of the re-execution control module, wherein both the error detection module and the error correction module are connected to the re-execution control module, and the method comprises: Using the instruction fetch control module to read the target instruction for the first time according to the target instruction address, generating a first re-execution signal, sending the first re-execution signal and the target instruction to the re-execution control module via the register, and sending the target instruction address to the clear generation module via the register and the re-execution control module; Using the re-execution control module to generate a data valid signal, and controlling the error detection module to perform error detection on the target instruction according to the first re-execution signal; When the target instruction fails, the error detection module generates a first clear signal, and sends the first clear signal to the clear generation module; Generate a target instruction address re-fetch request and a second clear signal using a clear generation module according to a data valid signal, a target instruction address and a first clear signal; Generate a second re-execution signal according to the second clear signal by using the instruction fetch control module, and read the target instruction for the second time according to the target instruction address in the re-fetch request; The re-execution control module is used to control the error detection module to perform error detection on the target instruction according to the second re-execution signal, and instruction error information is generated according to the bit value of the target instruction error, or the error correction module is controlled to perform error correction on the target instruction.

2. The method according to claim 1, characterized in that Generate instruction error information according to the bit value of the target instruction error or control the error correction module to correct the target instruction, including: When the bit value of the target instruction error is 1 bit, the control error correction module corrects the target instruction. When the bit value of the target instruction error exceeds 1 bit, the control module is re-executed to generate instruction error information.

3. The method according to claim 2, characterized in that The control error correction module performs error correction on the target instruction, including: The error-corrected instruction is written into the memory storing the target instruction to replace the target instruction, and the error-corrected instruction is sent downstream.

4. The method according to claim 1, characterized in that: The method comprises: generating a second re-execution signal according to the second clear signal by using the instruction fetch control module, and reading the target instruction for the second time according to the target instruction address in the re-fetch request of the target instruction address, including: The current instruction address in the instruction fetch control module is cleared, and the current instruction address is updated to the target instruction address in the target instruction address re-fetch request in the next beat, and a second re-execution signal is generated at the same time.

5. The method according to claim 1, characterized in that After using the re-execution control module to control the error detection module to perform error detection on the target instruction according to the first re-execution signal or the second re-execution signal, the method further includes: Using the error detection module, when there is no error in the target instruction, sending a request to the re-execution control module to send the target instruction to the downstream; Utilize the re-execution control module to send the target instruction downstream.

6. The method according to claim 1, characterized in that The register includes a first register and a second register, and sending the first re-execution signal and the target instruction to the re-execution control module via the register includes: Using the instruction fetch control module, sending the first re-execution signal to the re-execution control module via the first register and the second register; The instruction fetch control module is used to send the target instruction to the re-execution control module via the second register.

7. The method according to claim 6, characterized in that Generate a data valid signal using the re-execution control module, including: The re-execution control module is used to generate a data valid signal after the target instruction passing through the second register is error-checked by the error-checking module.

8. An instruction acquisition device, characterized in that: It includes an instruction fetch control module, a register connected to the instruction fetch control module, a re-execution control module connected to the register, an error detection module and an error correction module, and a clear generation module downstream of the re-execution control module, wherein the error detection module and the error correction module are both connected to the re-execution control module. The instruction fetch control module is used to read the target instruction for the first time according to the target instruction address, generate a first re-execution signal, send the first re-execution signal and the target instruction to the re-execution control module via the register, and send the target instruction address to the clear generation module via the register and the re-execution control module; and is also used to generate a second re-execution signal according to the second clear signal, and read the target instruction for the second time according to the target instruction address in the instruction re-fetch request; A re-execution control module is used to generate a data valid signal, and control the error detection module to perform error detection on the target instruction according to the first re-execution signal; and is also used to control the error detection module to perform error detection on the target instruction according to the second re-execution signal, and generate instruction error information according to the bit value of the target instruction error or control the error correction module to perform error correction on the target instruction; An error detection module, used for generating a first clear signal when an error occurs in the target instruction, and sending the first clear signal to the clear generation module; The clear generation module is used to generate a target instruction address re-fetch request and a second clear signal according to the data valid signal, the target instruction address and the first clear signal.

9. A computer device comprising: A memory and a processor, wherein the memory stores a computer program, and wherein the processor implements the steps of the instruction acquisition method according to any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the instruction acquisition method according to any one of claims 1 to 7 are implemented.

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