Dynamic error correction methods, controllers, and storage systems for 3D NAND flash memory

Abstract

This invention discloses a dynamic error correction method, controller, and storage system suitable for 3D NAND flash memory, belonging to the field of semiconductor storage technology. It includes: an encoding stage: polar code encoding of the data to be written to the 3D NAND flash memory to obtain a codeword sequence of length N; a decoding stage: calculating the LLR value of each bit of the data of length N read from the 3D NAND flash memory; after setting the list length of the SCL decoding algorithm, inputting the N-bit LLR values ​​into the SCL decoding algorithm to achieve decoding; setting the list length of the SCL decoding algorithm includes: obtaining the bit error rate of the SCL decoding algorithm at different list lengths under the current raw bit error rate of the 3D NAND flash memory, selecting list lengths with bit error rates lower than a preset performance threshold, and setting the list length of the SCL decoding algorithm to the selected minimum length. This invention is adapted to the error characteristics of 3D NAND flash memory and can reduce overhead while ensuring that error correction requirements are met.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor storage technology, and more specifically, relates to a dynamic error correction method, controller, and storage system suitable for three-dimensional NAND flash memory. Background Technology

[0002] The storage capacity and density of flash memory have been steadily increasing with the shrinking of feature size and the increase in the number of stacked layers. Its excellent storage capabilities and performance are essential for today's big data era and have been widely used in various scenarios such as servers and data centers. High-capacity solid-state drives using 3D NAND flash memory have also rapidly replaced hard disk drives in the storage market. However, the increased integration of 3D NAND flash memory arrays still comes at the cost of reduced lifespan and reliability. On the one hand, from SLC to TLC and possibly QLC and PLC in the future, multi-level storage cell technology compresses the threshold voltage distribution window of each state, resulting in more overlapping states and requiring more reference voltages, which seriously affects performance and reliability. On the other hand, the number of stacked layers brings more complex vertical interference and differences. The combination of these two factors exhibits error characteristics different from planar NAND flash memory, especially the inter-layer differences unique to three-dimensional structures, i.e., different layers have different RBERs, and the RBER changes differently over time in different layers.

[0003] Early commonly used BCH codes and now widely used LDPC codes are both common ECC schemes in flash memory. Polar codes, due to their unique structure, became the first constructive coding scheme that could be rigorously proven to achieve channel capacity using mathematical methods. They exhibit good error level performance and low encoding / decoding complexity, attracting scholarly attention. Some studies have investigated the performance of polar codes as flash memory ECC (Error Checking and Correction).

[0004] SC (Serial Cancellation) decoding is a classic decoding algorithm for polar codes. Based on the recursive coding structure of polar codes, it determines the value of each bit by traversing a full binary tree constructed from positional information. SCL (Serial Cancellation List) decoding is an improvement on SC decoding, aiming to enhance both accuracy and efficiency. SCL decoding significantly improves decoding performance by retaining multiple possible decoding paths and selecting the optimal path at each step, while sacrificing some complexity. The basic idea of ​​SCL decoding is to retain not just one optimal path at each decoding step, but L optimal paths in a list. These paths are sorted according to a path metric, typically calculated based on the log-likelihood ratio (LLR). At each step, the algorithm selects L optimal paths to continue decoding until a preset termination condition is met. Finally, the path with the highest path metric is selected as the decoding result. The decoding performance and complexity can be flexibly adjusted by changing the list length L.

[0005] However, current work on polar code ECC mainly focuses on planar flash memory, and the decoding algorithms are too simple, often directly using existing soft decoding algorithms in the field of communication, without taking into account the unique error characteristics of three-dimensional NAND flash memory, and thus failing to effectively balance decoding performance and decoding overhead. Summary of the Invention

[0006] To address the shortcomings and improvement needs of existing technologies, this invention provides a dynamic error correction method, controller, and storage system suitable for 3D NAND flash memory. The purpose is to flexibly adjust the list length of the decoding algorithm during the decoding process, taking into account the error characteristics of 3D NAND flash memory, while utilizing polar code encoding, so as to minimize overhead while ensuring that error correction requirements are met.

[0007] To achieve the above objectives, according to one aspect of the present invention, a dynamic error correction method suitable for three-dimensional NAND flash memory is provided, comprising: an encoding stage and a decoding stage;

[0008] The encoding stage includes: polar code encoding of the data to be written to the 3D NAND flash memory to obtain a codeword sequence of a preset length N; N=2 x x is a natural number;

[0009] The decoding stage includes: for data of length N read from the three-dimensional NAND flash memory, calculating the LLR value corresponding to each bit to obtain N bits of soft information; after setting the list length of the SCL decoding algorithm, inputting the N bits of soft information into the SCL decoding algorithm to achieve decoding;

[0010] Setting the list length for the SCL decoding algorithm includes the following steps:

[0011] S1. Determine the current raw bit error rate of the three-dimensional NAND flash memory, and obtain the bit error rate of the SCL decoding algorithm under different list lengths under the current raw bit error rate. Select the list lengths with bit error rates lower than the preset performance threshold to obtain the list length candidate set.

[0012] S2. Set the list length of the SCL decoding algorithm to the minimum length in the candidate list length set.

[0013] Furthermore, the interval between steps S1 and S2 also includes:

[0014] Obtain the bit error rate of the LDPC decoding algorithm under the current raw bit error rate as a reference benchmark;

[0015] Remove list lengths from the candidate list lengths whose corresponding bit error rate is higher than the reference benchmark;

[0016] If the candidate list length is empty, then the preset maximum list length is added to it.

[0017] Furthermore, the dynamic error correction method for three-dimensional NAND flash memory provided by the present invention further includes: plotting the curves of the bit error rate of the LDPC decoding algorithm and the SCL decoding algorithm under different list lengths as a function of the original bit error rate in the same two-dimensional coordinate system, and obtaining the intersection points of the curve corresponding to the LDPC decoding algorithm and the other curves; the horizontal and vertical coordinates of the two-dimensional coordinate system are the original bit error rate and the bit error rate of the decoding algorithm, respectively.

[0018] Using the original bit error rate corresponding to each intersection point as the boundary, multiple original bit error rate ranges are obtained;

[0019] SCL decoding algorithms with lower bit error rates than LDPC decoding algorithms are selected within each original bit error rate range, and the lengths of the list of SCL decoding algorithms selected within each original bit error rate range are used to form the preferred length set corresponding to the original bit error rate range.

[0020] Furthermore, list lengths with corresponding bit error rates higher than the reference baseline are removed from the candidate list length set, including:

[0021] Determine the range of raw bit error rates to which the current raw bit error rate belongs, and obtain the corresponding preferred length set as the current preferred length set;

[0022] Remove list lengths from the list length candidate set that are not currently preferred from the list length candidate set.

[0023] Furthermore, the SCL decoding algorithm is set according to the ECC capability requirements, which include decoding delay and decoding capability;

[0024] Furthermore, when ECC capability requirements focus more on decoding latency, the SCL decoding algorithm is the Fast-SCL algorithm; when ECC capability requirements focus more on decoding capability, the SCL decoding algorithm is the CA-SCL algorithm.

[0025] Furthermore, the data to be written to the 3D NAND flash memory is encoded using polar codes, including:

[0026] The reliability of each symbol in an N-bit binary symbol sequence after encoding is evaluated using a beta-expansion method. The R×N bits with the highest reliability are used as the information channel, and the remaining (1-R)×N bits are used as the freeze channel; R represents the code rate of the flash memory system in which the three-dimensional NAND flash memory is located.

[0027] The data to be written to the 3D NAND flash memory is divided into multiple data blocks according to R×N;

[0028] For each data block, R×N symbols are filled into the information channel, and the known (1-R)×N frozen bits are filled into the freeze channel, resulting in an N-bit binary symbol sequence U = {u1, u2, ..., u...} N After that, a recursive XOR operation is performed to obtain an N-bit binary symbol sequence Y = {y1, y2, ..., y}. N};

[0029] The recursive XOR operation includes the following steps:

[0030] T1. For a binary symbol sequence A = {a1, a2, ..., a...} M If its length M>1, then proceed to step T2; otherwise, end the current binary symbol sequence.

[0031] T2. According to the binary symbol sequence A = {a1, a2, ..., a...}, M} can be converted into a binary symbol sequence B = {b1, b2, ..., b} M The conversion method is as follows:

[0032]

[0033] T3. For the binary symbol sequence B = {b1, b2, ..., b...} M The symbols in the} are sorted so that the odd-numbered sign bits and the even-numbered sign bits are located in the first half and the second half, respectively;

[0034] T4. Divide the sorted binary symbol sequence B into two equal binary symbol sequences, and perform a recursive XOR operation on each of the resulting binary symbol sequences.

[0035] in, This indicates the XOR operation.

[0036] According to another aspect of the present invention, a dynamic error correction controller for three-dimensional NAND flash memory is provided, comprising a computer-readable storage medium and a processor; the computer-readable storage medium is used to store a computer program, and the processor is used to read the computer program stored in the computer-readable storage medium and execute the dynamic error correction method for three-dimensional NAND flash memory provided by the present invention.

[0037] According to another aspect of the present invention, a storage system is provided, comprising: a three-dimensional NAND flash memory and the dynamic error correction controller for three-dimensional NAND flash memory provided by the present invention.

[0038] In summary, the above-described technical solutions conceived in this invention can achieve the following beneficial effects:

[0039] (1) In the case of polar code encoding, the present invention uses the SCL decoding algorithm to decode the data read from the three-dimensional NAND flash memory, which can achieve better decoding performance. Before decoding, the list length that can meet the error correction requirements is determined according to the current original bit error rate of the three-dimensional flash memory, and the smallest list length is selected from it. This can adapt to the error situation of different layers in the three-dimensional NAND flash memory, reduce the decoding overhead and reduce the decoding delay while ensuring that the error correction requirements are met.

[0040] (2) LDPC (Low-Density Parity-Check) codes are a highly efficient error correction coding scheme widely used in NAND flash memory, primarily to improve the reliability of data storage. Due to its good balance between error correction capability and implementation complexity, LDPC codes have become the mainstream choice for many modern storage systems. In a preferred embodiment of this invention, the decoding performance of LDPC codes is used as a reference benchmark. List lengths with decoding performance lower than the reference benchmark are removed from the list lengths that can meet the error correction requirements. This allows the SCL decoding algorithm to have better decoding performance while meeting the error correction requirements.

[0041] (3) In a further preferred embodiment of the present invention, by plotting the curves of the bit error rate of the LDPC decoding algorithm and the SCL decoding algorithm under different list lengths in the same two-dimensional coordinate system, the intersection point of the curve corresponding to the LDPC decoding algorithm and the other curves is obtained. This intersection point will be used as the standard for switching the list length, thereby quickly determining the list length that makes the decoding performance of the SCL decoding algorithm better than that of the LDPC decoding algorithm. Attached Figure Description

[0042] Figure 1 A schematic diagram of the existing polar code encoding process;

[0043] Figure 2 This is a schematic diagram of the existing polar code decoding process; where (a), (b), and (c) represent three operations in different decoding processes, respectively.

[0044] Figure 3 A schematic diagram of a dynamic error correction method for three-dimensional NAND flash memory provided in an embodiment of the present invention;

[0045] Figure 4 A schematic diagram showing the changes in bit error rate as a function of the original bit error rate for the LDPC decoding algorithm and Fast-SCL decoding algorithm provided in the embodiments of the present invention under different list lengths;

[0046] Figure 5 The diagram shows the curves of the bit error rate of the LDPC decoding algorithm and CA-SCL decoding algorithm provided in the embodiments of the present invention as a function of the original bit error rate under different list lengths. Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0048] In this invention, the terms "first," "second," etc. (if present) in the invention and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0049] Before explaining the technical solution of this invention in detail, let's briefly introduce the traditional polar code encoding and decoding methods.

[0050] In polar code encoding, the original information data string is encoded using polar codes to obtain the encoded data string. Taking a total data length of 32 as an example... Figure 1 As shown, the reliability of the 32-bit data after encoding is first pre-evaluated using a beta-expansion method, and the data is sorted. Based on the code rate R required by the storage system where the 3D NAND flash memory is located, R×32 bits are selected as the information data, and the remaining (1-R)×32 bits are selected as the frozen channel to store the known frozen bits (usually 0). Then, assuming the original information symbols are {u1, u2, ..., u...} 32First, perform an XOR operation on pairs of u1 and u2. For example, for u1 and u2, we get: s1 = u1 ⊕ u2, s2 = u2, where ⊕ represents the XOR operation. Then, perform bit reordering so that the original odd-numbered bits are in the first half and the original even-numbered bits are in the second half. After bit reordering, the information symbols are evenly divided into subsequences {s1, s2, ..., s2}. 16} and {s 17 s 18 , ..., s 32 The above XOR-reordering-splitting steps are recursively performed on the subsequence until it cannot be split any further, resulting in {y1, y2, ..., y}. 32 After encoding, a data string of length 32 will be obtained.

[0051] Traditional decoding methods such as Figure 2 As shown, the sequence of symbols to be decoded is organized into a decoding tree. The leaf nodes of the decoding tree correspond to a single symbol, while the internal nodes are sequences of symbols or symbol sequences composed of their child nodes. During decoding, starting from the root node of the decoding tree, using the initial LLR value of the channel as the raw information, the information to be passed to the left child node is first calculated using formula f, such as... Figure 2 As shown in (a), where sgn(·) represents the sign function. After the hard decision value is calculated from the soft information of the left subtree and returned upwards, the soft information of the right child node is calculated using the g formula, as follows. Figure 2 As shown in (b) above. After the right subtree obtains the hard decision value through soft information, a final reverse encoding operation is performed to restore the hard decision value, as shown below. Figure 2 As shown in (c) in the figure.

[0052] The SCL (successive cancellation list) decoding algorithm introduces a list into the decoding algorithm described above. During decoding, it starts from the root node of the code tree and searches for paths layer by layer towards the leaf nodes. After each layer expansion, it retains as many paths as possible (the number of paths retained at each layer does not exceed the list length L), and selects the L paths with the smallest path metric (PM) to be stored in the list, awaiting expansion to the next layer. When L=1, the SCL decoding algorithm degenerates into the SC decoding algorithm. The longer the list length, the better the decoding performance, but the corresponding storage overhead and decoding latency are also higher.

[0053] Current work on polar code ECC mainly focuses on planar flash memory. When using the SCL decoding algorithm, a fixed list length is often set according to decoding performance requirements. However, with the same list length, the decoding performance of the SCL decoding algorithm varies with the raw bit error rate (RBER). In 3D NAND flash memory, due to inter-layer differences, the RBER differs between layers, and the RBER changes differently over time within different layers. A fixed list length may result in the decoding algorithm failing to meet error correction requirements in some layers, or incurring additional overhead in others. To address this technical problem, this invention provides a dynamic error correction method, controller, and storage system suitable for 3D NAND flash memory. The overall concept is to flexibly adjust the list length of the decoding algorithm during the decoding process, taking into account the error characteristics of 3D NAND flash memory, the raw bit error rate, error correction requirements, and decoding overhead, thereby minimizing overhead while ensuring that error correction requirements are met.

[0054] The following is an example.

[0055] Example 1:

[0056] A dynamic error correction method suitable for 3D NAND flash memory, such as Figure 3 As shown, it includes: the encoding stage and the decoding stage;

[0057] The encoding stage includes: polar code encoding of the data to be written to the 3D NAND flash memory to obtain a codeword sequence of a preset length N; N=2 x x is a natural number;

[0058] The decoding stage includes: for data of length N read from the three-dimensional NAND flash memory, calculating the LLR value corresponding to each bit to obtain N bits of soft information; after setting the list length of the SCL decoding algorithm, inputting the N bits of soft information into the SCL decoding algorithm to achieve decoding;

[0059] Setting the list length for the SCL decoding algorithm includes the following steps:

[0060] S1. Determine the current raw bit error rate of the three-dimensional NAND flash memory, and obtain the bit error rate of the SCL decoding algorithm under different list lengths under the current raw bit error rate. Select the list lengths with bit error rates lower than the preset performance threshold to obtain the list length candidate set.

[0061] S2. Set the list length of the SCL decoding algorithm to the minimum length in the candidate list length set.

[0062] In this embodiment, the data is encoded in the same way as in the traditional method during the encoding stage.

[0063] In practical applications, the specific SCL decoding algorithm selected can be set according to the actual ECC capability requirements, which include decoding latency and decoding capability. In this embodiment, compared to decoding capability, the ECC capability requirement focuses more on decoding latency. Accordingly, the SCL decoding algorithm is the Fast-SCL algorithm to obtain lower decoding latency. It should be noted that the Fast-SCL decoding algorithm is only one optional SCL decoding algorithm of this invention and should not be construed as the only limitation of this invention. In other embodiments of this invention, other SCL decoding algorithms with flexibly adjustable list lengths can also be selected.

[0064] The decoding performance of the Fast-SCL decoding algorithm varies with different list lengths. Furthermore, even with the same list length, the decoding performance of the Fast-SCL decoding algorithm also differs when the RBER (Relative Power Requirement) is different. Figure 4 As shown.

[0065] In practical applications, the RBER of NAND flash memory is related to the current number of erase / write operations and the retention time. There are already relevant models for estimating the RBER of NAND flash memory. After obtaining the current number of erase / write operations and the retention time, inputting them into the corresponding model will yield the current RBER of the three-dimensional NAND flash memory.

[0066] In this embodiment, when the data is encoded with polar codes, the SCL decoding algorithm is selected to decode the data read from the three-dimensional NAND flash memory, which can achieve better decoding performance. Before decoding, the list length that can meet the error correction requirements is determined according to the current original bit error rate of the three-dimensional flash memory, and the smallest list length is selected from it. This can adapt to the error situation of different layers in the three-dimensional NAND flash memory, reduce decoding overhead and decoding latency while ensuring that the error correction requirements are met.

[0067] LDPC (Low-Density Parity-Check) codes are a highly efficient error correction coding scheme widely used in NAND flash memory, primarily to improve data storage reliability. Due to their good balance between error correction capability and implementation complexity, LDPC codes have become the mainstream choice for many modern storage systems. To further improve decoding performance, as a preferred implementation, this embodiment uses the decoding performance of the LDPC decoding algorithm as a reference benchmark when setting the list length for the Fast-SCL decoding algorithm, aiming to ensure that the set list length allows the Fast-SCL decoding algorithm to achieve decoding performance superior to the LDPC decoding algorithm. Accordingly, steps S1 and S2 also include:

[0068] Obtain the bit error rate of the LDPC decoding algorithm under the current raw bit error rate as a reference benchmark;

[0069] Remove list lengths from the candidate list lengths whose corresponding bit error rate is higher than the reference benchmark;

[0070] If the candidate list length is empty, then the preset maximum list length is added to it.

[0071] Based on the above operations, when the list length reaches the preset maximum list length (usually set to 32) and the RBER rises to the maximum error correction capability of the polar code, the performance of dynamic polar codes is inferior to LDPC because LDPC is in the waterfall region. At this time, the list length is still set to this maximum list length to get as close as possible to the decoding performance of LDPC.

[0072] To quickly determine the relationship between the decoding performance of the Fast-SCL decoding algorithm and the LDPC decoding algorithm under different list lengths, as a preferred implementation, this embodiment further includes: plotting the bit error rate (BER) of the LDPC decoding algorithm and the Fast-SCL decoding algorithm as a function of the original BER under different list lengths in the same two-dimensional coordinate system, and obtaining the intersection points of the curve corresponding to the LDPC decoding algorithm with the other curves, such as... Figure 4 As shown, "FLL" represents fixed list length; the horizontal and vertical axes of the two-dimensional coordinate system represent the original bit error rate (RBER) and the bit error rate (BER) of the decoding algorithm, respectively.

[0073] Using the original bit error rate corresponding to each intersection point as the boundary, multiple original bit error rate ranges are obtained;

[0074] SCL decoding algorithms with lower bit error rates than LDPC decoding algorithms are selected within each original bit error rate range, and the lengths of the list of SCL decoding algorithms selected within each original bit error rate range are used to form the preferred length set corresponding to the original bit error rate range.

[0075] Furthermore, list lengths with corresponding bit error rates higher than the reference baseline are removed from the candidate list length set, including:

[0076] Determine the range of raw bit error rates to which the current raw bit error rate belongs, and obtain the corresponding preferred length set as the current preferred length set;

[0077] Remove list lengths from the list length candidate set that are not currently preferred from the list length candidate set.

[0078] This embodiment plots the bit error rate (BER) of the LDPC decoding algorithm and the SCL decoding algorithm as a function of the original BER under different list lengths in the same two-dimensional coordinate system. The intersection point of the LDPC decoding algorithm's curve with the other curves is obtained, and this intersection point will be used as the standard for switching list lengths. For example, if the current list length is 2... xWhen RBER increases to 2 (x-1) When the decoding capability intersects with the LDPC code at a point, the list length will be reduced to 2. (x-1) This indicates that 2 (x-1) Its decoding capabilities are sufficient to complete the decoding task.

[0079] Example 2:

[0080] A dynamic error correction method suitable for 3D NAND flash memory. This embodiment is similar to Embodiment 1 above, except that in this embodiment, ECC capability requirements are more focused on decoding capability than decoding latency. Therefore, in this embodiment, the CA-SCL algorithm is specifically selected for SCL decoding to obtain higher decoding capability.

[0081] In this embodiment, curves showing the bit error rate (BER) of the LDPC decoding algorithm and the CA-SCL decoding algorithm as a function of the original BER under different list lengths are plotted in the same two-dimensional coordinate system. The intersection points of the curve corresponding to the LDPC decoding algorithm and the other curves are obtained, such as... Figure 5 As shown, "FLL" stands for fixed list length.

[0082] In this embodiment, the specific implementation of the remaining steps can be referred to the description in Embodiment 1 above, and will not be repeated here.

[0083] Example 3:

[0084] A dynamic error correction controller for 3D NAND flash memory includes a computer-readable storage medium and a processor; the computer-readable storage medium is used to store a computer program, and the processor is used to read the computer program stored in the computer-readable storage medium and execute the dynamic error correction method for 3D NAND flash memory provided in Embodiment 1 or 2 above.

[0085] Example 4:

[0086] A storage system includes: a three-dimensional NAND flash memory and a dynamic error correction controller for three-dimensional NAND flash memory provided in Embodiment 3 above.

[0087] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A dynamic error correction method suitable for three-dimensional NAND flash memory, characterized in that, include: Encoding stage and decoding stage; The encoding stage includes: performing polar code encoding on the data to be written to the three-dimensional NAND flash memory to obtain a length of preset length. N The codeword sequence; N =2 x , x It is a natural number; The decoding stage includes: for the length read from the three-dimensional NAND flash memory, the decoding process ... N The data is used to calculate the LLR value corresponding to each bit, resulting in... N Bit-soft information; after setting the list length of the SCL decoding algorithm, the... N The soft information is input into the SCL decoding algorithm to achieve decoding; The step of setting the list length for the SCL decoding algorithm includes the following steps: S1. Determine the original bit error rate of each layer of the three-dimensional NAND flash memory, and obtain the bit error rate of the SCL decoding algorithm under different list lengths under the original bit error rate of each layer, and filter out the list lengths with bit error rates lower than the preset performance threshold to obtain a list length candidate set; S2. Set the list length of the SCL decoding algorithm to the minimum length in the candidate list length set.

2. The dynamic error correction method for three-dimensional NAND flash memory as described in claim 1, characterized in that, The step between step S1 and step S2 also includes: Obtain the bit error rate of the LDPC decoding algorithm under the current raw bit error rate as a reference benchmark; Remove list lengths from the candidate list lengths whose corresponding bit error rates are higher than the reference benchmark; If the candidate list length is empty, then the preset maximum list length is added to it.

3. The dynamic error correction method for three-dimensional NAND flash memory as described in claim 2, characterized in that, Also includes: Plot the curves of the bit error rate of the LDPC decoding algorithm and the SCL decoding algorithm with different list lengths under the same two-dimensional coordinate system, and obtain the intersection points of the curve corresponding to the LDPC decoding algorithm and the other curves. The horizontal and vertical coordinates of the two-dimensional coordinate system are the original bit error rate and the bit error rate of the decoding algorithm, respectively. Using the original bit error rate corresponding to each intersection point as the boundary, multiple original bit error rate ranges are obtained; SCL decoding algorithms with lower bit error rates than LDPC decoding algorithms within each original bit error rate range are selected, and the lengths of the list of SCL decoding algorithms selected within each original bit error rate range are used to form the preferred length set corresponding to the original bit error rate range. Furthermore, removing list lengths from the candidate list length set whose corresponding bit error rate is higher than the reference benchmark includes: Determine the range of raw bit error rates to which the current raw bit error rate belongs, and obtain the corresponding preferred length set as the current preferred length set; Remove list lengths from the list length candidate set that do not belong to the current preferred length set.

4. The dynamic error correction method for three-dimensional NAND flash memory as described in any one of claims 1 to 3, characterized in that, The SCL decoding algorithm is set according to the ECC capability requirements, which include decoding delay and decoding capability. Furthermore, when the ECC capability requirement focuses more on decoding latency, the SCL decoding algorithm is the Fast-SCL algorithm; when the ECC capability requirement focuses more on decoding capability, the SCL decoding algorithm is the CA-SCL algorithm.

5. The dynamic error correction method for three-dimensional NAND flash memory as described in claim 1, characterized in that, The data to be written to the three-dimensional NAND flash memory is encoded using polar codes, including: Evaluation using beta-expansion method N Each symbol in the bit binary symbol sequence represents its reliability level after encoding, and the one with the highest reliability is selected. R × N Bits serve as information channels, and the remaining (1- R )× N Bits are used to freeze the channel; R This indicates the bit rate of the flash memory system containing the three-dimensional NAND flash memory; according to R × N The data to be written to the three-dimensional NAND flash memory is divided into multiple data blocks; For each data block, take its portion R × N Symbols are filled into the information channel, and the known (1- R )× N Frozen bits are filled into the frozen channel to obtain N The binary symbol sequence U={ u 1, u 2, ..., u N After that, perform a recursive XOR operation to obtain... N The binary symbol sequence Y = { y 1, y 2, ..., y N }; The recursive XOR operation includes the following steps: T1, for a binary symbol sequence A={ a 1, a 2, ..., a M }, if its length M If the value is greater than 1, proceed to step T2; otherwise, end the current binary symbol sequence. T2, according to the binary symbol sequence A={ a 1, a 2, ..., a M } Convert to a binary symbol sequence B={ b 1, b 2, ..., b M The conversion method is as follows: T3, For the binary symbol sequence B={ b 1, b 2, ..., b M The symbols in the} are sorted so that the odd-numbered sign bits and the even-numbered sign bits are located in the first half and the second half, respectively; T4. Divide the sorted binary symbol sequence B into two binary symbol sequences in equal proportions, and perform the recursive XOR operation on each of the resulting binary symbol sequences. in, This indicates the XOR operation.

6. A dynamic error correction controller for three-dimensional NAND flash memory, characterized in that, The method includes a computer-readable storage medium and a processor; the computer-readable storage medium is used to store a computer program, and the processor is used to read the computer program stored in the computer-readable storage medium and execute the dynamic error correction method applicable to three-dimensional NAND flash memory as described in any one of claims 1 to 5.

7. A storage system, characterized in that, include: Three-dimensional NAND flash memory and the dynamic error correction controller for three-dimensional NAND flash memory as described in claim 6.

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