Data transmission method and device, electronic equipment and storage medium

Abstract

The invention provides a data transmission method and device, electronic equipment and a storage medium, and the method comprises the steps: splitting source data to obtain a plurality of data blocks; acquiring a plurality of pieces of routing information from the first processor to the second processor; one piece of routing information is added to each data block in the multiple data blocks, and the routing information added to different data blocks is different; and forwarding the data packet corresponding to each data block to the switching chip according to the routing information corresponding to each data block, so that the switching chip forwards the data packet to the next routing node according to the routing information until the data packet is transmitted to the second processor. Therefore, by splitting the source data into the plurality of data blocks, adding one piece of routing information from the source-end processor to the destination-end processor to each data block, and transmitting each data block to the destination-end processor according to the routing information corresponding to each data block, the data transmission rate between the processors is improved through parallel transmission.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a data transmission method, device, electronic device and storage medium. Background Art

[0002] The Serial Rapid IO (SRIO) protocol is a serial communication protocol that supports a minimum transmission rate of 1.25Gb / s and a maximum transmission rate of 10Gb / s. With the development of communication technology, more and more scenarios require large data exchange between chips. Since higher transmission rates require more expensive hardware support, the use of this protocol in the field of large-scale data transmission is limited. Although the SRIO protocol supports high-speed data transmission, it cannot meet the demand for large-scale data transmission. Summary of the invention

[0003] This application proposes a data transmission method, device, electronic device and storage medium. The specific scheme is as follows:

[0004] In one aspect, an embodiment of the present application provides a data transmission method, which is executed by a first processor. The method includes:

[0005] Split the source data to obtain multiple data blocks;

[0006] Acquire multiple routing information from the first processor to the second processor;

[0007] Adding a piece of routing information to each of the multiple data blocks, wherein the routing information added to different data blocks is different;

[0008] According to the routing information corresponding to each data block, the data packet corresponding to each data block is forwarded to the switching chip, so that the switching chip forwards the data packet to the next routing node according to the routing information until it is transmitted to the second processor.

[0009] Optionally, forwarding the data packet corresponding to each data block to the switching chip according to the routing information corresponding to each data block includes:

[0010] Read the routing information added to each data block, and add the routing information to the header of the data packet corresponding to each data block;

[0011] According to the routing information, the data packet is forwarded to the switching chip, so that the switching chip forwards the data packet to the next routing node according to the routing information until it is transmitted to the second processor.

[0012] Optionally, a piece of routing information is added to each of the multiple data blocks, including:

[0013] Compress each data block to obtain a compressed data block;

[0014] Add a routing information at the end of the compressed data block.

[0015] Optionally, the method further comprises:

[0016] Get the information that any data block returned by the switching chip fails to pass the verification;

[0017] According to the routing information corresponding to any data block, any data block continues to be transmitted to the second processor.

[0018] Optionally, the routing information includes the address of each routing node on the transmission path.

[0019] Another aspect of the present application provides a data transmission method, which is executed by a second processor. The method includes:

[0020] Acquire a plurality of data packets transmitted in parallel by the first processor;

[0021] The data blocks in multiple data packets are reassembled to obtain source data.

[0022] Optionally, data blocks in multiple data packets are reassembled to obtain source data, including:

[0023] Decompressing the compressed data blocks in each data packet to obtain the data blocks corresponding to each data packet;

[0024] Reorganize multiple data blocks to obtain source data.

[0025] Optionally, data blocks in multiple data packets are reassembled to obtain source data, including:

[0026] Verify each data packet;

[0027] When multiple data packets are verified, the compressed data blocks in each data packet are decompressed to obtain the data blocks corresponding to each data packet;

[0028] Reorganize multiple data blocks to obtain source data.

[0029] Another aspect of the present application provides an electronic device, including: a first processor, a second processor, and a switching chip, wherein a hardware topology structure between the first processor, the second processor, and the switching chip supports multiple routing information between the first processor and the second processor;

[0030] The first processor is used to split the source data to obtain multiple data blocks; obtain multiple routing information from the first processor to the second processor; add a routing information to each of the multiple data blocks, wherein the routing information added to different data blocks is different; and forward the data packet corresponding to each data block to the switching chip according to the routing information corresponding to each data block;

[0031] A switching chip, used to forward the data packet to the next routing node according to the routing information until it is transmitted to the second processor;

[0032] The second processor is used to obtain multiple data packets transmitted in parallel by the first processor; and reorganize the data blocks in the multiple data packets to obtain source data.

[0033] Optionally, the first processor is configured to:

[0034] Read the routing information added to each data block, and add the routing information to the header of the data packet corresponding to each data block;

[0035] According to the routing information, the data packet is forwarded to the switching chip.

[0036] Optionally, the first processor is configured to:

[0037] Compress each data block to obtain a compressed data block;

[0038] Add a routing information at the end of the compressed data block.

[0039] Optionally, the first processor is configured to:

[0040] Get the information that any data block returned by the switching chip fails to pass the verification;

[0041] According to the routing information corresponding to any data block, any data block continues to be transmitted to the second processor.

[0042] Optionally, the second processor is configured to:

[0043] Decompressing the compressed data blocks in each data packet to obtain the data blocks corresponding to each data packet;

[0044] Reorganize multiple data blocks to obtain source data.

[0045] Optionally, the second processor is configured to:

[0046] Verify each data packet;

[0047] When multiple data packets are verified, the compressed data blocks in each data packet are decompressed to obtain the data blocks corresponding to each data packet;

[0048] Reorganize multiple data blocks to obtain source data.

[0049] Optionally, the routing information includes the address of each routing node on the transmission path.

[0050] In another aspect, an embodiment of the present application provides a data transmission device, which is applied to a first processor, and includes:

[0051] A splitting module is used to split the source data to obtain multiple data blocks;

[0052] A first acquisition module, used to acquire multiple routing information from the first processor to the second processor;

[0053] An adding module, used for adding a piece of routing information to each of the multiple data blocks, wherein the routing information added to different data blocks is different;

[0054] The forwarding module is used to forward the data packet corresponding to each data block to the switching chip according to the routing information corresponding to each data block, so that the switching chip forwards the data packet to the next routing node according to the routing information until it is transmitted to the second processor.

[0055] Optionally, the forwarding module is used to:

[0056] Read the routing information added to each data block, and add the routing information to the header of the data packet corresponding to each data block;

[0057] According to the routing information, the data packet is forwarded to the switching chip, so that the switching chip forwards the data packet to the next routing node according to the routing information until it is transmitted to the second processor.

[0058] Optionally, add modules for:

[0059] Compress each data block to obtain a compressed data block;

[0060] Add a routing information at the end of the compressed data block.

[0061] Optionally, the device may further include:

[0062] The second acquisition module is used to obtain information that any data block returned by the switching chip fails to pass the verification;

[0063] The forwarding module is further used to continue transmitting any data block to the second processor according to the routing information corresponding to any data block.

[0064] Optionally, the routing information includes the address of each routing node on the transmission path.

[0065] In another aspect, an embodiment of the present application provides a data transmission device, which is applied to a second processor, and the device includes:

[0066] An acquisition module, used for acquiring a plurality of data packets transmitted in parallel by the first processor;

[0067] The reassembly module is used to reassemble the data blocks in multiple data packets to obtain source data.

[0068] Optionally, a recombinant module is used to:

[0069] Decompressing the compressed data blocks in each data packet to obtain the data blocks corresponding to each data packet;

[0070] Reorganize multiple data blocks to obtain source data.

[0071] Optionally, a recombinant module is used to:

[0072] Verify each data packet;

[0073] When multiple data packets are verified, the compressed data blocks in each data packet are decompressed to obtain the data blocks corresponding to each data packet;

[0074] Reorganize multiple data blocks to obtain source data.

[0075] Another aspect of the present application is a processor-readable storage medium, wherein the processor-readable storage medium stores a computer program, and the computer program is used to enable the processor to execute the data transmission method described in the above embodiment.

[0076] According to another aspect of the present application, a computer program product is provided. When instructions in the computer program product are executed by a processor, the aforementioned data transmission method is implemented.

[0077] The present application has the following technical effects: by splitting the source data into multiple data blocks, and adding a routing information from the source processor to the destination processor to each data block, each data block is transmitted to the destination processor according to the routing information corresponding to each data block, thereby improving the data transmission rate between processors through parallel transmission.

[0078] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present application, nor is it intended to limit the scope of the present application. Other features of the present application will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0079] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0080] Figure 1 A flowchart of a data transmission method provided in an embodiment of the present application;

[0081] Figure 2 A schematic diagram of a topological structure between a processor and a switching chip provided in an embodiment of the present application;

[0082] Figure 3 A schematic diagram of adding routing information to a data block provided in an embodiment of the present application;

[0083] Figure 4 A flowchart of another data transmission method provided in an embodiment of the present application;

[0084] Figure 5 A schematic diagram of a transmission protocol data packet format provided in an embodiment of the present application;

[0085] Figure 6 A flowchart of another data transmission method provided in an embodiment of the present application;

[0086] Figure 7 A schematic diagram of a data transmission process provided in an embodiment of the present application;

[0087] Figure 8 A schematic diagram of the structure of a data transmission device provided in an embodiment of the present application;

[0088] Fig. 9 A schematic diagram of the structure of another data transmission device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0089] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0090] With the development of communication technology, there are more and more scenarios where big data needs to be exchanged between chips. Since higher transmission rates require more expensive hardware support, the use of this protocol in the field of large-scale data transmission is limited. Although the SRIO protocol supports high-speed data transmission, it cannot meet the needs of large-scale data transmission.

[0091] Based on this, an embodiment of the present application proposes a data transmission method, which splits the source data into multiple data blocks, and adds a routing information from the source processor to the destination processor to each data block, and transmits each data block to the destination processor according to the routing information corresponding to each data block, thereby improving the data transmission rate between processors through parallel transmission.

[0092] The following describes the data transmission method, device, electronic device and storage medium of the embodiments of the present application with reference to the accompanying drawings.

[0093] Figure 1 A flowchart of a data transmission method provided in an embodiment of the present application.

[0094] The data transmission method according to the embodiment of the present application may be executed by the first processor.

[0095] like Figure 1 As shown, the data transmission method includes:

[0096] Step 101, split the source data to obtain multiple data blocks.

[0097] In the present application, the first processor is a source-end processor, and the first processor can split the source data to be transmitted into multiple data blocks, so that the size of each data block is appropriate to meet the data size of the data transmission protocol.

[0098] The size of each data block may be the same or different, and there is no limitation on this.

[0099] Step 102: Acquire multiple pieces of routing information from the first processor to the second processor.

[0100] In the present application, the hardware topology structure between the processor and the switching chip in the electronic device supports multiple routing information, the first processor is the source processor, and the second processor is the destination source processor, then the hardware topology structure between the first processor, the second processor and the switching chip supports multiple routing information between the first processor and the second processor.

[0101] For ease of understanding, the following Figure 2 To explain, Figure 2 A schematic diagram of a topological structure between a processor and a switching chip provided in an embodiment of the present application. Figure 2 The topology between three processors and four switch chips is shown.

[0102] In the present application, the routing table may include routing information from the first processor to the second processor, and may also include routing information between other processors, etc. The first processor may obtain multiple routing information from the first processor to the second processor from the routing table.

[0103] The routing information from the first processor to the second processor may include the address of each routing node on the transmission path from the first processor to the second processor.

[0104] The amount of the acquired routing information may be the same as the amount of the data blocks.

[0105] As a possible implementation manner, multiple pieces of routing information from the first processor to the second processor may be acquired in sequence from the routing table.

[0106] As another possible implementation manner, multiple pieces of routing information from the first processor to the second processor may be randomly selected from the routing table.

[0107] As another possible implementation, a piece of routing information from the first processor to the second processor can be selected from the routing table for the first data block, and then a piece of routing information from the first processor to the second processor can be selected from the remaining routing information for the second data block, until a piece of routing information from the first processor to the second processor is selected for the last data block.

[0108] Optionally, in the present application, each piece of routing information in the routing table may have a corresponding identifier, so that different routing information may be distinguished by the identifier, and then the corresponding routing information may be accurately obtained from the routing table by the identifier of the routing information.

[0109] Step 103: adding a piece of routing information to each of the multiple data blocks, wherein the routing information added to different data blocks is different.

[0110] In the present application, multiple pieces of routing information acquired in sequence may be added to the first data block, the second data block, and finally the last data block respectively.

[0111] For ease of understanding, the following Figure 3 To explain, Figure 3 A schematic diagram of adding routing information to a data block provided in an embodiment of the present application. Figure 3 As shown, the source data block is split into data block 1, data block 2 and data block 3, routing information 1 in the routing table is added to data block 1, routing information 2 is added to data block 2, and routing information 3 is added to data block 3.

[0112] Optionally, a piece of routing information can be selected from the routing table for the first data block, and the routing information can be added to the first data block. Then, a piece of routing information can be selected from the remaining routing information and added to the second data block, until a piece of routing information is selected from the remaining routing information for the last data block and the routing information is added to the last data block.

[0113] Step 104: forward the data packet corresponding to each data block to the switching chip according to the routing information corresponding to each data block, so that the switching chip forwards the data packet to the next routing node according to the routing information until it is transmitted to the second processor.

[0114] The data packet corresponding to each data block may be obtained by encapsulating each data block and the routing information corresponding to each data block by the first processor.

[0115] In the present application, the data packet corresponding to each data block may refer to a data packet of the transport layer in the data transmission protocol.

[0116] In the present application, the first processor can determine the next routing node according to the routing information added to each data block. The next routing node of the first processor is a switching chip. The first processor forwards the data packet corresponding to each data block to the corresponding switching chip according to the address of the switching chip in the routing information. After the switching chip receives the data packet, it can determine the next routing node according to the routing information in the data packet, and forward the data packet to the next routing node according to the address of the next routing node in the routing information. The next routing node continues to forward according to the routing information until the data packet is transmitted to the second processor.

[0117] For example, the routing information added to a data block is A1->A2->A3->A4, where A1 represents the first processor, A4 represents the second processor, A2 and A3 represent switching chips, and A1 determines that the next routing node is switching chip A2 according to the routing information. A1 forwards the data packet corresponding to the data block to switching chip A2, and A2 determines that the next routing node is switching chip A3 according to the routing information. A2 forwards the data packet corresponding to the data block to A3, and A3 determines that the next routing node is A4 according to the routing information. A3 forwards the data packet corresponding to the data block to A4.

[0118] In an embodiment of the present application, the source data is split to obtain multiple data blocks, and multiple routing information from the first processor to the second processor is obtained, and a routing information is added to each of the multiple data blocks, and then the data packet corresponding to each data block is forwarded to the switching chip according to the routing information corresponding to each data block, so that the switching chip forwards the data packet to the next routing node according to the routing information until it is transmitted to the second processor. Thus, by splitting the source data into multiple data blocks, and adding a routing information from the source end processor to the destination end processor to each data block, and transmitting each data block to the destination end processor according to the routing information corresponding to each data block, the data transmission rate between processors is improved through parallel transmission.

[0119] Figure 4A flowchart of another data transmission method provided in an embodiment of the present application.

[0120] The data transmission method according to the embodiment of the present application may be executed by the first processor.

[0121] like Figure 4 As shown, the data transmission method includes:

[0122] Step 401, split the source data to obtain multiple data blocks.

[0123] Step 402: Acquire multiple pieces of routing information from the first processor to the second processor.

[0124] Step 403: Add a piece of routing information to each of the multiple data blocks, wherein the routing information added to different data blocks is different.

[0125] In the present application, steps 401 to 403 can refer to the relevant contents recorded in the above embodiments, so they will not be repeated here.

[0126] Step 404: read the routing information added to each data block, and add the routing information to the header of the data packet corresponding to each data block.

[0127] In the present application, the first processor can add routing information at the end of each data block. During the transmission process, for each data block, the added routing information can be read, and according to the data transmission protocol, the routing information can be added to the header of the data packet corresponding to each data block.

[0128] In the present application, the data transmission protocol may include a logical layer, a transport layer and a physical layer. At the transport layer, the routing information at the end of the read data block may be added to the header of the data packet.

[0129] To facilitate understanding, the following Figure 5 To explain, Figure 5 A schematic diagram of a transmission protocol data packet format provided in an embodiment of the present application. Figure 5In the data packet format of the logical layer, the fields Ftype (indicating the transaction being requested), Transaction, Size (length, equal to the length of the encoded transaction), SourceTID (source transaction ID), and DataPayload (data load) may be added to the header of the transport layer data packet. The routing unit field may indicate the routing information of the data packet from the source processor to the destination processor. The transport layer data packet may also include the fields TT (indicating the mechanism type of the transmission address), Target Address (target address, indicating the address of the device to which the packet should be transmitted), Source Address (source address, indicating the address of the device generating the packet), Logical layer (logical layer data), etc. The physical layer data packet format may include the fields S (indicating whether this is a packet or a control symbol), AckID (indicating which packet the fabric will confirm with a control symbol), Prio (indicating the packet priority used for flow control), Rsrv, Prio (indicating the packet priority used for flow control), Logical and Transaction layer (transport layer data), and CRC (cyclic redundancy check code).

[0130] Step 405: forward the data packet to the switching chip according to the routing information, so that the switching chip forwards the data packet to the next routing node according to the routing information until it is transmitted to the second processor.

[0131] In the present application, step 405 can refer to the relevant contents recorded in the above embodiment, so it will not be repeated here.

[0132] In the embodiment of the present application, the routing information added to each data block can be read, the routing information can be added to the header of the data packet corresponding to each data block, and the data packet can be forwarded to the switching chip according to the routing information, so that the switching chip forwards the data packet to the next routing node according to the routing information until it is transmitted to the second processor. Thus, by adding the routing information to the header of the data packet, each routing node on the transmission path can transmit the data block to the next routing node according to the routing information, thereby realizing the parallel transmission of multiple data blocks to the destination processor, and improving the data transmission rate between processors.

[0133] In one embodiment of the present application, the first processor may first compress each data block to obtain a compressed data block, then add a routing information to the end of the compressed data block, and forward the data packet corresponding to each compressed data block to the switching chip according to the routing information corresponding to each compressed data block. The switching chip may forward the data packet to the next routing node according to the routing information until it is transmitted to the second processor.

[0134] The data packet corresponding to each compressed data block may be obtained by encapsulating the compressed data block and the routing information added at the end.

[0135] In the embodiment of the present application, the transmission rate can be further improved by adding routing information after compressing the data block and transmitting the compressed data block according to the routing information.

[0136] In one embodiment of the present application, during the transmission process of each data block, the routing node on the transmission path can verify each data block after receiving the data packet corresponding to the data block. If any data block fails the verification, the information that failed the verification can be returned to the previous routing node until it is returned to the first processor by the switching chip. The first processor then obtains the information that any data block returned by the switching chip that failed the verification, and then continues to transmit the data block to the second processor according to the routing information corresponding to the data block until it is transmitted to the second processor and passes the verification.

[0137] It should be noted that, in the present application, verifying a data block can be understood as verifying a data packet carrying the data block. If the data packet verification passes, it can be considered that the data block verification passes.

[0138] Optionally, a cyclic redundancy check (CRC for short) may be performed on the data block.

[0139] In an embodiment of the present application, if the first processor obtains information that any data block returned by the switching chip fails to pass the verification, it can continue to transmit any data block to the second processor according to the routing information corresponding to any data block, thereby improving the security of data transmission while realizing parallel data transmission.

[0140] Figure 6 A flowchart of another data transmission method provided in an embodiment of the present application.

[0141] The data transmission method according to the embodiment of the present application may be executed by the second processor.

[0142] like Figure 6 As shown, the data transmission method includes:

[0143] Step 601: Acquire multiple data packets transmitted in parallel by a first processor.

[0144] In the present application, the second processor can obtain multiple data packets transmitted in parallel by the first processor.

[0145] Step 602, reorganize the data blocks in the multiple data packets to obtain source data.

[0146] In the present application, after acquiring multiple data packets, the second processor may parse each data packet to obtain a data block, and reassemble the multiple data blocks in sequence to obtain source data.

[0147] Optionally, the first processor may compress each data block before transmitting, and after receiving multiple data packets transmitted by the first processor, the second processor may parse each data packet to obtain a compressed data block, and decompress each compressed data block to obtain a data block corresponding to each data packet, and then reassemble the multiple data packets obtained by decompression in order to obtain source data. Thus, the source data is obtained by decompression and reassembly.

[0148] Optionally, each data packet can be verified. If multiple data packets pass the verification, the compressed data in each data packet can be decompressed to obtain the data block corresponding to each data packet. The multiple data blocks can then be reassembled in sequence to obtain the source data, thereby improving data security.

[0149] In an embodiment of the present application, multiple data packets transmitted in parallel by the first processor can be obtained, and data blocks in the multiple data packets can be reorganized to obtain source data, thereby realizing parallel transmission of data and improving the data transmission rate between processors.

[0150] To facilitate understanding, the following Figure 7 To explain, Figure 7 A schematic diagram of a data transmission process provided in an embodiment of the present application.

[0151] like Figure 7 As shown, the source data of processor A needs to be transmitted to processor B. Processor A can split the source data to obtain 4 data blocks, so that each data block can be of appropriate size to meet the data size of the transmission protocol, and compress each data block to obtain compressed data blocks a, b, c and d to reduce the data transmission size. Then, routing information routing 1, routing 2, routing 3, and routing n are added to the compressed data blocks a, b, c and d respectively. Processor A can transmit the data packet corresponding to the compressed data block to the switching chip according to the routing information corresponding to each compressed data block, and the switching chip continues to forward the data packet to the next routing node according to the routing information until it is transmitted to processor B. After processor B obtains the 4 compressed data blocks, it can decompress the 4 compressed data blocks respectively, and reassemble the decompressed data blocks to obtain the destination data.

[0152] During the transmission process, the routing nodes on the transmission path can perform CRC check on each compressed data block to ensure the accuracy of data transmission. After the check passes, each data block is decompressed and reassembled into a source data block.

[0153] In order to implement the above embodiment, the embodiment of the present application further provides an electronic device. The electronic device includes a first processor, a second processor and a switching chip, wherein the switching chip may be one or more, and the hardware topology structure between the first processor, the second processor and the switching chip supports multiple routing information between the first processor and the second processor.

[0154] The first processor is used to split the source data to obtain multiple data blocks; obtain multiple routing information from the first processor to the second processor; add a routing information to each of the multiple data blocks, wherein the routing information added to different data blocks is different; and forward the data packet corresponding to each data block to the switching chip according to the routing information corresponding to each data block;

[0155] A switching chip, used to forward the data packet to the next routing node according to the routing information until it is transmitted to the second processor;

[0156] The second processor is used to obtain multiple data packets transmitted in parallel by the first processor; and reorganize the data blocks in the multiple data packets to obtain source data.

[0157] In a possible implementation manner of the embodiment of the present application, the first processor is configured to:

[0158] Read the routing information added to each data block, and add the routing information to the header of the data packet corresponding to each data block;

[0159] According to the routing information, the data packet is forwarded to the switching chip.

[0160] In a possible implementation manner of the embodiment of the present application, the first processor is configured to:

[0161] Compress each data block to obtain a compressed data block;

[0162] Add a routing information at the end of the compressed data block.

[0163] In a possible implementation manner of the embodiment of the present application, the first processor is configured to:

[0164] Get the information that any data block returned by the switching chip fails to pass the verification;

[0165] According to the routing information corresponding to any data block, any data block continues to be transmitted to the second processor.

[0166] In a possible implementation manner of the embodiment of the present application, the second processor is configured to:

[0167] Decompressing the compressed data blocks in each data packet to obtain the data blocks corresponding to each data packet;

[0168] Reorganize multiple data blocks to obtain source data.

[0169] In a possible implementation manner of the embodiment of the present application, the second processor is configured to:

[0170] Verify each data packet;

[0171] When multiple data packets are verified, the compressed data blocks in each data packet are decompressed to obtain the data blocks corresponding to each data packet;

[0172] Reorganize multiple data blocks to obtain source data.

[0173] In a possible implementation of the embodiment of the present application, the routing information includes the address of each routing node on the transmission path.

[0174] It should be noted here that the electronic device provided in the embodiment of the present application can implement all the method steps implemented in the above-mentioned data transmission method embodiment, and can achieve the same technical effect. The parts and beneficial effects of this embodiment that are the same as the method embodiment will not be described in detail here.

[0175] In order to implement the above embodiment, the present application also provides a data transmission device, which can be applied to the first processor. Figure 8 A schematic diagram of the structure of a data transmission device provided in an embodiment of the present application.

[0176] like Figure 8 As shown, the data transmission device 800 includes:

[0177] A splitting module 810 is used to split the source data to obtain multiple data blocks;

[0178] A first acquisition module 820, configured to acquire multiple routing information from the first processor to the second processor;

[0179] An adding module 830, configured to add a piece of routing information to each of the plurality of data blocks, wherein the routing information added to different data blocks is different;

[0180] The forwarding module 840 is used to forward the data packet corresponding to each data block to the switching chip according to the routing information corresponding to each data block, so that the switching chip forwards the data packet to the next routing node according to the routing information until it is transmitted to the second processor.

[0181] In a possible implementation of the embodiment of the present application, the forwarding module 840 is used to:

[0182] Read the routing information added to each data block, and add the routing information to the header of the data packet corresponding to each data block;

[0183] According to the routing information, the data packet is forwarded to the switching chip, so that the switching chip forwards the data packet to the next routing node according to the routing information until it is transmitted to the second processor.

[0184] In a possible implementation of the embodiment of the present application, a module 830 is added to:

[0185] Compress each data block to obtain a compressed data block;

[0186] Add a routing information at the end of the compressed data block.

[0187] In a possible implementation of the embodiment of the present application, the device may further include:

[0188] The second acquisition module is used to obtain information that any data block returned by the switching chip fails to pass the verification;

[0189] The forwarding module 840 is further configured to continue transmitting any data block to the second processor according to the routing information corresponding to any data block.

[0190] In a possible implementation of the embodiment of the present application, the routing information includes the address of each routing node on the transmission path.

[0191] It should be noted here that the data transmission device provided in the embodiment of the present application can implement all the method steps implemented by the data transmission method embodiment on the above-mentioned first processor side, and can achieve the same technical effect. The parts and beneficial effects of this embodiment that are the same as the method embodiment will not be described in detail here.

[0192] In order to implement the above embodiment, the present application also provides another data transmission device, which can be applied to the second processor. Fig. 9 A schematic diagram of the structure of another data transmission device provided in an embodiment of the present application.

[0193] like Fig. 9 As shown, the data transmission device 900 includes:

[0194] An acquisition module 910, configured to acquire a plurality of data packets transmitted in parallel by the first processor;

[0195] The reassembly module 920 is used to reassemble the data blocks in multiple data packets to obtain source data.

[0196] In a possible implementation of the embodiment of the present application, the reorganization module 920 is used to:

[0197] Decompressing the compressed data blocks in each data packet to obtain the data blocks corresponding to each data packet;

[0198] Reorganize multiple data blocks to obtain source data.

[0199] In a possible implementation of the embodiment of the present application, the reorganization module 920 is used to:

[0200] Verify each data packet;

[0201] When multiple data packets are verified, the compressed data blocks in each data packet are decompressed to obtain the data blocks corresponding to each data packet;

[0202] Reorganize multiple data blocks to obtain source data.

[0203] It should be noted here that the data transmission device provided in the embodiment of the present application can implement all the method steps implemented by the data transmission method embodiment on the above-mentioned second processor side, and can achieve the same technical effect. The parts and beneficial effects of this embodiment that are the same as the method embodiment will not be described in detail here.

[0204] It should be noted that the division of units in the embodiments of the present application is schematic and is only a logical function division. There may be other division methods in actual implementation. In addition, each functional unit in each embodiment of the present application may be integrated into a processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0205] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a processor-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server, or a network side device, etc.) or a processor (processor) to perform all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, referred to as RAM), disk or optical disk and other media that can store program codes.

[0206] It should be noted here that the above-mentioned device provided in the embodiment of the present application can implement all the method steps implemented in the above-mentioned method embodiment, and can achieve the same technical effect. The parts and beneficial effects of this embodiment that are the same as those in the method embodiment will not be described in detail here.

[0207] On the other hand, an embodiment of the present application further provides a processor-readable storage medium, which stores a computer program, and the computer program is used to enable the processor to execute the above-mentioned data transmission method of the present application.

[0208] Among them, the above-mentioned processor-readable storage medium can be any available medium or data storage device that can be accessed by the processor, including but not limited to magnetic storage (such as floppy disks, hard disks, magnetic tapes, magneto-optical disks (MO)), optical storage (such as CD, DVD, BD, HVD, etc.), and semiconductor storage (such as ROM, EPROM, EEPROM, non-volatile memory (NANDFLASH), solid-state drive (SSD)), etc.

[0209] On the other hand, an embodiment of the present application further provides a computer program product, which implements the above-mentioned data transmission method of the present application when the instructions in the computer program product are executed by a processor.

[0210] In the description of this specification, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0211] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A data transmission method, characterized in that: Executed by a first processor, comprising: Split the source data to obtain multiple data blocks; Acquire multiple routing information from the first processor to the second processor; Adding a piece of routing information to each of the multiple data blocks, wherein the routing information added to different data blocks is different; According to the routing information corresponding to each of the data blocks, the data packet corresponding to each of the data blocks is forwarded to the switching chip, so that the switching chip forwards the data packet to the next routing node according to the routing information until it is transmitted to the second processor.

2. The method according to claim 1, characterized in that The step of forwarding the data packet corresponding to each data block to the switching chip according to the routing information corresponding to each data block includes: Reading the routing information added to each of the data blocks, and adding the routing information to the header of the data packet corresponding to each of the data blocks; According to the routing information, the data packet is forwarded to the switching chip, so that the switching chip forwards the data packet to the next routing node according to the routing information until it is transmitted to the second processor.

3. The method according to claim 1, characterized in that The adding a piece of routing information to each of the multiple data blocks comprises: Compressing each of the data blocks to obtain a compressed data block; A piece of routing information is added to the end of the compressed data block.

4. The method according to claim 1, characterized in that Also includes: Obtaining information that any data block returned by the switching chip fails to pass verification; Continue to transmit the any data block to the second processor according to the routing information corresponding to the any data block.

5. The method according to any one of claims 1 to 4, characterized in that The routing information includes the address of each routing node on the transmission path.

6. A data transmission method, characterized in that: Executed by the second processor, including: Acquire a plurality of data packets transmitted in parallel by the first processor; The data blocks in the multiple data packets are reassembled to obtain source data.

7. The method according to claim 6, characterized in that The step of reorganizing the data blocks in the plurality of data packets to obtain source data includes: Decompressing the compressed data block in each data packet to obtain a data block corresponding to each data packet; The plurality of data blocks are reassembled to obtain the source data.

8. The method according to claim 6, characterized in that The step of reorganizing the data blocks in the plurality of data packets to obtain source data includes: Verifying each of the data packets; When all the multiple data packets are verified, decompressing the compressed data block in each data packet to obtain a data block corresponding to each data packet; The plurality of data blocks are reassembled to obtain the source data.

9. An electronic device, characterized in that: include: A first processor, a second processor and a switching chip, wherein a hardware topology structure between the first processor, the second processor and the switching chip supports multiple routing information between the first processor and the second processor; The first processor is used to split the source data to obtain multiple data blocks; obtain multiple routing information from the first processor to the second processor; add a piece of routing information to each of the multiple data blocks, wherein different routing information is added to different data blocks; and forward the data packet corresponding to each data block to the switching chip according to the routing information corresponding to each data block; The switching chip is used to forward the data packet to the next routing node according to the routing information until it is transmitted to the second processor; The second processor is used to obtain multiple data packets transmitted in parallel by the first processor; and reorganize the data blocks in the multiple data packets to obtain the source data.

10. The electronic device according to claim 9, further characterized in that the first processor is used for: Reading the routing information added to each of the data blocks, and adding the routing information to the header of the data packet corresponding to each of the data blocks; According to the routing information, the data packet is forwarded to the switching chip.

11. The electronic device according to claim 9, further characterized in that the first processor is used for: Compressing each of the data blocks to obtain a compressed data block; A piece of routing information is added to the end of the compressed data block.

12. The electronic device according to claim 9, further characterized in that the first processor is used for: Obtaining information that any data block returned by the switching chip fails to pass verification; Continue to transmit the any data block to the second processor according to the routing information corresponding to the any data block.

13. The electronic device as claimed in claim 9, further characterized in that the second processor is used for: Decompressing the compressed data block in each data packet to obtain a data block corresponding to each data packet; The plurality of data blocks are reassembled to obtain the source data.

14. The electronic device as claimed in claim 9, further characterized in that the second processor is used for: Verifying each of the data packets; When all the multiple data packets are verified, decompressing the compressed data block in each data packet to obtain a data block corresponding to each data packet; The plurality of data blocks are reassembled to obtain the source data.

15. The electronic device as claimed in any one of claims 9 to 14, further characterized in that the routing information includes the address of each routing node on the transmission path.

16. A data transmission device, characterized in that: Applied to a first processor, comprising: A splitting module is used to split the source data to obtain multiple data blocks; A first acquisition module, used to acquire multiple routing information from the first processor to the second processor; An adding module, used for adding a piece of routing information to each of the multiple data blocks, wherein the routing information added to different data blocks is different; The forwarding module is used to forward the data packet corresponding to each data block to the switching chip according to the routing information corresponding to each data block, so that the switching chip forwards the data packet to the next routing node according to the routing information until it is transmitted to the second processor.

17. A data transmission device, characterized in that: Applied to a second processor, comprising: An acquisition module, used for acquiring a plurality of data packets transmitted in parallel by the first processor; The reassembly module is used to reassemble the data blocks in the multiple data packets to obtain source data.

18. A processor-readable storage medium, characterized in that: The processor-readable storage medium stores a computer program, and the computer program is used to enable the processor to execute any one of the methods described in claims 1-5, or to execute any one of the methods described in claims 6-8.

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