Programmable logic circuit device and construction method thereof

Abstract

In a conventional eFPGA, there are a first problem of reducing the size of a logic cell and improving the packaging logic density, and a second problem of reducing the speed difference with an ASIC as much as possible. According to the present embodiment, it is possible to provide a method for configuring a programmable logic circuit that assigns a gate-level netlist to a 4-input 3-output combinatorial logic cell covering three (n) nodes of a graph configuring the netlist and in which three 2-input (m-input) basic logic cells are combined, and that is represented by the netlist.

Description

Technical Field

[0001] The present invention relates to a programmable logic circuit device suitable for being mounted on an application specific integrated circuit (ASIC) such as a SoC (System on Chip) and a construction method thereof. Background Art

[0002] There is an IC (integrated circuit) product called ASIC (Application Specific Integrated Circuit) that is specially designed and manufactured for a specific purpose. ASIC is a semiconductor integrated circuit designed and manufactured to combine necessary logical functions for a specific machine or purpose, but there are cases where the logical functions carried cannot be changed after manufacturing.

[0003] However, in recent years, as ASICs have become larger and more expensive, there has been an increase in the number of people who want to modify logic or add new functions due to defects discovered after manufacturing. Therefore, people have gradually adopted a method of mounting programmable logic circuit blocks such as FPGA (Field Programmable Gate Array) devices on ASICs to modify defects or add functions. Here, the FPGA part mounted on the ASIC is called "embedded FPGA (eFPGA)".

[0004] The logic cells of previous eFPGAs use LUTs (Look-Up Tables) that directly represent truth tables. Regarding the memory used in the LUT, compared with the use of SRAM (Static Random Access Memory) in standard FPGAs that are not used on ASICs, it is not easy to design a large amount of small SRAM memory in ASICs. Therefore, FFs (Flip-Flops) are used in eFPGAs within ASICs. However, FFs usually require several times (for example, 6 to 10 times) the area of ​​SRAM, resulting in the area of ​​logic cells that can package the same amount of logic in eFPGAs being several times larger than that of standard FPGAs. Therefore, from the perspective of packaged logic density, there are certain problems.

[0005] In addition, a logic unit using a LUT can encapsulate logic functions up to the number of its inputs. For example, a 4-input LUT can encapsulate logic functions up to 4 variables. Moreover, the number of memories required to form a LUT is 2 times the power of the number of inputs, and if the number of inputs increases, the number of memories increases exponentially. On the other hand, the speed of the encapsulated logic circuit is proportional to the number of levels (logic levels) passing through the LUT. Generally speaking, there is a trade-off relationship in which if the number of inputs of the LUT is increased, the number of logic levels decreases, and if the number of inputs of the LUT is reduced, the number of logic levels increases.

[0006] Therefore, although reducing the number of inputs to the LUTs used in the logic cells of the eFPGA will also reduce the amount of memory used, which can lead to miniaturization, there is a concern that the speed may decrease due to the increase in the number of logic levels. If there is a speed difference between the eFPGA mounted on the ASIC and other parts of the ASIC, it will become difficult to control, so sometimes it is not desirable to reduce the speed of the circuit on the eFPGA. Summary of the invention

[0007] As described above, in conventional eFPGAs, there is a first issue of miniaturization of logic units (improving packaged logic density) and a second issue of minimizing the speed difference with ASICs, and therefore a programmable logic circuit that can simultaneously resolve these issues is needed.

[0008] The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a programmable logic circuit having a novel structure that can solve the above problems.

[0009] To solve the above problems, the inventors of the present invention have come to the idea that a structure of a logic unit different from a conventional LUT can be realized by focusing on the structure of a netlist as a representation form of a packaged logic circuit, thereby completing the present invention.

[0010] According to the present invention, the following inventions can be provided.

[0011] (1) A programmable logic circuit, characterized in that: The programmable logic circuit has basic logic units of nodes constituting a gate-level netlist. The basic logic unit is a programmable circuit formed by adding a programmable NOT circuit to the basic logic operation unit. It is programmable in such a way that the input and output of the basic logic unit are switched according to the connection relationship of the nodes in the netlist.

[0012] (2) The programmable logic circuit as described in (1) above, characterized in that: The programmable logic circuit has a combinational logic unit formed by combining a plurality of the basic logic units. The combinatorial logic unit has a plurality of basic logic units covering a plurality of nodes constituting a graph of a netlist.

[0013] (3) The programmable logic circuit as described in (2) above is characterized in that: The combinational logic cell is a (m-1)×n+1-input n-output logic cell formed by combining and connecting n m-input basic logic cells so as to switch input signals in order to express node connections of two or more patterns.

[0014] (4) The programmable logic circuit as described in (3) above is characterized in that: The combinatorial logic unit includes a switching circuit for switching the connection relationship of basic logic nodes in order to express two or more patterns of node connection relationships.

[0015] (5) The programmable logic circuit as described in (4) above is characterized in that: The switching circuit is a multiplexer.

[0016] (6) The programmable logic circuit as described in (3) above is characterized in that: The programmable logic circuit has a memory for storing switching information of the switching circuit. The switching information is information for programming the basic logic unit in accordance with the connection relationship of the nodes constituting the netlist.

[0017] (7) A method for constructing a programmable logic circuit, characterized in that: Assign the nodes that make up the gate-level netlist to logic cells that can be programmed. The input and output of the logic unit are switched programmably according to the connection relationship of the nodes.

[0018] (8) The method for constructing a programmable logic circuit as described in (7) above is characterized in that: The above method has the following steps: a process of assigning the gate-level netlist to a combinatorial logic unit covering n nodes of the graph constituting the netlist and combining n m-input basic logic units; and, The process of constructing the above-mentioned combinational logic unit into a (m-1)×n+1 input n output logic unit. In order to express more than two modes of connection relationship between the above-mentioned multiple covered nodes, the above-mentioned (m-1)×n+1 input n output logic unit combines n m-input basic logic units and connects them in a way that can switch input signals.

[0019] (9) The method as described in (8) above, characterized in that: The method further comprises the step of allocating the basic logic unit to the nodes of the gate-level netlist. The basic logic unit is a programmable circuit formed by adding a programmable NOT circuit to the basic logic operation unit. It is programmable in such a way that the input and output of the basic logic unit are switched according to the connection relationship of the nodes in the netlist.

[0020] (10) The method as described in (8) above, characterized in that The method further comprises the step of arranging a switching circuit for switching the connection relationship between the basic logic nodes in the combinatorial logic unit in order to realize two or more patterns of node connection relationship.

[0021] (11) The method as described in (9) above, characterized in that: The method further includes a step of programming a basic logic unit by matching the switching information of the connection relationship with the connection relationship of nodes constituting a netlist.

[0022] According to the present invention, the number of memories constituting logic can be suppressed to a number proportional to the number of inputs. Therefore, compared with the case where logic is constituted by a conventional SRAM-based LUT, logic can be constituted by a very small number of memories. In addition, since the speed of the packaged logic circuit depends on the netlist, the number of logic unit levels has little effect on the speed increase, unlike the case where the logic is constituted by the conventional LUT.

[0023] It should be noted that the following description of the embodiments and the accompanying drawings illustrate features and other structures of the present invention viewed from other aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 This is a schematic diagram showing technology mapping of the gate level when it is assigned to a conventional LUT.

[0025] Figure 2 This is a diagram showing the schematic structure of a conventional LUT.

[0026] Figure 3It is an explanatory diagram for explaining the concept of the present invention.

[0027] Figure 4 This is an explanatory diagram for explaining a connection pattern of nodes in one embodiment of the present invention.

[0028] Figure 5 A schematic structural diagram showing the structure of a 2-node 4-input combinational logic unit in one embodiment of the present invention.

[0029] Figure 6 It is an explanatory diagram for explaining process mapping of a gate-level netlist in one embodiment of the present invention.

[0030] Figure 7 This is a table showing the performance comparison between the conventional LUT and the logic unit of this embodiment.

[0031] Figure 8 This is a schematic diagram showing the structure of a PA circuit in one embodiment of the present invention.

[0032] Fig. 9 A schematic diagram showing a configuration example of a PX circuit based on different basic logic operation units in one embodiment of the present invention.

[0033] Fig.10 A schematic diagram showing a configuration example of a PX circuit based on different basic logic operation units in one embodiment of the present invention.

[0034] Fig.11 This is an explanatory diagram for explaining a node connection pattern implemented by a combinatorial logic unit in one embodiment of the present invention.

[0035] Fig.12 A schematic structural diagram showing a combinational logic unit in one embodiment of the present invention.

[0036] Fig.13 This is an explanatory diagram showing a connection pattern of four nodes in one embodiment of the present invention.

[0037] Fig.14 A schematic structural diagram showing a combinational logic unit in one embodiment of the present invention.

[0038] Fig.15 A schematic structural diagram showing a combinational logic unit in one embodiment of the present invention.

[0039] Fig.16 A schematic structural diagram showing a combinational logic unit in one embodiment of the present invention.

[0040] Fig.17A schematic structural diagram showing a combinational logic unit in one embodiment of the present invention.

[0041] Fig.18 This is an explanatory diagram showing a connection pattern of four nodes and a combination pattern of basic logic units in one embodiment of the present invention.

[0042] Fig.19 A schematic structural diagram showing a combinational logic unit in one embodiment of the present invention.

[0043] Fig. 20 An illustration showing a gate-level netlist.

[0044] Fig.21 This is an explanatory diagram of a case where a gate-level netlist is allocated to a conventional LUT.

[0045] Fig. 22 This is an explanatory diagram of a case where a gate-level netlist is allocated to a conventional LUT.

[0046] Fig.23 This is an explanatory diagram of a case where a gate-level netlist is allocated to a conventional LUT.

[0047] Fig.24 This is an explanatory diagram of a case where a gate-level netlist is allocated to a conventional LUT.

[0048] Fig.25 It is an explanatory diagram for explaining the process of allocating a gate-level netlist to a logic cell according to the embodiment of the present invention.

[0049] Fig.26 It is an explanatory diagram for explaining the process of allocating a gate-level netlist to a logic cell according to the embodiment of the present invention.

[0050] Fig. 27 It is an explanatory diagram for explaining the process of allocating a gate-level netlist to a logic cell according to the embodiment of the present invention. DETAILED DESCRIPTION

[0051] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

[0052] 1. Basic Concepts Generally, the performance of logic cells used in FPGAs is measured by how little logic a packaged circuit, ie, a gate-level netlist, can be covered with, and the operating speed of the covered logic cell-level netlist.

[0053] Here, the operation of covering the gate-level netlist with logic cells is called process mapping. In addition, the gate-level netlist is represented using a graph of NAND gates (NAND graph) and a graph of AND gates and NOT gates (AIG (AND-Inverter graph)).

[0054] Figure 1 (a) shows the process mapping of the gate-level netlist used to package the conventional LUT. Figure 2 In the case of the 3-input LUT (3-LUT) shown in (a), if Figure 2 As shown in (b), the SRAM is used as configuration memory (M), and the truth value stored in it is selected by input value (X, Y, X) and output (f). Such a LUT implements a logic function by storing a truth table in the configuration memory.

[0055] When using the above conventional LUT ( Figure 2 In the example of process mapping shown in (a), Figure 1 The logic functions of the output S and CO of (a) are converted into truth tables, and Figure 1 As shown in (b), they are respectively encapsulated in different LUTs (two 4-LUTs).

[0056] In contrast, the logic unit of the present embodiment focuses on the logic of the structure itself of the gate-level netlist.

[0057] That is, in one embodiment of the present invention, Figure 3 As shown in (a), for AIG (And Inverter Gate) as a gate-level netlist, the combination of AND gate (○) and NOT gate (the dotted line part of the edge) is understood as a node, and the connection between nodes is understood as an edge. Figure 3 (b) The basic logic unit (PA circuit: programmable "AND" circuit) shown in FIG. Figure 3 (c) is a conceptual diagram showing a combination of storage values ​​stored in memories M0 and M1 and an output f for programming a PA circuit.

[0058] If the number of nodes (the number of basic logic units) included in the combinatorial logic unit is set to, for example, 3 (4 inputs), the number of connection patterns between the above nodes (basic logic units) is Figure 4 There are three modes (a) to (c) of . That is, Figure 4 (a) is a mode where one PA circuit is located on the first layer and two PA circuits are located on the second layer. Figure 4 (b) is a mode in which three PA circuits are arranged in series over the first to third layers. Figure 4(c) is a mode in which two PA circuits are arranged in the first layer and one PA circuit is arranged in the second layer. Furthermore, if we consider a 4-input 3-output combinational logic unit (PAE circuit) that implements all of these three modes ( Figure 5 (a)) structure, then ( Figure 5 As shown in (b), three PA circuits (basic logic units) are connected in a switchable manner.

[0059] Thus, the "basic logic unit" and the "combinatorial logic unit" (hereinafter, sometimes also referred to as "PAE circuit") combining the basic logic units are the basis of the present invention.

[0060] Furthermore, if the PAE circuit described above is used to implement the above-mentioned conventional LUT example ( Figure 1 (a)) The same gate-level netlist, then Figure 6 As shown in (a) and (b).

[0061] 2. Performance comparison The performance comparison between a logic unit using a conventional LUT and the logic unit according to the present embodiment is shown in FIG. Figure 7 .

[0062] exist Figure 7 In the comparative example shown in (a), comparison is performed between logic cells having four inputs.

[0063] First, regarding the number of memories used, in the case of a conventional 4-input LUT (4LUT), the number of memories used is 16 bits, whereas the 4-input PAE circuit of this embodiment uses 8 bits, which is half of the conventional 4-input LUT (4LUT).

[0064] In addition, the average coverage of the netlist of this embodiment is 2.52 nodes, which exceeds the 2.43 nodes of LUT. Therefore, in the evaluation using 29 benchmark circuits in this embodiment, the average configuration memory reduction rate reached 51.6%, which can reduce the configuration memory by half. In addition, the maximum configuration memory reduction rate is 66.5%, and the minimum configuration memory reduction rate is 23.0%, which can reduce the memory compared with the previous LUT.

[0065] It should be noted that the logic unit, i.e., PAE, of this embodiment is not limited to 4 inputs as described above. For example, when the number of inputs is increased (equivalent to increasing the number of PA nodes in the logic unit), in this embodiment, the number of configuration memories of the logic unit is proportional to the number of PA nodes. On the other hand, since the number of configuration memories of the LUT is proportional to the exponential power of the number of inputs, the performance difference will be amplified.

[0066] Figure 7 (b) is a performance comparison between the present embodiment and the conventional logic unit when the number of inputs is 5. It can be seen that the configuration memory reduction rate of the present embodiment is 75.7% on average, 82.3% at the maximum, and 68.1% at the minimum, and the performance difference is widening.

[0067] Next, the basic logic unit, the combinational logic unit, and the mapping of the netlist of this embodiment are described in detail.

[0068] 3. About basic logic units First, the basic logic unit is described.

[0069] Although the basic logic unit (PA circuit) described in one of the basic concepts of the present invention is an example of realizing the AND gate and NOT gate in AIG, the basic logic unit of the present invention is a structure in which a "Px circuit" ("X" means not limited to an AND gate) with a programmable "NOT" circuit added to the basic logic operation unit, and is not limited to the PA circuit.

[0070] That is, as described above, the netlist representing the logic circuit is a graph representing the logic circuit in which the basic logic operation units such as AND gates, OR gates, and NOT gates are used as nodes and the above units are connected in the form of edges. A netlist made with NAND gates as nodes is called a NAND graph, and a netlist made with AND gates and NOT gates as nodes is called an AIG (AND-Inverter Graph). In addition, a netlist can be made even if NOR gates are used for nodes, or even if OR gates and NOT gates are used. That is, in this embodiment, if the nodes are complete logic function sets, all logic circuits can be expressed.

[0071] Therefore, first of all, for Figure 3 The programmable NOT circuit of the PA circuit shown in (b) can be Figure 8 As shown in (a), it can be realized by NOT gate and multiplexer, or as Figure 8 As shown in (b), it is realized by an XOR gate. In addition, in addition to the case where the original netlist uses AND gates and NOT gates as basic logic cells, a structure using other logic cells can also be formed as a Px circuit. Fig. 9 (a), (b), and (c) are embodiments of the Px circuit when a NAND gate, a NOR gate, and an OR gate are used as basic logic operation units, respectively.

[0072] In addition, if Fig.10 As shown in (a), programmable NOT circuits can be configured at all inputs of the Px circuit. In addition, Fig.10(b) is an example of using an AND gate in which the number of inputs to the basic logic unit is 3. In this way, the number of inputs to the basic logic unit is not limited to 2.

[0073] 4. About Combinational Logic Unit Although the combinatorial logic cell described in one of the basic concepts of the present invention has a 4-input 3-output structure, the combinatorial logic cell is not limited to the above structure, just as the number of inputs of the basic logic cell is not limited to 2.

[0074] That is, according to this embodiment, when a combinational logic unit is formed by combining two or more graphs obtained by connecting n m-input basic logic units, the number of inputs is (m-1)×n+1 inputs, and the number of outputs is n. m and n can be any number greater than 2.

[0075] Fig.12 The combinational logic unit 1 is shown when the number of inputs m of the basic logic unit (Px) is 2 and the number of connection units n is 3. The number of inputs of the combinational logic unit 1 is (m-1)×n+1=(2-1)×3+1=4, and the number of outputs is n, that is, 3.

[0076] In addition, if Fig.11 As shown in (a) to (c), the number of inputs of the basic logic unit is m = 2, and there are three modes of connection relationship of the graph obtained by connecting n = 3 such basic logic units (circles represent basic logic units). In order to realize such a plurality of node connection relationships, the present combinational logic unit 1 has the function of switching the connection relationship of the internal logic nodes through a multiplexer or a circuit equivalent thereto ( Fig.12 In addition, the combinational logic unit 1 has a memory ( Fig.12 The internal memory of the logic unit can be set in accordance with the connection shape of the nodes constituting the netlist (indicated by symbol 3).

[0077] It should be noted that the basic logic unit (Px circuit) may be not only the Px circuit including the programmable NOT circuit described above, but may also be a NAND gate or a NOR gate monomer.

[0078] Next, other embodiments of the combinatorial logic unit implemented according to the values ​​of m and n are described.

[0079] Example of connecting n = 4 basic logic units with m = 2 inputs like Fig.13 As shown, the number of inputs of the basic logic unit is set to m=2, and n=4 such basic logic units are connected to obtain 7 patterns (circles represent basic logic units (PX circuits)).

[0080] Combine these 7 modes Fig.13 (b) with Fig.13 (c) These two types of (2-1)×4+1=5-input 4-output combinational logic units form, for example Fig.14 The structure is shown by reference numeral 5. Here, similarly to the above, the basic logic unit Px may be a NAND gate or a NOR gate alone.

[0081] Fig.15 Shows the combination of the above 7 patterns Fig.13 (a) and (c) are examples of 5-input 4-output logic cells.

[0082] Likewise, Fig.16 Shown Fig.13 An embodiment of a combinational logic unit of (c) and (d). Fig.17 for Fig.13 (c) and (f) are examples of combinational logic units. It should be noted that, as in the above, the basic logic unit (Px circuit) may also be a single NAND gate or NOR gate.

[0083] An example of a logic unit composed of three or more basic logics The above example uses one combinational logic unit to implement the connection relationship between two basic logic units (nodes), but is not limited to two types, and one combinational logic unit can be used to implement more than two types of node connection relationships.

[0084] Fig.18 To achieve Fig.13 (a), (c), (d), and (f) are examples of connection of logical units of node connection relationships of the four modes. Fig.19 The following is an example of the structure of a combinational logic unit that implements the node connection relationship of these four modes.

[0085] It should be noted that, although the above example is a case where four basic logic units are included, the number n included may be any number.

[0086] 5. Process Mapping Method of This Implementation Next, a process mapping method using the above-mentioned combinatorial logic unit in this embodiment is described.

[0087] In a given Fig. 20 In the case of the netlist (AIG) shown, the order of process mapping using a normal LUT is as follows.

[0088] (1) Based on graph theory, the directed acyclic graph (DAG) of AIG is decomposed into a tree; (2) Map the tree to the LUT; (3) Select the next Tree and perform the above (2); (4) The process ends after mapping all trees.

[0089] Here, in (2) above, when mapping a tree to a LUT, the minimum cover is explored, but due to the decomposition into a tree, multiple nodes are repeated, and these repeated nodes are mapped to different LUTs respectively. Therefore, according to their degree of repetition, the number of LUTs after mapping will increase.

[0090] That is, Figures 21 to 24 As shown, Fig. 20 The DAG of the AIG shown can be decomposed into a tree with the input signal PO as the vertex. Since each tree is independently mapped to the LUT, multiple nodes are shared in two trees and thus mapped to the LUT multiple times. As a result, a total of 14 LUTs are required. As a result, the amount of configuration memory required is 16 bits × 14, that is, 224 bits.

[0091] On the other hand, the procedure of process mapping using the logic cell of this embodiment is as follows.

[0092] (1) From AIG Fig.25 Any match in the node graph of (a)(b)(c); (2) Mapping to logical units; (3) Perform (1) until all nodes are covered; (4) The process ends after all nodes are mapped.

[0093] If the mapping method is the same as above, press Fig.26 The 4-input 3-output combinational logic cell shown in Fig. 20 The netlist shown in the figure is mapped. Fig. 27 As shown. In the case of mapping to the logic unit of this embodiment, since the output from the node within the covered range can be used, there will be no situation where the object node is repeatedly covered. Therefore, in this example, 8 4-input 3-output combinational logic units (configuration memory number 8 bits) can be mapped, and the configuration memory amount is 8 bits × 8, that is, 64 bits. This is less than 1 / 3 of the case of using 4-LUT.

[0094] According to the structure described above, a programmable logic circuit (PAE and its combination) can be provided, which is a logic unit for an embedded FPGA mounted on an ASIC, having a basic logic unit (PX circuit) of nodes constituting a gate-level netlist, and the basic logic unit is a programmable circuit constituted by adding a programmable "NOT" circuit to a basic logic operation unit, and the programmable circuit is configured to switch the input and output of the basic logic unit according to the connection relationship of the nodes in the above-mentioned netlist.

[0095] According to the above structure, the number of memories constituting the logic can be suppressed to a number proportional to the number of inputs. Therefore, compared with the case where the logic is constituted by the conventional SRAM-based LUT, the logic can be constituted using a very small number of memories. In addition, since the speed of the packaged logic circuit depends on the netlist, the number of levels of the logic unit has less influence on the speed increase, unlike the case where the logic is constituted by the conventional LUT.

[0096] It should be noted that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention. Explanation of symbols

[0097] 1…Combinational Logic Unit 2…Multiplexer 3…Memory 5…Combinational Logic Unit PA…Basic Logic Unit PX…Basic logic unit.

Claims

1. A programmable logic circuit, characterized in that: The programmable logic circuit has basic logic units constituting nodes of a gate-level netlist. The basic logic unit is a programmable circuit formed by adding a programmable NOT circuit to the basic logic operation unit. It is programmable in such a way that the input and output of the basic logic unit are switched according to the connection relationship of the nodes in the netlist.

2. The programmable logic circuit according to claim 1, wherein: The programmable logic circuit has a combinational logic unit formed by combining a plurality of the basic logic units. The combinatorial logic unit has a plurality of basic logic units covering a plurality of nodes of a graph constituting a netlist.

3. The programmable logic circuit according to claim 2, characterized in that: The combinational logic unit is a (m-1)×n+1-input n-output logic unit formed by combining and connecting n m-input basic logic units in a manner capable of switching input signals in order to express two or more node connections.

4. The programmable logic circuit according to claim 3, characterized in that: The combinatorial logic unit includes a switching circuit for switching the connection relationship of basic logic nodes in order to realize two or more modes of node connection relationship.

5. The programmable logic circuit according to claim 4, characterized in that: The switching circuit is a multiplexer.

6. The programmable logic circuit according to claim 3, characterized in that: The programmable logic circuit has a memory for storing switching information of the switching circuit. The switching information is information for programming the basic logic unit in accordance with the connection relationship of the nodes constituting the netlist.

7. A method for constructing a programmable logic circuit, characterized in that: Assign the nodes that make up the gate-level netlist to logic cells that can be programmed. The input and output of the logic unit are programmably switched according to the connection relationship of the nodes.

8. The method for constructing a programmable logic circuit according to claim 7, wherein: The method comprises the following steps: A process of assigning a gate-level netlist to a combinatorial logic unit that covers n nodes of a graph constituting the netlist and combines n m-input basic logic units; and, The process of constructing the combinational logic unit into a (m-1)×n+1 input n output logic unit, wherein the (m-1)×n+1 input n output logic unit is a combination of n m-input basic logic units and connected in a manner capable of switching input signals in order to express more than two modes of connection relationship between the multiple covered nodes.

9. The method according to claim 8, characterized in that The method further comprises the step of allocating the basic logic unit to the nodes of the gate-level netlist. The basic logic unit is a programmable circuit formed by adding a programmable NOT circuit to the basic logic operation unit. It is programmable in such a way that the input and output of the basic logic unit are switched according to the connection relationship of the nodes in the netlist.

10. The method according to claim 8, characterized in that The method further comprises the step of arranging a switching circuit for switching the connection relationship between the basic logic nodes in the combinatorial logic unit in order to realize two or more patterns of node connection relationship.

11. The method according to claim 9, characterized in that The method further includes a step of programming a basic logic unit by matching the switching information of the connection relationship with the connection relationship of nodes constituting a netlist.

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