Fault isolation processing method and device for functional safety system of automotive chip

Abstract

The application provides a fault isolation processing method, device and equipment for a functional safety system of a vehicle chip, and a medium. The method comprises the following steps: determining a fault node to be isolated based on a circuit topology structure of the chip in a simulation process; constructing an isolation module capable of replacing a fault module corresponding to the fault node to be isolated based on the fault node to be isolated; constructing a binding relationship between the isolation module and the circuit structure of the chip; and mapping a fault injection signal to the fault module to the isolation module based on the binding relationship during the simulation process of the chip, so as to complete fault simulation of the chip. The application can realize that the verilog source code of the chip does not need to be damaged, the reliability of the circuit structure is not damaged, the simulation speed is fast, the reliability is high, and the fault isolation function required by the industry can be met in large-scale fault simulation.

Description

Technical Field

[0001] This invention relates to the field of chip design technology, and in particular to a fault isolation and handling method, apparatus, equipment and medium for automotive-grade chip functional safety systems. Background Technology

[0002] When developing chips, using fault injection at the simulation level to evaluate security mechanisms requires a significant amount of time to simulate the behavior of faulty modules in specific hardware. Moreover, security assessments are often only conducted after the chip is fabricated, which greatly increases the assessment cost. Therefore, simulation-level fault injection has become the most mainstream fault injection method in the industry.

[0003] Simulation-level fault injection techniques can be divided into destructive (instrument) and non-destructive (non-instrument) fault injection. The main difference between the two is whether or not destructive modifications are made to the source code of the circuit module used for fault simulation. Non-destructive fault injection techniques have become a popular choice due to their faster simulation speed and more reliable fault injection models. However, their non-destructive nature makes it difficult to meet the industry's requirements for fault isolation (fault isolation in computer systems or networks is the process of effectively isolating the faulty part from other parts of the system to ensure system stability and security). This is because Verilog's built-in mechanism performs port folding optimization during simulation, resulting in two different node variables actually sharing the same value when externally assigned. In circuit simulation, this manifests as the fault's impact propagating backward, which contradicts the circuit propagation mode required by industry standards. Industry believes that the actual fault transmission behavior of a chip will not propagate backward to its driver side, but only forward. However, because non-destructive fault injection techniques do not change the source code, the simulator often performs port folding optimization after compilation, making it impossible to isolate the impact of the fault during simulation assignment operations. Destructive fault injection techniques often introduce a large number of circuit structures into the fault behavior of analog circuits. Although fault isolation can be achieved by inserting buffs in this process, the resulting reduction in simulation speed and the reliability of the circuit after modifying the source code are undeniable disadvantages.

[0004] Invention Content

[0005] To address the problems existing in the prior art, this invention provides a fault isolation and handling method, apparatus, equipment, and medium for automotive-grade chip functional safety systems.

[0006] This invention provides a fault isolation and handling method for an automotive-grade chip functional safety system, comprising:

[0007] Based on the circuit topology of the chip during the simulation process, the fault nodes that need to be isolated are identified.

[0008] Based on the faulty nodes that need to be isolated, an isolation module is constructed that can replace the faulty module corresponding to the faulty node that needs to be isolated.

[0009] Establish the binding relationship between the isolation module and the circuit structure of the chip;

[0010] During the simulation of the chip, based on the binding relationship, the fault injection signal for the faulty module is mapped onto the isolation module to complete the fault simulation of the chip.

[0011] According to the present invention, a fault isolation method for a functional safety system of an automotive-grade chip is provided, wherein determining the fault node to be isolated based on the circuit topology of the chip during simulation includes:

[0012] The VPI interface is used to automatically analyze the circuit topology and identify all potential backpropagation fault nodes;

[0013] By iteratively traversing from top to bottom, the connection relationships between ports of fault modules corresponding to all potential backpropagation fault nodes are obtained, thus obtaining a set of connection relationships;

[0014] Based on the port folding mechanism of the Verilog language and the set of connection relationships, the faulty nodes that need to be isolated are selected from all potential backpropagation faulty nodes.

[0015] According to the present invention, a fault isolation processing method for an automotive-grade chip functional safety system, wherein the method comprises constructing an isolation module capable of replacing the fault module corresponding to the fault node to be isolated based on the fault node to be isolated, including:

[0016] Analyze the inputs and outputs of the fault modules corresponding to the fault nodes that need to be isolated;

[0017] Obtain the instantiation parameters of the fault module corresponding to the fault node that needs to be isolated;

[0018] The isolation module is constructed based on the instantiation parameters, inputs, and outputs of the fault module.

[0019] According to the fault isolation processing method of the automotive-grade chip functional safety system provided by the present invention, the step of establishing the binding relationship between the circuit structure of the isolation module and the chip includes:

[0020] The isolation module is externally programmed using SystemVerilog's bind syntax, binding it to the chip's circuit structure. The output of the fault module in the chip's circuit structure is then changed to the output of the isolation module through VPI internal assignment.

[0021] According to the present invention, a fault isolation processing method for a functional safety system of an automotive-grade chip includes mapping a fault injection signal for the faulty module onto the isolation module based on the binding relationship, thereby completing fault simulation of the chip.

[0022] The packaging files for each isolation module are constructed and attached to the simulator's compilation and simulation stage in the form of SystemVerilog files. When injecting faults into fault modules that require fault isolation, the fault injection signals are mapped to the corresponding isolation modules with the same function to complete the fault simulation of the chip.

[0023] According to the present invention, a fault isolation method for a functional safety system of an automotive-grade chip includes, in the step of filtering out fault nodes to be isolated from all potential backpropagation fault nodes based on the port folding mechanism of Verilog language and the set of connection relationships, the method comprises:

[0024] Based on the port folding mechanism of the Verilog language, all port handles in the set of connections are accessed. If it is determined that the two variables connected inside and outside the port are both of type wire, then the fault node corresponding to the fault module where the port is located is the fault node that needs to be isolated.

[0025] According to the fault isolation processing method of the functional safety system of automotive-grade chip provided by the present invention, the step of obtaining the instantiation parameters of the fault module corresponding to the fault node to be isolated includes:

[0026] Use VPI to access the handle of the instantiated instance of the faulty module and obtain the instantiation parameters of the faulty module.

[0027] The present invention also provides a fault isolation and processing device for an automotive-grade chip functional safety system, comprising:

[0028] The screening module is used to identify fault nodes that need to be isolated based on the circuit topology of the chip during the simulation process.

[0029] The building module is used to build an isolation module that can replace the fault module corresponding to the fault node that needs to be isolated, based on the fault node that needs to be isolated.

[0030] An association module is used to establish the binding relationship between the isolation module and the circuit structure of the chip;

[0031] The processing module is used to map the fault injection signal of the fault module to the isolation module based on the binding relationship during the simulation of the chip, thereby completing the fault simulation of the chip.

[0032] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement a fault isolation processing method for any of the above-described automotive-grade chip functional safety systems.

[0033] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements a fault isolation processing method for any of the above-described automotive-grade chip functional safety systems.

[0034] The present invention also provides a computer program product, including a computer program, which, when executed by a processor, implements a fault isolation processing method for any of the above-described automotive-grade chip functional safety systems.

[0035] This invention provides a fault isolation processing method, apparatus, device, and medium for a functional safety system of automotive-grade chips. It constructs an isolation module based on the fault node to be isolated, capable of replacing the corresponding fault module. A binding relationship is established between the isolation module and the chip's circuit structure. During chip simulation, based on this binding relationship, fault injection signals to the fault module are mapped onto the isolation module, completing the chip's fault simulation. This achieves the goal of not damaging the chip's Verilog source code, preserving the reliability of the circuit structure, and offering fast simulation speed and high reliability. It can meet the fault isolation requirements of the industry in large-scale fault simulation. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0037] Figure 1 This is a flowchart illustrating the fault isolation and handling method for the automotive-grade chip functional safety system provided by the present invention.

[0038] Figure 2 This is a schematic diagram of the fault isolation and processing device for the automotive-grade chip functional safety system provided by the present invention;

[0039] Figure 3 This is a schematic diagram of the structure of the electronic device provided by the present invention. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0041] The following is combined with Figures 1-3 This invention describes a fault isolation processing method, apparatus, equipment, and medium for an automotive-grade chip functional safety system.

[0042] Figure 1 This diagram illustrates a fault isolation and handling method for an automotive-grade chip functional safety system provided by the present invention. (See attached diagram.) Figure 1 The method includes the following steps:

[0043] Step 11: Based on the circuit topology of the chip during the simulation process, determine the fault nodes that need to be isolated.

[0044] Step 12: Based on the faulty nodes that need to be isolated, construct an isolation module that can replace the faulty module corresponding to the faulty node that needs to be isolated.

[0045] Step 13: Establish the binding relationship between the isolation module and the chip's circuit structure.

[0046] Step 14: During the chip simulation process, based on the binding relationship, the fault injection signal of the faulty module is mapped to the isolation module to complete the fault simulation of the chip.

[0047] Regarding steps 11-14 above, it should be noted that the automotive-grade chip functional safety system aims to ensure that the chip can safely and reliably perform its intended functions throughout its entire lifecycle through a series of technical and management measures, avoiding safety hazards caused by systemic failures or random hardware malfunctions. With the increasing electrification and intelligence of automobiles, the use of automotive-grade chips has increased significantly, and their safety is directly related to the lives of drivers, passengers, and pedestrians. Therefore, ensuring the functional safety of chips is of paramount importance.

[0048] When developing chips, using fault injection at the simulation level to evaluate security mechanisms requires a significant amount of time to simulate the behavior of faulty modules in specific hardware. Moreover, security assessments are often only conducted after the chip is fabricated, which greatly increases the assessment cost. Therefore, simulation-level fault injection has become the most mainstream fault injection method in the industry.

[0049] Simulation-level fault injection techniques can be divided into destructive (instrument) and non-destructive (non-instrument) fault injection. The main difference between the two is whether or not destructive modifications are made to the source code of the circuit module used for fault simulation. Non-destructive fault injection techniques have become a popular choice due to their faster simulation speed and more reliable fault injection models. However, their non-destructive nature makes it difficult to meet the industry's requirements for fault isolation (fault isolation in computer systems or networks is the process of effectively isolating the faulty part from other parts of the system to ensure system stability and security). This is because Verilog's built-in mechanism performs port folding optimization during simulation, resulting in two different node variables actually sharing the same value when externally assigned. In circuit simulation, this manifests as the fault's impact propagating backward, which contradicts the circuit propagation mode required by industry standards. Industry believes that the actual fault transmission behavior of a chip will not propagate backward to its driver side, but only forward. However, because non-destructive fault injection techniques do not change the source code, the simulator often performs port folding optimization after compilation, making it impossible to isolate the impact of the fault during simulation assignment operations. Destructive fault injection techniques often introduce a large number of circuit structures into the fault behavior of analog circuits. Although fault isolation can be achieved by inserting buffs in this process, the resulting reduction in simulation speed and the reliability of the circuit after modifying the source code are undeniable disadvantages.

[0050] Therefore, this invention aims to insert isolation modules into the target circuit through incremental additional circuitry, thus avoiding damage to the original circuit structure while achieving the fault isolation requirements during simulation. To this end, the fault nodes requiring isolation are first determined based on the circuit topology of the chip during simulation. It should be noted that the chip's circuit structure contains multiple functional modules, and chip faults can occur at the port locations of these modules or within the modules themselves.

[0051] It's also important to note here that simulating chip safety testing requires modeling the chip's circuit structure. This involves executing code files within a simulator to simulate the chip's circuitry. Therefore, identifying faulty nodes can be done by selecting code segments from the code files representing the circuit modules on the chip.

[0052] In this invention, module faults can be monitored at certain fault nodes. Therefore, a correspondence exists between modules and fault nodes. After identifying the fault nodes requiring isolation, the corresponding fault modules in the chip's circuit structure can be determined. Following the design approach of inserting isolation modules into the original circuit through incremental additions, an isolation module capable of replacing the fault module corresponding to the fault node requiring isolation can be constructed. Here, the isolation module uses the `bind` syntax, allowing an externally written module to be bound to the fault module within the circuit for safe simulation testing without changing the source code. Therefore, a binding relationship needs to be established between the isolation module and the chip's circuit structure. Based on this binding relationship, the isolation module has the same circuit structure as the original module and possesses isolation functionality. This prevents port folding caused by Verilog's built-in mechanism, and fault injection within the isolation module avoids backpropagation of faults. Thus, during chip simulation, based on the binding relationship, the fault injection signal for the fault module is mapped to the isolation module, completing the chip's fault simulation.

[0053] A further method described above primarily explains the process of identifying fault nodes that need to be isolated based on the circuit topology of the chip during simulation, as detailed below:

[0054] The VPI interface is used to automatically analyze the circuit topology and identify all potential backpropagation fault nodes.

[0055] By iteratively traversing from top to bottom, the connection relationships between ports of faulty modules corresponding to all potential backpropagation fault nodes are obtained, thus obtaining a set of connection relationships.

[0056] Based on the port folding mechanism and connection set of the Verilog language, the faulty nodes that need to be isolated are selected from all potential backpropagation faulty nodes.

[0057] It should be noted that in this invention, for fault injection simulation, to achieve fault isolation, the system first needs to be able to automatically analyze and filter which fault points will cause backpropagation. This invention utilizes the VPI (Verilog programming language interface) to automatically analyze the circuit topology in the simulation and filter out all fault nodes that may cause backpropagation. The VPI example code allows external algorithms to access the connection relationships between ports of circuit modules. Specifically, through iterative traversal, the connection relationships between ports of fault modules corresponding to all potential backpropagation fault nodes are obtained from top to bottom, resulting in a set of connection relationships stored in a linked list structure of library functions for subsequent filtering and analysis.

[0058] Then, based on the port folding mechanism and connection set of the Verilog language, the fault nodes that need to be isolated are selected from all potential backpropagation fault nodes.

[0059] When both signal variables on either side of a Verilog port are of type wire, Verilog folds the variables on both sides of the port. During simulation, only the primary variable at the time of folding actually participates in the simulation; the values ​​of the folded secondary variables cannot differ from the primary variable values. Therefore, based on Verilog's port folding mechanism, all port handles in the connection set are accessed, and the variable types on both sides of the module port are filtered. If both variables are of type wire, then this port will experience backpropagation of the fault during simulation, and this type of port is saved to a new linked list. That is, the fault node corresponding to the faulty module where the port is located is the fault node that needs to be isolated.

[0060] In a further step of the above method, the process of constructing an isolation module that can replace the corresponding fault module based on the fault node that needs to be isolated is explained in detail below:

[0061] Analyze the inputs and outputs of the fault modules corresponding to the fault nodes that need to be isolated.

[0062] Obtain the instantiation parameters of the fault module corresponding to the fault node that needs to be isolated.

[0063] Based on the instantiation parameters, inputs, and outputs of the fault module, an isolation module is constructed.

[0064] It should be noted that while this invention has automatically identified all faulty ports requiring isolation through circuit structure analysis, the most crucial aspect is isolating the effects of these backpropagations. The reason faults propagate backward through module ports is due to Verilog's port folding mechanism. Therefore, from the simulation platform's perspective, the two folded variables actually share the same handle; they are essentially the same variable. This explains why it's impossible to assign different values ​​to two variables after compilation using other assignment methods. Therefore, this invention aims to achieve fault isolation without altering the Verilog circuit source code, utilizing the bind syntax combined with VPI library function algorithms.

[0065] The previously obtained set of ports that need to be isolated is processed and traversed. VPI library functions are used to analyze the faulty module in which it is located, and all inputs and outputs in the faulty module are obtained through traversal.

[0066] In addition, parameter passing is required for the isolated module. To ensure that the isolated module behaves exactly the same as the original module, the module's inputs, outputs, and instantiation parameters must be consistent with those in the faulty module of the original circuit. Therefore, VPI is used to access the handle of the instantiated instance of the faulty module to obtain its instantiation parameters.

[0067] Based on the instantiation parameters, inputs, and outputs of the fault module, a corresponding isolation module is created by passing and packaging these parameters, inputs, and outputs through a script. This isolation module has the same circuit structure as the original module but incorporates isolation functionality. By wrapping it with a port defined using logic, the port folding mechanism built into Verilog is prevented from occurring. Fault injection within the module avoids backpropagation of faults.

[0068] In a further step of the above method, the process of establishing the binding relationship between the isolation module and the chip's circuit structure is explained, as follows:

[0069] The system uses SystemVerilog's bind syntax to externally write the isolation module, binding it to the chip's circuit structure. The output of the fault module in the chip's circuit structure is then changed to the output of the isolation module through VPI internal assignment.

[0070] It should be noted that, in this invention, after obtaining all isolated instantiated modules, these modules need to be bound to the original circuit structure to replace the original non-isolated modules with modules that can be isolated and automatically generated by the algorithm.

[0071] In this invention, SystemVerilog provides the `bind` syntax to facilitate verification engineers in adding additional functions to the original circuit without modifying the source code, such as assertion coverage statistics. This syntax allows externally written modules to be bound to the internal circuit module for simulation without changing the source code. Therefore, using the `bind` syntax, the isolation module is externally written, bound to the chip's circuit structure, and the output of the faulty module in the chip's circuit structure is changed to the output of the isolation module through the VPI internal assignment method.

[0072] A further method described above primarily explains the process of mapping the fault injection signal from the faulty module to the isolation module based on the binding relationship, thereby completing the fault simulation of the chip. The details are as follows:

[0073] The packaging files for each isolation module are constructed and attached to the simulator's compilation and simulation stage in the form of SystemVerilog files. When injecting faults into fault modules that require fault isolation, the fault injection signals are mapped to the corresponding isolation modules with the same function to complete the fault simulation of the chip.

[0074] It should be noted that in this invention, the algorithm automatically analyzes the circuit structure, automatically generates a package file of the isolation module set, attaches it to the simulator compilation and simulation stage in the form of a SystemVerilog file, and automatically implements the mapping of isolation points in the algorithm. When injecting faults into fault modules that need to be isolated, the fault injection point is automatically mapped to the corresponding isolation module with the same function. Fault injection at the fault node of the isolation module will not cause back propagation, and the positive fault effect is consistent with the original circuit, thus realizing the fault isolation function.

[0075] The fault isolation processing method for automotive-grade chip functional safety systems provided by this invention constructs an isolation module that can replace the fault module corresponding to the fault node to be isolated based on the fault node to be isolated. It establishes a binding relationship between the isolation module and the chip's circuit structure. During chip simulation, based on the binding relationship, the fault injection signal for the fault module is mapped onto the isolation module to complete the chip fault simulation. This method does not require destroying the chip's Verilog source code and does not compromise the reliability of the circuit structure. It features fast simulation speed and high reliability, and can meet the fault isolation function required by the industry in large-scale fault simulation.

[0076] The fault isolation and processing device for automotive-grade chip functional safety systems provided by the present invention is described below. The fault isolation and processing device for automotive-grade chip functional safety systems described below can be referred to in correspondence with the fault isolation and processing method for automotive-grade chip functional safety systems described above.

[0077] Figure 2 This diagram illustrates a fault isolation and processing device for automotive-grade chip functional safety systems provided by the present invention. (See attached diagram.) Figure 2 The device includes a screening module 21, a construction module 22, an association module 23, and a processing module 24, wherein:

[0078] The screening module 21 is used to determine the fault nodes that need to be isolated based on the circuit topology of the chip during the simulation process.

[0079] Module 22 is used to build an isolation module that can replace the fault module corresponding to the fault node that needs to be isolated, based on the fault node that needs to be isolated.

[0080] The associated module 23 is used to establish the binding relationship between the circuit structure of the isolation module and the chip;

[0081] The processing module 24 is used to map the fault injection signal of the faulty module to the isolation module based on the binding relationship during the chip simulation process, thereby completing the fault simulation of the chip.

[0082] Since the apparatus of this embodiment is based on the same principle as the method of the above embodiment, more detailed explanations will not be repeated here.

[0083] It should be noted that, in the embodiments of the present invention, the relevant functional modules can be implemented by a hardware processor.

[0084] This invention provides a fault isolation processing device for automotive-grade chip functional safety systems. It constructs an isolation module based on the fault node requiring isolation, capable of replacing the corresponding fault module. A binding relationship is established between the isolation module and the chip's circuit structure. During chip simulation, based on this binding relationship, fault injection signals for the fault module are mapped onto the isolation module, completing the chip's fault simulation. This achieves the goal of not damaging the chip's Verilog source code, preserving the reliability of the circuit structure, and offering fast simulation speed and high reliability. It meets the fault isolation requirements of the industry in large-scale fault simulation.

[0085] Figure 3 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 3As shown, the electronic device may include a processor 31, a communication interface 32, a memory 33, and a communication bus 34. The processor 31, communication interface 32, and memory 33 communicate with each other via the communication bus 34. The processor 31 can call logic instructions in the memory 33 to execute a fault isolation processing method for automotive-grade chip functional safety systems. This method includes: determining the fault nodes to be isolated based on the circuit topology of the chip during simulation; constructing an isolation module that can replace the fault modules corresponding to the fault nodes to be isolated based on the fault nodes to be isolated; establishing a binding relationship between the isolation module and the chip's circuit structure; and mapping fault injection signals to the fault modules onto the isolation module based on the binding relationship during chip simulation, thereby completing the chip fault simulation.

[0086] Furthermore, the logical instructions in the aforementioned memory 33 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0087] On the other hand, the present invention also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the fault isolation processing method for automotive-grade chip functional safety systems provided by the above methods. The method includes: determining the fault nodes that need to be isolated based on the circuit topology of the chip during the simulation process; constructing an isolation module that can replace the fault modules corresponding to the fault nodes that need to be isolated based on the fault nodes that need to be isolated; establishing a binding relationship between the isolation module and the circuit structure of the chip; and mapping the fault injection signal for the fault module to the isolation module based on the binding relationship during the chip simulation process to complete the fault simulation of the chip.

[0088] In another aspect, the present invention also provides a non-transitory computer-readable storage medium storing a computer program thereon. When executed by a processor, the computer program is implemented to perform the fault isolation processing method for automotive-grade chip functional safety systems provided by the above methods. The method includes: determining the fault nodes to be isolated based on the circuit topology of the chip during simulation; constructing an isolation module that can replace the fault modules corresponding to the fault nodes to be isolated based on the fault nodes to be isolated; establishing a binding relationship between the isolation module and the circuit structure of the chip; and mapping fault injection signals to the fault modules onto the isolation module based on the binding relationship during the chip simulation process to complete the fault simulation of the chip.

[0089] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0090] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0091] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A fault isolation processing method for a functional safety system of an automotive chip, characterized by, The method comprises the following steps: determining the fault nodes to be isolated based on the circuit topology of the chip in the simulation process; constructing an isolation module capable of replacing the fault module corresponding to the fault nodes to be isolated based on the fault nodes to be isolated; constructing the binding relationship between the isolation module and the circuit structure of the chip; in the simulation process of the chip, based on the binding relationship, the fault injection signal to the fault module is mapped to the isolation module, and the fault simulation of the chip is completed; the method of determining the fault nodes to be isolated based on the circuit topology of the chip in the simulation process comprises the following steps: automatically analyzing the circuit topology by using the VPI interface, and identifying all potential fault nodes of reverse propagation; obtaining the connection relationship between the ports of the fault modules corresponding to all potential fault nodes of reverse propagation from top to bottom through iterative traversal, and obtaining a connection relationship set; screening the fault nodes to be isolated from all potential fault nodes of reverse propagation according to the port folding mechanism of the Verilog language and the connection relationship set; the method of constructing an isolation module capable of replacing the fault module corresponding to the fault nodes to be isolated based on the fault nodes to be isolated comprises the following steps: analyzing the input and output of the fault module corresponding to the fault nodes to be isolated; obtaining the instantiation parameters of the fault module corresponding to the fault nodes to be isolated; constructing the isolation module based on the instantiation parameters, input and output of the fault module; the method of constructing the binding relationship between the isolation module and the circuit structure of the chip comprises the following steps: using the bind syntax of SystemVerilog to externally write the isolation module, binding the isolation module to the circuit structure of the chip, and changing the output of the fault module in the circuit structure of the chip to the output of the isolation module through the VPI internal assignment method; the method of mapping the fault injection signal to the fault module to the isolation module based on the binding relationship to complete the fault simulation of the chip comprises the following steps: constructing the package file of each isolation module in the form of SystemVerilog file and attaching it to the simulator compilation simulation link, and when the fault injection signal is injected to the fault module, the fault injection signal is mapped to the isolation module with the same function corresponding to the fault module, and the fault simulation of the chip is completed.

2. The fault isolation handling method of a functional safety system of an automotive chip according to claim 1, wherein, the method of screening the fault nodes to be isolated from all potential fault nodes of reverse propagation according to the port folding mechanism of the Verilog language and the connection relationship set comprises the following steps: based on the port folding mechanism of the Verilog language, all port handles in the connection relationship set are accessed, and when the types of the two variables connected inside and outside the port are both wire type variables, the fault module corresponding to the port is the fault node to be isolated.

3. The method of fault isolation processing of a functional safety system of an automotive chip according to claim 1, wherein, the method of obtaining the instantiation parameters of the fault module corresponding to the fault nodes to be isolated comprises the following steps: using the VPI to access the handle of the instantiation example of the fault module to obtain the instantiation parameters of the fault module.

4. A device for fault isolation processing of a functional safety system of a chip for automotive use based on the fault isolation processing method of the functional safety system of the chip for automotive use according to any one of claims 1 to 3, characterized by ​ The screening module is configured to determine a fault node to be isolated based on a circuit topology of the chip in a simulation process; The construction module is configured to construct an isolation module capable of replacing a fault module corresponding to the fault node to be isolated based on the fault node to be isolated; The association module is configured to construct a binding relationship between the isolation module and a circuit structure of the chip; The processing module is configured to map a fault injection signal to the fault module to the isolation module based on the binding relationship during a simulation process of the chip, and complete fault simulation of the chip.

5. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The processor implements the fault isolation processing method of the functional safety system of the automotive-grade chip when executing the program.

6. A non-transitory computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program implements the fault isolation processing method of the functional safety system of the automotive-grade chip when executed by the processor.

Images