Method, device, equipment and storage medium for graphical design of testability circuit

Abstract

The present invention provides a method, device, equipment and storage medium for graphical design of testability circuit, which belongs to the technical field of testability design. The method for graphical design of testability circuit includes: searching for description information of the testability design circuit from the circuit description information of the chip testability design stage; and drawing the testability design circuit according to the description information of the testability design circuit using drawing parameters that are different from the original circuit. The original circuit and the DFT circuit can be displayed distinguishably.

Description

Technical Field

[0001] The present disclosure relates to the technical field of design for testability, and in particular to a method, device, equipment and storage medium for graphically designing a circuit for testability. Background Art

[0002] In chip design, hardware description languages ​​(such as Verilog) are widely used in circuit modeling and design. Although hardware description languages ​​provide powerful functions, their description method is closer to code and has poor readability, making it relatively inconvenient for designers to understand the principles and structures of circuits.

[0003] Therefore, many Electronic Design Automation (EDA) tools have emerged to display the structure and principle of circuits in a graphical way. EDA tools usually use blocks and wires to represent the various parts of the circuit and their connection relationships. This graphical method allows designers to understand the working principle of the circuit more intuitively. For example, a block diagram is a simplified circuit diagram that uses blocks and wires to show the basic functions of the circuit without involving specific component details. This method is particularly suitable for beginners and engineers who need to quickly understand the function of the circuit.

[0004] Existing EDA tools are mainly used to demonstrate chip design principles. However, in the Design for Test ability (DFT) stage, it is necessary to add a DFT circuit based on the original circuit designed in the chip design stage. Existing EDA tools cannot distinguish between the original circuit and the DFT circuit. Summary of the invention

[0005] The present disclosure provides a method, device, equipment and storage medium for graphically displaying a design for testability circuit; the method can distinguish and display the original circuit and the DFT circuit.

[0006] The technical solution of the present disclosure is achieved as follows:

[0007] In a first aspect, the present disclosure provides a method for graphically displaying a testability design circuit, the method comprising: searching for description information of the testability design circuit from circuit description information in a chip testability design phase; and drawing the testability design circuit based on the description information of the testability design circuit using drawing parameters that are different from those of the original circuit.

[0008] In a second aspect, the present disclosure provides a device for graphically graphing a testability design circuit, which device includes: a searching part and a drawing part; the searching part is configured to search for description information of a testability design circuit from circuit description information in a chip testability design stage; the drawing part is configured to draw the testability design circuit according to the description information of the testability design circuit and using drawing parameters that are different from those of the original circuit.

[0009] In a third aspect, the present disclosure provides an electronic device comprising a processor, a memory, and a program or instruction stored in the memory and executable on the processor, wherein the program or instruction, when executed by the processor, implements the steps of the method for graphically designing a circuit for testability as described in the first aspect.

[0010] In a fourth aspect, the present disclosure provides a readable storage medium storing a program or instruction, which, when executed by a processor, implements the steps of the method for graphically designing a circuit for testability as described in the first aspect.

[0011] In a fifth aspect, the present disclosure provides a computer program product, wherein the computer program product includes a computer program or instructions. When the computer program product runs on a processor, the processor executes the computer program or instructions to implement the steps of the method for graphically designing a circuit for testability as described in the first aspect.

[0012] In a sixth aspect, the present disclosure provides a chip, comprising a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run a program or instruction to implement the method for graphically designing a circuit for testability as described in the first aspect.

[0013] The present disclosure provides a method for graphically displaying a circuit for testability, which searches for description information of a DFT circuit from description information of both the original circuit and the DFT circuit, and draws a DFT circuit that is displayed differently from the original circuit based on the description information of the DFT circuit. In this way, the DFT circuit can be highlighted, which is convenient for DFT engineers to analyze the DFT circuit. DFT engineers do not need to analyze each module in the circuit one by one and then manually highlight the DFT components, which improves the efficiency of DFT engineers in analyzing circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 A schematic flow chart of a method for graphically designing a circuit for testability provided by the present disclosure;

[0015] Figure 2 A schematic diagram showing the difference between the DFT circuit and the original circuit provided by the present disclosure;

[0016] Figure 3 A flowchart of a method for adding a DFT circuit to an original circuit provided by the present disclosure;

[0017] Figure 4 A flowchart of a method for drawing an original circuit and a DFT circuit provided by the present disclosure;

[0018] Figure 5 A schematic flow chart of another method for graphically designing a testability circuit provided by the present disclosure;

[0019] Figure 6 A schematic diagram of the hierarchical structure of a DFT circuit provided by the present disclosure;

[0020] Figure 7 A schematic diagram of a test module B drawn under a test module A provided by the present disclosure;

[0021] Figure 8 A schematic diagram of a test module B and a connection relationship drawn under a test module A provided in the present disclosure;

[0022] Fig. 9 A schematic diagram of submodules and connection relationships drawn under test module A provided in the present disclosure;

[0023] Fig.10 A structural block diagram of a device for graphically designing a testability circuit provided by the present disclosure;

[0024] Fig.11 A schematic diagram of the hardware structure of an electronic device provided by the present invention. DETAILED DESCRIPTION

[0025] The following will be combined with the drawings in the present disclosure to clearly describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the present disclosure are within the scope of protection of the present disclosure.

[0026] In chip design, many EDA tools have been developed to convert circuit principles or circuit structures described in non-intuitive hardware description languages ​​into visual graphic structures. EDA tools analyze the structure and logic of the code to generate corresponding circuit schematics or circuit structure diagrams, which improves the readability of the circuit and helps designers better understand the circuit.

[0027] DFT is an important technology that introduces specific test structures and methods during the integrated circuit design phase to improve the test efficiency and reliability of the circuit after manufacturing. When performing DFT engineering, it is necessary to add DFT circuits on the basis of the original circuit, such as scan chain, built-in self-test (MBIST) and boundary scan. The newly added DFT circuit is crucial to improving the test coverage of the chip and reducing defects.

[0028] In the DFT stage, the circuit schematic is graphically displayed, and more attention is paid to the newly added DFT circuit in the DFT stage, and the original circuit is not paid much attention to. However, the existing EDA tools cannot distinguish between the original circuit and the DFT circuit, which means that in the DFT stage, engineers need to analyze all modules step by step to determine the DFT circuit, which increases the difficulty of circuit analysis.

[0029] Based on the above problems, the present disclosure aims to provide a method for graphically displaying a DFT circuit that can display a DFT circuit differently from an original circuit. The method for graphically displaying a DFT circuit provided by the present disclosure is described in detail below with reference to the accompanying drawings through specific embodiments.

[0030] like Figure 1 As shown, the present disclosure provides a method for graphically designing a circuit for testability, and the method for graphically designing a circuit for testability may include the following steps S101 and S102.

[0031] In step S101, description information of a design for testability circuit is searched from circuit description information in the chip design for testability stage.

[0032] The original circuit refers to the circuit designed according to the hardware design specifications during the chip design process. The original circuit realizes the expected functions and performance requirements of the chip. The original circuit includes multiple functional modules and the connection relationship between each functional module. Each functional module can be divided into parent modules and child modules according to the hierarchical relationship. The DFT circuit refers to the test logic introduced in the chip design process. The purpose is to test the original circuit after the chip is manufactured. The DFT circuit includes multiple test modules and the connection relationship between each test module and between the test module and the functional module. Each test module can also be divided into parent modules and child modules according to the hierarchical relationship. That is, the original circuit is the basic circuit design to realize the chip function, and the DFT circuit is a test circuit added to test the original circuit.

[0033] The circuit description information in the chip testability design stage refers to the principles and structures of the original circuit and the DFT circuit described in the hardware description language in the DFT stage. The circuit description information in the testability design stage includes the description information of the original circuit used to describe the principles and structures of the original circuit, and the description information of the DFT circuit used to describe the principles and structures of the DFT circuit.

[0034] In the circuit description information of the chip testability design stage, the description information is recorded according to the module, that is, the circuit description information of the chip testability design stage includes the description information of multiple modules, and the description information of each module is the description information of the functional module or the description information of the test module. The description information of each module may include the module identification, port list, function description, connection relationship, etc.

[0035] Specifically, searching for description information of the design for testability circuit from the circuit description information of the chip DFT stage can be performed by comparing the difference between the description information of the original circuit and the circuit description information of the DFT stage, and determining the description information of the circuit description information of the DFT stage except the description information of the original circuit as the description information of the DFT circuit.

[0036] However, since the description information of the original circuit and the circuit description information in the DFT stage include description information related to all circuits in the design stage and the DFT stage, the amount of data is usually large. The description information of each functional module in the original circuit is compared with the description information of each module in the circuit description information in the DFT stage until the description information of the module that is identical to the description information of the functional module is found in the circuit description information in the DFT stage, or the description information of the last module is found. This comparison method consumes both computing power and time.

[0037] Therefore, in some embodiments, reference Figure 4 The above step S101 searches for description information of the design for testability circuit from the circuit description information of the chip design for testability stage, which can be specifically implemented by the following step S101a.

[0038] In step S101a, it is determined whether the circuit description information in the chip testability design phase includes description information of a module that meets a preset condition.

[0039] In step S101b, the description information of the modules that meet the preset conditions is determined as the description information of the design for testability circuit.

[0040] The preset conditions include at least one of the following: the module identifier includes a testability design identifier, the number of sub-modules included in the module is within a preset number range, and the identifier of at least one sub-module includes a testability design identifier.

[0041] The circuit description information in the chip testability design stage includes description information of multiple modules. For the description information of each module, it is determined whether the description information of the module meets the preset conditions. If so, it is determined that the description information of the module is the description information of the DFT circuit.

[0042] The module identifier indicates the identity identifier of the module, which is used to distinguish different modules. When the module identifier in the module description information includes the DFT identifier, it can be determined that the module is a test module of the DFT circuit, and the corresponding module description information is the description information of the DFT circuit. For example, the DFT identifier is the "DFT" string.

[0043] Usually, the number of sub-modules in the test module of the DFT circuit is quite different from the number of sub-modules in the module in the chip design stage. Therefore, the preset number range of sub-modules can be determined based on the description information of the number of sub-modules in the description information of each module in the description information of the DFT circuit. When the number of sub-modules of a certain module is within the preset number range, it indicates that the module may be a test module; then check whether the sub-module identifier of the sub-module of the module includes the DFT identifier. If it is included, it indicates that the module is a test module, and the corresponding module description information is the description information of the DFT circuit.

[0044] The description information of the DFT circuit can be determined as long as one of the two preset conditions is met. In order to more accurately determine the description information of the DFT circuit, the description information that satisfies both preset conditions can also be determined as the description information of the DFT circuit.

[0045] In step S102, the design for testability circuit is drawn according to the description information of the design for testability circuit and using drawing parameters different from those of the original circuit.

[0046] Drawing parameters refer to parameters for graphically displaying the circuit principles and structures described in the hardware description language. For example, drawing parameters include: the thickness, color, and style of the connecting line between two modules or internal ports of a module, the thickness, color, and style of the envelope line representing a module, and the shape and fill color of a module.

[0047] Differentiation means drawing the DFT circuit using drawing parameters different from those of the original circuit, such as using connection lines of different colors and envelopes of modules of different colors to highlight the DFT circuit.

[0048] Specifically, the drawing parameters of the DFT circuit can be determined according to the drawing parameters of the original circuit and the default selection strategy, such as the default selection strategy is to preferentially modify the color of the connection line and the color of the envelope of the module, and the color of the connection line of each original circuit has a corresponding color of the connection line of the DFT circuit with a higher degree of difference, and the color of the envelope of each module of the original circuit has a corresponding color of the envelope of the module of the DFT circuit with a higher degree of difference, according to the color of the connection line and the color of the envelope of the original circuit, the connection line of the DFT circuit is drawn according to the color of the connection line of the DFT circuit corresponding to the color of the connection line of the original circuit, and the test module of the DFT circuit is drawn according to the color of the envelope of the module of the DFT circuit corresponding to the color of the envelope of the module of the original circuit. The drawing parameters of the DFT circuit can also be set by the user, and the user selects the drawing parameters of the DFT circuit in the graphical user interface as needed, and draws the DFT circuit according to the drawing parameters selected by the user.

[0049] For example, Figure 2 As shown, function module 1 and function module 2 are modules in the original circuit of chip 20. In the DFT stage, test module 3 and test module 4 are inserted and the connection relationship is determined at the same time. When drawing the envelopes and corresponding connecting lines of test module 3 and test module 4, connecting lines and envelopes with different thicknesses from those of the original circuit are used to draw the DFT circuit. Figure 2 It can be seen intuitively that the bold line shows the DFT circuit.

[0050] In the disclosed embodiment, the description information of the DFT circuit is obtained from both the description information of the original circuit and the description information of the DFT circuit, and a DFT circuit that is displayed differently from the original circuit is drawn based on the description information of the DFT circuit. In this way, during the DFT stage, the DFT engineer does not need to analyze each module in the circuit one by one and then manually highlight the DFT components, which improves the efficiency of the DFT engineer in analyzing the circuit.

[0051] In some embodiments, in combination Figure 1 ,like Figure 3 As shown, the above step S102 draws the design for testability circuit according to the description information of the design for testability circuit using drawing parameters that are different from the original circuit, which can be specifically implemented by the following step S102a.

[0052] In step S102a, the design for testability circuit is drawn in the original circuit according to the description information of the design for testability circuit and using drawing parameters different from those of the original circuit.

[0053] If the original circuit has been drawn, there is no need to redraw it in the DFT stage. Add the inserted DFT circuit directly to the original circuit according to the description information of the testability design circuit. In this way, there is no need to draw the circuits at different stages repeatedly. Only the newly added DFT circuits are drawn, which can improve the drawing efficiency and thus improve the DFT test efficiency.

[0054] In some embodiments, Figure 4 As shown, the method for graphically designing a circuit for testability further includes the following steps S103 and S104.

[0055] In step S103, the description information of the modules that do not meet the preset conditions is determined as the description information of the original circuit.

[0056] In step S104, the original circuit is drawn according to the description information of the original circuit and using the drawing parameters of the original circuit.

[0057] If the original circuit is not drawn, then in the DFT stage, the original circuit is drawn using the first drawing parameter, and the DFT circuit is drawn using the second parameter different from the first parameter. This allows the original circuit and the DFT circuit to be displayed separately in the drawn circuit, making it easier for DFT engineers to analyze the DFT circuit.

[0058] In some embodiments, multiple drawing modes can be set for drawing the original circuit. According to the description information of the original circuit, the drawing parameters of the original circuit and the input drawing mode are used to draw the original circuit. The drawing modes include no connection relationship mode, simple mode, and normal mode; wherein, in the no connection relationship mode, the connection relationship is excluded from the drawn original circuit, that is, only the functional modules in the original circuit are drawn, and there is no need to draw the connection relationship between the functional modules. In the simple mode, the functional modules that have no connection relationship with the design for testability circuit are excluded from the drawn original circuit, that is, only the functional modules associated with the DFT circuit (such as the test modules of the DFT circuit) are drawn. In the normal mode, all the functional modules and connection relationships in the original circuit are drawn. In this way, users can flexibly select different drawing modes according to different requirements for the original circuit.

[0059] In some embodiments, in combination Figure 4 ,like Figure 5 As shown, the method for graphically displaying a design for testability circuit also includes the following step S105. The above step S102 draws the design for testability circuit based on the description information of the design for testability circuit using drawing parameters that are different from the original circuit. Specifically, it can be implemented through the following step S102b or steps S102c to S102f.

[0060] In step S105 , it is determined whether there is an empirical layout among the multiple empirical layouts that matches the description information of the design for testability circuit.

[0061] If yes, execute step S102b; otherwise, execute steps S102c to S102f.

[0062] In step S102b, the design for testability circuit is drawn according to the matched empirical layout and using drawing parameters that are different from those of the original circuit.

[0063] Among them, the empirical layout is to pre-design the layout of the test modules in the commonly used DFT circuits based on experience and store it in the empirical layout database so that it can be used directly later, reducing the computing power consumption in the circuit drawing process and improving the drawing efficiency.

[0064] In some embodiments, each empirical layout includes: empirical layout conditions and empirical layout rules. The empirical layout conditions are used to limit specific test modules and the number of specific test modules, and the empirical layout rules are used to determine the arrangement positions of the test modules that meet the empirical layout conditions.

[0065] Traverse each of the multiple empirical layouts to determine whether the description information of the DFT circuit meets the empirical layout conditions of one of the empirical layouts, determine the satisfied empirical layout as the target empirical layout, determine the corresponding empirical layout conditions as the target empirical layout conditions, and determine the empirical layout rules as the target empirical layout rules. After the description information of the DFT circuit is matched to the target empirical layout, draw the design for testability circuit according to the target empirical rules and using drawing parameters that are different from the original circuit.

[0066] Exemplarily, the empirical layout includes a first empirical layout and a second empirical layout, and the first empirical layout condition corresponding to the first empirical layout is that it includes two A modules and three B modules, and the corresponding first empirical layout rule is that they are arranged in columns at the first preset position of the corresponding upper layout; the second empirical layout condition corresponding to the second empirical layout is that the number of C modules is greater than or equal to three, and the corresponding second empirical layout rule is that they are arranged in rows at the second preset position of the corresponding upper layout.

[0067] In the present disclosure, multiple empirical layouts are pre-stored. When the description information of the DFT circuit meets the empirical layout conditions of a certain empirical layout, the drawing position of the test module can be directly determined according to the empirical layout rule, thereby improving the drawing efficiency.

[0068] In step S102c, the hierarchical relationship between the test modules of the design for testability circuit is determined according to the description information of the design for testability circuit.

[0069] In order to more conveniently obtain the hierarchical relationship between the test modules of the testability design, in some embodiments, the initial circuit description information described in the hardware description language in the chip testability design phase is obtained; the initial circuit description information is converted into circuit description information in an abstract syntax tree structure; for example, for the initial circuit description information described in Verilog, the Verilog parser can be used to convert the initial circuit description information into circuit description information in an abstract syntax tree structure. In this way, the structure of the description information of the DFT circuit is an abstract syntax tree structure, and the hierarchical relationship is clear, which is convenient for subsequent circuit drawing according to the hierarchical relationship.

[0070] Exemplarily, it is taken that the description information of the DFT circuit includes description information of test module A, test module B and test module C.

[0071] The description of test module A is:

[0072] Module Definition - A;

[0073] Port List;

[0074] Output port out_B (wire);

[0075] Output port out_C (wire);

[0076] Internal Signal Declarations;

[0077] Clock signal clk (wire);

[0078] Reset signal rst (wire);

[0079] Intermediate signals b_out (wire), c_in (wire);

[0080] Instance Statements;

[0081] Instantiation of module B;

[0082] connect.clk(clk);

[0083] connect.rst(rst);

[0084] connect.out(b_out);

[0085] Instantiation of module C;

[0086] connect.in(b_out);

[0087] connect.out(out_C);

[0088] The description information of test module B is:

[0089] Module Definition - B;

[0090] Port List;

[0091] Input port clk (wire);

[0092] Input port rst (wire);

[0093] Output port out (reg);

[0094] The description information of test module C is:

[0095] Module Definition - C;

[0096] Port List;

[0097] Input port in (wire);

[0098] Output port out (wire);

[0099] Test module B and test module C are instantiated in test module A, which means that test module A is the parent node, and test module B and test module C are the child nodes of test module A. The hierarchical relationship determined accordingly is as follows: Figure 6 As shown, test module A is the parent node, located at the top layer, and test module B and test module C are child nodes under test module A, located at the next layer of test module A.

[0100] In step S102d, the test modules are drawn at the remaining positions of the drawing area according to the hierarchical relationship and the area information of the test modules included in the description information of the design for testability circuit.

[0101] According to the hierarchical relationship of the test modules, the drawing is done in order from the bottom layer to the top layer, that is, starting from the parent node of the top layer, for each test module, according to the area information of the test module included in the description information of the DFT circuit, and in accordance with the overall drawing rules (such as the drawing order is from left to right and from top to bottom), the test module is drawn at the remaining position of the drawing area. If the test module to be drawn is the parent node of the top layer, the drawing area is the drawable area of ​​the entire circuit. If the test module to be drawn is the child node after the parent node of the top layer, the drawing area is the parent node area corresponding to each child node.

[0102] Combined with the example in step S102c, the area information of the test module is determined by the number of logic gates in the description information of the DFT circuit. The description information of the DFT circuit in the above example does not show the number of logic gates. According to the hierarchical relationship, first draw the test module A, the test module A is the parent node of the top layer, and the drawing area is the drawable area (remaining position) of the entire test circuit. After the drawing of the test module A is completed, the test module A is determined to be the drawing area of ​​the test module B and the test module C. The area within the test module A is the remaining position of the drawing area. At the remaining position, the test module A is drawn according to the preset drawing rule from left to right. The drawing result is as follows: Figure 7 shown.

[0103] In step S102e, the connection relationship of the test module is drawn according to the connection relationship information included in the description information of the design for testability circuit.

[0104] After each test module is drawn, the test module is connected with other test modules or functional modules according to the connection relationship information included in the description information of the DFT circuit.

[0105] Combined with the example in step S102c and Figure 7 According to the example "Instantiation of module B; connection .clk(clk); connection .rst(rst); connection .out(b_out)", it can be determined that test module B is connected to test module A through input ports clk and rst and output port out, such as Figure 8 FIG. 1 is a schematic diagram showing the connection between test module A and test module B. FIG.

[0106] In step S102f, the remaining position of the drawing area is updated.

[0107] After a test module is drawn, the remaining position of the drawing area where the test module is located is reduced accordingly, and the remaining position is updated to facilitate drawing the next test module drawn in the drawing area.

[0108] Combined with the example in step S102c and Figure 7 , after the drawing of test module B is completed, the remaining position of the drawing area is the area inside test module A and outside test module B. Similarly, the schematic diagram after drawing test module C and the connection relationship is as follows Fig. 9 shown.

[0109] It should be noted that the above exemplary description is only part of the description information of the DFT circuit, and the amount of data included in the actual application is larger. In addition, for the drawing of the original circuit, you can refer to the drawing process of the DFT circuit, which will not be repeated here.

[0110] Based on the same concept as the above-mentioned method for graphically designing a circuit for testability, the present disclosure also provides a device for graphically designing a circuit for testability, such as Fig.10 As shown, the device 100 for graphically designing a testability design circuit includes: a searching part 110 and a drawing part 120; the searching part 110 is configured to search for description information of the testability design circuit from the circuit description information of the chip testability design stage; the drawing part 120 is configured to draw the testability design circuit according to the description information of the testability design circuit using drawing parameters that are different from the original circuit.

[0111] In some embodiments, the drawing part 120 is specifically configured to draw the design for testability circuit in the original circuit according to the description information of the design for testability circuit and using drawing parameters that are different from those of the original circuit.

[0112] In some embodiments, the drawing part 120 is specifically configured to draw the design for testability circuit according to the matched empirical layout using drawing parameters different from the original circuit when there is an empirical layout matching the description information of the design for testability circuit among multiple empirical layouts.

[0113] In some embodiments, each empirical layout includes: empirical layout conditions and empirical layout rules; the drawing part 120 is specifically configured to determine that the description information of the design for testability circuit matches the target empirical layout when the description information of the design for testability circuit meets the target empirical layout conditions of the target empirical layout; according to the target empirical layout rules of the target empirical layout, using drawing parameters that are differentiated from the original circuit, the design for testability circuit is drawn, and the target empirical layout is one of multiple empirical layouts.

[0114] In some embodiments, the drawing part 120 is specifically configured to determine the hierarchical relationship between the test modules of the design for testability circuit according to the description information of the design for testability circuit; draw the modules to be drawn at the remaining positions of the drawing area according to the hierarchical relationship and the area information of the test modules included in the description information of the design for testability circuit; draw the connection relationship of the test modules according to the connection relationship information included in the description information of the design for testability circuit; and update the remaining positions of the drawing area.

[0115] In some embodiments, the search portion 110 is specifically configured to determine the description information of a module that meets preset conditions from the circuit description information as the description information of a testability design circuit, and the preset conditions include at least one of the following: the module identifier includes a testability design identifier, the number of sub-modules included in the module is within a preset number range and the identifier of at least one sub-module includes a testability design identifier.

[0116] In some embodiments, the device 100 for graphically designing a testability design circuit also includes: a determination part; the determination part is configured to determine the description information of the module that does not meet the preset conditions from the circuit description information in the chip testability design stage as the description information of the original circuit; the drawing part 120 is also configured to draw the original circuit based on the description information of the original circuit and using the drawing parameters of the original circuit.

[0117] In some embodiments, the drawing part 120 is specifically configured to draw the original circuit according to the description information of the original circuit, using the drawing parameters of the original circuit and the input drawing mode, and the drawing modes include: no connection relationship mode, simple mode, and normal mode. The original circuit drawn in the no connection relationship mode excludes the connection relationship, the original circuit drawn in the simple mode excludes the functional modules that have no connection relationship with the testability design circuit, and the original circuit drawn in the normal mode includes all functional modules and connection relationships.

[0118] In the embodiment of the present disclosure, each part of the device 100 for graphically designing a circuit for testability can implement the method for graphically designing a circuit for testability provided by the above method embodiment, and can achieve the same technical effect. To avoid repetition, it will not be described here.

[0119] Please refer to Fig.11 , which shows a schematic diagram of the hardware structure of an electronic device provided by an exemplary embodiment of the present disclosure. In some examples, the electronic device may be at least one of a smart phone, a smart watch, a desktop computer, a laptop, a virtual reality terminal, an augmented reality terminal, a wireless terminal, and a laptop computer. The electronic device has a communication function and can access a wired network or a wireless network. The electronic device may generally refer to one of a plurality of terminals, and those skilled in the art may know that the number of the above terminals may be more or less. It can be understood that the electronic device undertakes the calculation and processing work of the technical solution of the present disclosure, and the present disclosure does not limit this.

[0120] like Fig.11 As shown, the electronic device in the present disclosure may include one or more of the following components: a processor 1110 and a memory 1120 .

[0121] Optionally, the processor 1110 uses various interfaces and lines to connect various parts of the entire electronic device, and executes various functions of the electronic device and processes data by running or executing instructions, programs, code sets or instruction sets stored in the memory 1120, and calling data stored in the memory 1120. Optionally, the processor 1110 can be implemented in at least one hardware form of digital signal processing (DSP), field programmable gate array (FPGA), and programmable logic array (PLA). The processor 1110 can integrate one or a combination of a central processing unit (CPU), a graphics processing unit (GPU), a neural network processor (NPU), and a baseband chip. Among them, the CPU mainly processes the operating system, user interface, and application programs; the GPU is responsible for rendering and drawing the content that needs to be displayed on the touch display; the NPU is used to implement artificial intelligence (AI) functions; and the baseband chip is used to process wireless communications. It is understandable that the above-mentioned baseband chip may not be integrated into the processor 1110, but may be implemented by a separate chip.

[0122] The memory 1120 may include a random access memory (RAM) or a read only memory (ROM). Optionally, the memory 1120 includes a non-transitory computer-readable storage medium. The memory 1120 may be used to store instructions, programs, codes, code sets, or instruction sets. The memory 1120 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as a touch function, a sound playback function, an image playback function, etc.), instructions for implementing the above various method embodiments, etc.; the data storage area may store data created according to the use of the electronic device, etc.

[0123] In addition, those skilled in the art can understand that the structure of the electronic device shown in the above drawings does not constitute a limitation on the electronic device, and the electronic device may include more or fewer components than shown, or combine certain components, or arrange the components differently. For example, the electronic device also includes a display screen, a camera assembly, a microphone, a speaker, a radio frequency circuit, an input unit, a sensor (such as an acceleration sensor, an angular velocity sensor, a light sensor, etc.), an audio circuit, a WiFi module, a power supply, a Bluetooth module and other components, which will not be described in detail here.

[0124] The present disclosure also provides a computer-readable storage medium storing at least one instruction, wherein the at least one instruction is used to be executed by a processor to implement the method for graphically designing a circuit for testability as described in the above embodiments.

[0125] The present disclosure also provides a computer program product, which includes computer instructions, which are stored in a computer-readable storage medium; a processor of an electronic device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the electronic device executes to implement the method of graphically designing a testability circuit as described in the above-mentioned embodiments.

[0126] The disclosed embodiment further provides a chip, which includes a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run programs or instructions to implement the various processes of the above-mentioned method embodiment of graphical circuit design for testability, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0127] It should be understood that the chip mentioned in the embodiments of the present disclosure may also be referred to as a system-level chip, a system chip, a chip system, or a system-on-chip chip, etc.

[0128] In the several embodiments provided in the present disclosure, it should be understood that the disclosed systems, devices, servers and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0129] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0130] In addition, each functional unit in each embodiment of the present disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0131] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present disclosure, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present disclosure. The aforementioned storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard drives, ROM, RAM, magnetic disks, or optical disks.

[0132] Those skilled in the art should be aware that in one or more of the above examples, the functions described in the present disclosure can be implemented using hardware, software, firmware, or any combination thereof. When implemented using software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any media that facilitates the transmission of computer programs from one place to another. Storage media can be any available media that can be accessed by a general or special-purpose computer.

[0133] It should be noted that the technical solutions described in the present disclosure can be combined arbitrarily without conflict.

[0134] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A method for graphically designing a testability circuit, characterized in that: The method for graphically designing a testability circuit comprises: Searching for description information of a design for testability circuit from circuit description information of a chip design for testability stage, wherein the circuit description information of the chip design for testability stage includes: description information of an original circuit for describing the principle and structure of the original circuit, and description information of a design for testability circuit for describing the principle and structure of the design for testability circuit; Drawing the design for testability circuit using drawing parameters that are different from the original circuit according to the description information of the design for testability circuit, wherein the drawing parameters refer to parameters for graphically displaying the circuit principle and structure described in the hardware description language; The step of searching for description information of the design for testability circuit from the circuit description information of the chip design for testability phase includes: From the circuit description information, the description information of the module that meets the preset conditions is determined as the description information of the testability design circuit, and the preset conditions include at least one of the following: the module identifier includes a testability design identifier, the number of sub-modules included in the module is within a preset number range and the identifier of at least one sub-module includes a testability design identifier.

2. The method for graphically designing a testability circuit according to claim 1, characterized in that: Drawing the design for testability circuit according to the description information of the design for testability circuit using drawing parameters that are different from the original circuit includes: According to the description information of the design for testability circuit, a design for testability circuit is drawn in the original circuit using drawing parameters that are different from those of the original circuit.

3. The method for graphically designing a testability circuit according to claim 1, characterized in that: Drawing the design for testability circuit according to the description information of the design for testability circuit using drawing parameters that are different from the original circuit includes: When there is an empirical layout matching the description information of the design for testability circuit among the multiple empirical layouts, the design for testability circuit is drawn according to the matched empirical layout using drawing parameters different from those of the original circuit.

4. The method for graphically designing a testability circuit according to claim 3, characterized in that: Each empirical layout includes: empirical layout conditions and empirical layout rules; when there is an empirical layout matching the description information of the design for testability circuit among the multiple empirical layouts, drawing the design for testability circuit according to the matched empirical layout using drawing parameters that are different from the original circuit, including: In a case where the description information of the design for testability circuit meets a target empirical layout condition of a target empirical layout, determining that the description information of the design for testability circuit matches the target empirical layout; According to the target empirical layout rule of the target empirical layout, the design for testability circuit is drawn using drawing parameters that are different from the original circuit, and the target empirical layout is one of multiple empirical layouts.

5. The method for graphically designing a testability circuit according to claim 1, characterized in that: Drawing the design for testability circuit according to the description information of the design for testability circuit using drawing parameters that are different from the original circuit includes: Determining the hierarchical relationship between the test modules of the design for testability circuit according to the description information of the design for testability circuit; Drawing the module to be drawn at the remaining position of the drawing area according to the hierarchical relationship and the area information of the test module included in the description information of the design for testability circuit; Drawing the connection relationship of the test modules according to the connection relationship information included in the description information of the design for testability circuit; Update the remaining position of the drawing area.

6. The method for graphically designing a testability circuit according to claim 1, characterized in that: The method for graphically designing a testability circuit further comprises: Determining the description information of the modules that do not meet the preset conditions from the circuit description information in the chip testability design phase as the description information of the original circuit; The original circuit is drawn according to the description information of the original circuit and using the drawing parameters of the original circuit.

7. The method for graphically designing a testability circuit according to claim 6, characterized in that: Drawing the original circuit according to the description information of the original circuit and using the drawing parameters of the original circuit includes: According to the description information of the original circuit, the original circuit is drawn using the drawing parameters of the original circuit and the input drawing mode, wherein the drawing modes include: a no-connection relationship mode, a simple mode, and a normal mode. The original circuit drawn in the no-connection relationship mode excludes the connection relationship, the original circuit drawn in the simple mode excludes the functional modules that have no connection relationship with the testability design circuit, and the original circuit drawn in the normal mode includes all functional modules and connection relationships.

8. A device for graphically designing a circuit for testability, characterized in that: The device for graphically designing a circuit for testability comprises: a searching part and a drawing part; The searching part is configured to search for description information of the design for testability circuit from the circuit description information of the chip design for testability stage, wherein the circuit description information of the chip design for testability stage includes: description information of the original circuit for describing the principle and structure of the original circuit, and description information of the design for testability circuit for describing the principle and structure of the design for testability circuit; The drawing part is configured to draw the design for testability circuit according to the description information of the design for testability circuit and using drawing parameters that are different from the original circuit, wherein the drawing parameters refer to parameters for graphically displaying the circuit principle and structure described in the hardware description language; The drawing part is specifically configured as follows: From the circuit description information, the description information of the module that meets the preset conditions is determined as the description information of the testability design circuit, and the preset conditions include at least one of the following: the module identifier includes a testability design identifier, the number of sub-modules included in the module is within a preset number range and the identifier of at least one sub-module includes a testability design identifier.

9. An electronic device, characterized in that: The invention comprises a processor, a memory and a program or instruction stored in the memory and executable on the processor, wherein the program or instruction, when executed by the processor, implements the steps of the method for graphically designing a circuit for testability as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The readable storage medium stores a program or an instruction, and when the program or the instruction is executed by a processor, the steps of the method for graphically designing a circuit for testability are implemented as claimed in any one of claims 1 to 7.

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