High-performance testing interface for semiconductor device

Abstract

To provide a semiconductor device having a testing facilitation engineering interface.SOLUTION: A semiconductor device may be tested within a manufacturing environment as one of a die and a packaged die. A testing facilitation engineering interface includes a physical layer having a transmitter, a receiver and a common lane. The testing facilitation engineering interface includes a semiconductor device logic and a test port interface logic connectable by an interface. The test port interface logic may include a 1:N deserializer logic, a 1:N CLK frequency divider logic, and an N:1 serializer logic.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The description generally relates to integrated circuit devices, testing of integrated circuit devices, units under test and connections between interconnect circuit devices. [Background technology]

[0002] Integrated circuit (IC) devices are critical to intelligent devices and systems such as personal computers, laptops, tablets, phones, servers, and other consumer and industrial products and systems. Manufacturing integrated circuit devices presents many challenges, and these challenges are amplified as IC devices become smaller, have more transistors, and have higher performance requirements. Testing and analysis of IC devices is an essential part of the manufacturing process.

[0003] The requirements governing the design of the physical mechanism that delivers test content to the device under test (DUT) are challenging due to the increasing transistor count that occurs as lithography advances. Traditionally, most test access for IC devices, such as application-specific integrated circuits (ASICs), has been via the Joint Action Test Group (JTAG) Institute of Electrical and Electronics Engineers (IEEE 1149.1) standard. This standard's narrow pin count (one IO (input / output) for data input and one IO for data output) and low data rates (typically no faster than 100 MHz) have limited the speed of test content transfer and significantly impacted test affordability. These test ports can consume a prohibitive number of package pins, may not scale up in bandwidth, and can impact design performance relative to other device features. The ever-increasing test content volume coupled with a design paradigm shift regarding die disaggregation has resulted in older test port-based designs having high complexity networks, either on-chip or on-package, to connect production test system interfaces during the high volume manufacturing process. [Brief explanation of the drawings]

[0004] The drawings are provided to aid in understanding the present disclosure. The figures may include diagrams and illustrations of example structures, assemblies, data, methods, and systems. To facilitate description and understanding of these structures, assemblies, data, methods, and systems, the drawings are not exhaustively detailed. Accordingly, the drawings should not be understood to depict the full extent of coverage of structures, assemblies, data, methods, and systems possible without departing from the scope of the present disclosure. Additionally, features are not necessarily drawn to scale relative to one another, due in part to the small size of some features and a desire to clarify the illustrations in the figures.

[0005] [Figure 1] FIG. 1 is a diagram of an architecture for design for test (DFT) features on a semiconductor device.

[0006] [Figure 2] FIG. 1 is a diagram of a semiconductor package coupled to a board and a system for testing semiconductor devices.

[0007] [Figure 3] FIG. 1 is a diagram of a semiconductor device and a semiconductor device testing unit coupled to a board.

[0008] [Figure 4] 1 is a diagram of an exemplary test interface waveform for operation of a DFT interface on a semiconductor chip.

[0009] [Figure 5] FIG. 1 is a diagram of a semiconductor chip having a DFT interface.

[0010] [Figure 6] FIG. 1 is a diagram of a method for testing a semiconductor device using a DFT interface.

[0011] [Figure 7] FIG. 1 is a diagram of an exemplary computing system.

[0012] A description of specific details and implementations follows, including non-limiting descriptions of drawings depicting several examples and implementations. DETAILED DESCRIPTION OF THE INVENTION

[0013] Reference to one or more examples is understood to describe particular features, structures, or characteristics present in at least one implementation. The phrases "one example" or "an example" do not necessarily all refer to the same example or embodiment. Any aspect described herein can potentially be combined with any other aspect or similar aspect described herein, regardless of whether the aspects are described with respect to the same figure or element.

[0014] The terms "connected" and / or "coupled" may indicate that two or more elements are in direct physical or electrical contact with each other. However, the term "coupled" can also mean that two or more elements are not in direct contact with each other, but rather are separated by one or more elements, but may still cooperate or interact with each other, for example, physically, magnetically, or electrically.

[0015] The words "first," "second," and similar words do not denote order, quantity, or importance, but rather are used to distinguish one element from another. The words "a" and "an" herein do not denote a limitation of quantity, but rather denote the presence of at least one of the referenced items. The terms "follow" or "after" may indicate immediately following or following some other event or events. Other sequences of operations may also be performed according to alternative embodiments. Furthermore, additional operations may be added or removed depending on the application.

[0016] Disjunctive language, such as the phrase "at least one of X, Y, or Z," is generally used to indicate that an element or feature can be either X, Y, or Z, or any combination thereof (e.g., X, Y, and / or Z). Therefore, this disjunctive language should not be understood to imply that a particular embodiment requires that at least one of X, at least one of Y, or at least one of Z, respectively, be present.

[0017] The flow diagrams shown herein provide examples of sequences of various process actions. The flow diagrams may depict operations and / or physical operations performed by software or firmware routines. The operations may be performed by a system for semiconductor testing. The order of the actions, although shown in a particular sequence or order, is modifiable unless otherwise specified. Therefore, the diagrams shown should be understood as examples only; processes may be performed in a different order, and some actions may be performed in parallel. Additionally, one or more actions may be omitted, and not all implementations will perform all actions.

[0018] The various components described may be means for performing the described operations or functions. Each described component may include software, hardware, or a combination thereof. Some components may be implemented as software modules, hardware modules, dedicated hardware (e.g., application-specific hardware, application-specific integrated circuits (ASICs), and digital signal processors (DSPs)), embedded controllers, or hardwired circuitry.

[0019] To the extent various computer operations or functions are described herein, they may be described or defined as software code, instructions, configuration, and / or data. Software content may be provided by an article of manufacture on which the content is stored or by a method that causes a communications interface to operate to transmit data through the communications interface. A machine-readable storage medium may cause a machine to perform the described functions or operations. A machine-readable storage medium includes any mechanism that stores information in a tangible form accessible by a machine (e.g., a computing device), such as recordable / non-recordable media (e.g., read-only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices). Instructions may be stored on a machine-readable storage medium in a non-transitory form. A communications interface includes any mechanism that interfaces, for example, to a hardwired, wireless, or optical medium, to communicate with another device, e.g., a memory bus interface, a processor bus interface, an Internet connection, a disk controller, etc.

[0020] Terms such as chip, die, integrated circuit (IC) chip, IC die, IC device, microelectronic chip, microelectronic die, semiconductor die, semiconductor device, and / or semiconductor chip are used interchangeably and refer to a semiconductor device comprising an integrated circuit.

[0021] Semiconductor chip manufacturing processes can be divided into front-end of the line (FEOL) processes and back-end of the line (BEOL) processes. Electronic circuits and active and passive devices within a chip, such as transistors, capacitors, resistors, and / or memory cells, are fabricated in what may be referred to as FEOL processes. Memory cells include electronic circuits for random access memory (RAM), such as static RAM (sRAM), dynamic RAM (DRAM), read-only memory (ROM), nonvolatile memory, and / or flash memory. FEOL processes may be, for example, complementary metal-oxide semiconductor (CMOS) processes. BEOL processes include chip metallization, where interconnects are formed within layers and the feature size of the interconnects increases in layers closer to the surface of the semiconductor chip. For example, interconnects in semiconductor chips integrated into heterogeneous packages (e.g., packages containing memory and logic chips) may also include through silicon vias (TSVs) that traverse semiconductor chip device regions. Semiconductor devices with TSVs can blur the distinction between BEOL and FEOL processes.

[0022] The terms "package," "packaging," "IC package," or "chip package," "microelectronic package," or "semiconductor chip package" are used interchangeably and generally refer to an encapsulated carrier of one or more dies in which the dies are attached to and encapsulated in a package substrate. The package substrate provides electrical interconnections for IO (input / output) communication and power between the die and / or other dies and / or a motherboard or other printed circuit board. A package with multiple dies can be, for example, a system in a package.

[0023] FIG. 1 provides an exemplary design for testability (DFT) interface for a semiconductor device. The semiconductor device includes logic for performing one or more computing functions and may be, for example, any of the semiconductor devices described herein with respect to FIGS. 2, 5, and 7. A test port physical layer (PHY) 101 includes a common lane 105, one or more RX (receivers) 110-110M, and one or more TX (transmitter) lanes 115-115N. The number of RX and TX lanes is adjustable (user-selected) from 1-M and 1-N, respectively, and may be selected, for example, based on the bandwidth requirements of a given semiconductor device. Smaller semiconductor devices may require fewer lanes than larger semiconductor devices. The number of RX lanes 110-110M may be different from the number of TX lanes 115-115N. Common lane 105 consists of JTAG test access port (TAP) logic 106, physical layer (PHY) control registers 107, and clock (CLK) buffer logic and distribution network logic 108. PHY control registers 107 can be accessed through a secondary TAP through a semiconductor device-level TAP network. There are other pins of the test port PHY exposed to the internal semiconductor device for management and / or programming. These pins include a reset pin, which a tester can program through the semiconductor device-level TAP network before mission mode and / or self-test are initiated. The JTAG test port registers (control registers 107) can be used to program the test port either in mission mode or for self-test, using, for example, pattern generator 117, and can be used to program register settings to implement termination resistance (e.g., 50 ohms, but other values ​​are possible).

[0024] Each RX lane 110-110M may include a termination resistor (e.g., 50 ohms, but other values ​​are possible) and RX buffer logic 111, as well as 1:2 deserializer logic 112 that can convert serial data to parallel data. The RX buffer logic can regulate the flow of data. Each TX lane 115-115N includes a high-speed TX driver that may include optional de-emphasis logic (not shown), 2:1 serializer logic 116 that can convert parallel data to serial data, programmable pattern generator logic 117 that can be used for initial timing calibration, and TX buffer logic 118 that can regulate the flow of data. The transmitter and receiver can operate at speeds from 1 bit per second (2 bps) to 2 gigabits per second (2 Gbps). The transmitter and receiver are synchronized to a CLK, which may have a frequency of, for example, 1 Hz to 1 GHz (1 Hertz to 1 GHz). Double data rate protocols (where data is latched on both the rising and falling edges) allow receiver and transmitter operation to vary from 2 bps to 2 Gbps. De-emphasis logic can remove distortion caused by pre-emphasis. Pre-emphasis is a technique that can protect a signal against expected noise by boosting frequency ranges that are susceptible to noise. De-emphasis removes this distortion caused by boosting frequency ranges.

[0025] The Test Access Port (TAP) 106 can be an industry standard (IEEE 1149.1) unit. The test port uses the TAP 106 to access and / or program multiple registers. The clock buffer 108 is an input buffer with a configurable termination resistor (typically programmed to 50 ohms by the tester through JTAG / TAP 106). Because the test port can be double data rate (data is sampled on both the rising and falling edges), a 50% duty cycle should be achieved. The clock distribution network can be timed to ensure a near 50% duty cycle. The clock buffer and distribution network logic 108 can be analog circuitry implemented to manage the quality of clock propagation within the design to achieve minimal skew, crosstalk, and ensure that the duty cycle is maintained throughout the network. The RX buffer 111 is an input buffer with a configurable termination resistor (typically programmed to 50 ohms by the tester through JTAG / TAP).

[0026] The 1:2 deserializer 112 is used to convert the double data rate protocol to a single data rate (where, for example, data is sampled only on the rising edge of the clock) and output it to the scan test network. Assuming a maximum speed of 1 GHz clock, the test port drives the 2:1 deserialized data to the scan network at 1 GHz, for example, on the rising edge. The scan network may also have a 1:N deserializer 151 that drives data downstream at a slower rate to achieve timing convergence by lowering the clock frequency but still maintaining bandwidth. For example, if the scan network is only timed to support a 500 MHz clock rate, then 151 may be a 1:2 deserializer; if the scan network is only timed to support a 250 MHz clock rate, then 151 may be a 1:4 deserializer, etc. The N:1 serializer 153 converts the scan network data to, for example, a 1 GHz single data rate and drives it to the test port (e.g., if the scan network is timed at 500 MHz, a 2:1 serializer is used; if the scan network is timed at 250 MHz, a 4:1 serializer is used, etc.). The 2:1 serializer converts the incoming 1 GHz single data rate signaling to 1 GHz double data rate signaling. The TX buffer 118 may include a transmitter main driver and a de-emphasis driver. The de-emphasis driver may optionally be turned on with a selected de-emphasis value, for example, if turning it on provides a larger signal eye margin and better signal integrity on the path to the tester.

[0027] The DFT interface PHY follows a forward clock architecture. The production test system may drive the DFT interface clock (CLK126). The CLK126 frequency can be anywhere from 1 Hz to 1 GHz. All RX and TX IOs 125M, 125, 127, and 127N are synchronized to CLK126. For RX operations, data is sent from the test system 130 to the DFT interface, and for TX operations, data is sent from the DFT interface to the test system 130. The DFT test interface PHY may not include any logic or state machines that may help calibrate resistors or adjust per-pin timing. The test system 130 may include automatic test equipment (ATE) to test semiconductor devices to determine whether functionality, speed, power consumption, reliability, and / or other attributes meet selected criteria. Native ATE capabilities to force current and measure voltages are used to calibrate the RX termination and TX pull-up and pull-down resistors to desired values ​​instead of implementing state machines. Similarly, the native ATE capability of timing search is used to deskew the RX and TX timing with respect to CLK instead of implementing any delay-locked loop (DLL) or deskew logic.

[0028] Input and output (IO) lanes (which are electrical connection IO bumps, pins, pads, or other structures on the semiconductor device) include RX_LANE[M] 125M, RX_LANE[0] 125, CLK signal 126, TX_LANE[0] 127, and TX_LANE[N] 127N. These signal lines may connect to a test system 130 for testing a semiconductor device having a design-for-testability interface. A voltage source 180 may be dedicated to the design-for-testability interface or may be part of a voltage supply to additional portions of the semiconductor device.

[0029] For RX operation, each IO's (125-125M) bit stream may be driven by a test system (supporting double data rate (DDR) operation) on both edges of the CLK signal, deserialized 1:2, and transmitted to test port interface logic 150 on the rising edge of the CLK signal as IO RX_DATA_EVEN[LANE] 160 and 162 for Lanes 0-M and as IO RX_DATA_ODD[LANE] 161 and 163 for Lanes 0-M. Test port interface logic 150 transmits the data (as bit streams) to each TX lane 115-115N on the rising edge of the CLK signal to IO TX_DATA_EVEN[LANE] 164 and 166 for Lanes 0-N and to IO TX_DATA_ODD[LANE] 165 and 167 for Lanes 0-N. Test port interface logic 150 may interface with semiconductor device logic. The semiconductor device logic is for performing one or more computing functions. Test port interface logic 150 includes 1:N deserializer logic 151, 1:N CLK divider logic 152, and N:1 serializer logic 153. Test port interface logic 150 also receives CLKOUT signal 170. Optionally, test port interface logic 150 may include additional frequency step-down logic to drive a semiconductor device scan system if a given semiconductor device cannot converge timing at 1 GHz with respect to the CLK signal.

[0030] Test port operation is fully deterministic and cycle accurate due to the test system forwarded clock. Test functionality is largely deterministic because the available test content is synchronous, i.e., the test system is locked to the CLK signal and delivers known data every cycle. The bit stream starts at a precise point in each CLK cycle. Due to single-ended operation and no encoding involved, the per-pin bandwidth of a production test system can be maximized as well. Data transmit and receiver efficiency can be up to 100%. Due to the clock driven by the source-synchronous test system, the PHY can operate at any clock frequency from 1 Hz to 1 GHz. The available DDR mode of operation means that supported data rates anywhere between 2 bps and 2 Gbps can be achieved. Advantageously, the DFT interface may not employ general purpose IO (GPIO) digital signal lanes, meaning that the focus of GPIO design and routing may be to enable platform and motherboard routing, while the test port does not require such a motherboard or platform breakout, and therefore the IO can be isolated within an uncongested area of ​​the floorplan / die.

[0031] With the DFT interface architecture, automatic resistance calibration and timing calibration can be handled by the production test system (i.e., test system 130, 210, 310). The DFT interface may have a relatively low risk of being non-functional at power-on. Furthermore, the DFT interface may be operated at a CLK frequency lower than the supported 1 GHz at power-on to support fault diagnosis and further reduce the risk of dead-on-arrival. Conventional HSIO Phys can take days to function. If only the highest data rate is supported (e.g., 2 Gbps) and that data rate is not immediately realized at power-on, this issue can delay testing the rest of the logic on the chip and significantly increase the risk that the semiconductor device will be deemed non-functional. Because the test port is flexible and can run at any data rate, if the 2 Gbps data rate is not immediately functional at power-on, the test port can still be enabled at an arbitrarily low data rate (e.g., 100 Mbps) to ungate the rest of the testing at power-on.

[0032] A DFT interface may be used during production test. For example, a DFT interface may be an interface that does not include features such as an embedded clock architecture, differential signaling, auto-resistors, deskew, and timing calibration. These features are typically used with high-speed IO (HSIO) PHYs because they must operate at high speeds on test boards with different channel qualities and lengths. Even if a DFT interface PHY is designed for a specific impedance value (e.g., 50 ohms), there may be a wide variation in the actual silicon value due to process variations. To resolve this within different systems, a complex auto-calibration scheme using external precision resistors may be required.

[0033] A DFT interface can avoid the aforementioned complexities. While a production test system may have limitations, including a lower tolerance for non-deterministic behavior compared to a real system, it may have advantages as well. First, a production test system supports high-precision direct current (DC) measurement circuitry on each test system channel that can be used to measure device resistance (it can force a voltage and measure the current on a given pin, or vice versa). A production test system can also drive or strobe with precisely programmed voltages and perform fine timing searches. These features are typically not feasible in a non-test system environment. It may also be true that a semiconductor device test interface is used during production testing on a production test system, and the test interface is not used outside of the manufacturing environment.

[0034] Traditional high-speed IO PHYs use differential signaling, which halves the effective bandwidth per pin from the actual data rate because differential pairs (RXP / RXN, TXP / TXN) are used. An additional 20% bandwidth reduction can occur due to 8b10b encoding, where each 8-bit signal is encoded into 10 bits to allow for clock recovery. This means that the effective bandwidth achieved is approximately 40% of the data rate for a given pin. For example, if a traditional high-speed IO PHY architecture were used instead of a DFT interface (assuming the non-determinism issue is resolved), the bandwidth per pin would be approximately 40% of the test system driving bandwidth. If the test system were driving a 2 Gbps data rate using an 8b / 10b-encoded data stream onto twice as many pins, the effective data rate would be only 800 Mbps per pin.

[0035] Traditional high-speed serial IO PHYs can only operate at specific frequencies. For example, PCI Express PHYs can only operate at 2.5 / 5 / 10 / 16 / 32 Gbps. In a production environment, testing needs to function at any data rate. For example, a product die-level test environment may only support a maximum operation of 1 Gbps, and therefore the PHY must be able to support this. Silicon debug relies heavily on the flexibility to check timing margins using any of these speeds. The ability of a DFT interface to run at any speed allows for flexible use across multiple test phases and test platforms.

[0036] The test ports of the DFT interface may be accessible at both the die level and the package level, and testing for a given semiconductor device may be accomplished using the same IO pins and interfaces at the die level or the package level. The test system view of the semiconductor device and the test modes required to access a given semiconductor device may be the same for both die- and package-level testing. The test system may have direct access to a given semiconductor device at the package level, meaning that test IO signals from a first semiconductor device are not routed through a second semiconductor device. Because each semiconductor device may be directly connected to the test system through the DFT interface, the semiconductor devices may be tested in parallel. The test application mechanism may be the same for both die- and package-level testing, and the same test vectors may be used for both die- and package-level testing.

[0037] 2 illustrates a system for package-level semiconductor device testing. The system for semiconductor device testing includes a test board 205 and a semiconductor device test system 210. The test board 205 may be a printed circuit board that provides a mechanical and electrical interface connecting a device under test (DUT) to the test system 210. The device under test (DUT) may be connected to the test board 205 for production testing. The test board 205 may also include power and reset interconnect points for a semiconductor package 215 (i.e., the DUT). The interconnect points may be pins, pads, balls, bumps, or have other shapes that mate with the interconnect points of the semiconductor package 215. The test system 210 may include an ATE that tests the semiconductor device to determine whether functionality, speed, power consumption, reliability, and / or other attributes meet selected criteria.

[0038] In FIG. 2 , a system for package-level semiconductor device testing is illustrated with a semiconductor package 215 including a semiconductor device 220 and an IO chip 221. Other numbers and arrangements of semiconductor devices 220 and 221 within the semiconductor package 215 are possible. Furthermore, the semiconductor device 220 may be any number of microprocessors, central processing units (CPUs), graphics processing units (GPUs), processing cores, chiplets, systems-on-chips, other processing hardware, combinations of processors or processing cores or chiplets, programmable general-purpose or special-purpose microprocessors, accelerators, DSPs, IO management devices, programmable controllers, ASICs, programmable logic devices (PLDs), high bandwidth memory (HBM), and / or other memory devices, and / or combinations thereof. The semiconductor device package 215 may be a heterogeneous package that combines different types of semiconductor devices into one package. The semiconductor device 220 may be, for example, any of the chips described herein with respect to FIG. 7 . A chiplet may be a processing core or a processor. The semiconductor devices 220 and 221 include a design for testability (DFT) interface. The design for testability (DFT) interface is coupled to test port IO signal lines 225 within the semiconductor package 215. The test port IO signal lines 225 include the RX_LANE[M] 125M, RX_LANE[0] 125, CLK signal 126, TX_LANE[0] 127, and TX_LANE[N] 127N of FIG. 1 that may connect the semiconductor devices 220 and 221 to the test system 210 through the test board 205. The semiconductor device 220 includes a test port physical layer (PHY) 101 that includes a common lane 105, one or more RX (receivers) 110-110M, and one or more TX (transmitter) lanes 115-115N (described herein with reference to FIGS. 1, 3-5).Test port IO signal lines 225 are shown in semiconductor package 215 and are connected to semiconductor device test system 210 through test board 205. Test board 205 also includes test port IO signal lines 225 and interconnect points that mate with interconnect points in semiconductor package 215 for test port IO signal lines 225 in semiconductor package 215. Test board 205 connects the signal lines to semiconductor device test system 210 through the interconnects.

[0039] Test board 205 may also include high-speed serial IO connections 235, low-speed serial IO connections 237, loopbacks 240 for some TX and / or RX signals, and / or double data rate synchronous dynamic random-access memory (DDR SRAM) and / or low-power DDR SRAM connections 245. Semiconductor package 215 may also optionally include universal chiplet interconnect express (UCIe) interconnects 230 between semiconductor chips 220 and 221.

[0040] FIG. 3 shows a system for chip-level semiconductor device testing. The system for semiconductor device testing includes a test board 305 and a semiconductor device test system 310. The test board 305 may be a printed circuit board that provides a mechanical and electrical interface for connecting a DUT to the test system 310. The DUT may be connected to the test board 305 for production testing. The test board 305 may also include power and reset interconnect points for the semiconductor device 315 (i.e., the DUT in this example). The interconnect points may be pins, pads, balls, bumps, or have other shapes that match the interconnect points of the semiconductor device 315. The interconnect points of the semiconductor device 315 may also be pins, pads, balls, bumps, or have other shapes. Where the numbering of parts in FIGS. 2 and 3 is the same, the description herein of the like-numbered parts with respect to FIG. 2 may be used with respect to FIG. 3. The test port IO signal lines 225 in the test board 305 are connected to DFT interfaces on the semiconductor device 315. Test board 305 connects signal lines through interconnects to a semiconductor device test system 310. Test system 310 may include an ATE that tests semiconductor devices to determine whether functionality, speed, power consumption, reliability, and / or other attributes meet selected criteria.

[0041] Figure 4 provides example waveforms for DFT interface operation, assuming 8 RX and 8 TX lanes. Waveform 405 shows test port RX operation, where a signal is driven from the automatic testing equipment (ATE) to the test port (TP). Waveform 410 shows test port TX operation, where a signal is driven from the test port (TP) to the ATE. TX and RX data are driven by the ATE on both the rising and falling edges of clock (CLK) 126, supporting double data rate (DDR) operation. Data bitstream packets 420 and 421 are numbered to indicate system operation. Where the numbering of portions in Figures 1 and 4 is the same, the description herein of the similarly numbered portions with respect to Figure 1 may be used with respect to Figure 4. The test port input lanes include RX_LANE [LANE] 125 and CLK signal 126. The test port interface logic sends data to the ATE on RX_DATA_EVEN[LANE] 162 and IO RX_DATA_ODD[LANE] 163 based on the CLKOUT signal 170 .

[0042] FIG. 5 provides a diagram of a semiconductor device 505 having a DFT interface 510. The DFT interface 510 is described herein with respect to FIG. 1. The DFT interface includes, for example, the test port physical layer (PHY) 101 and associated features and the test port interface logic 150 and associated features of FIG. 1. The semiconductor device 505 includes logic for performing one or more computing functions and may be, for example, a microprocessor, a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), a processing core, a chiplet, a system-on-chip, a programmable general-purpose or special-purpose microprocessor, an accelerator, a DSP, an IO management device, a programmable controller, an ASIC, a programmable logic device (PLD), a high-bandwidth memory (HBM), or other memory device. A chiplet may be a processor core or a processor.

[0043] Due to manufacturing process variations, the RX termination and TX pull-up and pull-down resistor values ​​may deviate from the desired 50 ohm value and therefore may require calibration. The TP PHY may use the native DC measurement capabilities of the production test system to measure the RX termination and TX pull-up / down resistors and calibrate them to 50 ohms instead of requiring an auto-calibration state machine. These resistors may be programmable by driving a specific code through the common lane TAP port. A binary search may be performed by the test system by driving a known code and then measuring the resistance value of that code. Upon completion of this test system operation, the DUT may have the optimal code for each resistor to achieve, for example, 50 ohms. The code is the value that is programmed into the RX termination and TX pull-up / down resistor settings.

[0044] The TP may use the test system's timing search and programmable voltage capabilities for CLK duty cycle calibration. To do this, the TX pattern generator is loaded with a known pattern and kicked off using the test system-driven CLK as the clock source. The test system then performs a timing search on the TX-driven bitstream to measure the duty cycle seen by the TP PHY. For the first search, default values ​​for the CLK high input level (VIH) and low input level (VIL) are selected. The VIH and VIL values ​​are then updated, and the search is performed again. After this procedure, the test system may have optimized VIH / VIL settings for a near 50 / 50 duty cycle after the CLK receiver.

[0045] Once the resistor and CLK duty cycle calibration is complete, the TP PHY's far-end loopback mode (RX → TX loopback) capability is used for final RX timing (tester driver) and TX (tester strobe) calibration. After this method, the tester has optimal driver and strobe timing values ​​for each lane, and the TP PHY is ready for content validation.

[0046] The PHY 101 in FIG. 1 may have a dedicated power supply that is isolated from the power delivery network of the semiconductor device. The PHY 101 with a dedicated power supply may be tied to ground on the end-user platform so that the test-only PHY 101 does not contribute to any active / dynamic power leakage during end use. The power penalty associated with the PHY 101 with a dedicated power supply in non-production use cases may be zero. Furthermore, using a dedicated power supply for the PHY 101 allows production test use cases to perform voltage searches on the DUT without impacting PHY performance.

[0047] FIG. 6 illustrates a method for testing a semiconductor device. In FIG. 6, a semiconductor device is selected for testing (600). The semiconductor device may be in die form or may be a packaged semiconductor device. A package may include multiple semiconductor devices, which may be tested in parallel, such that multiple semiconductor devices in the package are selected for testing in a single test run. The semiconductor device (or multiple devices) each includes a design for test interface. The design for test interface may be the design for test interface described herein with respect to FIGS. 1, 4, and 5. If the semiconductor device is unpackaged, the test assembly may be the assembly of FIG. 3. If the semiconductor device is packaged, the test assembly may be the assembly of FIG. 4. Test data is sent to the design for test interface (605). The design for test interface may include a transmitter lane 115, a common lane 105, a receiver lane 110, and test port interface logic 150. A clock signal is sent to the common lane (610). Second test data is received from a transmitter lane of the design for testability interface (615). The second test data provides information about the operation of the logic of the semiconductor device. Operations 600, 605, 610, and / or 615 may be performed by a semiconductor device test system, such as automatic test equipment (ATE).

[0048] 7 depicts an exemplary computing system. The computing system may be a system used for a semiconductor test system. For example, instructions for operating automatic test equipment (ATE) or for performing one or more aspects of the process described in FIG. 6 may be stored on and / or executed on the computing system. Computing system 700 may include more, different, or fewer features than those described with respect to FIG. 7.

[0049] Computing system 700 includes a processor 710 that provides processing, operational management, and instruction execution for system 700. Processor 710 may include any type of microprocessor, CPU (Central Processing Unit), GPU (Graphics Processing Unit), processing core, or other processing hardware that provides processing for system 700, or a combination of processors or processing cores. Processor 710 controls the overall operation of system 700 and may be or include one or more programmable general-purpose or special-purpose microprocessors, DSPs, programmable controllers, ASICs, programmable logic devices (PLDs), or the like, or a combination of such devices.

[0050] In one example, system 700 includes an interface 712 coupled to processor 710, which may represent a higher speed or high throughput interface to system components requiring a higher bandwidth connection, such as memory subsystem 720 or graphics interface component 740, and / or accelerator 742. Interface 712 represents interface circuitry that may be a standalone component or that may be integrated on the processor die. If present, graphics interface 740 interfaces to a graphics component for providing a visual display to a user of system 700. In one example, the display may include a touchscreen display.

[0051] The accelerators 742 may be fixed-function or programmable offload engines that can be accessed or used by the processor 710. For example, one accelerator among the accelerators 742 may provide a data compression (DC) function, a cryptographic service such as public key encryption (PKE), a cipher, a hash / authentication function, decryption, or other function or service. In some cases, the accelerators 742 may be integrated into a CPU socket (e.g., a connector to a motherboard (or circuit board, printed circuit board, main board, system board, or logic board) that contains the CPU and provides an electrical interface with the CPU). For example, the accelerators 742 may include a single or multi-core processor, a graphics processing unit, a logical execution unit, a single or multi-level cache, a functional unit usable to execute programs or threads, an application-specific integrated circuit (ASIC), a neural network processor (NNP), programmable control logic, and a programmable processing element such as a field programmable gate array (FPGA) or a programmable logic device (PLD). The accelerator 742 may provide multiple neural networks, a CPU, processor cores, a general-purpose graphics processing unit, or the graphics processing unit may be made available for use by artificial intelligence (AI) or machine learning (ML) models.

[0052] Memory subsystem 720 represents the main memory of system 700 and provides storage for code executed by processor 710 or data values ​​used in the execution of routines. Memory subsystem 720 may include one or more memory devices 730, such as read-only memory (ROM), flash memory, one or more types of random access memory (RAM), such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), and / or other memory devices, or a combination of such devices. Among other things, memory 730 stores and hosts an operating system (OS) 732, which provides a software platform for executing instructions in system 700, and stores and hosts applications 734 and processes 736. In one example, memory subsystem 720 includes memory controller 722, which is a memory controller for generating and issuing commands to memory 730. Memory controller 722 may be a physical part of processor 710 or a physical part of interface 712. For example, memory controller 722 may be an integrated memory controller integrated onto circuitry within processor 710 .

[0053] System 700 may also optionally include one or more buses or bus systems between devices, such as a memory bus, a graphics bus, and / or an interface bus. A bus or other signal line may communicatively or electrically couple components to each other, or may both communicatively and electrically couple components. A bus may include a physical communication line, a point-to-point connection, a bridge, an adapter, a controller, or other circuitry, or a combination thereof. A bus may include, for example, one or more of a system bus, a peripheral component interface (PCI) or PCI express (PCIe) bus, a HyperTransport or industry standard architecture (ISA) bus, a small computer system interface (SCSI) bus, a universal serial bus (USB), or a Firewire bus.

[0054] In one example, system 700 includes interface 714, which may be coupled to interface 712. In one example, interface 714 represents an interface circuit, which may include a standalone component and an integrated circuit configuration. In one example, a user interface component, a peripheral component, or both, couples to interface 714. Network interface 750 provides system 700 with the ability to communicate with remote devices (e.g., servers or other computing devices) over one or more networks. Network interface 750 may include an Ethernet adapter, a wireless interconnection component, a cellular network interconnection component, USB, or other wired or wireless standards-based or proprietary interface. Network interface 750 may transmit data to devices in the same data center or rack or to remote devices, which may include sending data stored in memory.

[0055] Some examples of network interface 750 are part of or used by an infrastructure processing unit (IPU) or data processing unit (DPU). An xPU may refer to at least an IPU, DPU, GPU, GPGPU (general purpose computing on graphics processing unit), or other processing unit (e.g., accelerator device). An IPU or DPU may include a network interface with one or more programmable pipelines or fixed function processors for offloading operations that could be performed by a CPU. An IPU or DPU may include one or more memory devices.

[0056] In one example, system 700 includes one or more input / output (I / O) interfaces 760. I / O interface 760 may include one or more interface components (e.g., audio, alphanumeric, haptic / touch, or other interface connections) through which a user interacts with system 700. Peripheral interface 770 may include additional types of hardware interfaces, such as, for example, interfaces to semiconductor manufacturing units and / or static charge management devices.

[0057] In one example, system 700 includes a storage subsystem 780. Storage subsystem 780 includes storage device 784, which can be or include any conventional medium for storing data in a non-volatile manner, such as one or more magnetic, solid-state, and / or optical-based disks. Storage 784 may be considered generically “memory,” although memory 730 is typically the execution or operating memory that provides instructions to processor 710. While storage 784 is non-volatile, memory 730 may include volatile memory (e.g., the value or state of the data is indeterminate if power to system 700 is interrupted). In one example, storage subsystem 780 includes a controller 782 that interfaces with storage 784. In one example, controller 782 is a physical part of interface 712 or processor 710, or can include circuitry or logic within both processor 710 and interface 714.

[0058] A power source (not shown) provides power to the components of system 700. More specifically, the power source typically interfaces with one or more power sources of system 700 to provide power to the components of system 700.

[0059] Exemplary systems may be implemented in various types of computing, smartphones, tablets, personal computers, and networking units, such as switches, routers, rack, and blade servers, such as those employed in data center and / or server farm environments. (example)

[0060] The semiconductor device may include logic for performing one or more computing functions; and a design-for-test interface, the design-for-test interface having a physical layer including one or more receiver lanes, where the one or more receiver lanes include receiver buffer logic, one or more transmitter lanes, where the one or more transmitter lanes include transmitter buffer logic, and a common lane, where the common lane includes clock buffer logic and network distribution logic; the design-for-test interface is coupled to the logic for performing one or more computing functions, and the design-for-test interface is capable of being coupled to a semiconductor device test system. The design-for-test interface may also include test port interface logic capable of interfacing with the logic for performing one or more computing functions. The design-for-test interface may also include a test port interface including serializer logic, deserializer logic, and clock divider logic. The one or more receiver lanes may also include deserializer logic. The one or more transmitter lanes may also include serializer logic. The one or more transmitter lanes may also include pattern generator logic. The design for testability interface may have a dedicated power supply.

[0061] The semiconductor assembly may include a semiconductor package substrate having test port input / output (IO) signal lines, where the test port IO signal lines include a transmitter line, a clock signal line, and a receiver line; and a semiconductor device having a design-for-test interface, where the design-for-test interface includes a transmitter lane, a common lane, and a receiver lane, and where the test port IO signal lines are operably coupled to the design-for-test interface. The semiconductor assembly may further include three or more processor chiplets, where each of the three or more processor chiplets has a design-for-test interface; and where each of the three or more processor chiplets is operably coupled to a separate test port IO signal line within the semiconductor package substrate. The semiconductor package substrate may have interconnect regions capable of coupling semiconductor test equipment to the test port IO signal lines. The design-for-test interface may also include a test port interface including deserializer logic and clock divider logic. The common lane may include clock buffer logic and network distribution logic. The design for testability interface may include a plurality of transmitter lanes and the signal lines may include a plurality of transmitter lines. The design for testability interface may have a dedicated power supply.

[0062] A method for testing a semiconductor device may include: transmitting first test data to a design-for-test interface in a semiconductor device, where the semiconductor device includes logic for performing one or more computing functions, the design-for-test interface including a transmitter lane, a common lane, and a receiver lane; transmitting a clock signal to the common lane; and receiving second test data from the transmitter lane of the design-for-test interface, where the second test data provides information about operation of the logic of the semiconductor device. The semiconductor device may be a packaged semiconductor device, and a testing system transmits the first test data to the design-for-test interface of the semiconductor device through a package substrate. The transmitting the first data may be performed at a data rate between 2 bps and 2 Gbps. The transmitting the first data may be performed at a clock frequency between 1 Hz and 1 GHz. The direct current (DC) measurement capability of the semiconductor device test system may be used to calibrate a receiver termination resistance of the design-for-test interface. The common lane may include clock buffer logic and network distribution logic.

[0063] In addition to what is described herein, various modifications can be made to the disclosure without departing from its scope. Accordingly, the figures and examples herein should be interpreted in an illustrative rather than a limiting sense. (Other possible items) (Item 1) logic for performing one or more computing functions; and Design for Testability Interface the design for testability interface comprising: a physical layer including one or more receiver lanes, where the one or more receiver lanes include receiver buffer logic, one or more transmitter lanes, where the one or more transmitter lanes include transmitter buffer logic, and a common lane, where the common lane includes clock buffer logic and network distribution logic; the design for testability interface is coupled to the logic for performing one or more computing functions, and the design for testability interface is capable of being coupled to a semiconductor device test system. Semiconductor devices. (Item 2) Item 10. The semiconductor device of item 1, wherein the design for testability interface also includes test port interface logic capable of interfacing with the logic for performing one or more computing functions. (Item 3) Item 1. The semiconductor device of item 1, wherein the design for testability interface also has a test port interface including serializer logic, deserializer logic, and clock divider logic. (Item 4) Item 1. The semiconductor device of item 1, wherein the one or more receiver lanes also include deserializer logic. (Item 5) Item 1. The semiconductor device of item 1, wherein the one or more transmitter lanes also include serializer logic. (Item 6) Item 10. The semiconductor device of item 1, wherein the one or more transmitter lanes also include pattern generator logic. (Item 7) Item 1. The semiconductor device of item 1, wherein the design for testability interface has a dedicated power supply. (Item 8) a semiconductor package substrate, wherein the semiconductor package substrate has test port input output (IO) signal lines, wherein the test port IO signal lines include a transmitter line, a clock signal line, and a receiver line; and a semiconductor device, the semiconductor device having a design for testability interface, wherein the design for testability interface includes a transmitter lane, a common lane, and a receiver lane, and wherein the test port IO signal lines are operably coupled to the design for testability interface; A semiconductor assembly comprising: (Item 9) Item 10. The semiconductor assembly of item 8, further comprising: three or more processor chiplets, each of the three or more processor chiplets having a design for testability interface; and each of the three or more processor chiplets operably coupled to a separate test port IO signal line in the semiconductor package substrate. (Item 10) Item 9. The semiconductor assembly of item 8, wherein the semiconductor package substrate has interconnect areas capable of coupling semiconductor test equipment to the test port IO signal lines. (Item 11) Item 9. The semiconductor assembly of item 8, wherein the design for testability interface also includes a test port interface including deserializer logic and clock divider logic. (Item 12) Item 9. The semiconductor assembly of item 8, wherein the common lane includes clock buffer logic and network distribution logic. (Item 13) Item 9. The semiconductor assembly of item 8, wherein the design for testability interface includes a plurality of transmitter lanes and the signal lines include a plurality of transmitter lines. (Item 14) Item 9. The semiconductor assembly of item 8, wherein the design for testability interface has a dedicated power supply. (Item 15) transmitting first test data to a design for testability interface in a semiconductor device, wherein the semiconductor device includes logic for performing one or more computing functions, and the design for testability interface includes a transmitter lane, a common lane, and a receiver lane; transmitting a clock signal to the common lane; and receiving second test data from the transmitter lane of the design for testability interface, wherein the second test data provides information about operation of the logic of the semiconductor device; 1. A method for testing a semiconductor device, comprising: (Item 16) Item 16. The method of item 15, wherein the semiconductor device is a packaged semiconductor device, and the testing system transmits first test data to the design for testability interface of the semiconductor device through a package substrate. (Item 17) Item 16. The method according to item 15, wherein the step of transmitting the first data is performed at a data rate between 2 bps and 2 Gbps. (Item 18) Item 16. The method according to item 15, wherein the step of transmitting the first data is performed at a clock frequency between 1 Hz and 1 GHz. (Item 19) Item 16. The method of item 15, wherein a direct current (DC) measurement capability of a semiconductor device test system is used to calibrate a receiver termination resistance of the design for testability interface. (Item 20) Item 16. The method of item 15, wherein the common lane includes clock buffer logic and network distribution logic.

Claims

1. Logic for performing one or more computing functions; and Design for Testability Interface the design for testability interface comprising: having a physical layer including one or more receiver lanes, where the one or more receiver lanes include receiver buffer logic, one or more transmitter lanes, where the one or more transmitter lanes include transmitter buffer logic, and a common lane, where the common lane includes clock buffer logic and network distribution logic; the design for testability interface is coupled to the logic for performing one or more computing functions, the design for testability interface being capable of being coupled to a semiconductor device test system. Semiconductor devices.

2. 10. The semiconductor device of claim 1, wherein the design for testability interface also comprises test port interface logic capable of interfacing with the logic for performing one or more computing functions.

3. 10. The semiconductor device of claim 1, wherein the design for testability interface also includes a test port interface including serializer logic, deserializer logic, and clock divider logic.

4. The semiconductor device of claim 1 , wherein the one or more receiver lanes also include deserializer logic.

5. The semiconductor device of claim 1 , wherein the one or more transmitter lanes also include serializer logic.

6. The semiconductor device of claim 1 , wherein the one or more transmitter lanes also include pattern generator logic.

7. The semiconductor device of claim 1 , wherein the design for testability interface has a dedicated power supply.

8. a semiconductor package substrate, wherein the semiconductor package substrate has test port input output (IO) signal lines, wherein the test port IO signal lines include a transmitter line, a clock signal line, and a receiver line; and a semiconductor device, the semiconductor device having a design for testability interface, wherein the design for testability interface includes a transmitter lane, a common lane, and a receiver lane, and wherein the test port IO signal lines are operably coupled to the design for testability interface; A semiconductor assembly comprising:

9. 9. The semiconductor assembly of claim 8, further comprising: three or more processor chiplets, each of the three or more processor chiplets having a design for testability interface; and each of the three or more processor chiplets operably coupled to a separate test port IO signal line in the semiconductor package substrate.

10. 9. The semiconductor assembly of claim 8, wherein the semiconductor package substrate has interconnect areas capable of coupling semiconductor test equipment to the test port IO signal lines.

11. The semiconductor assembly of claim 8 , wherein the design for testability interface also includes a test port interface that includes deserializer logic and clock divider logic.

12. The semiconductor assembly of claim 8 , wherein the common lane includes clock buffer logic and network distribution logic.

13. 9. The semiconductor assembly of claim 8, wherein the design for testability interface includes a plurality of transmitter lanes and the test port IO signal lines include a plurality of transmitter lines.

14. The semiconductor assembly of claim 8 , wherein the design for testability interface has a dedicated power supply.

15. transmitting first test data to a design for testability interface in a semiconductor device, wherein the semiconductor device includes logic for performing one or more computing functions, and the design for testability interface includes a transmitter lane, a common lane, and a receiver lane; transmitting a clock signal to the common lane; and receiving second test data from the transmitter lane of the design for testability interface, wherein the second test data provides information about operation of the logic of the semiconductor device; 1. A method for testing a semiconductor device, comprising:

16. 16. The method of claim 15, wherein the semiconductor device is a packaged semiconductor device including a package substrate, and the testing system transmits first test data to the design for testability interface of the semiconductor device through the package substrate.

17. 16. The method of claim 15, wherein the step of transmitting the first data is performed at a data rate between 2 bps and 2 Gbps.

18. 16. The method of claim 15, wherein the step of transmitting the first data occurs at a clock frequency between 1 Hz and 1 GHz.

19. 16. The method of claim 15, wherein a direct current (DC) measurement capability of a semiconductor device test system is used to calibrate a receiver termination resistance of the design for testability interface.

20. The method of claim 15 , wherein the common lane includes clock buffer logic and network distribution logic.

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