Signal processing method, digital module, analog module and chip

Abstract

The invention discloses a signal processing method, a digital module, an analog module and a chip, and relates to the technical field of chip design and testing, the digital module of the chip is responsible for transmitting a test mode control signal and an original analog control signal, the analog module autonomously processes signal logic in a test mode, and the test mode control signal and the original analog control signal are transmitted to the digital module; and all registers on the digital side can be subjected to uplink scanning. Compared with the process that the number needs to manually screen the downlink register in the traditional scheme, the method has the advantages that the process that the number and simulation repeatedly confirm the downlink register is omitted, the communication cost is reduced, meanwhile, the problem that the register is missed to be tested due to downlink is avoided, and the coverage rate of testability design is increased.

Description

Technical Field

[0001] The present application relates to the field of chip design and testing technology, and in particular to a signal processing method, a digital module, an analog module and a chip. Background Art

[0002] In the field of Design for Test (DFT) for System-on-Chip (SOC), specialized processing of analog module control signals is crucial for accurate and reliable testing of mixed-signal chips. Through signal isolation, state preservation, and timing control, analog circuits can maintain a stable state during testing, thereby obtaining valid test results. This process relies on close collaboration between digital and analog design teams from architecture planning to implementation.

[0003] In existing DFT systems, digital modules must latch or downlink analog control signals. This essentially fixes the signal path so that the digital output remains constant, thus stabilizing the analog input. This allows control signal switching through the test mode, allowing the digital module to be safely scan tested. Downlinking refers to digital registers that are not connected to the scan chain. Without scanning, these digital registers cannot be directly controlled or observed during testing. This necessitates repeated confirmation between digital designers and analog designers regarding which registers should be downlinked, resulting in cumbersome communication and significant time and labor costs. Furthermore, downlink registers cannot be scan tested, so manufacturing defects in these registers remain undetected, impacting DFT coverage. Summary of the Invention

[0004] The present application provides a signal processing method, a digital module, an analog module and a chip to at least solve the problems of cumbersome processes and coverage bottlenecks in related technologies.

[0005] The present application provides a signal processing method, which is applied to the digital module of a chip, the digital module including a test sub-module and a functional sub-module, and the method includes: when the test mode control signal output by the test sub-module is at a high level, transmitting the test mode control signal to the analog module to control the analog module to enter the test mode; transmitting the analog control signal output by the functional sub-module to the analog module, so that the analog module processes the analog control signal in the test mode, the analog control signal including an enable signal and a calibration signal.

[0006] As an optional implementation provided in an embodiment of the present application, the method further includes: after the chip is powered on, determining that the enable signal is a hardware default value, and determining that the calibration signal is a hardware calibration value.

[0007] As an optional implementation provided in an embodiment of the present application, the method further includes: when the test mode control signal is at a high level, controlling the analog control signal to flip.

[0008] The present application provides a signal processing method, which is applied to the analog module of a chip, including: receiving an analog control signal and a test mode control signal transmitted by a digital module of the chip, the analog control signal including an enable signal and a calibration signal; when the test mode control signal is at a high level, entering the test mode; in the test mode, using the test mode control signal to latch the calibration value corresponding to the calibration signal, and controlling the enable signal to jump according to the design requirements of the analog module.

[0009] An embodiment of the present application further provides a digital module, the digital module comprising:

[0010] A test submodule, used for outputting a test mode control signal;

[0011] A functional submodule is used to output analog control signals, which include enable signals and calibration signals;

[0012] The test submodule is specifically configured to transmit the test mode control signal to the analog module when the test mode control signal is at a high level, so as to control the analog module to enter the test mode;

[0013] The functional submodule is specifically configured to transmit the analog control signal to the analog module, so that the analog module processes the analog control signal in a test mode.

[0014] As an optional implementation provided in an embodiment of the present application, the digital module further includes an initialization submodule for determining, after the chip is powered on, that the enable signal is a hardware default value and that the calibration signal is a hardware calibration value.

[0015] As an optional implementation provided in an embodiment of the present application, the functional sub-module is further configured to: control the analog control signal to be flipped when the test mode control signal is at a high level.

[0016] An embodiment of the present application further provides a simulation module, which includes:

[0017] A receiving submodule, configured to receive analog control signals and test mode control signals transmitted by the digital module, wherein the analog control signals include enable signals and calibration signals;

[0018] The processing submodule is used to enter the test mode when the test mode control signal is at a high level; in the test mode, the calibration value corresponding to the calibration signal is latched using the test mode control signal, and the enable signal is controlled to jump according to the design requirements of the analog module.

[0019] The application further provides a chip comprising the digital module and the analog module.

[0020] The application further provides an electronic device comprising a memory for storing a computer program and a processor for executing the computer program to implement the steps of any of the signal processing methods.

[0021] The application further provides a computer readable storage medium, wherein the computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the steps of any of the signal processing methods.

[0022] The application further provides a computer program product comprising a computer program, and the computer program is executed by a processor to implement the steps of any of the signal processing methods.

[0023] In the application, the digital module of the chip is responsible for transmitting test mode control signals and original analog control signals, and the analog module is responsible for processing signal logic autonomously in the test mode, so that all registers on the digital side can be fully scanned. Compared with the process of manually screening downlink registers on the digital side in the traditional scheme, the process of repeatedly confirming downlink registers by the digital and the analog is omitted, the communication cost is reduced, the problem of missed register caused by downlink is avoided, and the DFT coverage is improved. BRIEF DESCRIPTION OF DRAWINGS

[0024] In order to more clearly illustrate the embodiments of the application, the drawings needed in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0025] Figure 1A A structural diagram of interaction between internal modules of a chip in a related chip design for test technology;

[0026] Figure 1B A timing diagram of chip testing in a related design for test technology;

[0027] Figure 2 A flowchart of a signal processing method provided by an embodiment of the application;

[0028] Figure 3 A structural diagram of interaction between internal modules of a chip provided by an embodiment of the application;

[0029] Figure 4 A timing diagram of chip testing provided by an embodiment of the application;

[0030] Figure 5A schematic diagram of a signal processing method provided in an embodiment of the present application Figure 2 ;

[0031] Figure 6 A schematic diagram of the structure of a digital module provided in an embodiment of the present application;

[0032] Figure 7 A schematic diagram of the structure of a simulation module provided in an embodiment of the present application. DETAILED DESCRIPTION

[0033] In order to more clearly illustrate the embodiments of the present application, the following briefly introduces the technical terms used in the embodiments:

[0034] A system-on-chip (SOC) chip is an integrated circuit that integrates the processor, memory, analog circuits, digital logic, and other functional modules required for a complete electronic system on a single silicon wafer. It highly integrates multiple functional modules to achieve system-level functions.

[0035] Digital modules typically include a central processing unit (CPU), a digital signal processor (DSP), and logic circuits. They are responsible for algorithm processing and system control, outputting control signals through general-purpose input / output (GPIO) or dedicated registers. Analog modules, including phase-locked loops (PLLs), analog-to-digital converters / digital-to-analog converters (ADCs / DACs), and radio frequency (RF) front ends, are sensitive to power supply noise and clock jitter. Analog modules adjust power supply status, oscillator frequency, or gain calibration values ​​based on control signals.

[0036] Design for Test (DFT) is a design approach that integrates test logic into chip design, enabling efficient fault detection after chip manufacturing. By adding dedicated test circuits (such as scan chains and boundary scan), chip testability is improved and testing costs are reduced.

[0037] DFT mode is a special operating mode set to support test functions during chip design for testability. This mode activates the DFT circuitry within the chip, causing the chip to exit its normal functional state and enter a test state specifically for fault detection.

[0038] DFT coverage is a core indicator to measure the quality of test, which directly reflects the detection ability of test vectors to potential defects of the chip. By calculating the proportion of detected faults to all testable faults in the circuit (test coverage), the completeness of the test scheme can be quantitatively evaluated.

[0039] As shown in Figure 1A , Figure 1A is a structural diagram of the interaction of internal modules of a chip in a related chip design for testability technology. The top structure (TOP) includes a digital module (DIGITAL) and an analog module (ANALOG).

[0040] The digital module includes a test submodule (TEST) and a functional submodule (MODULE1 / 2 / 3). The test submodule is responsible for generating a test mode control signal (DFT_MODE) for determining whether the chip enters a test mode; the functional submodule is responsible for generating analog control signals such as an enable signal (EN1 / 2) and a calibration signal (TRIM1), which are used to adjust the power supply, clock, or calibration parameters of the analog module. The analog module includes an oscillator (OSC), a power supply circuit, and a radio frequency (RF) circuit that is sensitive to interference, and needs to receive stable analog control signals (EN1 / EN2 / TRIM1) to ensure performance.

[0041] In normal working mode, DFT_MODE is invalid, and EN1 / EN2 / TRIM1 is directly controlled by the functional submodule to adjust the analog circuit as needed. In test mode, DFT_MODE is valid, and the TEST module forcibly locks / calibrates the analog control signal through DFT_MODE to ensure that EN1 / EN2 is not frequently switched, to stabilize the analog power supply, fix the calibration value, and avoid performance drift of the analog circuit during testing.

[0042] Analog circuits are extremely sensitive to power supply noise and signal jitter, and if the control signal changes randomly during testing, it will interfere with the real performance test of the analog circuit. Related technologies control analog control signals through DFT_MODE to ensure that the chip can stably and repeatedly verify the analog circuit during production testing, and avoid interference of digital test logic with the analog module.

[0043] As shown in Figure 1B , Figure 1B is a timing diagram of chip testing in a related design for testability technology. The diagram is divided into a hardware initialization phase, a software initialization phase, and a DFT scan phase. The analog circuit is configured as needed, and at the same time, it is in a locked state during testing to avoid interference of digital test logic with the analog module.

[0044] Specifically, after the chip is powered on, the analog module enable signals (EN1 / EN2) directly control the power switch of the analog module according to the hardware design. The hardware default calibration values, such as 32'h5a and 32'hcf, are loaded, and the hardware logic automatically completes initialization.

[0045] After hardware initialization is complete, the software further adjusts the configuration and enters the software initialization phase. The software fine-tunes the enable state to ensure that the analog circuit enters the expected test state and maintains the analog calibration values ​​(TRIM1 / TRIM2) initialized by the hardware.

[0046] When the test mode control signal (DFT_MODE) is pulled high, the chip enters test scan mode. The digital module shifts the scan chain using the scan clock (SCANCK) to detect faults. Because the digital module latches / downlinks the enable (EN1 / EN2) and calibration signals (TRIM1 / TRIM2), the signal path is fixed, the digital output remains stable, and the analog input also stabilizes. Switching to DFT_MODE allows the digital module to safely perform scan tests (SCANCK operation), keeping the analog circuit in the desired state during design. This prevents signal fluctuations during the test scan from interfering with the analog circuit and causing test misjudgments.

[0047] Downlinking refers to digital registers that are not connected to the scan chain, meaning they are not scanned. Therefore, they cannot be directly controlled or observed during testing. Digital designers must repeatedly confirm with analog designers which registers should be downlinked, resulting in cumbersome communication and significant time and labor costs. Furthermore, downlink registers cannot be scan tested, so if they contain manufacturing defects, testing will not reveal them, impacting DFT coverage. Furthermore, if an analog circuit test fails, it is unclear whether the fault lies with the downlink registers or the analog circuit itself, making fault location difficult.

[0048] To this end, an embodiment of the present application provides a signal processing method, in which the digital module notifies the analog module to enter the test mode through a test mode control signal, but does not interfere with the signal processing logic inside the analog module, leaving it to the analog module to independently process the signal logic; the digital module of the chip outputs the original analog control signal, and all digital registers are on-chain, without the need to process the downlink logic, and the process and verification are uniformly handled according to the scan chain. The analog side independently implements signal processing, and the digital side only ensures the timing compliance of the test mode control signal and the analog control signal. The verification link is carried out independently, solving the technical problem of high communication costs. All digital registers are on-chain and testable, which improves the DFT coverage.

[0049] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0050] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0051] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0052] An embodiment of the present application provides a signal processing method, and the method is described in detail in conjunction with the execution flow of the signal processing method.

[0053] like Figure 2 As shown, the method is applied to the digital module of the chip, which includes a test submodule and a function submodule. The signal processing method includes the following steps S201 to S202:

[0054] S201 : When the test mode control signal output by the test submodule is at a high level, transmit the test mode control signal to the analog module to control the analog module to enter a test mode.

[0055] like Figure 3 As shown, the test submodule (TEST) outputs the test mode control signal (DFT_MODE), skips the intermediate forwarding of the functional submodule (MODULE1 / 2 / 3), does not perform downlink processing, and directly transmits it to the analog module (ANALOG).

[0056] In some embodiments, after the chip is powered on, only basic initialization is completed through hardware logic, without the need for software intervention. Hardware initialization includes: determining the enable signal to the hardware default value and the calibration signal to the hardware calibration value. The determination of the hardware default and calibration values ​​clarifies the initial interface state between the digital and analog modules, eliminating the need for complex parameter negotiation and synchronization between the digital module and the analog module. When switching between test modes, only the DFT_MODE signal needs to be monitored for control of the digital module, further reducing cross-module interaction processes and simplifying design and verification.

[0057] It is understandable that after the chip is powered on, it is in the hardware initialization stage, and the test submodule (TEST) outputs the test mode control signal (DFT_MODE) to maintain a low level, such as Figure 4 As shown, it means that the digital module has not entered the test mode and only the most basic initialization is completed through the hardware logic, including determining that the enable signal (EN1 / EN2) is the hardware default value, such as EN1 low and EN2 high, and determining that the calibration signal (TRIM1 / TRIM2) is the hardware calibration value, such as 32'h5a and 32'hcf.

[0058] The above embodiment solidifies the hardware default values ​​of the enable signals (EN1 / EN2) and the hardware calibration values ​​of the calibration signals (TRIM1 / TRIM2), allowing the analog circuit to quickly enter a preset stable operating state after power-on. This eliminates the need for software initialization, reduces the time overhead and instruction execution steps required for software configuration, and enables the chip to complete startup and reach a testable state in a shorter time. Furthermore, the absence of software involvement reduces the complexity of the initialization process, reduces the risk of initialization failure due to software code defects, and improves the robustness of the system.

[0059] In some embodiments, when the test mode control signal is at a high level, the digital module performs a scan test to detect faults by shifting the scan chain through SCANCK, such as Figure 4 As shown in Figure 1. A scan chain is a series of registers connected end-to-end. During testing, the internal chip state is serially read and written using the SCANCK bit shifter, used to detect faults. If a digital register is connected to the chain, it can be controlled or observed by the test vector. If it is disconnected from the chain, the digital register is not connected to the scan chain and therefore cannot be covered by the test.

[0060] The digital registers in this application include general registers, shift registers, status registers, counter registers, built-in self-test registers, boundary scan registers, etc. All digital registers in this application are connected to the scan chain, and their values ​​can be directly read and written through SCANCK and DFT_MODE during testing. Figure 4 As shown, the action of linking digital registers is reflected by the scan clock (SCANCK) and data shifting. SCANCK flips periodically, driving the registers in the scan chain to shift one by one. At this time, the values ​​of all the registers on the chain will be serially read or written for testing.

[0061] Register states are fully transparent and measurable, capturing everything from initialization values ​​to changes during testing. If an analog circuit test fails, the scan chain can be used to read the actual EN / TRIM output values ​​to quickly determine if the problem lies with the digital register or the analog circuit itself.

[0062] In some embodiments, when the test mode control signal is at a high level, the analog control signal is controlled to flip. It is understandable that after the test mode control signal (DFT_MODE) is pulled high, it is in the DFT scanning phase and the analog control signal is normally flipped. Figure 4 As shown, TRIM1 changes from 32'h55 to 32'h66.

[0063] The calibration signal changes during the scanning phase, simulating operating conditions under various parameter configurations and ensuring that the chip's performance can be verified under different calibration values. By controlling the analog signal inversion after pulling DFT_MODE high, the performance stability of the analog circuit under different parameters can be fully verified during the test phase, ensuring the consistency of the analog circuit performance.

[0064] It should be noted that when the test mode control signal output by the test submodule (TEST) is at a low level, the test mode control signal will also be transmitted to the test module. Figure 4 As shown, in normal mode, the test mode control signal is in low level and is invalid.

[0065] S201 : Transmitting an analog control signal output by a functional submodule to an analog module, so that the analog module processes the analog control signal in a test mode.

[0066] like Figure 3 As shown, analog control signals including enable signals (EN1 / EN2) and calibration signals (TRIM1 / TRIM2) are still output by functional sub-modules (MODULE1 / 2 / 3).

[0067] After the test mode control signal DFT_MODE is pulled high, the analog control signals output by the functional sub-module, namely the enable signals (EN1 / EN2) and the calibration signals (TRIM1 / TRIM2), are transmitted to the analog module (ANALOG).

[0068] On the analog module side, the transition of the enable signal (EN1 / EN2) is determined by the analog module's internal logic, without the need for digital module intervention, allowing the analog circuit to switch power / clock states according to its own needs. The analog module latches the calibration value corresponding to the calibration signal (TRIM1 / TRIM2), cutting off the dynamic modification path of the digital module. Therefore, regardless of how the digital output flips, the calibration signal inside the analog module always maintains the initialized value.

[0069] In the above embodiment, the digital module of the chip is only responsible for transmitting the original test mode control signal and the analog control signal, and does not need to care about the signal processing logic in the DFT mode. Compared with the traditional solution, it eliminates the need for mode collaborative verification with the analog module. The digital module does not need to deeply coordinate how the signal changes in the DFT mode, simplifying cross-domain docking.

[0070] In summary, the signal processing method provided by the embodiments of the present application is applied to the digital module of the chip. In this application, the digital module is only responsible for transparently transmitting the test mode control signal (DFT_MODE) and the original analog control signal, so that the analog module can independently process the signal logic. The digital side does not need to care about how the analog side processes it, which greatly reduces the number of communication nodes. The digital module does not need to perform DFT processing on the analog control signal, and there is no need to process the digital registers off-link. All digital registers are on-link, thereby improving DFT coverage.

[0071] like Figure 5 As shown, Figure 5 A signal processing method provided in an embodiment of the present application is applied to an analog module of a chip. The method includes the following steps S501 to S503:

[0072] S501 : Receive an analog control signal and a test mode control signal transmitted by a digital module of a chip.

[0073] The analog control signal includes an enable signal (EN1 / EN2) and a calibration signal (TRIM1 / TRIM2). S502: When the test mode control signal is at a high level, enter the test mode.

[0074] When the test mode control signal DFT_MODE is at a high level, it indicates that the analog module enters the test mode. Figure 4 As shown, after the test mode control signal DFT_MODE is pulled high, the scan test is started and SCANCK starts to shift.

[0075] S503 : In the test mode, the test mode control signal is used to latch the calibration value corresponding to the calibration signal, and the enable signal is controlled to jump according to the design requirements of the analog module.

[0076] When the analog module is in test mode, it autonomously processes the enable signals (EN1 / EN2) and calibration signals (TRIM1 / TRIM2). This includes latching the calibration values ​​corresponding to the calibration signals to maintain stable calibration values, such as maintaining TRIM1 at 32'h55 and TRIM2 at 32'hcc, to prevent calibration value fluctuations from interfering with testing. It also autonomously transitions the enable signals (EN1 / EN2) based on the analog module's design requirements, such as turning EN1 off and EN2 on, to achieve power / clock control in the test state. The EN1 / EN2 transitions are determined by the analog module's internal logic, such as AND / OR gates and state machines on the analog side. No intervention is required on the digital side, allowing the analog circuit to switch power / clock states according to its own needs.

[0077] It can be understood that after DFT_MODE is pulled high, the analog module controls the latch circuit to latch the calibration value corresponding to the current calibration signal (TRIM1 / TRIM2) to make it fixed. In this way, during the test phase, the dynamic modification path of the digital side is cut off, and the TRIM value is forced to be stable. Regardless of how the calibration signal changes, the TRIM signal inside the analog module always maintains the initialized value, avoiding digital side fluctuations interfering with the analog performance. Exemplarily, the analog module independently defines how DFT_MODE handles EN / TRIM, such as AND gate / OR gate operations. Thus, during the test phase, the EN signal state is uniformly controlled, such as fully closed / fully open, to ensure that the analog power supply, clock, etc. are in a safe state for testing.

[0078] In some embodiments, analog module design requirements include functional implementation, performance optimization, compatibility and interface requirements, reliability and robustness requirements, and testing and debugging requirements. For example, enable signals control the start and stop of oscillators, control filter switching operating frequency bands, and control the ADC / DAC to initiate sampling or conversion processes. In test mode, the enable signal must be forced to transition, and the scan chain must be used to verify the analog module's response in different states.

[0079] By dynamically controlling the enable signal transition according to the requirements of the analog module, it is possible to accurately match the analog circuit working scenario, improve system stability and reliability, enhance design flexibility and scalability, and optimize test and debugging efficiency.

[0080] In this embodiment, the analog module independently processes signals according to analog circuit requirements, eliminating the need for digital process verification. This reclaims control of the DFT control logic. The analog circuit independently controls the transition of the test enable signal, and the TRIM value is latched on the analog side, preventing digital fluctuations from interfering with analog performance and achieving purer test results.

[0081] In some embodiments, if analog EN transitions cause power supply noise, power supply decoupling capacitors are added and the transition slope is controlled to avoid interference with other analog module tests. If digital output flips are asynchronous with analog, synchronization registers are added and clock edges are aligned to prevent the scan chain from capturing erroneous data. If TRIM latch logic fails, dual latches and readback checks are added to the analog side to prevent unexpected TRIM value changes during testing.

[0082] In summary, the signal processing method provided by the embodiments of the present application is applied to an analog module of a chip, the analog module autonomously enters a test mode according to a received DFT_MODE signal, and independently determines how to process an EN / TRIM signal. The calibration value (such as TRIM1 / 2) is autonomously latched, so that the digital side calibration register can be completely accessed to a scan chain without a downlink, the register state can be directly controlled / observed during testing, and the DFT coverage is improved. The analog module dynamically toggles the enable signal according to its own design requirements, without the participation of the digital side in specific logic design, thereby reducing the cross-domain communication requirements from the root and improving the design verification efficiency. The analog side autonomously realizes latching of the calibration signal, the verification link is independently performed, and repeated alignment with the digital module is not required, thereby reducing the communication cost. The analog module dynamically processes the signal according to its own requirements, which not only ensures the stability of the test, but also releases the scan test capability of the digital side, thereby realizing the dual improvement of the DFT coverage and the design efficiency.

[0083] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be realized by means of software and the necessary general hardware platform, of course, it can also be realized by hardware, but in many cases, the former is a better embodiment.

[0084] The embodiments of the present application also provide a digital module, as shown in the figure, the digital module comprises: Figure 6 as shown in the figure, the digital module comprises:

[0085] The test submodule 601 is configured to output a test mode control signal.

[0086] The function submodule 602 is configured to output an analog control signal, and the analog control signal comprises an enable signal and a calibration signal.

[0087] The test submodule 601 is specifically configured to, in a case where the test mode control signal is at a high level, transmit the test mode control signal to the analog module to control the analog module to enter a test mode.

[0088] The function submodule 602 is specifically configured to transmit the analog control signal to the analog module, so that the analog module processes the analog control signal in the test mode.

[0089] As an optional embodiment provided by the embodiments of the present application, the digital module further comprises an initialization submodule, configured to: after the chip is powered on, determine that the enable signal is a hardware default value, and determine that the calibration signal is a hardware calibration value.

[0090] As an optional embodiment provided by the embodiments of the present application, the function submodule 602 is further configured to: in a case where the test mode control signal is at a high level, control the analog control signal to be toggled.

[0091] The description of the features in the embodiments of the digital module can be referred to the related description of the embodiments of the signal processing method applied to the digital module, which will not be repeated here.

[0092] The embodiments of the present application further provide an analog module, as shown in the figure, which comprises: Figure 7

[0093] The receiving submodule 701 is configured to receive the analog control signal and the test mode control signal transmitted by the digital module, wherein the analog control signal comprises the enable signal and the calibration signal.

[0094] The processing submodule 702 is configured to enter the test mode when the test mode control signal is at a high level; in the test mode, the calibration value corresponding to the calibration signal is latched by using the test mode control signal, and the enable signal is controlled to jump according to the design requirement of the analog module.

[0095] The description of the features in the embodiments of the analog module can be referred to the related description of the embodiments of the signal processing method applied to the analog module, which will not be repeated here.

[0096] The embodiments of the present application further provide a chip comprising the digital module and the analog module according to any one of the signal processing method embodiments.

[0097] The embodiments of the present application further provide an electronic device comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to perform the steps in any one of the signal processing method embodiments.

[0098] The embodiments of the present application further provide a computer readable storage medium, which stores a computer program, wherein the computer program is configured to perform the steps in any one of the signal processing method embodiments when running.

[0099] In an example embodiment, the computer readable storage medium can include, but is not limited to, a U disk, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store computer programs.

[0100] The embodiments of the present application further provide a computer program product, which comprises a computer program, and the computer program is executed by a processor to perform the steps in any one of the signal processing method embodiments.

[0101] ​An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above-mentioned signal processing method embodiments are implemented.

[0102] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0103] The above is a detailed introduction to the signal processing method, digital module, analog module and chip provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core ideas of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A signal processing method, characterized in that: A digital module applied to a chip, the digital module including a test submodule and a functional submodule, the method comprising: When the test mode control signal output by the test submodule is at a high level, the test mode control signal is transmitted to the analog module to control the analog module to enter the test mode; The analog control signal output by the functional submodule is transmitted to the analog module, so that the analog module processes the analog control signal in the test mode, where the analog control signal includes an enable signal and a calibration signal.

2. The method according to claim 1, characterized in that The method further comprises: After the chip is powered on, the enable signal is determined to be a hardware default value, and the calibration signal is determined to be a hardware calibration value.

3. The method according to claim 1, characterized in that The method further comprises: When the test mode control signal is at a high level, the analog control signal is controlled to be flipped.

4. A signal processing method, characterized in that: Analog modules used in chips include: receiving an analog control signal and a test mode control signal transmitted by a digital module of the chip, wherein the analog control signal includes an enable signal and a calibration signal; When the test mode control signal is at a high level, entering the test mode; In the test mode, the test mode control signal is used to latch the calibration value corresponding to the calibration signal, and the enable signal is controlled to jump according to the design requirements of the analog module.

5. A digital module, characterized in that: include: A test submodule, used for outputting a test mode control signal; A functional submodule, configured to output an analog control signal, wherein the analog control signal includes an enable signal and a calibration signal; The test submodule is specifically configured to transmit the test mode control signal to the analog module when the test mode control signal is at a high level, so as to control the analog module to enter the test mode; The functional submodule is specifically configured to transmit the analog control signal to the analog module, so that the analog module processes the analog control signal in the test mode.

6. A simulation module, characterized in that: include: A receiving submodule, configured to receive analog control signals and test mode control signals transmitted by the digital module, wherein the analog control signals include an enable signal and a calibration signal; a processing submodule, configured to enter a test mode when the test mode control signal is at a high level; In the test mode, the test mode control signal is used to latch the calibration value corresponding to the calibration signal, and the enable signal is controlled to jump according to the design requirements of the analog module.

7. A chip, characterized in that: include: The digital module as claimed in claim 5, and the analog module as claimed in claim 6.

8. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the signal processing method according to any one of claims 1 to 4 when executing the computer program.

9. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein the computer program implements the steps of the signal processing method according to any one of claims 1 to 4 when executed by a processor.

10. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the signal processing method according to any one of claims 1 to 4 are implemented.

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