An emulation optimization method compatible with different layer via fan-out performance

Abstract

The application relates to a simulation optimization method compatible with different layer via fan-out performance, which establishes several vias of different layer fan-out wiring in a same model; groups multiple ground plane reference layers of the via with the largest layer span; configures an independent back pad size variable for each group of ground plane reference layers; determines the back pad size variable combination of each via; sets an optimization target; and simulates all vias according to the back pad size variable combination of the model and the optimization target. The model of the application divides all ground plane reference layers of the long via with the largest layer span into several groups, and configures an independent back pad size variable for each group. The method not only solves the problem that the simulation result does not meet the expectation under high frequency, but also establishes a set of back pad variable combination. The multiple vias of different layer fan-out wiring share the set of back pad variable combination for scanning optimization, and the back pad size combination compatible with the upper layer fan-out wiring via and the lower layer fan-out wiring via can be simultaneously simulated.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of electronic technology, in particular, to a simulation optimization method compatible with different layer via fan-out performance. BACKGROUND

[0002] Printed Circuit Board (PCB) is also known as printed circuit board, and is an important component of physical support and signal transmission of electronic products. The optimization of high-speed via is generally completed by 3D simulation software. The common practice is to set a unified default value for the reverse pads of all layers of via, define the reverse pad parameters as variable parameters, set the optimization target, and start the software to automatically scan the variable parameters to simulate the best optimization scheme.

[0003] For example, using 3D simulation software (HFSS), the size of the reverse pad of all layers is set as variable R, and the return loss of the via at 20GHz frequency is used as the optimization target to find the ideal parameter value that makes the return loss less than-25dB. Then the optimization result is obtained by automatic scanning simulation. Since the optimization frequency is high (up to 20GHz), it is not necessarily possible to achieve the set target by selecting the best one from multiple simulation results after comprehensive scanning. Finally, the size needs to be manually adjusted based on the selected result to obtain a more ideal simulation result, which is very time-consuming.

[0004] In addition, there are multiple vias in a circuit design project, and different vias have different layer changes, i.e., the fan-out wiring of each via from the surface layer to a certain inner layer is different. For example, via A fan-out wiring from the surface layer to the 6th layer, and via B fan-out wiring from the surface layer to the 12th layer. Using the above method is time-consuming, and it is found that the reverse pad parameters suitable for via A cannot be directly applied to via B. Therefore, for different layer vias, the above simulation and debugging method needs to be repeated, which is very inconvenient.

[0005] Therefore, there is an urgent need for a more effective via simulation optimization method that not only efficiently obtains results that meet the optimization target, but also solves the optimization problem of two or more via models with different layer fan-out wiring. SUMMARY

[0006] In order to overcome the low efficiency of the existing simulation optimization method, especially for the optimization problem of multiple vias with different layer fan-out wiring, the present application provides a simulation optimization method compatible with different layer via fan-out performance.

[0007] The technical scheme of the present application is as follows:

[0008] A simulation optimization method compatible with different layer via fan-out performance, comprising the following steps:

[0009] Step 1, several vias of different layer fan-out wires are established in the same model;

[0010] Step 2, a plurality of ground plane reference layers of the via with the largest layer span are grouped;

[0011] The via with the largest layer span is defined as a long via, and the plurality of ground plane reference layers passed by the long via are divided into several groups;

[0012] Step 3, an independent solder pad size variable is configured for each group of ground plane reference layers;

[0013] Step 4, a combination of solder pad size variables of each via is determined;

[0014] According to the ground plane reference layer group passed by each via, the solder pad size variable corresponding to the ground plane reference layer group is determined, and a combination of solder pad size variables of each via is obtained;

[0015] Step 5, an optimization target for simulating all vias is set;

[0016] Step 6, according to the combination of solder pad size variables of the model and the optimization target, all vias are simulated.

[0017] As a preferred technical solution of the present application, the size of the solder pad is defined as: from the center of the long via to the edge of the solder pad.

[0018] As a preferred technical solution of the present application, the step 1 specifically includes the following steps:

[0019] Step 101, a multi-layer circuit board model is established;

[0020] Step 102, in the multi-layer circuit board model, first establish the via with the largest layer span and its solder pad structure;

[0021] Step 103, other vias to be simulated are established in the same multi-layer circuit board model, and the solder pad structure of the previous step is copied to each via.

[0022] As a preferred technical solution of the present application, the step 2 specifically includes the following steps:

[0023] Step 201, the via with the largest layer span is defined as a long via, and the long via is divided into several unit vias;

[0024] Step 202, the ground plane reference layers passed by the same unit via are divided into a group, so that the plurality of ground plane reference layers are divided into several groups.

[0025] Further, the lengths of the several unit vias are equal.

[0026] Preferably, the length of the unit via is 1mm.

[0027] As a preferred technical solution of the present application, the step 3 specifically comprises the following steps:

[0028] As a preferred technical solution of the present application, the step 5 specifically comprises the following steps:

[0029] Step 501, selecting signal return loss as the optimization criterion;

[0030] Step 502, selecting a frequency value as the target frequency in the high frequency band;

[0031] Step 503, setting the target value of return loss at the target frequency according to the signal quality requirement;

[0032] Step 504, all vias are set with the optimization target of the previous step.

[0033] Preferably, the target frequency in step 502 is 20GHz, and the target value in step 503 is -25dB.

[0034] As a preferred technical solution of the present application, the step 6 specifically comprises the following steps:

[0035] Step 601, setting the starting scanning value, scanning range and scanning step value of the plurality of solder pad size variables;

[0036] Step 602, according to the scanning parameters, traversing a plurality of solder pad size combinations to obtain the return loss curves of each via under different solder pad size combinations through simulation;

[0037] Step 603, the system automatically screens out a plurality of solder pad size combinations that make all via simulation results meet the optimization target, and the simulation results;

[0038] Step 604, among the screened plurality of solder pad size combinations, a combination of parameters is selected that can make the return loss results of each via more ideal.

[0039] Further, in step 604, the evaluation criterion for judging whether the return loss results of each via are ideal is one of the following conditions:

[0040] The target value difference between all return losses at the target frequency is less than 1dB;

[0041] All return loss curves within the entire working frequency band are smoother, without sharp fluctuations or sharp peaks.

[0042] Preferably, in step 601, the scanning range is 12 mil to 22 mil, and the scanning step value is 1x10 - 5 mil, 1x10 -8 mil or 1x10 -10 mil.

[0043] The present application according to the above scheme has the beneficial effects that:

[0044] The via back pad size parameter is no longer set as a unified value, but different back pad parameters are applied to several ground plane reference layers considering the capacitive or inductive differences of different positions of the via. Specifically, all ground plane reference layers of the long via with the largest layer change span are divided into several groups, and each group is configured with an independent back pad size variable. Not only can the high-performance via with the best back pad parameter combination that meets the set target be simulated and scanned, solving the problem that the simulation result does not meet the expectation under high-frequency conditions, but also a set of back pad variable combination parameters are established for the model, so that multiple vias of different layer fan-out wires share a set of back pad variable combination parameters for scanning optimization, realizing synchronous simulation operation of all vias, and obtaining a back pad size combination compatible with the upper layer fan-out wire via and the lower layer fan-out wire via. BRIEF DESCRIPTION OF DRAWINGS

[0045] Figure 1 The method flowchart of the present application is shown in the figure;

[0046] Figure 2 The structure schematic diagram of the via model of the present application is shown in the figure;

[0047] Figure 3 The plane schematic diagram of the via model of the present application is shown in the figure;

[0048] Figure 4 The wave loss curve diagram of two vias under a set of preferred back pad size combinations in a specific embodiment is shown in the figure.

[0049] In the figure,

[0050] 1, circuit board; 2, via; 3, back pad; 4, surface layer wire; 5, inner layer fan-out wire. DETAILED DESCRIPTION

[0051] In order to better understand the purpose, technical solution and technical effect of the present application, the present application will be further explained in the following in combination with the figures and embodiments. It should be noted that similar labels and letters represent similar items in the following figures, so once an item is defined in one figure, it does not need to be further defined and explained in the subsequent figures. At the same time, it is declared that the following described embodiments are only for explaining the present application, and are not used to limit the present application.

[0052] It is to be noted that when an element is referred to as being "on" or "connected to" another element, it can be directly on the other element or intervening elements can also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements can also be present. The term "a plurality" means two or more unless specifically indicated otherwise.

[0053] As shown in Figures 1 to 3 An emulation optimization method compatible with different layer via fan-out performance, comprising the following steps:

[0054] Step 1, establishing several vias of different layer fan-out traces in the same model, step 1 specifically comprises the following steps:

[0055] Step 101, establishing a multi-layer circuit board model;

[0056] Step 102, in the multi-layer circuit board model, first establish the via and its anti-pad structure with the largest layer span;

[0057] Step 103, establish other vias to be emulated in the same multi-layer circuit board model, and copy the anti-pad structure of the previous step to each via.

[0058] In this embodiment, the circuit board 1 of the model is a multi-layer board, such as a 12-layer board, a 14-layer board, a 16-layer board, or other layer boards, and the multi-layer board has two pairs of differential vias. The top end of differential via A is connected to the surface layer trace 4, penetrates from the surface layer board, and fans out at the 12th layer board, that is, differential via A has an inner layer fan-out trace 5 at the 12th layer board, and the layer change structure of differential via A is from the surface layer to the 12th layer board. The top end of differential via B is connected to the surface layer trace 4, penetrates from the surface layer board, and fans out at the 6th layer board, that is, differential via B has an inner layer fan-out trace 5 at the 6th layer board, and the layer change structure of differential via B is from the surface layer to the 6th layer board.

[0059] First, establish differential via A with the largest layer span and the anti-pad structure of differential via A, and then establish differential via B in this multi-layer circuit board model and copy the anti-pad structure of differential via A to differential via B. The size of the anti-pad 3 is defined as the distance from the center of the long via 2 to the edge of the anti-pad 3, that is, R. In other optional embodiments, the distance from the edge of the via to the edge of the anti-pad can be used as the size of the anti-pad.

[0060] Step 2, grouping the multiple ground plane reference layers of the via with the largest layer span;

[0061] Define the via with the largest layer span as a long via, and divide the multiple ground plane reference layers passed by the long via into several groups, which specifically comprises the following steps:

[0062] Step 201, define the via with the largest layer change span as a long via, and divide the long via into a plurality of unit vias;

[0063] Step 202, the ground plane reference layers passed by a same unit via are divided into a group, so as to divide a plurality of ground plane reference layers into a plurality of groups.

[0064] In the embodiment, the differential via A is defined as a long via, and the differential via A with a length of 4 mm can be divided into four unit vias along the axial direction according to a division length of 1 mm. The plurality of ground plane reference layers passed by each unit via are divided into a group. It can be seen that the lengths of the plurality of unit vias in the embodiment are equal. In other optional embodiments, the differential via A can be divided into a plurality of unit vias with unequal lengths.

[0065] Step 3, configuring an independent solder pad size variable for each group of ground plane reference layers;

[0066] The specific steps are as follows: configuring a solder pad size value for each group of ground plane reference layers, and setting a plurality of solder pad size values as variables, so that the model has a plurality of independent solder pad size variables.

[0067] In the embodiment, the four unit vias of the differential via A are configured with four solder pad size variables R1, R2, R3 and R4.

[0068] As can be seen from steps 2 and 3, the plurality of ground plane reference layers of the differential via A no longer adopt the structure of the same solder pad parameter, but consider the capacitive or inductive difference of different positions of the via, and apply different solder pad parameters to the plurality of ground plane reference layers respectively. The solder pad size value of each group of ground plane reference layers is set as a variable, so that the model has a plurality of solder pad size variables, allows the plurality of solder pad size variables to be adjusted independently, and can obtain a solder pad variable combination containing a plurality of solder pad size variables, so as to adapt to the electrical characteristic difference of each position and improve the authenticity and accuracy of simulation.

[0069] After the previous three steps, the solder pad parameters of the two via structures can be set as the same set, specifically, step 4 is executed

[0070] Step 4, determining the solder pad size variable combination of each via; specifically, according to the group of ground plane reference layers passed by each via, determining the solder pad size variable corresponding to the group of ground plane reference layers, and obtaining the solder pad size variable combination of each via;

[0071] In this embodiment, according to the ground plane reference layers (from the surface layer to the 6th layer board) passed by the differential via B, there are corresponding solder pad size variables R1 and R2, so the solder pad size variable combination of the differential via B is R1+R2. It can be seen that the differential via A and the differential via B both use the same set of solder pad parameters, and are based on four solder pad size variables R1, R2, R3, and R4, so in the simulation process, the differential via A and the differential via B change synchronously.

[0072] Step 5, set an optimization target, and the optimization target constrains the simulation of all vias; the optimization target can be return loss, insertion loss, or crosstalk suppression; in this embodiment, return loss is taken as the optimization target, and return loss is an important parameter for measuring the degree of signal reflection, which is particularly critical for high-frequency applications, because it directly affects the integrity and transmission efficiency of the signal, which specifically includes the following steps:

[0073] Step 501, select signal return loss as the optimization standard;

[0074] Step 502, select a frequency value in the high-frequency band as the target frequency;

[0075] Step 503, set the target value of the return loss at the target frequency according to the signal quality requirement;

[0076] Step 504, all vias use the optimization target set in the previous step.

[0077] In this embodiment, the target frequency is 20 GHz, and the target value is -25 dB, that is, at a frequency of 20 GHz, the expected return loss should not exceed -25 dB, so as to minimize signal reflection and improve the quality and efficiency of signal transmission. Therefore, the return loss of the differential via A and the differential via B is set together, and both are set to meet the 20GHz, -25db index.

[0078] In other optional embodiments, different high-frequency bands (such as 18GHz, 22GHz, etc.) can be selected as the target frequency according to different application fields or working environments; according to the specific signal quality and system requirements, the target value of the return loss (such as -20dB, -30dB, etc.) can be adjusted to adapt to different design standards and performance indicators.

[0079] Step 6, simulate all vias according to the solder pad size variable combination of the model and the optimization target, which specifically includes the following steps:

[0080] Step 601, set the starting scan value, scan range, and scan step value of a plurality of solder pad size variables;

[0081] determining the starting scan value of each anti-pad size variable, defining the scan range of each anti-pad size variable, setting the step increment at each scan. In this embodiment, the scan range and scan step increment of the four anti-pad size variables are the same. The scan range is 12mil to 22mil; this range covers common anti-pad sizes, ensuring that the optimization process covers a wide enough range of possibilities. The scan step value is 1x10 -5 mil, 1x10 -8 mil, or 1x10 -10 mil; the appropriate step value depends on the specific optimization requirements and the availability of computing resources, a smaller step value can provide higher precision, but will increase simulation time and computational complexity.

[0082] Step 602, according to the scan parameters, traverse multiple anti-pad size combinations, and simulate to obtain the return loss curves of each via under different anti-pad size combinations;

[0083] In this embodiment, the scan range is 12mil to 22mil, and the scan step value is 1x10 -8 mil, traverse different combinations of anti-pad size variables R1, R2, R3, R4, and obtain multiple return loss curves of differential via A and multiple return loss curves of differential via B under each combination.

[0084] Step 603, the system automatically filters out several anti-pad size combinations that make all via simulation results meet the optimization target, and the corresponding via return loss curves under the combinations;

[0085] In this embodiment, according to the set optimization target: (20GHz, -25dB), the system automatically filters out anti-pad size combinations 1, 2, and 3 that can make the return loss curves of differential via A and differential via B meet the indicators, and the three return loss curves of differential via A and the three return loss curves of differential via B under combinations 1-3; the return loss curves of differential via A and differential via B are displayed in two curve graphs respectively.

[0086] Step 604, select a combination of parameters from the filtered several anti-pad size combinations that can make the return loss results of each via more ideal.

[0087] In this embodiment, observe the three return loss curves A1, A2, A3 of differential via A in curve graph A and the three return loss curves B1, B2, B3 of differential via B in curve graph B, and select an anti-pad size combination that makes the return loss curves of differential via A and differential via B more ideal.

[0088] Wherein, judging whether the echo loss result of the via hole is ideal or not can be judged from one of the following conditions:

[0089] a. The target value difference between all echo losses at the target frequency is less than 1dB;

[0090] b. All echo loss curves in the entire working frequency range are more smooth, without sharp fluctuations or peaks.

[0091] In the embodiment, according to condition a, it can be selected that the echo loss curve A3 and the echo loss curve B3 are ideal under the combination of the reverse pad sizes R1=15.69mil, R2=20.98mil, R3=21.34mil and R4=20.98mil. Figure 4 .

[0092] In summary, the application establishes a variable parameter combination of the reverse pad of the long via hole as the same set of variable parameters of all via holes on the model, realizes that a set of reverse pad parameters is shared by multiple via holes of different layer fan-out wires for scanning optimization, can synchronously simulate and operate all via holes, and obtains the reverse pad parameter combination compatible with the via hole of the upper layer fan-out wire and the via hole of the lower layer fan-out wire. It is not necessary to optimize a set of parameters for each layer, and then a design engineer designs the reverse pad of the via hole fan-out structure layer by layer. From the simulation, it is very time-saving, and it is very friendly to the design engineer, and it does not need to spend a lot of effort to design the reverse pad layer by layer. The method is worth promoting.

[0093] The technical features of the above embodiments can be combined arbitrarily, and in order to make the description simple, all possible combinations of the technical features in the above embodiments are not described, however, as long as the combination of the technical features does not exist contradictory, it should be considered that it is within the scope of the present application.

[0094] The above embodiments only express several implementation manners of the application, and the description is more specific and detailed, but it should not be understood as the limitation of the patent scope of the application. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the application, a number of modifications and improvements can be made, which are within the protection scope of the application. Therefore, the protection scope of the patent of the application should be subject to the appended claims.

Claims

1. A simulation optimization method compatible with different layer via fan-out performance, comprising the following steps: Step 1, establishing several vias of different layer fan-out traces in the same model, specifically comprising the following steps: Step 101, establishing a multi-layer circuit board model; Step 102, in the multi-layer circuit board model, first establish the via with the largest layer span and its anti-pad structure; Step 103, establish other vias to be simulated in the same multi-layer circuit board model, and copy the anti-pad structure of the previous step to each via; Step 2, grouping the multiple ground plane reference layers of the via with the largest layer span; Step 3, configuring an independent anti-pad size variable for each group of ground plane reference layers; Step 4, determining the anti-pad size variable combination of each via; According to the ground plane reference layer group passed by each via, determine the anti-pad size variable corresponding to the ground plane reference layer group, and obtain the anti-pad size variable combination of each via; Step 5, setting an optimization target that constrains the simulation of all vias; Step 6, simulating all vias according to the anti-pad size variable combination of the model and the optimization target, specifically comprising the following steps: Step 601, setting the starting scan value, scan range and scan step value of several anti-pad size variables; Step 602, according to the scan parameters, traverse multiple anti-pad size combinations to obtain the return loss curve of each via under different anti-pad size combinations; Step 603, the system automatically screens out several anti-pad size combinations that make the simulation results of all vias meet the optimization target, as well as the simulation results; Step 604, in the screened several anti-pad size combinations, select a combination of parameters that can make the return loss results of each via more ideal.

2. The method for simulation optimization of different layer via fan-out compatibility performance according to claim 1, wherein, The step 2 specifically comprises the following steps: Step 201, define the via with the largest layer span as a long via, and divide the long via into several unit vias; Step 202, the ground plane reference layers passed by the same unit via are divided into a group, so that the multiple ground plane reference layers are divided into several groups.

3. The method of claim 1, wherein, The step 3 specifically comprises the following steps: configuring an anti-pad size value for each group of ground plane reference layers, and setting several anti-pad size values as variables, so that the model has several independent anti-pad size variables.

4. The method of claim 1, wherein The step 5 specifically comprises the following steps: Step 501, selecting signal return loss as the optimization standard; Step 502, selecting a frequency value as the target frequency in the high frequency band; Step 503, setting the target value of the return loss at the target frequency according to the signal quality requirement; Step 504, all vias use the optimization target setting of the previous step.

5. The method for simulation optimization of different layer via fan-out compatibility performance according to claim 4, characterized in that, In step 502, the target frequency is 20 GHz, and the target value in step 503 is -25 dB.

6. The method of claim 1, wherein, The size of the anti-pad is defined as the distance from the center of the long via to the edge of the anti-pad.

7. The method of claim 1, wherein, In step 601, the scan range is 12 mil to 22 mil, the scan step value is 1 x 10 -5 mil, 1 x 10 -8 mil or 1 x 10 -10 mil.

8. The method of claim 1, wherein, In step 604, the judgment standard for judging whether the return loss results of each via are ideal is one of the following conditions: a. At the target frequency, the target value difference between all return losses is less than 1 dB; b. All return loss curves in the entire working frequency band are smoother, without sharp fluctuations or sharp peaks.

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