A design rule checking method and related equipment

Abstract

The present application discloses a design rule checking method and related equipment, including: obtaining the design rules required for wiring, and parsing the design rules to obtain the parsed design rules; in the wiring process, obtaining each unit element in the metal wire path, and obtaining the shape coordinates of each unit element corresponding to the three-dimensional line track grid coordinates; according to the parsed design rules, performing a first processing operation on the shape represented by each shape coordinate, making a prediction based on the processing result of the first processing operation, and determining the relevant violation situation based on the parsed design rules, and avoiding it; after the wiring is completed, obtaining each actual unit element in each actual metal wire path in all the wirings, and obtaining the actual shape coordinates of each actual unit element; according to the parsed design rules, performing a second processing operation on the actual shape represented by each actual shape coordinate to determine the inspection result of whether it is a violation or not.

Description

Technical Field

[0001] The present specification relates to the field of electronic design automation, and more specifically, the present application relates to a design rule checking method and related equipment. Background Art

[0002] With the development of FinFET technology, the complexity of routing in integrated circuit design has increased significantly. Routing DRC under traditional technology usually only involves a few simple rules such as spacing (SPACE), width (WIDTH), enclosure (Enclosure), and performs global checks on each object.

[0003] However, in the FinFET process, due to the introduction of multiple mask technology, the number of design rules has increased exponentially. At the same time, the 3D stacking process has brought cross-metal layer design rules that the planar process does not have, resulting in the existing design rule check (DRC) algorithm facing the problem of rapid expansion of the solution space, and the planar design rule pre-evaluation method cannot accurately reflect the placement and routing accuracy caused by the three-dimensional design rules of FinFET. In particular, the existing technology cannot effectively cope with the layout and routing of ultra-large-scale designs and meet the manufacturing requirements of DRC Clean.

[0004] Therefore, it is necessary to propose a design rule checking method and related equipment to cope with the design rule checking under the FinFET process. Summary of the invention

[0005] A series of simplified concepts are introduced in the Summary of the Invention section, which will be further described in detail in the Detailed Description of the Invention section. The Summary of the Invention section of this application does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0006] In a first aspect, the present application proposes a design rule checking method, comprising:

[0007] Obtaining design rules required for integrated circuit wiring, and parsing the design rules to obtain parsed design rules;

[0008] During the routing process, each time the routing of a signal path is completed, the corresponding metal wire path and each unit element in the metal wire path are obtained, and the shape coordinates of each unit element corresponding to the three-dimensional line track grid coordinates are obtained;

[0009] According to the analyzed design rules, a first processing operation is performed on the shape represented by each of the shape coordinates, a prediction is performed according to the processing result of the first processing operation to obtain an estimated violation probability, and according to the analyzed design rules, relevant violation conditions are determined, and the relevant violation conditions are avoided to complete routing;

[0010] After the routing is completed, each actual metal wire path in the entire routing and each actual unit element in each of the actual metal wire paths are obtained, and the actual shape coordinates of each of the actual unit elements corresponding to the three-dimensional line track grid coordinates are obtained;

[0011] According to the analyzed design rules, a second processing operation is performed on the actual shape represented by each actual shape coordinate, and a violation inspection result is determined according to a processing result of the second processing operation.

[0012] In a feasible implementation manner, the method of obtaining the design rules required for integrated circuit wiring, parsing the design rules, and obtaining the parsed design rules includes: obtaining the design rules required for the integrated circuit wiring from a library exchange format file and a rule set file; and using a parsing unit to parse each of the design rules into a vector consisting of key-value relationship pairs to obtain the parsed design rules.

[0013] In a feasible implementation manner, the parsing unit is used to parse each of the design rules into a vector consisting of key-value pairs to obtain the parsed design rules, including: if there is a first design rule in the obtained design rules, and the first design rule is accompanied by an additional conditional rule, then the parsing unit is used to parse both the first design rule and the additional conditional rule into a vector consisting of key-value pairs to obtain the parsed first design rule; if there are multiple second design rules in the obtained design rules, and the multiple second design rules have the same rule name but different rule contents and constraints, then the parsing unit is used to parse each of the second design rules into a vector consisting of key-value pairs to obtain multiple parsed second design rules.

[0014] In a feasible implementation manner, the parsing unit is used to parse each of the design rules into a vector composed of key-value pairs to obtain the parsed design rules, including: if it is determined that there is a conflict between the design rules corresponding to different mask layers, the different mask layers are colored and marked respectively, and the conflicting design rules between different areas of the same mask layer are merged to obtain the merged design rules; the parsing unit is used to parse the merged design rules into a vector composed of key-value pairs to obtain the parsed design rules.

[0015] In a feasible implementation, the first processing operation is performed on each shape represented by the shape coordinates according to the parsed design rules, and a prediction result of whether there is a violation or not is determined according to the processing result of the first processing operation, including: according to the spacing requirements in the parsed design rules, each first shape is enlarged to generate a corresponding new first shape, and the first shape is a shape that does not include vias among the multiple shapes; pre-wiring is performed on the coordinate points covered by each new first shape, and a pre-wiring shape is generated according to the parsed design rules; geometric operations are performed on the new first shape and the pre-wiring shape to obtain first geometric information, and if the first geometric information meets the constraints in the parsed design rules, the prediction result is determined to be that the first geometric information has a violation.

[0016] In a feasible implementation, the first processing operation is performed on each shape represented by the shape coordinates according to the parsed design rules, and a prediction result of whether there is a violation or not is determined according to the processing result of the first processing operation, including: according to the spacing requirements in the parsed design rules, each second shape is enlarged to generate a corresponding new second shape, and the second shape is a shape of multiple shapes including the via; vias are pre-arranged for each coordinate point covered by the new second shape, and the shape of the pre-arranged vias is generated according to the parsed design rules; geometric operations are performed on the new second shape and the shape of the pre-arranged vias to obtain second geometric information, and if the second geometric information satisfies the constraints in the parsed design rules, the prediction result is determined to be that the second geometric information is in violation.

[0017] In a feasible implementation, the method further includes: generating a corresponding initial wiring evaluation index for each coordinate point in the three-dimensional linear track grid coordinates; during the wiring process, calculating a corresponding intermediate wiring evaluation index for each coordinate point on the metal wire path; adding the intermediate wiring evaluation index to the initial wiring evaluation index corresponding to the corresponding coordinate point to obtain a final wiring evaluation index corresponding to each coordinate point on the metal wire path; if there is a violation in the first geometric information, updating the final wiring evaluation indexes corresponding to the two coordinate points contained in the shape coordinates of the first shape to obtain an updated wiring evaluation index; if there is a violation in the second geometric information, updating the final wiring evaluation indexes corresponding to the two coordinate points contained in the shape coordinates of the second shape to obtain an updated wiring evaluation index.

[0018] In a feasible implementation, the method further includes: storing each coordinate point in the three-dimensional linear track grid coordinates in a routing path vector; if there is a violation in the first geometric information, deleting the two coordinate points contained in the shape coordinates of the first shape from the routing path vector; if there is a violation in the second geometric information, deleting the two coordinate points contained in the shape coordinates of the second shape from the routing path vector.

[0019] In a feasible implementation manner, the method of determining relevant violations according to the analyzed design rules and avoiding the relevant violations to complete wiring includes: determining an estimated violation area in wiring and a shape of the estimated violation area according to the estimated violation probability; amplifying the shape of the estimated violation area according to the spacing requirements in the analyzed design rules to generate an enlarged shape; marking the coordinate points within the coverage range of the enlarged shape as a blocking state, and adjusting the blocking range of the estimated violation area accordingly according to the shape, direction, metal level or via level of the estimated violation area to avoid violations in the wiring process, thereby completing wiring.

[0020] In a feasible implementation manner, the related violation situations are determined according to the parsed design rules, and the related violation situations are avoided to complete wiring, including: according to the parsed design rules, special rules are determined therein, and the special rules are rules hidden in the library exchange format file but existing in the rule set file; according to the special rules, a prohibited rule group is generated, and the coordinate points matching the prohibited rule group are avoided to complete wiring.

[0021] In a feasible implementation, the method further includes: generating a corresponding initial routing evaluation index for each coordinate point in the three-dimensional linear track grid coordinates; updating the initial routing evaluation index of the coordinate point matching the prohibition rule group to obtain an updated routing evaluation index.

[0022] In a feasible implementation manner, the method of determining relevant violations based on the parsed design rules and avoiding the relevant violations to complete wiring includes: establishing multiple three-dimensional bodies for the three-dimensional rules in the parsed design rules, wherein the three-dimensional bodies are composed of a set of coordinate points spanning multiple levels; performing logical operations on the three-dimensional rules in each of the three-dimensional bodies to determine the situations in which the wiring in each of the three-dimensional bodies violates the three-dimensional rules; and avoiding the situations in which the wiring in the three-dimensional bodies that are determined to violate the three-dimensional rules to complete wiring.

[0023] In a feasible implementation, the method further includes: generating a corresponding initial wiring evaluation index for each coordinate point in the three-dimensional linear track grid coordinates; if it is determined that the wiring within a target three-dimensional body among the multiple three-dimensional bodies violates the three-dimensional rules, updating the initial wiring evaluation index of all coordinate points within the target three-dimensional body to obtain an updated wiring evaluation index.

[0024] In a feasible implementation, the second processing operation is performed on the actual shape represented by each of the actual shape coordinates according to the parsed design rules, and the inspection result of whether there is a violation or not is determined according to the processing result of the second processing operation, including: according to the spacing requirements in the parsed design rules, the actual shape represented by each of the actual shape coordinates is enlarged to generate a corresponding enlarged shape; according to the constraints in the parsed design rules, each of the enlarged shapes is judged according to logical operations; if it is judged that a target enlarged shape among the multiple enlarged shapes has a condition that triggers a violation, then through geometric operations, the associated shape of the target enlarged shape is searched, and if the associated shape is found, it is determined that the inspection result is that there is a violation between the target enlarged shape and the associated shape.

[0025] In a feasible implementation, the method further includes: recording shape information of the target enlarged shape and the associated shape, and position information of the target enlarged shape and the associated shape causing violations; and storing the recorded shape information and position information in a design rule check mark library.

[0026] In a feasible implementation, the method further includes: generating a corresponding initial wiring evaluation index for each coordinate point in the three-dimensional linear track grid coordinates; updating the initial wiring evaluation index of the coordinate point corresponding to the recorded position information to obtain an updated wiring evaluation index.

[0027] In a feasible implementation, the method further includes: if there is a wire removal and rerouting or metal wire completion operation, marking the design rules that need to be rechecked to remind the user to recheck after the wire removal and rerouting or metal wire completion operation.

[0028] In a second aspect, the present application proposes a design rule checking device, comprising:

[0029] A parsing unit configured to obtain design rules required for integrated circuit wiring, and parse the design rules to obtain parsed design rules;

[0030] A first acquisition unit is configured to acquire the corresponding metal wire path and each unit element in the metal wire path each time the wiring of a signal path is completed during the wiring process, and acquire the shape coordinates of each unit element corresponding to the three-dimensional line track grid coordinates;

[0031] A first processing unit is configured to perform a first processing operation on the shape represented by each of the shape coordinates according to the parsed design rules, perform prediction according to the processing result of the first processing operation to obtain an estimated violation probability, and determine relevant violation conditions according to the parsed design rules, and avoid the relevant violation conditions to complete routing;

[0032] A second acquisition unit is configured to acquire, after the wiring is completed, each actual metal wire path in all the wirings and each actual unit element in each of the actual metal wire paths, and acquire the actual shape coordinates of each of the actual unit elements corresponding to the three-dimensional line track grid coordinates;

[0033] The second processing unit is configured to perform a second processing operation on the actual shape represented by each actual shape coordinate according to the analyzed design rule, and determine a violation inspection result according to a processing result of the second processing operation.

[0034] In a third aspect, an electronic device comprises: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor is configured to implement the steps of the design rule checking method of any one of the first aspects described above when executing the computer program stored in the memory.

[0035] In a fourth aspect, the present application further proposes a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the design rule checking method of any one of the first aspects is implemented.

[0036] In summary, the design rule checking method proposed in the present application, during the wiring process, each time the wiring of a signal path is completed, the corresponding metal wire path and its unit element are obtained, and the shape coordinates in the three-dimensional line track grid coordinates corresponding to the unit element are obtained. According to the parsed design rules, the shape represented by the shape coordinates is processed to obtain an estimated violation probability, and the relevant violations are avoided to complete the wiring. After the wiring is completed, the actual metal wire path and its unit element are obtained, and the actual shape coordinates corresponding to the unit element are obtained. According to the parsed design rules, the actual shape represented by the actual shape coordinates is processed to determine the inspection result of whether there is a violation or not. Through the above scheme, violations can be effectively predicted and avoided to ensure the accuracy and compliance of the wiring. Compared with the prior art, the method of the present application can better cope with complex design rules, especially for the multiple masks and 3D overlay rules in the FinFET process, and provides a more accurate wiring inspection and avoidance scheme. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present specification. Also, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0038] Figure 1 A schematic diagram of the process of a design rule checking method provided in an embodiment of the present application.

[0039] Figure 2 A schematic diagram of the process of a design rule checking method provided in an embodiment of the present application.

[0040] Figure 3 A schematic diagram of the process of a design rule checking method provided in an embodiment of the present application.

[0041] Figure 4 A schematic diagram of the process of a design rule checking method provided in an embodiment of the present application.

[0042] Figure 5 A schematic diagram of the process of a design rule checking method provided in an embodiment of the present application.

[0043] Figure 6 A schematic diagram of the process of a design rule checking method provided in an embodiment of the present application.

[0044] Figure 7 A schematic diagram of the structure of a design rule checking device provided in an embodiment of the present application.

[0045] Figure 8 A schematic diagram of the structure of a design rule checking electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0046] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices. The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments.

[0047] See also Figure 1 , is a schematic diagram of a design rule checking method provided in an embodiment of the present application, the method comprising:

[0048] Step S110, obtaining design rules required for integrated circuit wiring, and parsing the design rules to obtain parsed design rules;

[0049] Step S120, during the routing process, each time the routing of a signal path is completed, the corresponding metal wire path and each unit element in the metal wire path are obtained, and the shape coordinates of each unit element corresponding to the three-dimensional line track grid coordinates are obtained;

[0050] Step S130: According to the analyzed design rules, a first processing operation is performed on the shape represented by each shape coordinate, and a prediction is performed according to the processing result of the first processing operation to obtain an estimated violation probability, and according to the analyzed design rules, relevant violation situations are determined, and relevant violation situations are avoided to complete routing;

[0051] Step S140, after the routing is completed, obtaining each actual metal wire path in the entire routing and each actual unit element in each actual metal wire path, and obtaining the actual shape coordinates of each actual unit element corresponding to the three-dimensional line track grid coordinates;

[0052] Step S150: Perform a second processing operation on the actual shape represented by each actual shape coordinate according to the analyzed design rule, and determine a violation inspection result according to a processing result of the second processing operation.

[0053] These steps are described in detail below.

[0054] In step S110, design rules required for integrated circuit wiring are acquired, and the design rules are parsed to obtain parsed design rules.

[0055] The wiring of integrated circuits is to determine the way in which various circuit elements, such as transistors, capacitors, resistors, etc., are connected with metal wires during the chip design process to achieve specific circuit functions. Design rules are guidelines that must be followed during the chip manufacturing process. They specify the physical size limits and electrical performance requirements of wiring and other layout elements. For example, the accuracy of photolithography technology determines the minimum line width and spacing, and the electrical performance requirements limit the range of resistance and capacitance. These rules are formulated based on the capabilities and characteristics of the chip manufacturing process.

[0056] The design rules required for integrated circuit wiring are generally extracted from the process files provided by chip manufacturers. To parse the design rules, a specific algorithm is usually written. First, the rules are divided into different categories, such as line width rules, spacing rules, electrical performance rules, etc. Then, the logical relationship between the various rules is deeply analyzed, and the complex rule descriptions are converted into a format that the computer can understand and process, and finally the parsed design rules are obtained, so that in the subsequent wiring design automation process, the wiring can be accurately planned, optimized and checked according to these rules, ensuring that the designed integrated circuit layout can meet both the functional requirements and the limitations of the manufacturing process, thereby achieving successful chip manufacturing and good performance.

[0057] In step S120 , during the routing process, each time a signal path is routed, the corresponding metal wire path and each unit element in the metal wire path are obtained, and the shape coordinates of each unit element in the three-dimensional track grid coordinates are obtained.

[0058] In the wiring process of an integrated circuit, after completing the wiring operation of a signal path, relevant information needs to be collected.

[0059] First, obtain the metal wire path corresponding to the completed signal path. This metal wire path contains several important components: the first is the access point with both the starting point and the end point being Pin. These access points are where the signal starts and ends in the circuit; the second is the metal wires used to transmit electrical signals, which constitute the main channel for signal transmission; the third is the VIA (via) that has the function of connecting different circuit layers. Its function is to realize the electrical connection between different metal layers and ensure that the signal can be smoothly transmitted in the multi-layer circuit structure, so that the entire circuit forms a complete and effective signal transmission system, providing basic information for the subsequent analysis and processing of the metal wire path.

[0060] Next, the metal wire path is divided into unit elements according to the rectangle as the division unit. For each unit element divided in this way, a specific shape coordinate is used to describe it, and its shape coordinate is expressed as (xlow, ylow, xhigh, yhigh), where xlow represents the minimum value of the rectangular element in the horizontal axis direction, ylow represents the minimum value in the vertical axis direction, xhigh is the maximum value in the horizontal axis direction, and yhigh is the maximum value in the vertical axis direction.

[0061] Through such a clear coordinate representation, the specific range and position of each unit element in the entire wiring space can be accurately known, providing accurate data basis for subsequent tasks such as checking compliance with design rules and evaluating the electrical performance of the circuit, ensuring that the integrated circuit wiring can meet the corresponding requirements.

[0062] In step S130, according to the parsed design rules, a first processing operation is performed on the shape represented by each shape coordinate, and a prediction is made based on the processing result of the first processing operation to obtain an estimated violation probability, and according to the parsed design rules, relevant violations are determined and avoided to complete the wiring.

[0063] In the design process of integrated circuits, accurate and compliant wiring is the key to ensuring chip performance. This process begins with the analysis of design rules, which cover requirements from line width, spacing, stacking relationships to electrical characteristics and serve as guidelines for wiring.

[0064] Once the design rules are parsed, the next step is to perform the first processing operation on each shape represented by the shape coordinates. These shapes may be lines representing metal circuits, vias connecting different layers, or outlines of circuit modules with specific functions. The first processing operation may involve a variety of actions, such as enlarging or reducing the shape according to the spacing rules to ensure that it maintains a sufficient safe distance from adjacent shapes; or adjusting the height, depth and other dimensions of the shape according to the stacking rules to make it in the correct hierarchical position in the three-dimensional space; it may also be to optimize the angle and direction of the shape to meet the requirements of electrical performance.

[0065] After the first processing operation is completed, a prediction is performed based on the processing results to calculate an estimated violation probability. This probability value quantitatively represents the possibility of the current shape violating the design rules in the subsequent routing process. For example, if a shape is processed and its spacing with adjacent shapes is near the critical value required by the rules, then its estimated violation probability will be relatively high; on the contrary, if the various attributes of the shape meet the requirements of the rules well, its violation probability will be low.

[0066] Next, further identify the relevant violations based on the previously analyzed design rules. Finally, take effective avoidance measures for these identified violations. If it is a line width violation, you may need to reselect a more appropriate routing path or adjust the line width parameters; if it is a spacing problem, you may need to fine-tune the shape, change its position or direction, and ensure that the spacing with adjacent elements meets the standard. Through the fine processing of each shape, violation prediction and avoidance operations, the entire routing process is gradually completed, so that the final routing plan fully meets the requirements of the design rules, thus laying a solid foundation for the normal operation and excellent performance of the integrated circuit.

[0067] In step S140 , after the routing is completed, each actual metal wire path in the entire routing and each actual unit element in each actual metal wire path are obtained, and the actual shape coordinates of each actual unit element corresponding to the three-dimensional track grid coordinates are obtained.

[0068] After the wiring of the integrated circuit is completed, in order to ensure that the wiring is strictly in line with the design requirements and can guarantee the normal operation of the chip in the future, it is necessary to conduct detailed inspections based on specific strategies and rules. Here, the heuristic strategy is used to perform DRC rule checks on the actual metal wire paths of the wiring. The heuristic strategy can help us find potential non-compliance with the rules more efficiently and specifically. It guides the entire inspection process based on past experience and established logic.

[0069] The actual metal wire paths to be checked have clear components, and their starting and ending points are both pin access points. The pin access point is like the "interface" of the circuit connection. The electrical signal is connected from the pin at the starting point and then transmitted along the metal wire path, and finally reaches the corresponding circuit module through the pin access point at the end point, thereby realizing the connectivity of the entire circuit. The metal wire is the main "channel" for the transmission of electrical signals, carrying the current to flow between various parts. VIA (via) plays a key role in connecting different metal layers, allowing the signal to shuttle smoothly in the multi-layer structure of the integrated circuit, so this complete actual metal wire path is crucial to the functional realization of the entire circuit.

[0070] When performing DRC rule checking, these actual metal line paths are further analyzed in units of rectangles. That is, each actual metal line path is divided into actual unit elements. The reason why rectangles are chosen as units is that their shape is regular, which is convenient for unifying standards and conducting quantitative analysis during the rule checking process. For each actual unit element divided out, there is a corresponding actual shape coordinate to accurately locate its position in space. Its actual shape coordinates are expressed as (xlow, ylow, xhigh, yhigh), where xlow represents the minimum value of the rectangular element in the horizontal coordinate direction, ylow represents the minimum value in the vertical coordinate direction, xhigh is the maximum value in the horizontal coordinate direction, and yhigh is the maximum value in the vertical coordinate direction. Through such clear coordinate definition, the specific range and position of each actual unit element in the three-dimensional space of the entire integrated circuit can be clearly known, which is very critical basic information for accurately judging whether it complies with DRC rules.

[0071] In step S150, according to the analyzed design rules, a second processing operation is performed on the actual shape represented by each actual shape coordinate, and a violation inspection result is determined according to the processing result of the second processing operation.

[0072] In the critical process of integrated circuit design, after completing the routing and obtaining the actual shape represented by each actual shape coordinate, the next steps are crucial to ensure the accuracy and reliability of the design.

[0073] First, we work based on the design rules that we have analyzed before. These design rules are based on the physical limitations of chip manufacturing processes and circuit performance requirements, covering many key parameters such as line width, spacing, and the relative position relationship between layers.

[0074] For each actual shape, a second processing operation will be performed. This operation may involve complex geometric calculations and logical judgments. For example, for a rectangular shape, it may be necessary to accurately calculate its side length, diagonal length, and the distance difference with adjacent shapes in all directions. At the same time, its hierarchical relationship in the entire wiring layout will also be considered to determine whether it has unreasonable overlap with the elements of the upper and lower layers or too large gaps.

[0075] The detailed data and information obtained through the second processing operation will be compared with each standard in the design rules one by one. If a parameter of the actual shape, such as line width, is less than the minimum line width value specified in the design rules, or the distance between it and the adjacent shape is less than the safety distance requirement, then it will be determined that the actual shape has a violation, and the result of the violation check is "yes"; conversely, if all parameters meet the requirements of the design rules, then the result of the check is "no", that is, the actual shape complies with the design rules and there is no violation.

[0076] This precise inspection mechanism is an important line of defense to ensure the quality of integrated circuit design. Only by strictly performing second processing operations and violation inspections on each actual shape can potential design defects be discovered and corrected in a timely manner, ensuring that the final manufactured chip can operate stably according to the expected performance indicators, meet the needs of various complex electronic systems, and provide a solid foundation for the development of the modern science and technology industry.

[0077] The design rule checking method of the embodiment of the present application, during the wiring process, each time the wiring of a signal path is completed, the corresponding metal wire path and its unit element are obtained, and the shape coordinates in the three-dimensional line track grid coordinates corresponding to the unit element are obtained. According to the parsed design rules, the shape represented by the shape coordinates is processed to obtain an estimated violation probability, and the relevant violations are avoided to complete the wiring. After the wiring is completed, the actual metal wire path and its unit element are obtained, and the actual shape coordinates corresponding to the unit element are obtained. According to the parsed design rules, the actual shape represented by the actual shape coordinates is processed to determine the inspection result of whether there is a violation or not. Through the above scheme, violations can be effectively predicted and avoided to ensure the accuracy and compliance of the wiring. Compared with the prior art, the method of the present application can better cope with complex design rules, especially for the multiple masks and 3D overlay rules in the FinFET process, and provides a more accurate wiring inspection and avoidance scheme.

[0078] In some embodiments of the present application, Figure 2 As shown, step S110 may specifically include steps S210 to S220, which are described in detail as follows:

[0079] Step S210: Obtain design rules required for integrated circuit wiring from the library exchange format file and the rule set file.

[0080] The Library Exchange Format (LEF) plays an important role in the field of integrated circuit design. It is mainly used to describe the information of various basic elements in the physical design of integrated circuits, such as standard cells (such as various logic gates, etc.), macro cells (relatively complex functional modules) and their related physical properties. These physical properties include the location of the pins, the information of the metal layer, the height and width of the cell, etc. For the design rules required for wiring, the library exchange format file can provide rule information such as connection restrictions when wiring between different cells, the range of each layer of metal that can be used for wiring, and some specific requirements for wiring at the pins. Through this type of file, you can clearly understand the relevant rules followed at different physical element levels when performing specific wiring operations, ensuring that the wiring can be adapted to the existing physical structures such as cells and modules.

[0081] Rule Deck is a collection of files used to define design rules in the integrated circuit design process. It is a text file containing many rules, which are the guidelines that must be followed in chip design from physical layout to electrical performance. Physical rules cover minimum line width, line spacing, via size and location, etc.; electrical rules include resistance and capacitance limits, signal integrity related rules, etc. In the physical design stage, especially in the wiring process, it plays a key role in the successful manufacture of chips and the performance of chips.

[0082] Obtaining the design rules required for integrated circuit wiring from these two types of files is a basic step in the entire wiring design process. Only by accurately extracting and mastering these rules can we reasonably plan the direction of metal wires, determine the placement of vias, and ensure that the connections between various parts meet the physical and electrical performance requirements in the subsequent wiring work. Without accurate rules obtained from these files, the wiring work may fall into a blind state, resulting in many problems in the designed circuits, such as short circuits, signal transmission errors, or failure to meet chip manufacturing process requirements, which in turn affects the quality of the entire integrated circuit and the final performance.

[0083] Step S220: parse each design rule into a vector consisting of key-value pairs using a parsing unit to obtain a parsed design rule.

[0084] After reading each rule text, it is processed with the help of professional parsing units, which will call the lexical analyzer and the grammatical analyzer. The lexical analyzer is mainly responsible for splitting the rule text into basic language units such as words and symbols, such as identifying identifiers such as "LEF58_SPACING" and numerical values ​​such as "10". On this basis, the grammatical analyzer analyzes the structural relationship between these basic units according to the grammatical rules of the language, and then determines how they constitute a complete rule expression. Through the collaborative work of these two analyzers, each corresponding rule R will be deeply analyzed and parsed into a Constraint vector composed of key-value pairs. For example, a rule about spacing may be presented as a key-value pair such as ("LEF58_SPACING", "10") after parsing. Multiple such key-value pairs are combined to form a Constraint vector, which clearly shows the correspondence between the elements in the rule.

[0085] After the parsing is completed, the key-value relationship in the Constraint vector will be stored in the key-value vector. Just like the corresponding relationship of "LEF58_SPACING 10" mentioned above, it will be stored in the key-value vector in an orderly manner. This storage method is of great significance. It converts the originally complex rule text into a clear and organized data structure that is easy for computer programs to quickly retrieve and process. In the subsequent automatic routing process, whether it is to judge the legality of routing, avoid violating DRC rules, or optimize and adjust the routing plan according to the rules, you can rely on these key-value relationship pairs stored in the key-value vector to quickly obtain rule information, thereby ensuring that the automatic routing work can strictly follow the design requirements, be completed efficiently and accurately, and ensure the final performance and quality of the integrated circuit.

[0086] By parsing into vectors, complex design rules can be effectively managed and applied, especially in FinFET processes, where the number and complexity of design rules have greatly increased due to the introduction of multi-mask technology. By parsing design rules into vector form, the rule processing process can be simplified and design efficiency and accuracy can be improved.

[0087] In some embodiments of the present application, different types of design rule situations may be encountered during the processing of integrated circuit design rules. If there is a first design rule in the acquired design rules, and the rule is also accompanied by an additional conditional rule, the parsing unit will parse the first design rule and the additional conditional rule attached thereto respectively, and convert each of them into a vector form composed of key-value relationship pairs. For example, if the first design rule is a requirement for metal line width, such as "the metal line width is 8 nanometers in a specific area", and the additional conditional rule is "when the temperature is higher than 50 degrees Celsius, the line width is allowed to deviate by ±0.5 nanometers", after parsing, they will become vectors composed of key-value relationship pairs such as ("metal line width", "8 nanometers"), ("temperature condition", "higher than 50 degrees Celsius"), ("line width deviation", "±0.5 nanometers"), etc., thereby obtaining the parsed first design rule, so that these rules can be applied more accurately in the design process later.

[0088] In addition, when there are multiple second design rules in the acquired design rules, these rules have the same rule name, but their respective rule contents and constraints are different. Similarly, the parsing unit is used to independently parse each second design rule and convert them into vectors consisting of key-value relationship pairs. For example, for multiple second design rules about the sizes of vias between different layers, some rules are "the diameter of the via between the signal layer is 5 microns", and some are "the diameter of the via between the power layer and the ground layer is 8 microns and the depth is 10 microns", etc. After parsing, multiple corresponding key-value relationship pair vectors will be obtained, and then multiple parsed second design rules will be obtained, so that in the actual design process, the corresponding rule requirements can be accurately followed according to different scenarios to ensure the accuracy and reliability of integrated circuit design.

[0089] In some embodiments of the present application, the design rules are closely related to different mask layers. When conflicts are found in the design rules corresponding to different mask layers after a specific determination process, a series of measures need to be taken to resolve these issues to ensure the accuracy and consistency of the design.

[0090] First, in order to clearly distinguish and identify conflicting mask layers, different mask layers will be colored and marked separately. This visual approach helps designers quickly locate and understand which mask layers have inconsistent rules. At the same time, conflicting design rules between different areas in the same mask layer will be merged. For example, in a mask layer, one area stipulates that the minimum spacing of metal lines is 8 nanometers, while another area stipulates 10 nanometers. At this time, it is necessary to comprehensively consider various factors, such as circuit performance, feasibility of manufacturing process, etc., to merge these conflicting rules into a reasonable value, such as 9 nanometers, so as to obtain the merged design rules.

[0091] Next, a dedicated parsing unit is used to process the merged design rules. This tool converts complex rule texts into a form that is easier for computers to understand and process, namely a vector consisting of key-value pairs. For example, for the rule of minimum metal line spacing mentioned above, after parsing, a key-value pair such as ("minimum metal line spacing", "9 nanometers") will be formed. All merged rules are parsed in this way to finally obtain the parsed design rules. These parsed rules can be efficiently used by subsequent design automation tools. When performing wiring, layout, and other physical design operations, unified and non-conflicting design rules can be strictly followed to ensure that the integrated circuit can smoothly transition from the design stage to the manufacturing stage and meet the expected performance and functional requirements.

[0092] In some embodiments of the present application, in step S130, according to the analyzed design rules, a first processing operation is performed on the shape represented by each shape coordinate, and according to the processing result of the first processing operation, determining the prediction result of whether or not there is a violation may specifically include the following steps:

[0093] First, according to the spacing requirements in the analyzed design rules, each first shape is enlarged to generate a corresponding new first shape, where the first shape is a shape that does not include a via among the multiple shapes.

[0094] Then, pre-wiring is performed on each coordinate point covered by the new first shape, and a pre-wiring shape is generated according to the analyzed design rules.

[0095] Furthermore, a geometric operation is performed on the new first shape and the pre-wired shape to obtain first geometric information. If the first geometric information satisfies the constraint conditions in the parsed design rules, a prediction result is determined to be that the first geometric information has a violation.

[0096] Specifically, in integrated circuit design, after the design rules are parsed, the spacing requirements (SPACING) play a key role. The "first shapes" mentioned here are those shapes that are specially selected from the many shapes involved in the design and do not contain vias, such as simple metal wire shapes or specific circuit component shapes. In order to ensure that these shapes meet the spacing standards in the design rules, each first shape must be enlarged according to the spacing requirements.

[0097] Specifically, the coordinate range of the first shape is adjusted according to the spacing value specified in the design rules. The original first shape is defined by the coordinates (xlow, ylow, xhigh, yhigh) to define its range on the plane. By expanding it outward in the horizontal (x direction) and vertical (y direction) directions according to the spacing requirements, that is, changing it to a new coordinate range of (xlow - SPACING, ylow - SPACING, xhigh + SPACING, yhigh + SPACING), the corresponding new first shape is generated. This enlargement operation is to reserve enough space in advance to avoid violating the design rules due to insufficient spacing in the future, so that it can meet the safety spacing specifications in the subsequent layout and when it cooperates with other shapes.

[0098] After obtaining the new first shape, the next step is to perform pre-wiring operations on each coordinate point covered by the new first shape. The track grid coordinate points are the basic reference points used to plan the line direction in integrated circuit design. Pre-wiring is performed based on these points, and its purpose is to simulate possible wiring methods and paths in advance.

[0099] The shape of the pre-wiring is generated strictly according to the parsed design rules. The design rules cover many aspects such as line width requirements, wiring direction restrictions, conditions for connecting to other layers, etc. These regulations must be fully followed during pre-wiring to determine the shape of the pre-wiring, which can also be represented by coordinates (xlpre, ylpre, xhpre, yhpre) to represent its range and position. Whether the shape of the pre-wiring is planned reasonably will directly affect the subsequent entire circuit layout and whether it can meet the overall requirements of the design rules.

[0100] After the new first shape and the pre-wired shape are determined, a series of geometric operations need to be performed on them, such as calculating the distance between the two, determining whether there is a containment relationship, checking whether the edges are orthogonal, and performing projection addition, projection subtraction and other operations. These operations are used to obtain the first geometric information, such as the PRL, Manhattan distance, geometric center distance and other similar specific geometric parameter information mentioned above.

[0101] Then, the first geometric information obtained is compared with the constraints in the parsed design rules. The constraints here include many aspects, such as the minimum spacing value allowed between different shapes, the limitation of geometric relationships, etc. Normal understanding may think that if the constraints are met, it is compliant, but in this case, if the first geometric information happens to meet these constraints, it means that there is a possibility of DRC violation. This is because under the current layout that meets the conditions, it may be impossible to add other necessary lines, components, etc. according to the rules in the future due to the overly compact space utilization or lack of flexibility, thereby violating some other potential design rule requirements. Therefore, once the first geometric information meets the constraints, it is determined that the prediction result is that the first geometric information has a violation. Such a prediction can help designers discover potential problems in advance, so as to adjust the layout and wiring scheme in time, ensure that the entire integrated circuit design complies with all design rules, and smoothly carry out subsequent manufacturing and other links.

[0102] In some embodiments of the present application, in step S130, according to the analyzed design rules, a first processing operation is performed on the shape represented by each shape coordinate, and according to the processing result of the first processing operation, determining the prediction result of whether or not there is a violation may specifically include the following steps:

[0103] First, according to the spacing requirements in the analyzed design rules, each second shape is enlarged to generate a corresponding new second shape, where the second shape includes a via among the multiple shapes;

[0104] Then, pre-arrange vias for each coordinate point covered by the new second shape, and generate the shape of the pre-arranged vias according to the analyzed design rules;

[0105] Furthermore, a geometric operation is performed on the new second shape and the shape of the pre-arranged via to obtain second geometric information. If the second geometric information satisfies the constraint conditions in the parsed design rules, the prediction result is determined to be that the second geometric information has a violation.

[0106] Specifically, in the integrated circuit design process, after the design rules are analyzed, the spacing requirements are the key factors to ensure the rationality and compliance of the design. The second shape is defined as those shapes that contain vias among the many shapes involved in the design. For example, in the multi-layer structure of the chip, the vias connecting different metal layers and their surrounding related structural shapes all belong to this category.

[0107] In order to make these second shapes meet the spacing standards in the design rules, they need to be enlarged according to the spacing requirements. According to the SPACING requirements specified in the parsed design rules, the coordinate range of the second shape is adjusted accordingly. Originally, the second shape was determined by the coordinates (xlow, ylow, xhigh, yhigh) to determine its range on the plane. Now, according to the spacing requirements, it is expanded outward in the horizontal (x direction) and vertical (y direction) directions to become a new coordinate range of (xlow -SPACING, ylow - SPACING, xhigh + SPACING, yhigh + SPACING), and then the corresponding new second shape is generated. Through such an amplification operation, appropriate space is reserved in advance to meet the design rule requirements for spacing in subsequent layout and coordination with other shapes, avoiding violations of the rules such as insufficient spacing.

[0108] After obtaining the new second shape, the next step is to pre-layout vias for each line track grid coordinate point covered by the new second shape. In the FinFET process of integrated circuits, the layout of vias is very complex because it needs to meet multiple complex spacing requirements at the same time, such as VIA to VIA (between vias), cross-level VIA to VIA (between vias at different levels), and cross-level VIA to metal wire (between vias at different levels). The spacing requirements must be strictly followed.

[0109] Based on these complex DRC rules, pre-routing vias is performed on the covered coordinate points, and the shape of the pre-routing vias is generated, which is represented here as PreRouteBox, and its coordinate range is defined by (xlpre, ylpre, xhpre, yhpre). The shape generation of this pre-routing via is not arbitrary, but is determined in all aspects based on the analyzed design rules, and it is necessary to comprehensively consider factors such as the size, position, connection relationship with the surrounding structure, and various spacing restrictions of the vias to ensure that it can meet the requirements of the entire circuit design in subsequent actual application scenarios.

[0110] When the new second shape and the shape of the pre-arranged vias are determined, a series of geometric operations need to be performed on them, such as calculating the distance between the two, determining whether there is a containment relationship between them (i.e., whether one shape is completely inside another shape), checking whether the edges are orthogonal (whether the two edges are perpendicular to each other), and performing projection addition, projection subtraction, etc. Through these geometric operations, the second geometric information can be obtained, such as PRL, Manhattan distance, geometric center distance and other specific information reflecting the geometric relationship between them.

[0111] After that, the obtained second geometric information is compared with the constraints in the parsed design rules. The constraints here cover many rules related to vias and the overall layout, involving multiple dimensions such as spacing and positional relationships. Generally speaking, it may be felt that satisfying the constraints is in compliance with the rules, but in this situation, if the second geometric information happens to fully satisfy these constraints, it means that there is a possibility of DRC violation. This is because under the current seemingly compliant layout, as the circuit design is further improved, it may be impossible to add other necessary elements, wiring or meet other potential design rule requirements according to the rules due to insufficient flexibility in space reservation or too compact layout, resulting in violations of the rules. Therefore, once the second geometric information satisfies the constraints, it is necessary to determine that the prediction result is that the second geometric information has violations. Such a prediction mechanism helps designers to detect potential problems in advance, adjust and optimize the via layout and the overall circuit design scheme in a timely manner, and ensure that the entire integrated circuit design strictly follows all design rules and smoothly advances to subsequent links such as manufacturing.

[0112] In some embodiments of the present application, a corresponding initial wiring evaluation index can be generated for each coordinate point in the three-dimensional track grid coordinates; during the wiring process, a corresponding intermediate wiring evaluation index is calculated for each coordinate point on the metal wire path; the intermediate wiring evaluation index is added to the initial wiring evaluation index corresponding to the corresponding coordinate point to obtain a final wiring evaluation index corresponding to each coordinate point on the metal wire path; if there is a violation in the first geometric information, the final wiring evaluation indexes corresponding to the two coordinate points contained in the shape coordinates of the first shape are updated to obtain an updated wiring evaluation index, and the updated wiring evaluation index is used to guide the wiring; if there is a violation in the second geometric information, the final wiring evaluation indexes corresponding to the two coordinate points contained in the shape coordinates of the second shape are updated to obtain an updated wiring evaluation index.

[0113] In the field of integrated circuit wiring design, various planning tasks are carried out based on the three-dimensional line track grid coordinate system. For each coordinate point in this three-dimensional line track grid coordinate, a corresponding initial wiring evaluation index, namely EVA, will be generated. EVA preliminarily measures the suitability and potential impact of the coordinate point for wiring work from multiple key dimensions, and it is vectorial and covers 6 directions, which means that it can comprehensively reflect the characteristics of the coordinate point in space from different angles. For example, these 6 directions may involve the spatial association direction between the coordinate point and different functional modules of the chip, the direction of influence on the wiring direction between different layers, etc. By comprehensively considering these factors, an initial EVA value is assigned to each coordinate point, laying the foundation for dynamic evaluation in the subsequent wiring process.

[0114] As the wiring work progresses, each coordinate point on the metal wire path will generate new considerations due to the real-time situation during the wiring process. At this time, the corresponding intermediate wiring assessment index (EVA) needs to be calculated. In this process, many real-time influencing factors need to be analyzed, such as the actual spacing between the metal wire and the adjacent metal wires in 6 directions when the metal wire passes through the coordinate point, the immediate impact of the change in the direction of the metal wire at this point on the signal transmission in all directions (such as whether it will cause additional attenuation and reflection of the signal in certain directions), and the electromagnetic compatibility of the coordinate point with the surrounding wired parts in different directions. By quantitatively analyzing these complex factors or calculating based on specific models, the corresponding intermediate EVA value is obtained, so as to more carefully and comprehensively reflect the actual situation of the coordinate point in all directions at the current wiring stage.

[0115] After obtaining the initial EVA value of each coordinate point and the intermediate EVA value generated during the wiring process, they should be integrated to obtain the final wiring evaluation index (EVA). The specific approach is to add the calculated intermediate EVA value to the initial EVA value originally corresponding to the corresponding coordinate point according to the corresponding rules, so as to determine the final EVA value corresponding to each coordinate point on the metal wire path. This final EVA value combines the expected situation before wiring and the actual state during the wiring process, and accurately reflects the comprehensive pros and cons of the coordinate point in the entire wiring system from the six directions of its vector nature, whether it meets the design requirements, and the potential impact on subsequent wiring and overall circuit performance in various directions, etc., providing a key basis for subsequent judgment of whether the wiring is compliant and whether it needs to be optimized.

[0116] When the first geometric information is found to be in violation of the rules through the previous geometric operations and other judgment processes (the first geometric information here is usually related to the geometric parameters and relationships of the first shape that does not contain vias), it is necessary to update the final EVA values ​​corresponding to the two coordinate points contained in the shape coordinates of the first shape. Given that the EVA value is vectorial and the update operation can be a variety of methods such as addition, subtraction, weighted average, and maximum likelihood estimation, the appropriate update method will be selected according to the specific violation situation. For example, if the violation of the first geometric information leads to a serious occupation of the wiring space in a certain direction, affecting the feasibility of subsequent wiring, then the EVA value may be reduced by subtracting the EVA value in the corresponding direction to reflect this adverse effect; or according to the comprehensive impact of the violation on the wiring in different directions around, the EVA value is adjusted by weighted average to more accurately reflect the current changes caused by the violation. Through such an update, the updated EVA value is obtained, so that the wiring conditions at these coordinate points and the impact on the overall design in various directions can be more accurately grasped in the future, and then corresponding optimization measures can be taken.

[0117] Similarly, once it is determined that the second geometric information has a violation (the second geometric information here is generally associated with the second shape containing the via), the final EVA values ​​corresponding to the two coordinate points contained in the shape coordinates of the second shape must also be updated. Since vias play a vital role in the connection between different layers of the integrated circuit and signal transmission, the violation of the second geometric information means that the wiring involving the via part does not comply with the design rules in terms of geometric relationship, which will have a significant impact on the normal operation of the entire circuit in multiple directions and the rationality of the wiring. Based on this, according to the specific circumstances of the violation, such as the difference in different directions due to the non-compliance of the via spacing requirements, the interference of adjacent wiring and components in various directions, etc., the final EVA values ​​corresponding to the two coordinate points will be adjusted using appropriate update operations (such as addition, subtraction, weighted average, maximum likelihood estimation, etc.), so that the updated EVA value can fully reflect the impact of the violation in all directions, and also provide an important reference basis for further revising the wiring scheme and ensuring that the wiring complies with the design rules in all vector directions, so as to ensure that the wiring quality and circuit performance of the entire integrated circuit can meet the expected requirements.

[0118] In some embodiments of the present application, in the wiring design process of the integrated circuit, the three-dimensional line track grid coordinate system constructs the spatial framework of the entire wiring, in which each coordinate point has a unique meaning and value. In order to facilitate the subsequent unified management, analysis and operation of the wiring situation, each coordinate point in the three-dimensional line track grid coordinate will be stored in the wiring path vector (Route). This wiring path vector is like an ordered "container" that records the information of each coordinate point in a certain order. It can fully outline the direction and coverage of the wiring in the entire three-dimensional space. For example, assuming that there are coordinate points (x1, y1, z1), (x2, y2, z2), etc. in the three-dimensional line track grid, they will be added to the wiring path vector Route in turn, thereby forming a set that can reflect the wiring trajectory, which provides basic data support for subsequent wiring planning, evaluation and adjustment.

[0119] When the first geometric information is found to be in violation after a series of geometric operations and rule judgments, the wiring path vector needs to be adjusted accordingly. The first geometric information here is often associated with those first shapes that do not contain vias, such as the spacing between the first shapes, relative position relationships and other geometric parameters that do not meet the established design rule requirements. The two coordinate points contained in the shape coordinates of the first shape are the key elements for determining the position of the shape in three-dimensional space. Once the corresponding first geometric information violates the rules, it means that the location of these two coordinate points may have a negative impact on the compliance of the entire wiring and circuit performance. Therefore, in order to ensure the accuracy of the wiring path and comply with the design rules, these two coordinate points should be deleted from the wiring path vector. This is equivalent to removing the potential wiring track that does not comply with the rules, so as to prevent it from continuing to affect the subsequent wiring optimization and the normal operation of the circuit, so that the wiring scheme represented by the remaining wiring path vector is more likely to meet the design requirements.

[0120] Similarly, if there is a violation in the second geometric information, a similar treatment method is also required. The second geometric information is usually related to the second shape containing the via. Since the via plays an important role in connecting different layers and ensuring smooth signal transmission in the multi-layer structure of the integrated circuit, whether the related geometric relationship conforms to the rules is particularly critical. When the second geometric information is violated, it means that the geometric conditions of the positions of the two coordinate points contained in the shape coordinates of the second shape do not meet the design rules. For example, the spacing and relative position between the via and the surrounding structure do not meet the requirements, which is likely to cause signal transmission abnormalities, circuit short circuits and other problems. Therefore, these two coordinate points should also be deleted from the wiring path vector to correct the wiring path and eliminate the potential risks caused by these non-compliant coordinate points, so that the wiring scheme reflected by the wiring path vector is more reasonable and compliant, ensuring that the wiring of the entire integrated circuit can proceed smoothly and ultimately meet the expected goals of the chip in terms of function and performance.

[0121] By deleting the corresponding coordinate points of the wiring path vector according to whether the geometric information violates the rules, the wiring plan can be continuously optimized to closely fit the design rules, laying a solid foundation for the successful manufacture of integrated circuit chips with excellent performance.

[0122] In some embodiments of the present application, Figure 3 As shown, in step S130, the relevant violation is determined according to the analyzed design rules, and the relevant violation is avoided to complete the wiring, which can specifically include steps S310 to S330, which are specifically described as follows:

[0123] Step S310: Determine the estimated violation region and the shape of the estimated violation region in the wiring according to the estimated violation probability.

[0124] When we get the estimated violation probability corresponding to each area, we use it as a basis to determine the estimated violation area. If the estimated violation probability of a certain area is relatively high, it means that there is a high possibility of violation in this area and it needs to be paid special attention. When the estimated violation probability reaches 100%, it means that from the perspective of the existing design rules, this area will definitely violate the rules and there is no possibility of complying with the rules. Therefore, the specific spatial range corresponding to this 100% estimated violation probability is undoubtedly identified as the estimated violation area.

[0125] For example, in a wiring area, there is a metal line. After analyzing and evaluating its line width, the spacing between it and adjacent lines and vias, the layer it is located in according to the design rules, it is found that all conditions do not meet the requirements of the rules. After comprehensive calculation, the probability of violation is 100%. Then this metal line and the surrounding space that is closely related to it and will be affected by it constitute the estimated violation area.

[0126] After the estimated violation area is identified, it is also critical to further determine its shape. The shape of the estimated violation area depends on the distribution characteristics of the wiring elements in the area and the spatial relationship between them. It may present a relatively regular geometric shape, such as a rectangular shape. It may be a violation area composed of multiple parallel metal wires with non-compliant spacing, which looks approximately rectangular overall; it may also be circular or elliptical, such as around a via, because the spacing between it and the surrounding lines in all directions does not meet the standards, a circular violation area is formed with the via as the center.

[0127] Step S320: According to the spacing requirement in the analyzed design rule, the shape of the estimated violation area is enlarged to generate an enlarged shape.

[0128] In integrated circuit wiring design, the spacing requirements in the design rules are very critical. For the estimated violation area, the shape is enlarged according to the spacing requirements to generate the enlarged shape.

[0129] Step S330, mark the coordinate points within the coverage range of the enlarged shape as a blocked state, and adjust the blocking range of the estimated illegal area accordingly according to the shape, direction, metal layer or via layer to which the illegal area belongs, so as to avoid violations during the wiring process and complete the wiring.

[0130] In the integrated circuit routing process, marking the coordinate points covered by the enlarged shape and adjusting the blocking range is a key operation to ensure the accuracy and compliance of the routing.

[0131] First, when the shape of the estimated violation area is enlarged according to the spacing requirements in the design rules, the coordinate points within its coverage will be marked as blocked. This means that when the automatic routing algorithm runs, the area where these marked coordinate points are located will be considered as a non-routable area.

[0132] Then, the blocking range is finely adjusted according to the specific characteristics of the estimated violation area, such as whether the shape is circular, square or irregular, whether the direction is horizontal, vertical or inclined, and the metal layer or via layer to which it belongs. If it is a long strip of estimated violation area and the direction is horizontal, then the blocking range may be appropriately extended in the horizontal direction to ensure that it fully covers the area where routing conflicts may occur; if it is at a specific metal level, the electrical characteristics of the metal layer and the interaction with the adjacent layers will also be considered to further optimize the blocking range, ensuring that during the entire routing process, the special properties of the estimated violation area are fully utilized, and interference with other routing areas is avoided, and finally the routing task that meets the design requirements is successfully completed, improving the performance and reliability of the integrated circuit.

[0133] In some embodiments of the present application, Figure 4 As shown, in step S130, according to the analyzed design rules, relevant violations are determined, and relevant violations are avoided to complete the wiring, which may specifically include steps S410 to S420, which are described in detail as follows:

[0134] Step S410: Determine the special rules according to the parsed design rules, where the special rules are rules hidden in the library exchange format file but exist in the rule set file.

[0135] Specifically, during integrated circuit wiring design, there are some hidden contents in related design files, such as library exchange format files, but there are special rules corresponding to them in the rule set files.

[0136] Step S420: Generate a prohibited rule group according to the special rule, and avoid the coordinate points matching the prohibited rule group to complete the routing.

[0137] For these special rules, it is necessary to use the clear rules in the rule set file and the experience accumulated by experts in long-term practice to pre-process them. Because these special rules involve some unique shapes, specific coordinates and their mutual relationships, after the above pre-processing process, these shapes, coordinates and their mutual relationships with special properties will be unified and defined as the Forbidden Shape rule group.

[0138] Afterwards, during the routing process, once a coordinate point or shape is found to match the range covered by this prohibited rule group, it will be avoided to ensure that the routing operation does not violate these special rule requirements, thereby ensuring that the entire routing work can be carried out in an orderly manner in strict accordance with the design rules, and ultimately successfully completing the routing task, so that the integrated circuit can meet the expected standards in terms of performance and function.

[0139] In some embodiments of the present application, in the integrated circuit wiring design work, first of all, for each coordinate point in the three-dimensional line track grid coordinates, a corresponding initial wiring evaluation index will be generated accordingly. Then, for those coordinate points that can match the prohibited rule group, the original initial wiring evaluation index is updated, and finally the updated wiring evaluation index can be obtained. As mentioned above, the initial wiring evaluation index is EVA. EVA preliminarily measures the suitability, potential impact, etc. of the coordinate point for the wiring work from multiple key dimensions, and it is vectorial and covers 6 directions. The update of the initial wiring evaluation index can be operations such as addition, subtraction, weighted average, and maximum likelihood estimation.

[0140] In some embodiments of the present application, Figure 5 As shown, in step S130, according to the analyzed design rules, relevant violations are determined, and relevant violations are avoided to complete the wiring, which may specifically include steps S510 to S530, which are described in detail as follows:

[0141] Step S510: For the three-dimensional rules in the analyzed design rules, multiple three-dimensional bodies are established, where the three-dimensional bodies are composed of a group of coordinate points spanning multiple levels.

[0142] In the field of integrated circuit wiring design, the analyzed design rules contain various dimensions and types of rule requirements, among which three-dimensional rules are of great significance. The application of advanced processes such as multi-mask technology has brought more complex three-dimensional rule scenarios. In order to better respond to and reflect these rules, it is necessary to establish multiple three-dimensional bodies for concrete presentation and subsequent rule application.

[0143] For three-dimensional rules, a three-dimensional body with rule boundaries must be established. This three-dimensional body is not a simple geometric shape, but is composed of a set of grid point coordinates across multiple levels. The multiple levels here may involve different metal layers, dielectric layers, etc. in the integrated circuit. These grid point coordinates are combined together to accurately define the scope and boundaries of this three-dimensional body in three-dimensional space. This three-dimensional body represents the corresponding rule boundary range. Based on the rule range determined by these three-dimensional bodies, it can be judged whether the wiring is compliant and whether it meets the corresponding space and process requirements, etc., to ensure that the entire integrated circuit wiring can follow the complex three-dimensional rules and proceed smoothly.

[0144] Step S520: Perform a logical operation on the three-dimensional rules in each three-dimensional volume to determine whether the wiring in each three-dimensional volume violates the three-dimensional rules.

[0145] In the wiring design of integrated circuits, there are complex rules involving multiple metal layers and multiple VIA (via) layers. In order to accurately control whether the wiring meets these rules, logical operations such as AND, OR, and NOT need to be performed on it.

[0146] For example, the "AND" logic operation means that only when multiple conditions are met at the same time, it is judged to comply with the rules. If one of the conditions is not met, it is a violation. For example, a wiring must meet the requirements of a specific metal level range and pass through a specific VIA level range at the same time to be considered to comply with the rules. If any of the conditions is missing, it is considered to be a violation. The "OR" logic operation means that as long as one of the multiple conditions is met, it is considered to comply with the rules. Conversely, if all conditions are not met, it is a violation. The "NOT" logic operation is to negate the established rule conditions. For example, it is stipulated that it cannot pass through a certain metal level and VIA level combination area. If the wiring appears in this area, it is a violation.

[0147] By rigorously applying various logical operations, it is possible to accurately determine which wiring is violating the rules that span multiple metal layers and multiple VIA layers.

[0148] Moreover, each constructed three-dimensional body here represents an independent inspection unit. Since each three-dimensional body is relatively independent and there is no interdependent order relationship, the above-mentioned logical operations and violation judgment work can be performed on them in parallel. In this way, the efficiency of judging violations is greatly improved, and all wiring situations that do not meet the rules can be quickly and accurately sorted out in a complex integrated circuit wiring environment, thereby providing a strong basis for subsequent wiring adjustment and optimization, and ensuring that the entire wiring work strictly follows the design rules and proceeds smoothly.

[0149] Step S530: Avoid the situation where the wiring in the determined three-dimensional volume violates the three-dimensional rule to complete the wiring.

[0150] In the wiring design of integrated circuits, a three-dimensional body is constructed based on relevant design rules to reflect the complex three-dimensional rules, and through a series of logical operations and other means, the wiring violations of the three-dimensional rules in each three-dimensional body have been clarified. These violations may be varied, such as the wiring does not follow the corresponding spacing requirements and connection sequence requirements when crossing different metal layers or VIA (via) layers, or the line direction does not meet the pre-set angles, paths and other rules in three-dimensional space. Once these violations are found, appropriate measures must be taken to avoid them. Specifically, in the subsequent wiring process, the wiring tools or designers will actively adjust the wiring plan, re-plan the line direction, select appropriate coordinate points and hierarchical connection methods, etc., to ensure that the new wiring will not have the problems that have been determined to violate the three-dimensional rules.

[0151] For example, if a line is found to pass through a specific metal layer area in a three-dimensional body where wiring is prohibited, the direction of the line must be changed to bypass the area and select other layers and coordinate points that meet the rules to complete the connection.

[0152] By continuously avoiding violations in this way, all wiring can strictly follow the requirements of the three-dimensional rules, and ultimately the wiring work of the entire integrated circuit can be successfully completed, ensuring that the circuit will not experience performance degradation, signal interference, or malfunction due to wiring not complying with the rules during subsequent manufacturing and actual operation, thereby ensuring that the chip can achieve the expected functions and performance goals.

[0153] In some embodiments of the present application, in the integrated circuit wiring design work, first of all, for each coordinate point in the three-dimensional line track grid coordinates, a corresponding initial wiring evaluation index will be generated accordingly. Then, if it is determined that the wiring in the target three-dimensional body among the multiple three-dimensional bodies violates the three-dimensional rules, the initial wiring evaluation index of all coordinate points in the target three-dimensional body can be updated to obtain an updated wiring evaluation index. As mentioned above, the initial wiring evaluation index is EVA. EVA preliminarily measures the suitability, potential impact, etc. of the coordinate point for the wiring work from multiple key dimensions, and it is vectorial and covers 6 directions. The update of the initial wiring evaluation index can be operations such as addition, subtraction, weighted average, and maximum likelihood estimation.

[0154] In some embodiments of the present application, Figure 6 As shown, step S150 may specifically include steps S610 to S620, which are described in detail as follows;

[0155] Step S610: According to the spacing requirement in the analyzed design rule, the actual shape represented by each actual shape coordinate is enlarged to generate a corresponding enlarged shape.

[0156] Specifically, in integrated circuit design, after the design rules are parsed, the spacing requirements (SPACING) play a key role. The "actual shape" mentioned here refers to the shape represented by the shape coordinates of the actual unit elements on the metal wire path after wiring is completed. In order to ensure that these shapes meet the spacing standards in the design rules, each actual shape must be enlarged according to the spacing requirements.

[0157] Specifically, the coordinate range of the actual shape is adjusted according to the spacing value specified in the design rules. The original actual shape is defined by the coordinates (xlow, ylow, xhigh, yhigh) on the plane, and it is expanded outward in the horizontal (x direction) and vertical (y direction) directions according to the spacing requirements, that is, it becomes a new coordinate range of (xlow - SPACING, ylow - SPACING, xhigh + SPACING, yhigh + SPACING), thereby generating the corresponding enlarged shape.

[0158] Step S620: According to the constraints in the analyzed design rules, each enlarged shape is judged by logical operation.

[0159] In integrated circuit wiring design, the analyzed design rules cover many key constraints, such as WIDTH (line width related requirements), ENDOFLINE (line end related regulations), ENCLOSURE (enclosure, coverage and other limitations), etc. These constraints jointly regulate all aspects of wiring to ensure that it meets design expectations and electrical performance requirements.

[0160] This embodiment uses logical operations to comprehensively consider the relationship between various conditions based on established design rules. For example, when the "AND" operation is used, only when WIDTH meets the specific line width range, ENDOFLINE meets the specific setting requirements of the line end, and ENCLOSURE also meets the corresponding enclosing or covering standards, and these conditions are met at the same time, it meets a certain rule requirement; "OR" operation means that as long as one of the conditions of WIDTH, ENDOFLINE, ENCLOSURE meets the corresponding setting rule, it is considered to meet the corresponding rule; "NOT" operation is to perform a reverse judgment on a certain condition, such as stipulating that a certain area cannot appear in a situation that does not meet the specific ENCLOSURE requirements, etc.

[0161] For each enlarged shape generated by the previous steps, it is necessary to use the above-mentioned logical operation method to determine whether it has the conditions to trigger DRC (design rule check) violations based on these constraints. In other words, check whether this enlarged shape does not meet the requirements of WIDTH, ENDOFLINE, ENCLOSURE, etc. stipulated in the design rules in terms of its line width, line ends, and the surrounding or covering relationship with the surrounding area. If it is found after logical operation that it does not meet the rules in these key constraints, it means that the area where this enlarged shape is located may trigger DRC violations; if it is judged that all the rule requirements are met, it means that the enlarged shape will not currently cause DRC violations due to these conditions.

[0162] Step S630: If it is determined that the target enlarged shape among the multiple enlarged shapes has the condition of triggering a violation, then through geometric operations, the associated shape of the target enlarged shape is searched, and if the associated shape is found, it is determined that the inspection result is that there is a violation between the target enlarged shape and the associated shape.

[0163] After the previous judgment, if it is confirmed that a target magnified shape among multiple magnified shapes has the conditions to trigger a violation, it is necessary to use 3D geometric operations for further in-depth analysis. The 3D geometric operations mentioned here include various specific operations such as spacing, inclusion, orthogonality, projection addition, projection subtraction, projection spacing, and projection inclusion.

[0164] Taking the spacing operation as an example, it can measure the distance between the target enlarged shape and other shapes in three-dimensional space; the containment operation can determine whether a shape is completely covered by another shape; the orthogonal operation is used to examine whether the angular relationship between shapes meets specific requirements; projection addition and projection subtraction can analyze the relationship by merging or removing shapes in a specific projection direction; projection spacing and projection containment also start from the projection angle to check the distance and containment between shapes on the projection surface.

[0165] By applying these 3D geometric operations, the purpose is to find other shapes that are associated with the target enlarged shape, which is the so-called "associated shape". This associated shape may be closely related to the target enlarged shape in terms of spatial position, geometric relationship, etc., and the interaction between them may affect whether the entire wiring is compliant.

[0166] Once the associated shapes are found through these operations, it means that after comprehensive judgment, it can be determined that the final inspection result is that there is a violation between the target enlarged shape and the associated shape. For example, through the spacing operation, it is found that the distance between the target enlarged shape and a certain associated shape is less than the minimum spacing allowed by the design rules, or through the inclusion operation, it is known that the target enlarged shape should not be included in a certain associated shape, but the actual situation is the opposite. Such geometric relationships that do not comply with the design rules indicate that there is a violation between the two. Subsequently, it is necessary to make corresponding adjustments to the wiring or take other remedial measures based on such violations to ensure that the wiring of the entire integrated circuit strictly follows the design rules and guarantees the performance and normal operation of the circuit.

[0167] In some embodiments of the present application, after determining that a violation exists between a target enlarged shape and an associated shape, shape information of the target enlarged shape and the associated shape, as well as location information of the target enlarged shape and the associated shape causing the violation may be recorded; then, the recorded shape information and location information may be stored in a design rule check mark library.

[0168] In some embodiments of the present application, the three-dimensional line track grid coordinates construct a framework for the entire wiring space, which clarifies the specific coordinates of each position in the three-dimensional space. Each coordinate point has unique properties and influence on wiring, so corresponding initial wiring evaluation indicators can be generated for each of them. This initial wiring evaluation indicator is a quantitative measurement standard that comprehensively considers multiple factors to judge the suitability of the coordinate point for wiring. The initial wiring evaluation indicator of the coordinate point corresponding to the position information recorded above can be further updated to obtain an updated wiring evaluation indicator.

[0169] In some embodiments of the present application, if there is a wire removal and rerouting or metal line completion operation, the design rules that need to be rechecked can be marked for rechecking to remind the user to recheck after the wire removal and rerouting or metal line completion operation.

[0170] When a metal wire violates the regulations because its size is smaller than the specified requirements, it is necessary to perform a wire removal and rerouting operation. First, the EVA of each enlarged shape is calculated based on the shape information stored in the tag library. Then, the shapes with higher EVA are removed from the route vector, and then the entire route vector is updated. Finally, the routing process is started again to ensure that the new routing meets the size requirements and avoids problems caused by the metal wire being too small, thereby improving the quality and stability of the routing and ensuring the normal operation of the circuit.

[0171] For those illegal metal lines that do not meet the size requirements such as MinAREA (minimum area) and Metal Density (metal density), auxiliary metal is inserted to complete them. Specifically, according to the shape information in the tag library, the difference between the enlarged shape and the required area, size, and density is calculated in detail to obtain ΔBox (that is, the part that needs to be supplemented). Subsequently, according to the EVA of the grid points on the four sides of the enlarged shape, ΔBox is supplemented to one side of the enlarged shape. After completing the insertion of auxiliary metal, a comprehensive DRC (design rule check) process is performed to verify whether there are no new DRC violations. If there are still new DRC violations, these problems will be recorded in the tag library for further processing and optimization according to the established process to ensure that the final layout of the metal line can meet the size requirements without introducing new design rule conflicts, thereby ensuring the performance and reliability of the entire integrated circuit.

[0172] In some embodiments of the present application, DRC (design rule check) rule distributed computing is a method used to improve computing efficiency and cope with complex large-scale chip design. It provides two operation modes, namely local multi-threaded operation and remote public-private cloud computing operation.

[0173] The local multi-threaded operation mode uses the multi-threaded processing capabilities of the local computer to allow different threads to process different parts of the chip design at the same time, thereby speeding up the DRC inspection. The remote public-private cloud computing operation mode uses external cloud computing resources, whether public or private, to transmit chip design-related data and use the powerful computing power of cloud computing to complete the DRC inspection work.

[0174] In order to better implement this distributed computing, the entire chip design will be divided into N×N areas, which correspond to N×N grids. Each grid area is assigned an Agent (which can be understood as an intelligent execution unit) to be responsible for the DRC inspection work in this area. Through such division of labor and cooperation, the entire DRC inspection process can be more orderly and efficient, avoiding the problems of tight computing resources and low efficiency that may be caused by centralized inspection of the entire chip design.

[0175] The divided grids need to be effectively spliced, and this process is achieved through the SVIA function.

[0176] SVIA: SVIA is a special via (VIA), which is automatically generated based on conventional VIA and DRC rules. Its main function is reflected in the boundary position of the grid. When a metal line needs to cross two different grids, SVIA can play a connecting role, so that the metal line can be smoothly continued between different grids, ensuring the continuity and integrity of the wiring when crossing the grid, and meeting the requirements of chip design in terms of electrical connection.

[0177] SVIA interconnection: There are two cases when dealing with the connection between different SVIAs. For those overlapping SVIAs, the processing method is relatively simple and direct, that is, direct splicing to connect them smoothly. For non-overlapping SVIAi and SVIAj, special interconnection operations are required. This operation will generate a new metal wire, and then add this newly generated metal wire to the Route vector (Route vectors are usually used to record a collection of wiring-related information, such as wiring paths, etc.), so as to improve the entire wiring structure and ensure that the wiring between different grids can be accurately and reasonably connected through SVIA and related interconnection operations, so as to ensure that the circuit connections inside the chip meet the design rules and function normally.

[0178] In general, the distributed computing of DRC rules and the operations related to grid stitching are all aimed at more efficient DRC checking and ensuring the reasonable continuity of wiring in complex chip designs, improving the quality and efficiency of chip design, and enabling it to better meet various performance requirements in practical applications.

[0179] In a second aspect, the present application also proposes a design rule checking device, such as Figure 7 As shown, it includes: a parsing unit 701, a first acquiring unit 702, a first processing unit 703, a second acquiring unit 704 and a second processing unit 704.

[0180] The parsing unit 701 is configured to obtain the design rules required for integrated circuit wiring, and parse the design rules to obtain the parsed design rules; the first acquisition unit 702 is configured to obtain the corresponding metal wire path and each unit element in the metal wire path after each signal path is completed during the wiring process, and obtain the shape coordinates of each unit element corresponding to the three-dimensional line track grid coordinates; the first processing unit 703 is configured to perform a first processing operation on the shape represented by each shape coordinate according to the parsed design rules, and make a prediction based on the processing result of the first processing operation to obtain an estimated violation probability. rate, and according to the parsed design rules, determine the relevant violations, and circumvent the relevant violations to complete the wiring; the second acquisition unit 704 is configured to obtain each actual metal wire path in all the wirings and each actual unit element in each of the actual metal wire paths after the wiring is completed, and obtain the actual shape coordinates of each of the actual unit elements corresponding to the three-dimensional line track grid coordinates; the second processing unit 705 is configured to perform a second processing operation on the actual shape represented by each of the actual shape coordinates according to the parsed design rules, and determine the inspection result of whether there is a violation or not according to the processing result of the second processing operation.

[0181] In some examples, the parsing unit 701 is also configured to obtain the design rules required for the integrated circuit wiring from the library exchange format file and the rule set file; and use the parsing unit to parse each of the design rules into a vector consisting of key-value relationship pairs to obtain the parsed design rules.

[0182] In some examples, the parsing unit 701 is also configured to, if there is a first design rule in the acquired design rules, and the first design rule is accompanied by an additional conditional rule, then, using the parsing unit, parse both the first design rule and the additional conditional rule into a vector consisting of key-value relationship pairs to obtain the parsed first design rule; if there are multiple second design rules in the acquired design rules, and the multiple second design rules have the same rule name but different rule contents and constraints, then, using the parsing unit, parse each of the second design rules into a vector consisting of key-value relationship pairs to obtain multiple parsed second design rules.

[0183] In some examples, the parsing unit 701 is also configured to color and mark the different mask layers respectively if it is determined that there is a conflict between the design rules corresponding to different mask layers, and merge the conflicting design rules between different regions of the same mask layer to obtain merged design rules; and use the parsing unit to parse the merged design rules into a vector composed of key-value relationship pairs to obtain the parsed design rules.

[0184] In some examples, the first processing unit 703 is further configured to enlarge each first shape according to the spacing requirements in the parsed design rules to generate a corresponding new first shape, where the first shape is a shape that does not include vias among the multiple shapes; pre-wire the coordinate points covered by each of the new first shapes, and generate a pre-wired shape according to the parsed design rules; perform geometric operations on the new first shapes and the pre-wired shapes to obtain first geometric information, and if the first geometric information meets the constraints in the parsed design rules, determine that the prediction result is that the first geometric information has a violation.

[0185] In some examples, the first processing unit 703 is further configured to enlarge each second shape according to the spacing requirements in the parsed design rules to generate a corresponding new second shape, where the second shape is a shape including the via among the multiple shapes; pre-arrange vias at each coordinate point covered by the new second shape, and generate the shape of the pre-arranged vias according to the parsed design rules; perform geometric operations on the new second shape and the shape of the pre-arranged vias to obtain second geometric information, and if the second geometric information meets the constraints in the parsed design rules, determine that the prediction result is that the second geometric information has a violation.

[0186] In some examples, the device also includes: generating a corresponding initial wiring evaluation index for each coordinate point in the three-dimensional linear track grid coordinates; during the wiring process, calculating the corresponding intermediate wiring evaluation index for each coordinate point on the metal wire path; adding the intermediate wiring evaluation index to the initial wiring evaluation index corresponding to the corresponding coordinate point to obtain the final wiring evaluation index corresponding to each coordinate point on the metal wire path; if there is a violation in the first geometric information, updating the final wiring evaluation index corresponding to the two coordinate points contained in the shape coordinates of the first shape to obtain an updated wiring evaluation index; if there is a violation in the second geometric information, updating the final wiring evaluation index corresponding to the two coordinate points contained in the shape coordinates of the second shape to obtain an updated wiring evaluation index.

[0187] In some examples, the device also includes: storing each coordinate point in the three-dimensional linear track grid coordinates in a routing path vector; if there is a violation in the first geometric information, deleting two coordinate points contained in the shape coordinates of the first shape from the routing path vector; if there is a violation in the second geometric information, deleting two coordinate points contained in the shape coordinates of the second shape from the routing path vector.

[0188] In some examples, the first processing unit 703 is further configured to determine an estimated violation area in the wiring and a shape of the estimated violation area according to the estimated violation probability; amplify the shape of the estimated violation area according to the spacing requirements in the parsed design rules to generate an enlarged shape; mark the coordinate points within the coverage range of the enlarged shape as a blocking state, and adjust the blocking range of the estimated violation area accordingly according to the shape, direction, metal level or via level of the estimated violation area to avoid violations in the wiring process, thereby completing the wiring.

[0189] In some examples, the first processing unit 703 is further configured to determine special rules according to the parsed design rules, wherein the special rules are rules hidden in the library exchange format file but present in the rule set file; and generate a prohibited rule group according to the special rules, and avoid coordinate points matching the prohibited rule group to complete routing.

[0190] In some examples, the device further includes: generating a corresponding initial routing evaluation index for each coordinate point in the three-dimensional linear track grid coordinates; updating the initial routing evaluation index of the coordinate point matching the prohibition rule group to obtain an updated routing evaluation index.

[0191] In some examples, the first processing unit 703 is further configured to establish multiple three-dimensional bodies for the three-dimensional rules in the parsed design rules, wherein the three-dimensional bodies are composed of a set of coordinate points spanning multiple levels; perform logical operations on the three-dimensional rules in each of the three-dimensional bodies to determine situations in which the wiring in each of the three-dimensional bodies violates the three-dimensional rules; and avoid situations in which the wiring in the three-dimensional bodies that is determined to violate the three-dimensional rules to complete the wiring.

[0192] In some examples, the first processing unit 703 is further configured to generate a corresponding initial wiring evaluation index for each coordinate point in the three-dimensional track grid coordinates; if it is determined that the wiring within a target three-dimensional body among the multiple three-dimensional bodies violates the three-dimensional rules, the initial wiring evaluation indexes of all coordinate points within the target three-dimensional body are updated to obtain updated wiring evaluation indexes.

[0193] In some examples, the second processing unit 705 is further configured to enlarge the actual shape represented by each of the actual shape coordinates according to the spacing requirements in the parsed design rules to generate a corresponding enlarged shape; judge each of the enlarged shapes according to the constraints in the parsed design rules by logical operations; if it is determined that a target enlarged shape among the multiple enlarged shapes has a condition that triggers a violation, then through geometric operations, find an associated shape of the target enlarged shape; if the associated shape is found, determine that the inspection result is that there is a violation between the target enlarged shape and the associated shape.

[0194] In some examples, the second processing unit 705 is further configured to record shape information of the target enlarged shape and the associated shape, and position information of the target enlarged shape and the associated shape causing a violation; and store the recorded shape information and position information in a design rule check mark library.

[0195] In some examples, the second processing unit 705 is further configured to generate a corresponding initial routing evaluation index for each coordinate point in the three-dimensional linear track grid coordinates; update the initial routing evaluation index of the coordinate point corresponding to the recorded position information to obtain an updated routing evaluation index.

[0196] In some examples, the apparatus further includes marking the design rules that need to be rechecked if there is a wire removal and rerouting or metal line completion operation, so as to remind the user to recheck after the wire removal and rerouting or metal line completion operation.

[0197] like Figure 8 As shown, an embodiment of the present application also provides an electronic device 800, including a memory 810, a processor 820, and a computer program 811 stored in the memory 810 and executable on the processor, and when the processor 820 executes the computer program 811, the steps of any of the above-mentioned design rule checking methods are implemented.

[0198] Since the electronic device introduced in this embodiment is a device used to implement a design rule checking device in the embodiment of the present application, based on the method introduced in the embodiment of the present application, the technical personnel in this field can understand the specific implementation mode of the electronic device of this embodiment and its various variations. Therefore, how the electronic device implements the method in the embodiment of the present application is not introduced in detail here. As long as the technical personnel in this field implement the device used by the method in the embodiment of the present application, it belongs to the scope of protection of this application.

[0199] In a specific implementation process, when the computer program 811 is executed by a processor, any implementation method in the above embodiments can be implemented.

[0200] It should be noted that in the above embodiments, the description of each embodiment has its own emphasis, and for parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0201] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0202] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded computer, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0203] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0204] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0205] An embodiment of the present application further provides a computer program product, which includes computer software instructions. When the computer software instructions are executed on a processing device, the processing device executes the design rule checking process in the corresponding embodiment.

[0206] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, the process or function according to the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website site, a computer, a server, or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server, or data center. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a server or a data center that includes one or more available media integrations. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid state drive (SSD)), etc.

[0207] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0208] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0209] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0210] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0211] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store program codes.

[0212] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A design rule checking method, characterized in that: include: Obtaining design rules required for integrated circuit wiring, and parsing the design rules to obtain parsed design rules; During the routing process, each time the routing of a signal path is completed, the corresponding metal wire path and each unit element in the metal wire path are obtained, and the shape coordinates of each unit element corresponding to the three-dimensional line track grid coordinates are obtained; According to the analyzed design rules, a first processing operation is performed on the shape represented by each of the shape coordinates, a prediction is performed according to the processing result of the first processing operation to obtain an estimated violation probability, and according to the analyzed design rules, relevant violation conditions are determined, and the relevant violation conditions are avoided to complete routing; After the routing is completed, each actual metal wire path in the entire routing and each actual unit element in each of the actual metal wire paths are obtained, and the actual shape coordinates of each of the actual unit elements corresponding to the three-dimensional line track grid coordinates are obtained; According to the analyzed design rules, a second processing operation is performed on the actual shape represented by each actual shape coordinate, and a violation inspection result is determined according to a processing result of the second processing operation.

2. The method according to claim 1, characterized in that The step of obtaining the design rules required for integrated circuit wiring and parsing the design rules to obtain the parsed design rules includes: Acquire the design rules required for the integrated circuit wiring from a library exchange format file and a rule set file; A parsing unit is used to parse each of the design rules into a vector consisting of key-value relationship pairs to obtain the parsed design rules.

3. The method according to claim 2, characterized in that The utilizing a parsing unit to parse each of the design rules into a vector consisting of key-value relationship pairs to obtain the parsed design rules includes: If there is a first design rule in the acquired design rules, and the first design rule is accompanied by an additional condition rule, the first design rule and the additional condition rule are parsed into vectors consisting of key-value relationship pairs by using the parsing unit to obtain the parsed first design rule; If there are multiple second design rules in the acquired design rules, and the multiple second design rules have the same rule name but different rule contents and constraints, then the parsing unit is used to parse each of the second design rules into a vector composed of key-value relationship pairs to obtain multiple parsed second design rules.

4. The method according to claim 2, characterized in that: The utilizing a parsing unit to parse each of the design rules into a vector consisting of key-value relationship pairs to obtain the parsed design rules includes: If it is determined that there is a conflict between the design rules corresponding to different mask layers, the different mask layers are colored and marked respectively, and the conflicting design rules between different regions of the same mask layer are merged to obtain a merged design rule; The merged design rules are parsed into a vector consisting of key-value relationship pairs by using the parsing unit to obtain the parsed design rules.

5. The method according to claim 1, characterized in that The step of performing a first processing operation on the shape represented by each of the shape coordinates according to the analyzed design rule, and determining a prediction result of whether or not there is a violation according to a processing result of the first processing operation, comprises: According to the spacing requirement in the analyzed design rule, each first shape is enlarged to generate a corresponding new first shape, where the first shape is a shape that does not include a via among the multiple shapes; Pre-routing each coordinate point covered by the new first shape, and generating a pre-routing shape according to the analyzed design rule; A geometric operation is performed on the new first shape and the pre-wired shape to obtain first geometric information. If the first geometric information satisfies the constraint conditions in the parsed design rules, it is determined that the prediction result is that the first geometric information has a violation.

6. The method according to claim 5, characterized in that The step of performing a first processing operation on the shape represented by each of the shape coordinates according to the analyzed design rule, and determining a prediction result of whether or not there is a violation according to a processing result of the first processing operation, comprises: According to the spacing requirement in the analyzed design rule, each second shape is enlarged to generate a corresponding new second shape, where the second shape is a shape including the via hole in the plurality of shapes; Pre-arrange via holes at each coordinate point covered by the new second shape, and generate a shape of the pre-arranged via holes according to the analyzed design rule; A geometric operation is performed on the new second shape and the shape of the pre-arranged via to obtain second geometric information. If the second geometric information satisfies the constraint conditions in the parsed design rules, it is determined that the prediction result is that the second geometric information has a violation.

7. The method according to claim 6, characterized in that The method further comprises: Generating a corresponding initial routing evaluation index for each coordinate point in the three-dimensional track grid coordinates; During the wiring process, for each coordinate point on the metal wire path, a corresponding intermediate wiring evaluation index is calculated; Adding the intermediate wiring evaluation index to the initial wiring evaluation index corresponding to the corresponding coordinate point to obtain a final wiring evaluation index corresponding to each coordinate point on the metal wire path; If there is a violation in the first geometric information, the final wiring evaluation indexes corresponding to two coordinate points included in the shape coordinates of the first shape are updated to obtain an updated wiring evaluation index; If there is a violation in the second geometric information, the final wiring evaluation indexes respectively corresponding to two coordinate points included in the shape coordinates of the second shape are updated to obtain updated wiring evaluation indexes.

8. The method according to claim 6, characterized in that The method further comprises: Storing each coordinate point in the three-dimensional linear track grid coordinates into a routing path vector; If there is a violation in the first geometric information, two coordinate points included in the shape coordinates of the first shape are deleted from the routing path vector; If there is a violation in the second geometric information, two coordinate points included in the shape coordinates of the second shape are deleted from the routing path vector.

9. The method according to claim 1, characterized in that: Determining relevant violation conditions according to the analyzed design rules and avoiding the relevant violation conditions to complete wiring includes: Determining an estimated violation region in the wiring and a shape of the estimated violation region according to the estimated violation probability; According to the spacing requirement in the analyzed design rule, the shape of the estimated violation area is enlarged to generate an enlarged shape; The coordinate points within the coverage range of the enlarged shape are marked as blocked, and the blocking range of the estimated violation area is adjusted accordingly according to the shape, direction, metal layer or via layer to which the estimated violation area belongs, so as to avoid violations during the wiring process and complete the wiring.

10. The method according to claim 1, characterized in that Determining relevant violation conditions according to the analyzed design rules and avoiding the relevant violation conditions to complete wiring includes: Determine, according to the parsed design rules, special rules therein, wherein the special rules are rules hidden in the library exchange format file but existing in the rule set file; According to the special rule, a prohibited rule group is generated, and the coordinate points matching the prohibited rule group are avoided to complete the routing.

11. The method according to claim 10, characterized in that The method further comprises: Generating a corresponding initial routing evaluation index for each coordinate point in the three-dimensional track grid coordinates; The initial wiring evaluation index of the coordinate point matching the prohibition rule group is updated to obtain an updated wiring evaluation index.

12. The method according to claim 1, characterized in that Determining relevant violation conditions according to the analyzed design rules and avoiding the relevant violation conditions to complete wiring includes: For the three-dimensional rules in the analyzed design rules, establish a plurality of three-dimensional bodies, wherein the three-dimensional bodies are composed of a set of coordinate points spanning multiple levels; Performing a logical operation on the three-dimensional rule in each of the three-dimensional bodies to determine a situation in which the wiring in each of the three-dimensional bodies violates the three-dimensional rule; The situation where the wiring in the three-dimensional volume violates the three-dimensional rule is avoided to complete the wiring.

13. The method according to claim 12, characterized in that The method further comprises: Generating a corresponding initial routing evaluation index for each coordinate point in the three-dimensional track grid coordinates; If it is determined that the wiring in a target three-dimensional body among the multiple three-dimensional bodies violates the three-dimensional rule, the initial wiring evaluation index of all coordinate points in the target three-dimensional body is updated to obtain an updated wiring evaluation index.

14. The method according to claim 1, characterized in that The step of performing a second processing operation on the actual shape represented by each of the actual shape coordinates according to the analyzed design rules, and determining a violation inspection result according to a processing result of the second processing operation, comprises: According to the spacing requirements in the analyzed design rules, the actual shape represented by each actual shape coordinate is enlarged to generate a corresponding enlarged shape; According to the constraints in the analyzed design rules, each of the enlarged shapes is judged by logical operation; If it is determined that a target enlarged shape among the multiple enlarged shapes has a condition that triggers a violation, an associated shape of the target enlarged shape is searched through geometric operations. If the associated shape is found, it is determined that the inspection result is that there is a violation between the target enlarged shape and the associated shape.

15. The method according to claim 14, characterized in that The method further comprises: Recording shape information of the target enlarged shape and the associated shape, and position information of the target enlarged shape and the associated shape causing the violation; The recorded shape information and the position information are stored in a design rule check mark library.

16. The method according to claim 15, characterized in that The method further comprises: Generating a corresponding initial routing evaluation index for each coordinate point in the three-dimensional track grid coordinates; The initial wiring evaluation index of the coordinate point corresponding to the recorded position information is updated to obtain an updated wiring evaluation index.

17. The method according to claim 1, characterized in that The method further comprises: If there is an operation of wire removal and rerouting or metal wire completion, the design rules that need to be rechecked are marked for rechecking to remind the user to recheck after the wire removal and rerouting or metal wire completion operation.

18. A design rule checking device, characterized in that: include: A parsing unit configured to obtain design rules required for integrated circuit wiring, and parse the design rules to obtain parsed design rules; A first acquisition unit is configured to acquire the corresponding metal wire path and each unit element in the metal wire path each time the wiring of a signal path is completed during the wiring process, and acquire the shape coordinates of each unit element corresponding to the three-dimensional line track grid coordinates; A first processing unit is configured to perform a first processing operation on the shape represented by each of the shape coordinates according to the parsed design rules, perform prediction according to the processing result of the first processing operation to obtain an estimated violation probability, and determine relevant violation conditions according to the parsed design rules, and avoid the relevant violation conditions to complete routing; A second acquisition unit is configured to acquire, after the wiring is completed, each actual metal wire path in all the wirings and each actual unit element in each of the actual metal wire paths, and acquire the actual shape coordinates of each of the actual unit elements corresponding to the three-dimensional line track grid coordinates; The second processing unit is configured to perform a second processing operation on the actual shape represented by each actual shape coordinate according to the analyzed design rule, and determine a violation inspection result according to a processing result of the second processing operation.

19. An electronic device comprising: A memory and a processor, wherein the processor is used to implement the steps of the design rule checking method according to any one of claims 1 to 17 when executing a computer program stored in the memory.

20. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the design rule checking method according to any one of claims 1 to 17 are implemented.

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