Row hammer mitigation reliability in stacked memory architecture

Abstract

The invention relates to row hammer mitigation reliability in a stacked memory architecture. A backup counter may be implemented at a first interface block of a logic die to achieve improved reliability and efficiency of row hammer mitigation. The first interface block may use a backup counter when an error associated with a counter at a memory array die occurs. A second interface block of the array die may identify an error associated with a counter of the memory array and may transmit an indication of the error to the first interface block. The first interface block may receive the indication and may activate a backup counter to track an access operation on a row based on the indication (e.g., row activation). The first interface block may use the backup counter to evaluate whether to transmit refresh signaling to the second interface block for row hammer mitigation.

Description

[0001] Cross Reference

[0002] This patent application claims priority to U.S. patent application No. 18 / 763,983, filed by Liu et al. on July 3, 2024, entitled “ROW HAMMER MITIGATION RELIABILITY IN STACKED MEMORY ARCHITECTURES,” and U.S. Provisional Patent Application No. 63 / 530,910, filed by Liu et al. on August 4, 2023, entitled “ROW HAMMER MITIGATION RELIABILITY IN STACKED MEMORY ARCHITECTURES,” each of which is assigned to its assignee and the entire contents of each of which are expressly incorporated herein by reference.

[0003] The technical field relates to one or more systems for memory, including row hammer mitigation reliability in stacked memory architectures. Background Art

[0004] Memory devices are widely used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and others. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell is programmable to one of two supported states, typically represented by a logical 1 or a logical 0. In some instances, a single memory cell may support more than two states, either of which may be stored. To access stored information, a memory device may read (e.g., sense, detect, retrieve, determine) a state from a memory cell. To store information, a memory device may write (e.g., program, set, assign) a state to a memory cell.

[0005] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selection memory, chalcogenide memory technology, NOR and NAND memory devices, and others. Memory cells can be described in terms of volatile configurations or non-volatile configurations. Memory cells in non-volatile configurations can maintain a stored logic state for a long time, even in the absence of external power. Memory cells in volatile configurations lose their stored state when disconnected from external power. Summary of the invention

[0006] A system is described. The system may include: a first semiconductor die including: a first interface, the first interface including first circuitry operable to transmit access signaling; and a first counter; and a second semiconductor die coupled to the first semiconductor die, the second semiconductor die including: one or more memory arrays; a second counter; and a second interface coupled to the first interface, the one or more memory arrays, and the second counter, the second interface including second circuitry operable to access the one or more memory arrays based on receiving the access signaling, wherein the first circuitry of the first interface is operable to transmit refresh signaling indicating refresh operations associated with one or more addresses of the one or more memory arrays to the second interface based on a number of access operations to the one or more memory arrays indicated by the first counter or by the second counter.

[0007] An apparatus is described. The apparatus may include: a first semiconductor die including a first interface, the first interface including circuitry operable to: transmit first signaling including a first command to activate a row of a memory array of the second semiconductor die to a second interface of a second semiconductor die coupled to the first semiconductor die; receive second signaling from the second interface indicating an error associated with a first counter of the second semiconductor die for counting activations of the row of the memory array based on transmitting the first signaling; activate a second counter of the first semiconductor die for counting activations of the row of the memory array based on receiving the second signaling indicating the error; and transmit third signaling including a second command to refresh one or more rows of the memory array different from the row to the second interface based on a value of the second counter or the second signaling indicating the error.

[0008] A method is described that may include: transmitting, from a first interface of a first semiconductor die to a second interface of a second semiconductor die coupled to the first semiconductor die, first signaling including a first command to activate a row of a memory array of the second semiconductor die; receiving, at the first interface from the second interface, second signaling indicating an error associated with a first counter of the second semiconductor die for counting activations of the rows of the memory array based on transmitting the first signaling; activating, at the first interface, a second counter of the first semiconductor die for counting activations of the rows of the memory array based on receiving the second signaling indicating the error; and transmitting, from the first interface to the second interface, third signaling including a second command to refresh one or more rows of the memory array different from the row based on the indication of the error or the value of the second counter.

[0009] An apparatus is described. The apparatus may include: a second semiconductor die including a second interface, the second interface including circuitry operable to: receive first signaling including a first command to activate a row of a memory array of the second semiconductor die from a first interface of a first semiconductor die; identify an error associated with a counter of the second semiconductor die for counting activations of the row of the memory array based on the first signaling; transmit second signaling including an indication of the error to the first interface based on identifying the error; and receive third signaling including a second command to refresh one or more second rows of the memory array different from the row based on transmitting the second signaling from the first interface.

[0010] A method is described that may include: receiving, at a second interface of a second semiconductor die, first signaling from a first interface of a first semiconductor die comprising a first command to activate a row of a memory array of the second semiconductor die; identifying, at the second interface based on the first signaling, an error associated with a counter of the second semiconductor die used to count activations of the row of the memory array; transmitting, from the second interface to the first interface, second signaling comprising an indication of the error based on identifying the error; and receiving, from the first interface, third signaling comprising a second command to refresh one or more second rows of the memory array different from the row based on transmitting the second signaling. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 An example of a system supporting row hammer mitigation reliability in a stacked memory architecture according to examples disclosed herein is presented.

[0012] Figure 2An example of a system supporting row hammer mitigation reliability in a stacked memory architecture according to examples disclosed herein is presented.

[0013] Figure 3 An example of an interface architecture supporting row hammer mitigation reliability in a stacked memory architecture according to examples disclosed herein is shown.

[0014] Figure 4 An example of a system supporting row hammer mitigation reliability in a stacked memory architecture according to examples disclosed herein is presented.

[0015] Figures 5 to 7B An example of a process to support row hammer mitigation reliability in a stacked memory architecture according to examples disclosed herein is presented.

[0016] Figure 8 A block diagram showing a logic die supporting row hammer mitigation reliability in a stacked memory architecture according to examples disclosed herein.

[0017] Fig. 9 A block diagram showing an array die supporting row hammer mitigation reliability in a stacked memory architecture according to examples disclosed herein.

[0018] Fig.10 and 11 A flow chart illustrating a method of supporting row hammer mitigation reliability in a stacked memory architecture according to examples disclosed herein is shown. DETAILED DESCRIPTION

[0019] Some memory systems may include a semiconductor die stack including one or more memory dies above a logic die, which is operable to access a set of memory arrays distributed across one or more memory dies. This architecture may be implemented as part of a tightly coupled dynamic random access memory (TCDRAM) system, and may support solutions for memory-centric logic, such as a graphics processing unit (GPU) and other implementations. In some examples, the TCDRAM system may be tightly coupled (e.g., physically coupled, electrically coupled) to a processor (e.g., a GPU or other host) as part of a physical memory map accessible to the processor. This coupling may include one or more processors implemented in the same semiconductor die as at least a portion of the TCDRAM system (e.g., as part of a logic die) or a processor implemented in a die that is directly coupled (e.g., fused) to another die that includes at least a portion of the TCDRAM system. Unlike cache-based memory, TCDRAM cannot be supported by an external memory hierarchy with the same physical address. For example, TCDRAM may be associated with and located within a dedicated base address, wherein each portion of the TCDRAM may not overlap within the address.

[0020] In some memory systems implementing semiconductor die stacking, the memory access circuitry may be distributed among (e.g., distributed across, distributed between) multiple semiconductor dies. For example, the multiple semiconductor dies of a TCDRAM system may include a semiconductor die stack (e.g., a stack of multiple directly coupled semiconductor dies), including a first die (e.g., a logic die) operable to access a set of memory arrays distributed across one or more second dies (e.g., array dies). In some cases, memory cells (e.g., of the set of memory arrays) may be subject to adverse accesses, such as a row hammer attack, in which a row of memory cells (e.g., an aggressor row) is repeatedly accessed to adversely affect other memory cells of one or more adjacent rows (e.g., a victim row, a neighboring row). For example, repeatedly accessing a row may interfere with memory cells of one or more adjacent rows, such that data stored by memory cells of one or more adjacent rows may be modified (e.g., corrupted, damaged).

[0021] In some cases, a first interface block (e.g., a memory interface block (MIB)) of a logic die may exchange signaling (e.g., one or more signals, one or more indications) with a second interface block of an array die to perform one or more row hammer mitigation operations. For example, the second interface block may transmit an alarm signaling to the first interface based on the value of a counter for tracking the number of access operations (e.g., address activations) to an address (e.g., a row) of a memory array of the array die. The alarm signaling may indicate that the value of the counter meets one or more thresholds, which may indicate a row hammer attack on the row. In response to the alarm signaling, the first interface block may issue one or more refresh commands to mitigate the adverse effects of the row hammer attack. However, the counter used to evaluate potential adverse accesses may experience errors, which may reduce the reliability of the adverse access mitigation technique. For example, an error associated with the counter may cause the second interface block to fail to identify or erroneously identify a row hammer attack on the memory array. Thus, when a row hammer attack occurs, the alarm signaling is not transmitted due to the failure to identify the row hammer attack, which may increase the risk of data corruption or modification. In some other instances, false identification of a row hammer attack may result in unnecessary transmission of alert signaling and refresh commands, which may degrade the performance of a system including logic and array dies (eg, a TCDRAM system).

[0022] According to the techniques described herein, a standby counter may be implemented at a logic die (e.g., as part of or coupled to a first interface block of the logic die) to support reliability improvement of row hammer mitigation. For example, the first interface block may use (e.g., activate) a standby counter at a logic die (e.g., at the first interface block) in response to an error associated with a counter at an array die coupled to the logic die. In some examples, a second interface block of the array die may identify an error associated with a counter for tracking access operations (e.g., address activation) to an address (e.g., row) of a memory array of the array die and may transmit an alarm signaling including an indication of the error to the first interface block. Based on the indication of the error, the first interface block may activate the standby counter to track access operations to the row. For example, the first interface block may increment the standby counter based on transmitting access signaling to access (e.g., activate) the row to the second interface block. When the standby counter is activated, the first interface block may use the standby counter to evaluate whether to transmit refresh signaling to the second interface block for row hammer mitigation associated with the row, e.g., not based on the alarm signaling received from the second interface block. Implementing backup counters according to the described techniques may enable a system to compensate for errors associated with counters, reduce processing and signaling overhead, reduce unnecessary refresh operations to improve system performance, and increase the reliability of row hammer mitigation techniques, among other benefits.

[0023] Features of the present disclosure are illustrated and described in the context of systems and dies. Features of the present disclosure are further illustrated and described in the context of interface architectures, block diagrams, and flow charts.

[0024] Figure 1 An example of a system 100 that supports row hammer mitigation reliability in a stacked memory architecture according to examples disclosed herein is illustrated. The system 100 may include a portion of an electronic device, such as a computing device, a mobile computing device, a wireless communication device, a graphics processing device, a vehicle, or other system. The system 100 includes a host system 105, a memory system 110, and one or more channels 115 (e.g., for providing a communicative coupling) coupling the host system 105 and the memory system 110. The system 100 may include one or more memory systems 110, but aspects of the one or more memory systems 110 may be described in the context of a single memory system 110.

[0025] The host system 105 may be an example of a processor (e.g., circuitry, processing circuitry, one or more processing components) that uses memory to perform processes, such as a processing system of a computing device, a mobile computing device, a wireless communication device, a graphics processing device, a wearable device, an Internet connection device, a vehicle controller, a single chip system (SoC), or other fixed or portable electronic device, among other examples. The host system 105 may include one or more of an external memory controller 120, a processor 125, a basic input / output system (BIOS) component 130, or other components (e.g., peripheral components, input / output controllers not shown). The components of the host system 105 may be coupled to each other using a bus 135.

[0026] The external memory controller 120 may be configured to enable information (e.g., data, commands, control information, configuration information) communication between components of the system 100 (e.g., between components of the host system 105 (e.g., the processor 125) and the memory system 110). The external memory controller 120 may process (e.g., convert, translate) communications exchanged between the host system 105 and the memory system 110. In some examples, the external memory controller 120 or other components of the system 100 or associated functionality described herein may be implemented by or be part of the processor 125. For example, the external memory controller 120 may be hardware, firmware, or software (e.g., instructions), or some combination thereof, implemented by the processor 125 or other components of the system 100 or the host system 105. Although the external memory controller 120 is illustrated as being external to the memory system 110, in some examples, the external memory controller 120 or its functionality described herein may be implemented by one or more components of the memory system 110 (e.g., the memory system controller 155, the local memory controller 165), or vice versa. In various examples, the host system 105 or the external memory controller 120 may be referred to as a host.

[0027] Processor 125 is operable to provide functionality (e.g., control functionality) for system 100 or host system 105. Processor 125 may be a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof. In some examples, processor 125 may be an example of a central processing unit (CPU), a graphics processing unit (GPU), a general purpose GPU (GPGPU), or a SoC, among other examples.

[0028] In some examples, the system 100 or the host system 105 may include an input component, an output component, or a combination thereof. The input component may include a sensor, a microphone, a keyboard, another processor (e.g., on a printed circuit board), an interface (e.g., a user interface, an interface between other devices), or a peripheral device that interfaces with the system 100 via one or more peripheral components, as well as other examples. The output component may include a display, an audio speaker, a printing device, another processor on a printed circuit board, or a peripheral device that interfaces with the system 100 via one or more peripheral components, as well as other examples.

[0029] The memory system 110 may be a component of the system 100 operable to provide physical memory locations (e.g., addresses) that may be used or referenced by the system 100. The memory system 110 may include a memory system controller 155 and one or more memory dies 160 (e.g., memory chips) for supporting data storage capacity. The memory system 110 may be configured to cooperate with one or more different types of host systems 105, and may respond to and execute commands provided by the host system 105 (e.g., via the external memory controller 120). For example, the memory system 110 (e.g., the memory system controller 155) may receive a write command indicating that the memory system 110 is to store data received from the host system 105, or receive a read command indicating that the memory system 110 is to provide data stored in the memory die 160 to the host system 105, or receive a refresh command indicating that the memory system 110 is to refresh data stored in the memory die 160, as well as other types of commands and operations.

[0030] The memory system controller 155 may include components (e.g., circuitry, logic) operable to control the operation of the memory system 110. The memory system controller 155 may include hardware, firmware, or instructions that enable the memory system 110 to perform various operations, and may be operable to receive, transmit, or execute commands, data, or control information related to the operation of the memory system 110. The memory system controller 155 may be operable to communicate with one or more of the external memory controller 120, one or more memory dies 160, or the processor 125. In some examples, the memory system controller 155 may cooperate with the local memory controller 165 of the memory die 160 to control the operation of the memory system 110.

[0031] Each memory die 160 may include a local memory controller 165 and a memory array 170. The memory array 170 may be a collection of memory cells, each of which may be operable to store one or more bits of data. The memory die 160 may include a two-dimensional (2D) array of memory cells or a three-dimensional (3D) array of memory cells. In some examples, a 2D memory die 160 may include a single memory array 170. In some examples, a 3D memory die 160 may include two or more memory arrays 170, which may be stacked on top of each other or positioned side-by-side with each other (e.g., relative to a substrate).

[0032] The local memory controller 165 may include components (e.g., circuitry, logic) operable to control the operation of the memory die 160. In some examples, the local memory controller 165 may be operable to communicate (e.g., receive or transmit data or commands or both) with the memory system controller 155. In some examples, the memory system 110 may not include a memory system controller 155, and the local memory controller 165 or the external memory controller 120 may perform the various functions described herein. Thus, the local memory controller 165 may be operable to communicate with the memory system controller 155, with other local memory controllers 165, or directly with the external memory controller 120 or the processor 125, or any combination thereof. Examples of components that may be included in the memory system controller 155 or the local memory controller 165 or both may include a receiver for receiving signals (e.g., from the external memory controller 120), a transmitter for transmitting signals (e.g., to the external memory controller 120), a decoder for decoding or demodulating received signals, an encoder for encoding or modulating signals to be transmitted, a sensing component for sensing the state of memory cells of the memory array 170, a writing component for writing states to memory cells of the memory array 170, or various other components operable to support the described operations of the memory system 110.

[0033] The host system 105 (e.g., external memory controller 120) and the memory system 110 (e.g., memory system controller 155) may communicate information (e.g., data, commands, control information, configuration information) using one or more channels 115. Each channel 115 may be an example of a transmission medium that carries information, and each channel 115 may include one or more signal paths (e.g., transmission media, electrical conductors, conductive paths) between terminals associated with components of the system 100. For example, a channel 115 may be associated with a first terminal (e.g., including one or more pins, including one or more pads) at the host system 105 and a second terminal at the memory system 110. A terminal may be an example of a conductive input or output point of a device of the system 100, and a terminal may be operable to serve as part of a channel 115. In some implementations, at least the channel 115 between the host system 105 and the memory system 110 may include or be referred to as a host interface (e.g., a physical host interface). In some implementations, the host interface may include or be associated with interface circuitry (e.g., signal drivers, signal latches) at the host system 105 (e.g., at the external memory controller 120) or at the memory system 110 (e.g., at the memory system controller 155), or both.

[0034] In some examples, channels 115 (e.g., associated signal paths and terminals) may be dedicated to conveying one or more types of information. For example, channels 115 may include one or more command and address channels, one or more clock signal channels, one or more data channels, and other channels or combinations thereof. In some examples, signaling may be conveyed via channels 115 using single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol (e.g., signal level) of a signal may be recorded for each clock cycle (e.g., on either a rising or falling edge of a clock signal). In DDR signaling, two modulation symbols of a signal may be recorded for each clock cycle (e.g., on both a rising edge and a falling edge of a clock signal).

[0035] In some examples, at least a portion of system 100 may implement a stacked die architecture in which multiple semiconductor dies are physically and communicatively coupled. In some implementations, one or more semiconductor dies may include multiple instances of interface circuitry (e.g., memory system 110, memory interface block), each associated with accessing a corresponding set of one or more memory arrays 170 of one or more other semiconductor dies. In some cases, the circuitry for accessing one or more memory arrays 170 may be distributed among multiple semiconductor dies in a stack (e.g., a stack of multiple directly coupled semiconductor dies). For example, a first die may include a logic block (e.g., a common logic block, a central logic block, logic circuitry) operable to configure a set of multiple first interface blocks (e.g., MIBs, instances of first interface circuitry) of the first die. In some examples, the system may include a respective controller (e.g., a memory controller, a host interface controller, at least a portion of the memory system controller 155, at least a portion of the external memory controller 120, or a combination thereof) for each first interface block to support access operations (e.g., for accessing one or more memory arrays 170) via the first interface blocks. The system 100 may also include a non-volatile storage device, one or more sensors, or a combination thereof to support various operations of the system 100.

[0036] In some examples, a plurality of semiconductor dies of a memory system 110 (e.g., a TCDRAM system) may include one or more second dies (e.g., memory die 160, array die) stacked with a first die (e.g., a logic die including a host system 105, a logic die coupled to a third die including a host system 105), the first die including an interface block operable to access a group of memory arrays 170 distributed across the one or more second dies. In some cases, memory cells in the memory array group 170 may be subject to adverse accesses, such as row hammer attacks. To mitigate (e.g., avoid, reduce) adverse effects caused by row hammer attacks, the memory system 110 may distribute row hammer mitigation techniques across the circuitry of the memory system 110. In some cases, counters associated with rows of the memory array 170 may enable the memory system 110 to identify row hammer attacks on the rows and transmit alarm signaling to the interface blocks of the logic die to support row hammer mitigation operations associated with the rows. However, some counters used to monitor row hammer attacks may experience errors. For example, one or more bits of the counter may be stuck in a logic state (e.g., '1' or '0') or may experience a transient bit flip. Such counter errors may reduce the reliability of row hammer mitigation operations, for example by causing failure to identify or misidentify a row hammer attack on the memory array.

[0037] According to the techniques described herein, a spare counter may be implemented at a first interface block of a logic die to support improved reliability of row hammer mitigation. For example, the first interface block may use (e.g., activate) a spare counter at a logic die in response to an error associated with a counter at an array die coupled to the array die. For example, the first interface block may receive an indication of an error associated with a counter for counting access operations (e.g., row activations) to a row of the memory array 170 from a second interface block at the array die. Based on receiving the indication, the first interface block may activate a spare counter to track (e.g., count) activations of the row. The first interface block may use the spare counter to evaluate whether to transmit refresh signaling for one or more neighboring rows of a refresh row, such as not evaluating whether to transmit refresh signaling based on alert signaling from a second interface block. Implementing the spare counter and techniques described herein may compensate for errors associated with the counter, reduce processing and signaling overhead, reduce unnecessary refresh operations to improve system performance, and improve the reliability of row hammer mitigation techniques at the memory system 110.

[0038] In addition to being applied in the memory systems described herein, the techniques for row hammer mitigation reliability in stacked memory architectures may also be implemented generally to support artificial intelligence applications. As the use of artificial intelligence increases to support machine learning, analysis, decision making, or other related applications, it may be desirable for electronic devices to support artificial intelligence applications and processes. For example, artificial intelligence applications may be associated with accessing relatively large amounts of data for analytical purposes and may benefit from memory devices that are able to effectively and efficiently store relatively large amounts of data or access stored data relatively quickly. Implementation of the techniques described herein may support artificial intelligence or machine learning techniques by supporting robust protection of information accessed via relatively large numbers of tightly coupled interfaces (e.g., channels, data paths, supporting stacking) between a host and a memory array of one or more semiconductor dies stacked on a logic die (e.g., by improving the reliability and efficiency of row hammer mitigation operations, among other benefits).

[0039] Figure 2An example of a system 200 (e.g., a semiconductor system, a system coupling semiconductor dies) supporting row hammer mitigation reliability in a stacked memory architecture according to examples disclosed herein is illustrated. The system 200 illustrates an example of a die 205 (e.g., a semiconductor die, a host die, a processor die, a logic die) coupled with one or more dies 240 (e.g., dies 240-a-1 and 240-a-2, semiconductor dies, memory dies, array dies). The die 205 or die 240 may be formed using a respective semiconductor substrate (e.g., a crystalline semiconductor material substrate such as silicon, germanium, silicon-germanium, gallium arsenide, or gallium nitride) or a silicon-on-insulator (SOI) substrate (e.g., silicon on glass (SOG), silicon on sapphire (SOS)), or an epitaxial semiconductor material formed on another substrate, among other examples. Although the illustrated example of the system 200 includes two dies 240, the system 200 according to the described techniques may include any number of one or more dies 240 coupled with the die 205. Furthermore, although the non-limiting examples of system 200 herein are generally described in terms of application to a memory system, memory subsystem, memory device, or combination thereof, examples of system 200 are not limited thereto. For example, aspects of the present disclosure may be equally applicable to any computing system, computing subsystem, processing system, processing subsystem, component, device, structure, or other type of system or subsystem used for applications such as data collection, data processing, data storage, networking, communication, power, artificial intelligence, single chip system, control, telemetry, sensing and monitoring, digital entertainment, or any combination thereof.

[0040] System 200 illustrates an example of interface circuitry between a host and memory (e.g., via a host interface, via a physical host interface) implemented in (e.g., distributed among) multiple semiconductor dies (e.g., a stack of directly coupled dies). For example, die 205 may include a set of one or more interface blocks 220 (e.g., interface blocks 220-a-1 and 220-a-2, memory interface blocks), and each die 240 may include a set of one or more interface blocks 245 and one or more memory arrays 250 (e.g., die 240-a-1 includes interface block 245-a-1 coupled to a set of one or more memory arrays 250-a-1, die 240-a-2 includes interface block 245-a-2 coupled to a set of one or more memory arrays 250-a-2). Memory array 250 may be an example of memory array 170 and may include memory cells of various architectures, such as RAM, DRAM, SDRAM, SRAM, FeRAM, MRAM, RRAM, PCM, chalcogenide, NOR, or NAND memory cells, or any combination thereof.

[0041] Although the example of system 200 is illustrated as including one interface block 245 in each die 240, a die 240 in accordance with the described techniques may include any number of one or more interface blocks 245, each coupled to a set of corresponding one or more memory arrays 250 and each coupled to a corresponding interface block 220 of die 205. Thus, the interface circuitry of system 200 may include one or more interface blocks 220 of die 205, wherein each interface block 220 is coupled (e.g., in communication) with a corresponding interface block 245 of die 240 (e.g., external to die 205). In some examples, the coupled combination of interface blocks 220 and interface blocks 245 (e.g., coupled via a bus associated with one or more channels, such as one or more data channels, one or more control channels, one or more clock channels, or a combination thereof) may include or be referred to as a data path associated with a set of corresponding one or more memory arrays 250.

[0042] In some implementations, the die 205 may include a host processor 210. The host processor 210 may be an example of the host system 105 or a portion thereof (e.g., an aspect of the processor 125, the external memory controller 120, or both). The host processor 210 may be configured to perform operations that implement storage of the memory array 250. For example, the host processor 210 may receive data read from the memory array 250 or may transmit data written to the memory array 250, or both (e.g., according to an application or other operation of the host processor 210). Additionally or alternatively, the host processor 210 may be external to the die 205, such as in another semiconductor die or other component that is coupled (e.g., communicatively coupled, directly coupled, bonded) to the die 205 via one or more contacts 212.

[0043] The host processor 210 may be configured to communicate (eg, transmit, receive) signals with the interface block 220 via one or more host interfaces 216 (eg, physical host interfaces). The host interface 216 may implement a reference Figure 1For example, the host processor 210 may be configured to transmit access signaling (e.g., control signaling, access command signaling, configuration signaling) via the host interface 216, which may be received by the interface block 220 to support access operations (e.g., read operations, write operations) to the memory array 250. In some examples, the host interface 216 may include a set of one or more signal paths for each interface block 220, so that the host processor 210 can communicate with each interface block 220 via a corresponding set of signal paths (e.g., according to a selection of a corresponding set of interface blocks 220 for performing access operations via the host processor 210). Additionally or alternatively, the host interface 216 may include one or more signal paths (not shown) shared between multiple interface blocks 220, and the interface blocks 220 or the host processor 210 or both may interpret, ignore, respond to, or suppress response signaling via the shared signal paths of the host interface 216 based on logical indications (e.g., addressing indications associated with the interface blocks 220 or interface enable signals, which may be provided by the host processor 210 or the corresponding interface blocks 220, depending on the signaling direction).

[0044] In some examples, a respective host interface 216 may be coupled between a set of one or more interface blocks 220 and a controller 215 (e.g., host interface 216-a-1 is coupled between interface block 220-a-1 and controller 215-a-1, and host interface 216-a-2 is coupled between interface block 220-a-2 and controller 215-a-2). The one or more interface blocks 220 and controller 215 may communicate (e.g., cooperate) to perform one or more operations associated with the memory array 250 (e.g., scheduling operations, access operations, operations initiated by the host processor 210). The controller 215 may be an instance of a control circuit system (e.g., memory controller circuit system, host interface control circuit system), and may be associated with a respective instance for each interface block 220 that implements one or more aspects of the external memory controller 120 or the memory system controller 155, or a combination thereof. In some examples, controller 215 may be implemented in die 205, whether host processor 210 is included in die 205 or external to die 205, and interface block 220 may communicate with host processor 210 via one or more controllers 215. In some other examples, controller 215 may be implemented external to die 205 (e.g., in another die (not shown) coupled to respective interface block 220 via respective terminals of each of respective host interfaces 216), which may be in the same or different die as that including host processor 210. In some other examples, aspects of one or more controllers 215 may be included in host processor 210. Although the example of system 200 is illustrated as including a controller 215 for each interface block 220, in various examples, the controller 215 may be coupled to any number of one or more interface blocks 220, and a given interface block 220 may be operated based on a single controller 215 or by one or more of a group of multiple controllers 215 (e.g., according to a controller multiplexing scheme).

[0045] In some examples, the host processor 210 may determine an access address (e.g., a logical address of the memory array 250, a physical address of the memory array 250, an address of the interface block 220) and determine to which controller 215 to transmit access signaling for the access address (e.g., the controller 215 or the interface block 220 corresponding to the address). In some examples, the address may be associated with a row of memory cells of the memory array 250. The host processor 210 may transmit the access signaling to the determination controller 215, and the determination controller 215 may in turn transmit the access signaling to the corresponding interface block 220. The corresponding interface block 220 may then transmit access signaling to the coupling interface block 245 to access the determination address (e.g., in the corresponding memory array 250).

[0046] The die 205 may also include a logic block 230 (e.g., a shared logic block, a central logic block, a common logic circuit system) that may be configured to communicate (e.g., transmit, receive) signaling with the interface block 220 of the die 205. In some cases, the logic block 230 may be configured to communicate information (e.g., commands, instructions, instructions, data) with one or more interface blocks 220 to facilitate operation of the system 200. For example, the logic block 230 may be configured to transmit configuration signaling (e.g., initialization signaling, evaluation signaling) that may be received by the interface block 220 to support configuration of the interface block 220 or other aspects of operating the die 240 (e.g., via a corresponding interface block 245). The logic block 230 may be coupled to each interface block 220 via a corresponding bus 231 (e.g., bus 231-a-1 associated with interface block 220-a-1, bus 231-a-2 associated with interface block 220-a-2). In some examples, the respective buses 231 may each include a set of respective one or more signal paths so that the logic block 230 can communicate with each interface block 220 via a respective set of signal paths. Additionally or alternatively, the respective buses 231 may include one or more signal paths (not shown) shared between multiple interface blocks 220.

[0047] In some implementations, logic block 230 may be configured to perform signaling communications (e.g., transmit, receive) with host processor 210 (e.g., via bus 232, via contacts 212 of host processor 210 external to die 205) such that logic block 230 may support an interface between interface block 220 and host processor 210. For example, host processor 210 may be configured to transmit initialization signaling (e.g., boot commands) or other configuration or operational signaling, which may be received by logic block 230 to support initialization, configuration, or other operations of interface block 220. Additionally or alternatively, in some implementations, logic block 230 may be configured to perform signaling communications (e.g., transmit, receive) with components external to system 200 via bus 233 (e.g., and via contacts 234) such that logic block 230 may support an interface that bypasses host processor 210. Additionally or alternatively, logic block 230 may communicate with host processor 210 and may communicate with one or more memory arrays 250 of one or more dies 240 (e.g., for performing self-test operations on memory arrays 250). In some examples, such implementations may support evaluation, configuration, or other operations of system 200 during manufacturing, assembly, validation, or other operations associated with system 200 (e.g., prior to coupling with host processor 210, when host processor 210 is not implemented, for operations independent of a host processor) via contacts 234 accessible at a physical interface of the system.

[0048] Each interface block 220 may be coupled to at least one respective bus 221 of die 205 and a respective bus 246 of die 240, which is configured to communicate signaling with the corresponding interface block 245 (e.g., via one or more associated signal paths). For example, interface block 220-a-1 may be coupled to interface block 245-a-1 via bus 221-a-1 and bus 246-a-1, and interface block 220-a-2 may be coupled to interface block 245-a-2 via bus 221-a-2 and bus 246-a-2. In some examples, die 240 may include a bus, such as bus 255, that bypasses the operational circuitry of die 240 (e.g., bypasses the interface block 245 of a given die 240). For example, interface block 220-a-2 may be coupled to interface block 245-a-2 of die 240-a-2 via bus 255-a-1 of die 240-a-1, which may bypass interface block 245 of die 240-a-1. Such techniques may be extended for interconnection between more than two dies 240 (e.g., for interconnection via respective buses 255 of multiple dies 240).

[0049] The respective signal paths of buses 221, 246, and 255 may be coupled to one another from one die to another via various arrangements of contacts at the surfaces of the interfacing dies. For example, bus 221-a-1 may be coupled to bus 246-a-1 via contacts 222-a-1 of die 205 (e.g., at the surface of die 205) and contacts 247-a-1 of die 240-a-1, bus 221-a-2 may be coupled to bus 255-a-1 via contacts 222-a-2 of die 205 and contacts 256-a-1 of die 240-a-1, bus 255-a-1 may be coupled to bus 246-a-2 via contacts 257-a-1 of die 240-a-1 and contacts 247-a-2 of die 240-a-2, and so on. Although each respective bus is illustrated with a single line coupled via a singular contact, it should be understood that each signal path of a given bus may be associated with a respective contact to support separate communication coupling of each signal path via the given bus. In some examples, bus 255 may pass through a portion of die 240 (e.g., in an in-plane direction, along a direction different from the thickness direction, in a waterfall arrangement), which may support the arrangement of contacts 222 along the surface of die 205 to couple with interface blocks 245 of different dies 240 along the stacking direction (e.g., via respective contacts 256 and 257 that do not overlap when viewed along the thickness direction).

[0050] The interconnection of the interface contacts may be supported by a variety of techniques. For example, in a hybrid bonding implementation, the interface contacts may be coupled by fusing the conductive material (e.g., electrically conductive material) of the interface contacts (e.g., without solder or other intervening material between the contacts). For example, in an assembled condition, the coupling of die 205 to die 240-a-1 may include fusing the conductive material of contact 222-a-2 to the conductive material of contact 256-a-1, and the coupling of die 240-a-1 to die 240-a-2 may include fusing the conductive material of contact 257-a-1 to the conductive material of contact 247-a-2, and so on. In some examples, such coupling may include inoperable fusion of contacts (e.g., non-communicative coupling, physical coupling), such as fusion of contact 260-a-1 and contact 256-a-2, both of which are not coupled to the operable circuitry of die 240-a-1 or 240-a-2. In some examples, such techniques may be implemented to improve coupling strength or uniformity (e.g., implementing contact 260 that may not be operably coupled to interface block 245 or interface block 220), or such coupling may be a byproduct of duplication of components that may be operable or inoperable in various configurations. (For example, where for a die 240 having contacts 256 and 257 arranged together, contacts 256-a-1 and 257-a-1 provide a communication path between interface block 245-a-2 and interface block 220-a-2, but contacts 256-a-2 and 257-a-2 do not provide a communication path between interface block 245 and interface block 220).

[0051] In some examples, the fusion of conductive material between the dies (e.g., between contacts) may be accompanied by fusion of other materials at one or more surfaces of the interfacing dies. For example, in an assembled condition, the coupling of die 205 with die 240-a-1 may include fusion of dielectric material 207 (e.g., non-conductive material) of die 205 with dielectric material 242 of die 240-a-1, and the coupling of die 240-a-1 with die 240-a-2 may include fusion of dielectric material 242 of die 240-a-1 with dielectric material 242 of die 240-a-2. In some examples, such dielectric materials may include oxides, nitrides, carbides, oxide-nitrides, oxide-carbides, or other conversions or doping of semiconductor materials of die 205 or die 240, as well as other materials that may support such fusion. However, the coupling between die 205 and die 240 may be implemented according to other techniques, which may implement solder, adhesives, thermal interface materials, and other intervening materials.

[0052] In some examples, the dies 240 may be coupled into a stack (e.g., forming a "cube" or other arrangement of dies 240), and the stack may then be coupled to the die 205. In some examples, a group of respective one or more dies 240 may be coupled to each die 205 of the plurality of dies 205 formed in a wafer (e.g., in a chip-to-wafer bonding arrangement, before dicing the wafer of dies 205), and the dies 205 coupled to their respective groups of dies 240 may be separated from each other (e.g., by dicing at least the wafer of dies 205). In some other examples, a group of respective one or more dies 240 may be coupled to the respective die 205 after the dies 205 are separated from the wafer of dies 205 (e.g., in a chip-to-chip bonding arrangement).

[0053] The buses 221, 246, and 255 may be configured to provide configuration signaling (e.g., coordination signaling, logic signaling, modulation signaling, digital signaling) between the interface block 220 and the corresponding interface block 245, which may involve various modulation or coding techniques through the transmission interface block (e.g., via the driver component of the transmission interface block). In some examples, this signaling may be supported (e.g., accompanied) by clock signaling communicated (e.g., coordinated with the signal transmission) via the corresponding bus. For example, the bus may be configured to pass one or more clock signals transmitted by the interface block 220 for reception by the interface block 245 (e.g., for triggering a latch or other receiving component of the interface block 245 to receive a signal, for supporting the timing control operation of the interface block 245). Additionally or alternatively, the bus may be configured to pass one or more clock signals transmitted by the interface block 245 for reception by the interface block 220 (e.g., for triggering a latch or other receiving component of the interface block 220 to receive a signal, for supporting the timing control operation of the interface block 220). Such clock signals may be associated with the communication (e.g., unidirectional communication, bidirectional communication) of various signaling (e.g., control signaling, command signaling, data signaling, or any combination thereof). For example, a bus may include one or more signal paths for a data bus (e.g., one or more data lanes, a DQ bus, a data interface via an interface block) to communicate according to one or more corresponding clock signals (e.g., a data clock signal) or one or more signal paths for a control bus (e.g., a command / address (C / A) bus, a command interface via an interface block) to communicate according to one or more clock signals (e.g., a control clock signal), or any combination thereof.

[0054] Interface block 220, interface block 245, and logic block 230 may each include circuitry (signaling circuitry, multiplexing circuitry, processing circuitry, controller circuitry) in various configurations (e.g., hardware configurations, logic configurations, software or instruction configurations) that support functionality assigned to the respective blocks for accessing or otherwise operating a set of corresponding memory arrays 250. For example, interface block 220 may include circuitry configured to perform a first subset of operations supporting access of memory arrays 250, and interface block 245 may include circuitry configured to support a second subset of operations supporting access of memory arrays 250. In some examples, interface blocks 220 and 245 may support functional partitioning or distribution of functionality associated with memory system controller 155, local memory controller 165, or both across multiple dies (e.g., die 205 and at least one die 240). In some implementations, logic block 230 may be configured to coordinate or configure aspects of the operation of interface block 220, interface block 245, or both and may support one or more aspects of implementing memory system controller 155. Such operations or subsets of operations may include operations performed in response to commands from host processor 210 or operations performed without commands from host processor 210 (e.g., operations determined or initiated by interface block 220, operations determined or initiated by interface block 245, operations determined or initiated by logic block 230), or various combinations thereof.

[0055] In some implementations, system 200 may include one or more instances of nonvolatile storage devices, such as nonvolatile storage device 235 of die 205, nonvolatile storage device 270 of one or more dies 240, or a combination thereof. In some examples, logic block 230, interface block 220, interface block 245, or a combination thereof may be configured to communicate signaling with the one or more instances of nonvolatile storage devices. For example, logic block 230, interface block 220, or interface block 245 may be appropriately coupled to the one or more instances of nonvolatile storage devices via one or more buses (not shown) or corresponding contacts (not shown) that may each include one or more signal paths operable to convey signaling (e.g., command signaling, data signaling). In some examples, logic block 230, one or more interface blocks 220, one or more interface blocks 245, or a combination thereof may configure one or more operations based on information stored in one or more instances of nonvolatile storage devices. Additionally or alternatively, in some examples, logic block 230, one or more interface blocks 220, one or more interface blocks 245, or a combination thereof may write information (eg, configuration information) stored in one or more instances of non-volatile storage.

[0056] In some embodiments, the system 200 may include one or more sensors (e.g., one or more sensors 237 of the die 205, one or more sensors 275 of the die 240, or a combination thereof). In some embodiments, the logic block 230, the interface block 220, the interface block 245, or a combination thereof may be configured to receive one or more indications based on measurements of one or more sensors of the system 200. For example, the logic block 230, the interface block 220, or the interface block 245 may be coupled to the one or more sensors via one or more buses (not shown) or corresponding contacts (not shown). Such sensors may include temperature sensors, current sensors, voltage sensors, counters, and other types of sensors. In some examples, the logic block 230, the one or more interface blocks 220, the one or more interface blocks 245, or a combination thereof may configure one or more operations based on the output of the one or more sensors. For example, the logic block 230 may configure one or more operations of the interface block 220 based on signaling (e.g., indications, data) received from the one or more sensors. Additionally or alternatively, the interface block 220 may generate access signaling for transmission to a corresponding interface block 245 based on one or more sensors.

[0057] In some examples, the circuitry of interface block 220, interface block 245, or logic block 230, or any combination thereof, may include components (e.g., transistors) formed at least in part from doped portions of a substrate of a respective die. In some examples, the substrate of die 205 may have characteristics that differ from characteristics of a substrate of die 240. Additionally or alternatively, in some examples, transistors formed from the substrate of die 205 may have characteristics that differ from transistors formed from the substrate of die 240 (e.g., according to different transistor architectures).

[0058] In some examples, interface block 220 may support a layout of one or more components within 220. For example, the layout may include paired components sharing access ports (e.g., command ports, data ports). Further, in some examples, the layout may support an interface for controller 215 (e.g., host interface 216) that is different from an interface for interface block 245 (e.g., via bus 221). For example, host interface 216 may be synchronous and have separate channels for read and write operations, while the interface via buses 221 and 246 may be asynchronous and support both read and write operations with the same channel.

[0059] The die 240 may include one or more cells 265 (e.g., modules) separated from a semiconductor wafer having a pattern (e.g., a two-dimensional pattern) of cells 265. Although each die 240 of the system 200 is illustrated as having a single cell 265 (e.g., cell 265-a-1 of die 240-a-1, cell 265-a-2 of die 240-a-2), a die 240 according to the described techniques may include any number of cells 265 that may be arranged in various patterns (e.g., groups of one or more cells 265 along a row direction, groups of one or more cells 265 along a column direction, and other patterns). Each cell 265 may include at least the circuitry of a corresponding interface block 245 and a memory array 250, a bus 251, a bus 246, and one or more contacts 247 corresponding to the corresponding interface block 245. In some instances, each unit 265 may also appropriately include one or more buses 255, contacts 256, contacts 257, or contacts 260 (e.g., associated with corresponding interface blocks 245 of units 265 of different dies 240), which may support various degrees of stackability or modularity between units 265 of other dies 240 or via units 265 of other dies 240.

[0060] In some examples, the interface block 220 may include circuitry configured to receive first access command signaling from the host processor 210 or controller 215 (e.g., via the host interface 216, from the host processor 210 or controller 215 external to the die 205 via one or more contacts 212) and transmit second access command signaling to a corresponding (e.g., coupled) interface block 245 based on (e.g., in response to) the received first access command signaling. The interface block 245 may thus include circuitry configured to receive second access command signaling from the corresponding interface block 220 and, in some examples, access a corresponding set of one or more memory arrays 250 based on (e.g., in response to) the received second access command signaling. In various examples, the first access command signaling may include an access command associated with an operation type (e.g., a read operation, a write operation, a refresh operation, a memory management operation), which may be associated with an indication of an address (e.g., a logical address, a physical address) of the one or more memory arrays 250. In some examples, the first access command signaling may include an indication of a logical address associated with the memory array 250, and the circuit system of the interface block 220 may be configured to generate a second access command signaling to indicate a physical address associated with the memory array 250 (e.g., a row address, a column address, using a logical-to-physical (L2P) table or other mapping or calculation functionality of the interface block 220).

[0061] In some examples, to support write operations of the system 200, the circuitry of the interface block 220 may be configured to receive first data signaling associated with the first access command signaling (e.g., from the host processor 210, from the controller 215, via the host interface 216, from the host processor 210 or the controller 215 external to the die 205 via one or more contacts 212) and transmit second data signaling (e.g., associated with the second access command signaling) based on the received first access command signaling and the first data signaling. The interface block 245 may thus be configured to receive the second data signaling and write data to the one or more memory arrays 250 based on the received second access command signaling and the second data signaling (e.g., according to the indicated address associated with the first access command signaling). In some instances, interface block 220 may include error control functionality (e.g., error detection circuitry, error correction circuitry, error correction code (ECC) logic, an ECC engine) that supports interface block 220 in generating second data signaling based on performing error control operations using received first data signaling (e.g., detecting or correcting errors in the first data signaling, determining one or more parity bits conveyed in the second data signaling and written with the data).

[0062] In some examples, to support read operations of system 200, the circuitry of interface block 245 may be configured to read data from memory array 250 based on received second access command signaling and transmit first data signaling based on the read data. Interface block 220 may thus be configured to receive first data signaling and transmit second data signaling based on the received first data signaling (e.g., to host processor 210, to controller 215, via host interface 216, to host processor 210 or controller 215 external to die 205 via one or more contacts 212). In some examples, interface block 220 may include error control functionality that enables interface block 220 to generate second data signaling based on performing error control operations using received first data signaling (e.g., detecting or correcting errors in the first data signaling, which may include calculations involving one or more parity bits received with the first data signaling).

[0063] In some examples, access command signaling and other signaling transmitted by the interface block 220 to the interface block 245 may be generated (e.g., based on access command signaling received from the host processor 210, based on start signaling received from the host processor 210, without receiving or otherwise independently of signaling from the host processor 210) according to various determination or generation techniques configured at the interface block 220 (e.g., based on a configuration modified at the interface block 220 for accessing the memory array 250). In some examples, such techniques may involve signaling or other coordination with the logic block 230, the host processor 210, one or more controllers 215, one or more instances of non-volatile storage devices, one or more sensors, or any combination thereof. Such techniques may support the interface block 220 in configuring aspects of access operations and other operations performed by the corresponding interface block 245 on the memory array 250. For example, interface block 220 may include evaluation circuitry, access configuration circuitry, signaling circuitry, scheduling circuitry, repair circuitry, refresh circuitry, error control circuitry, adverse access circuitry, and other circuitry that may be operable to configure operations associated with one or more dies (e.g., operations associated with accessing memory array 250 of die 240).

[0064] In some cases, memory cells in the memory array 250 may be subject to adverse accesses, such as a row hammer attack, that may modify (e.g., destroy, corrupt) data stored by the memory cells. For example, as part of a row hammer attack, a row of memory cells (e.g., an aggressor row) of the memory array 250 may experience repeated activations within a relatively short duration, which may adversely affect the logic states stored by memory cells in one or more rows adjacent to the aggressor row. To mitigate the adverse effects of a row hammer attack, a counter associated with a row of the memory array 250 (e.g., a counter included in or coupled to the memory array 250) may count (e.g., monitor, track) the number of access operations (e.g., row activations) to the row and identify when the number of access operations meets (e.g., reaches, exceeds) one or more thresholds. However, the counters used to evaluate potential adverse accesses may experience errors, which may reduce the reliability of the adverse access mitigation technique.

[0065] According to the techniques described herein, a spare counter may be implemented by the interface block 220 of the die 205 to support improved reliability of row hammer mitigation and to compensate for errors of the counters at the die 240. For example, the interface block 220 may activate and use the spare counter in response to an error associated with the counter at the memory array 250. For example, the interface block 220 may receive from the interface block 245 an alarm signaling indicating an error associated with the counter of the corresponding die 240 for counting row activations. Based on the alarm signaling indicating the error, the interface block 220 may activate the spare counter to track the activation of the row. The interface block 220 may use the spare counter to evaluate whether to transmit refresh signaling to the interface block 245 for row hammer mitigation (e.g., when the spare counter remains activated). Using the spare counter and techniques described herein may improve the reliability and efficiency associated with the row hammer mitigation techniques at the system 200.

[0066] Figure 3 An example of an interface architecture 300 that supports row hammer mitigation reliability in a stacked memory architecture according to examples disclosed herein is shown. Interface architecture 300 illustrates an example of an interface block 245-b (e.g., of die 240) coupled with an interface block 220-b (e.g., of die 205). Interface block 245-b may be communicatively coupled with interface block 220-b via one or more of bus 301, bus 302, bus 303, and bus 304, each of which may be an example of one or more signal paths of bus 221 and bus 246 as well as bus 255, as appropriate.

[0067] The interface block 245-b includes a control interface 310 (e.g., a command interface) that can be configured to communicate with the interface block 220-b for signaling. For example, the control interface 310 can include a circuit system (e.g., a receiver, one or more latches) configured to receive control signaling (e.g., modulation control signaling, access command signaling, configuration signaling, address signaling, such as row address signaling or column address signaling) via the bus 301-a. The control interface 310 can also include a circuit system configured to receive clock signaling (e.g., clock signaling associated with the control interface 310, clock signaling with one or more phases (e.g., true and complementary phases), dk_t / c signaling from the interface block 220-b) via the bus 302-a. The control interface 310 can use the bus 302-a to receive control signaling of the bus 301-a (e.g., for triggering one or more latches). The control interface 310 may transmit (eg, forward) control signaling, clock signaling (eg, for timing of other operations of the interface block 245 - b ) to the interface controller 320 .

[0068] Interface block 245-b also includes two data interfaces 330 (e.g., data interfaces 330-a-1 and 330-a-2), which may also be configured for signaling communication with interface block 220-b. Each data interface 330 may include a corresponding bus and circuitry, the operation of which may be associated with (e.g., controlled by, coordinated with, operated based on) control signaling via control interface 310. Although the example of interface block 245-b includes two such data interfaces 330 associated with control interface 310 (e.g., in a "channel pair" arrangement), the techniques described for interface block 245 may include any number of one or more data interfaces 330 and associated buses and circuitry for a given control interface 310 of interface block 245. Each data interface 330 may be associated with a corresponding data path circuit system, which may include corresponding first-in-first-out (FIFO) and serialization / deserialization (SERDES) circuit systems (e.g., FIFO / SERDES 340), corresponding write / sense circuit systems 350, corresponding synchronization and sequencing circuit systems (e.g., synchronization / sequencing logic 360), and corresponding timing circuit systems 370, as well as interconnecting signal paths (e.g., one or more buses). However, in some other examples, the data path circuit systems may be arranged in a different manner or may include different circuit system components, which may include circuit systems dedicated to the corresponding data paths or shared between data paths, or various combinations thereof. Each data interface 330 may also be associated with a set of corresponding one or more memory arrays 250. In some examples, each memory array 250 may be understood to include corresponding addressing circuit systems, such as storage body logic or decoders (e.g., row decoders, column decoders), and other array circuit systems. However, in some other examples, at least a portion of this circuit system may be included in the interface block 245.

[0069] Each data interface 330 may include circuitry (e.g., one or more latches, one or more drivers) configured to communicate (e.g., receive, transmit) data signaling (e.g., modulated data signaling, DQ signaling) via the corresponding bus 303. Each data interface 330 may also include circuitry for communicating clock signaling via the corresponding bus 304, which may support the data interface 330 to receive a clock signal (e.g., a first clock signaling associated with the data interface 330, a clock signaling having one or more phases (e.g., true and complementary phases), DQS_t / c signaling from the interface block 220-b, clock signaling associated with a data reception or write operation) or the data interface 330 to transmit a clock signal (e.g., a second clock signaling associated with the data interface 330, RDQS_t / c signaling to the interface block 220-b, clock signaling associated with a data transmission or read operation), or both. Each data interface 330 may transmit clock signaling (eg, received clock signaling, DQS_t / c signaling) to the synchronization / sequencing logic 360 via a respective bus (eg, for timing of other operations of the interface block 245 - b ).

[0070] The interface controller 320 may support various control or configuration functionalities of the interface block 245-b for accessing the coupled memory array 250 or otherwise managing the operation of the coupled memory array 250. For example, the interface controller 320 may support access command coordination or configuration, delay or timing compensation, access command buffering (e.g., according to a FIFO or other organizational scheme), mode registers or logic for configuration settings or test functionality, and other functions or combinations thereof. For each data path of the interface block 245 (e.g., associated with a corresponding data interface 330), the interface controller 320 may be configured to transmit signaling (e.g., address signaling, such as row address or row activation signaling) to the corresponding memory array 250 via a bus 321. For each data path of the interface block 245, the interface controller 320 may communicate signaling (e.g., timing signaling (which may be based on clock signaling received from the control interface 310), configuration signaling) with the corresponding timing circuit system 370 and synchronization / sequencing logic 360 via a corresponding bus.

[0071] For each data path, a respective timing circuitry 370 may support timing of various operations (e.g., activation, coupling operations, signal latching, signal driving) relative to timing signaling received from the interface controller 320. For example, the timing circuitry 370 may include a timing chain (e.g., a global column timing chain) configured to generate one or more clock signals or other enable signals for controlling the operation of the respective data paths, and such signaling may include transitions (e.g., rising edge transitions, falling edge transitions, on / off transitions) that are offset from transitions of the signaling from the interface controller 320, occur at a different rate than the transitions, or otherwise differ from the transitions to support a given operation or combination of operations. For example, the timing circuitry 370 may be configured to transmit signaling (e.g., column select signaling, column address signaling) to the respective memory array 250, transmit signaling (e.g., latch or driver timing signaling) to the respective write / sense circuitry 350, and transmit signaling (e.g., timing signaling) to the respective synchronization / sequencing logic.

[0072] For each data path, a respective FIFO / SERDES 340 may be configured to convert between data signaling of a first bus width (e.g., a relatively wider bus width, a data read / write (DRW) bus, a bus for communicating with a write / sense circuitry 350 having a relatively greater number of signal paths) and a second bus width (e.g., a relatively narrower bus width, a bus for communicating with a data interface 330 having a relatively lesser number of signal paths). In some examples, such conversion may be accompanied by changing the signaling rate between signaling from the data interface 330 and the write / sense circuitry 350 (e.g., for maintaining a given throughput). In various examples, the FIFO / SERDES 340 may receive data signaling from the data interface 330 and transmit data signaling to the write / sense circuitry 350 (e.g., for supporting write operations), or may receive data signaling from the sense circuitry 350 and transmit data signaling to the data interface 330 (e.g., for supporting read operations). In some examples (eg, for supporting read operations), the FIFO / SERDES 340 may be configured to transmit clock signaling (eg, RDQS_t / c signaling) to the data interface 330, which may be forwarded to the interface block 220-b.

[0073] The timing or other synchronization of the operations performed by the FIFO / SERDES 340 may be supported by one or more clock signals and other signaling received from the corresponding synchronization / sequencing logic 360. For example, the synchronization / sequencing logic 360 may generate or otherwise coordinate clock signaling to support different signaling rates for different buses (e.g., based on received clock signaling). Additionally or alternatively, the FIFO / SERDES 340 may operate in one direction (e.g., for data transmission to the data interface 330, for data reception from the data interface 330) or other modes based on configuration signaling received from the synchronization / sequencing logic 360.

[0074] For each data path, a respective write / sense circuitry 350 may be configured to support access (e.g., data signaling, write signaling, read signaling) of a respective group of one or more memory arrays 250. For example, the write / sense circuitry 350 may be coupled to the memory arrays 250 via a bus (e.g., a global input / output (GIO) bus), which may include respective signal paths associated with each memory array 250 or may include signal paths shared by all memory arrays 250 of the group, in which case the memory array circuitry may include multiplexing circuitry operable to couple the bus with selected ones of the memory arrays 250. In some examples, the bus between the write / sense circuitry and the group of one or more memory arrays 250 may include the same number of signal paths as the bus between the write / sense circuitry 350 and the FIFO / SERDES 340 (e.g., for signaling GIO[287:0]) or the same number of signal paths as the number of columns in each memory array 250. In some other examples, the memory array 250 may include a number of columns that is an integer multiple of the number of signal paths of the bus, in which case the memory array circuitry (e.g., each memory array 250) may include decoding circuitry operable to couple a subset of the memory cell columns or associated circuitry to the bus.

[0075] To support write operations, write / sense circuitry 350 may be configured to drive signaling operable to write one or more logic states to memory cells of memory array 250 (e.g., based on received data, based on received timing signaling, based on data signaling received via bus 303, and based on control signaling received via bus 301-a). In some examples, such signaling may be transmitted to or otherwise associated with supporting circuitry of memory array 250 (e.g., as an output of a signal corresponding to the logic state to be written), such as sense amplifier circuitry, voltage sources, current sources, or other driver circuitry operable to apply a bias across a storage element of a memory cell (e.g., across a capacitor, across a ferroelectric capacitor) or to apply a charge, current, or other signaling to a storage element of a memory cell (e.g., applying current to a chalcogenide or other configurable memory material, applying charge to a gate of a NAND memory cell), as well as other examples.

[0076] To support read operations, the write / sense circuitry 350 may be configured to receive signaling, which the write / sense circuitry 350 may further amplify for communication through the interface block 245-b. For example, the write / sense circuitry 350 may be configured to receive signaling corresponding to a logic state read from the memory array 250, but at a relatively low driver strength (e.g., relatively 'analog' signaling, which may be associated with a relatively low drive strength of a sense amplifier of the memory array 250). The write / sense circuitry 350 may therefore include further sense amplification (e.g., data sense amplifiers (DSAs) between a signal path between the write / sense circuitry and the set of one or more memory arrays and a corresponding signal path between the write / sense circuitry and the FIFO / SERDES), each of which may have a relatively high drive strength (e.g., for driving relatively 'digital' signaling).

[0077] Features of interface architecture 300 may be repeated in various numbers and arrangements to support semiconductor systems having multiple dies, such as various instances of system 200. In an example embodiment, each die 240 may be configured with 64 instances of interface block 245-b, which may support a data signaling width of 9,216 signal paths for each die 240 (e.g., where each bus 303 of a channel pair is associated with 72 signal paths). For system 200 having a stack of 8 dies 240 coupled to die 205, die 205 may thus be configured with 512 instances of interface block 220-b, thereby supporting a total data signaling width of 73,738 signal paths for system 200. However, in other embodiments, die 205 and die 240 may be configured with different numbers of interface blocks 220 and 245, respectively, and system 200 may be configured with different numbers of dies 240 per die 205.

[0078] In some examples, the memory array 250 may be organized with rows of memory cells, each row being associated with an address of the memory array 250. Each memory array 250 may be associated with (e.g., coupled to, including) a set of counters 380-a (e.g., located in the die 240). The set of counters 380-a may track access operations associated with the memory array 250 and may include a respective counter 380-a for each row of the memory array 250. For example, each counter 380-a may track a respective number of access operations (e.g., respective row activations) to a respective row of the memory array 250. In some examples, the interface controller 320 may operate (e.g., read, increment, write, reset) the counters 380-a via the bus 321. Additionally or alternatively, the interface controller 320 may operate the counters 380-a via a dedicated bus 322 (e.g., a dedicated GIO bus, a dedicated access line). The interface controller 320 may detect a row hammer attack on the memory array 250 by monitoring the number of access operations to the memory array 250 via the counter 380-a. For example, the interface controller 320 may compare the value of the counter 380-a with one or more thresholds to determine whether the row associated with the counter 380-a is likely to be subject to a row hammer attack based on whether the value satisfies at least one of the one or more thresholds.

[0079] Based on comparing the corresponding value of the counter 380-a with one or more thresholds, for example, if the value of the counter 380-a satisfies at least one of the one or more thresholds, the interface block 245-b may transmit an alert signaling to the interface block 220-b (e.g., via one or more signal paths of the bus 301, via one or more alert pins of the bus 301) to perform a row hammer mitigation operation. The interface block 220 may evaluate the received alert signaling and may transmit a refresh signaling including one or more refresh commands to the interface block 245-b in response to the alert signaling (e.g., via the bus 301). The refresh command may instruct the interface block 245-b (e.g., the interface controller 320) to refresh one or more rows (e.g., the victim rows) of the memory array 250 that are adjacent to the row (e.g., the aggressor row) associated with the alert signaling, which may mitigate the adverse effects of the row hammer attack. However, in some cases, there may be errors associated with one or more of the counters 380-a, which may inhibit the interface block 245-b from accurately detecting a row hammer attack on the memory array 250 and thereby reduce the reliability of the row hammer mitigation.

[0080] According to the techniques described herein, a set of one or more counters 385-a (e.g., spare counters) may be implemented at the interface block 220-b to support improved reliability of row hammer mitigation operations. For example, the interface block 245-b may identify an error associated with a counter 380-a (e.g., or multiple counters 380-a) that tracks access operations (e.g., row activation) to a row of the memory array 250. The interface block 245-b may transmit an alarm signaling indicating the error to the interface block 220-b and, in some examples, may refresh (e.g., reset) the counter 380-a. In response to the alarm signaling indicating the error, the interface block 220-b may activate the counter 385-a of the interface block 220-b to track access operations to the row (e.g., in place of or in addition to the counter 380-a). The interface block 220-b may then use the counter 385-a to evaluate whether to transmit refresh signaling for one or more adjacent (e.g., adjacent) rows adjacent to the row based on the value of the counter 385-a. This implementation of the counter 385 - a at the interface block 220 - b may improve the reliability of row hammer mitigation operations by enabling a system (eg, a TCDRAM system) to compensate for (eg, tolerate, recover from) errors associated with the counter 380 - a .

[0081] Figure 4 An example of a system 400 that supports row hammer mitigation reliability in a stacked memory architecture according to examples disclosed herein is shown. System 400 illustrates an example of an interface block 245-c (e.g., of die 240) coupled to an interface block 220-c (e.g., of die 205). Interface block 245-c and interface block 220-c may include circuitry operable to perform the operations described herein. Interface block 245-c may be communicatively coupled to interface block 220-c (e.g., via one or more of bus 301, bus 302, bus 303, or bus 304). Interface block 245-c may be coupled to one or more memory arrays 250 (including memory array 250-c). One or more memory arrays 250 may each include a plurality of rows 405-a (e.g., rows 405-a-1 to 405-a-7), and each row 405-a may include a set of memory cells and be associated with a corresponding address (e.g., a physical address).

[0082] Each row 405 of the one or more memory arrays 250 may be associated with a corresponding counter 380-b (e.g., counters 380-b-1 through 380-b-7 corresponding to rows 405-a-1 through 405-a-7). In some examples, the counters 380-b may be included in the memory array 250-c or may be located elsewhere in the die 240. The interface block 220-c may also include one or more counters 385-b (e.g., spare counters). In some examples, the one or more counters 385-b may be included in a memory (e.g., SRAM, latches) of the interface block 220-c that may be allocated and deallocated to the counters 385-b. In some examples, the system 400 may use one or more counters 385-b based on an error in one of the counters 380-b. By including one or more counters 385-b, the system 400 may improve reliability and efficiency associated with row hammer mitigation procedures.

[0083] In some cases, the system 400 may be subject to a row hammer attack, in which a large number of access commands are issued (e.g., via the interface block 220-c in a relatively small amount of time) to a row 405 of the memory array 250, which may be referred to as the aggressor row 405. Due to the continuous access commands, charge from the aggressor row 405 may leak to or from one or more memory cells of other rows 405 near the aggressor row 405 (e.g., a neighboring row 405 not associated with the address in the access command). The charge leakage or other associated disturbances may affect the state (e.g., charge) of the memory cells in the victim row, which may result in modification of data stored in the memory cells of the victim row. Therefore, the system 400 may perform a row hammer mitigation procedure to reduce (e.g., avoid) such adverse effects, which may include refreshing the state (e.g., logic state, electrical state) of the memory cells of the victim row (e.g., to restore their correct state).

[0084] In some examples, the interface block 220-c may transmit access signaling 410 (e.g., an ACT command) to activate a first row 405-a (e.g., row 405-a-4) of the memory array 250-c to the interface block 245-c via a bus (e.g., bus 301). Based on receiving the access signaling 410, the interface block 245-c may activate (e.g., access) a first row 405-a of a plurality of rows 405-a of the memory array 250-c. Each counter 380-b may be used (e.g., maintained, incremented) to track (e.g., count) a respective number of activations of a corresponding row 405-a (e.g., a respective number of access operations to the corresponding row 405-a). For example, the counter 380-b may be implemented as a per-row counter to count a respective number of activations of each row 405-a. For example, counter 380-b-1 may be used to track the number of activations of row 405-a-1, counter 380-b-2 may be used to track the number of activations of row 405-a-2, etc. Thus, upon accessing (e.g., activating) the first row 405-a, interface block 245-c may increment a first counter 380-b (e.g., counter 380-b-4) associated with the first row 405-a to track the number of activations of the first row 405-a.

[0085] The counter 380-b may be used to support row hammer mitigation. For example, the interface block 245-c may transmit an alarm signaling 415 to the interface block 220-c (e.g., via the bus 301) based on determining that the value of the first counter 380-b satisfies one or more thresholds. In some examples, the counter 380-b may be a multi-bit (e.g., 14-bit) counter, where different subsets of the bits of the counter 380-b are used to determine whether the value of the counter 380-b satisfies one or more thresholds or identify an error associated with the counter 380-b. Each counter 380-b may include a plurality of portions 425 (e.g., a portion 425-a-1 and a portion 425-b-1) corresponding to respective subsets of one or more bits of the counter 380-b. The interface block 245-c may use the portion 425 to determine whether the value of the counter 380-b satisfies one or more thresholds or identify an error associated with the counter 380-b. For example, each counter 380-b may include a portion 425-a-1 (e.g., a row hammer 1 (RH1) counter) for tracking the number of activations (e.g., access operations) of the corresponding row 405-a, which may indicate whether the value of the counter 380-b satisfies a first threshold.

[0086] Each counter 380-b may also include a portion 425-b-1 (e.g., a row hammer 2 (RH2) counter) that may track the number of occurrences at which the counter 380-b (e.g., portion 425-a-1) satisfies a first threshold. For example, the interface block 245-c may increment the portion 425-b-1 based on the value of the counter 380-b satisfying the first threshold, such as incrementing the portion 425-b-1 each time the portion 425-a-1 satisfies the first threshold (e.g., each time the portion 425-a-1 is reset). The portion 425-b-1 may indicate whether the value of the counter 380-b satisfies a second threshold. In some examples, for example, based on the RH2 counter incrementing in response to the first threshold being satisfied, the second threshold may be greater than the first threshold (e.g., may be a multiple of the first threshold).

[0087] The interface block 245-c may generate the alarm signaling 415 according to various alarm types based on comparing the value of the counter 380-b to one or more thresholds or identifying an error of the counter 380-b. A first alarm type (e.g., RH1 alarm, RHALERT1) may be associated with the value of the counter 380-b (e.g., in portion 425-a-1) satisfying a first threshold. A second alarm type (e.g., RH2 alarm, RHALERT2) may be associated with the value of the counter 380-b (e.g., in portion 425-b-1) satisfying a second threshold. A third alarm type may be associated with the value of the counter 380-b failing to satisfy one or more thresholds (e.g., the first threshold and the second threshold) and not identifying an error of the counter 380-b. In some examples, if the value of the counter 380-b fails to satisfy one or more thresholds, the interface block 245-c may refrain from generating the alarm signaling 415 according to a third alarm type (e.g., no alarm). For example, the third alarm type may correspond to no alarm being sent.

[0088] Based on receiving the alert signaling 415 indicating that one or more of the thresholds are satisfied, the interface block 220-c may transmit to the interface block 245-c a refresh signaling 420 (e.g., via the bus 301) indicating (e.g., causing, commanding) the interface block 245-c to refresh one or more rows 405-a of the memory array 250-c that are adjacent to (e.g., adjacent to) the first row 405-a. The refresh signaling 420 may include one or more refresh commands based on the alert type for the one or more rows 405-a. In some examples, if the alert type is a first alert type (e.g., RH1ALERT), the refresh signaling 420 may include one or more refresh commands for refreshing one or more rows 405-a that are close to (e.g., directly adjacent to, adjacent to) the first row 405-a associated with the alert signaling 415 (e.g., an aggressor row). For example, if the alert signaling 415 indicates a first alert type and is associated with row 405-a-4, the interface block 220-c may issue one or more (e.g., corresponding) refresh commands for rows 405-a-3 and 405-a-5 that are directly adjacent to row 405-a-4. If the alert type indicates a second alert type (e.g., RH2ALERT), the refresh signaling 420 may include one or more sets of refresh commands for one or more rows 405-a that are not directly adjacent to the first row 405-a, plus the directly adjacent rows 405-a. For example, the interface block 220-c may issue one or more (e.g., corresponding) refresh commands for rows 405-a-2 and 405-a-6, plus one or more refresh commands for rows 405-a-3 and 405-a-5.

[0089] Such a refresh operation may mitigate the undesired effects of a row hammer attack or other adverse accesses (e.g., data modification). However, in some cases, the counter 380-b may experience an error that corrupts the value stored at the counter 380-b. Thus, the interface block 245-c may not accurately identify a row hammer attack or may misidentify a row hammer attack. For example, the counter 380-b may have a permanent error including one or more bits of the counter 380-b being permanently stuck at either a '1' or a '0', which may result in inaccuracies associated with whether the value of the counter 380-b satisfies one or more thresholds. For example, depending on which bits are stuck and in which state the bits are stuck, such a permanent error may cause the value of the counter 380-b to satisfy the threshold more often than expected (e.g., for every ACT command issued) or less often than expected (e.g., not satisfying the threshold regardless of the number of ACT commands issued). Additionally or alternatively, the counter 380-b may experience a transient error (e.g., a temporary error) in which one or more bits of the counter 380-b temporarily become incorrect states, but its error is not permanent. Such transient errors may cause the interface block 245-c to inadvertently issue or fail to issue an alarm signaling 415 to the interface block 220-c. Therefore, techniques for compensating for errors associated with the counter 380-b may improve system reliability, for example, by supporting more reliable issuance of refresh signaling 420 to protect against row hammer attacks, and improve system efficiency, for example, by reducing unnecessary execution of refresh operations.

[0090] According to the techniques described herein, the interface block 245-c may identify an error associated with the counter 380-b and may transmit an alarm signaling 415 including an indication of the error associated with the counter 380-b to the interface block 220-c. For example, the counter 380-b may also include a portion 425-c (e.g., one or more parity bits, a cyclic redundancy check (CRC) portion, an error correction code (ECC) portion), which the interface block 245-c may use to identify an error associated with the counter 380-b. For example, the interface block 245-c may use one or more parity bits or error correction bits of the counter 380-b, perform a CRC operation based on reading the portion 425-c, or a combination thereof to identify (e.g., detect) an error associated with the counter 380-b. The fourth alarm type (e.g., counter error alarm, RHALERTERR) may be associated with the interface block 245-c identifying an error (e.g., permanent error, transient error) of the counter 380-b (e.g., indicated by portion 425-c), and the interface block 245-c may transmit alarm signaling 415 indicating the fourth alarm type based on identifying the error. In some examples, the interface block 245-c may reset the counter 380-b in response to identifying the error or transmitting the alarm signaling 415, for example, by resetting portions 425-a-1 and 425-b-1 (e.g., and portion 425-c).

[0091] In response to receiving the alarm signaling 415 including an indication of an error associated with the counter 380-b (e.g., corresponding to the first row 405-a), the interface block 220-c may activate (e.g., add, allocate) a counter 385-b (e.g., a spare counter), which may be associated with (e.g., mapped to) one or more rows of the memory array 250-c that experienced the error of the counter 380-b. The counter 385-b may be located in a memory of the interface block 220-c, such as a volatile memory (e.g., SRAM), a latch, a content addressable memory (CAM), or a combination thereof. Additionally or alternatively, the counter 385-b may be located in a memory of the die 205 that is accessible by the interface block 220-c. Because the error may corrupt the information stored in the counter 380-b, whether the value of the counter 380-b satisfies one or more thresholds (e.g., the first threshold or the second threshold) may be unknown. Thus, in some examples, the interface block 220-c may transmit refresh signaling 420 to refresh one or more rows 405-a adjacent to the first row 405-a based on receiving the alarm signaling 415. For example, the refresh signaling 420 may include one or more sets of refresh commands for one or more rows 405-a that are not directly adjacent to the first row 405-a, plus the directly adjacent rows 405-a, such as if the alarm signaling 415 indicated the second alarm type. For example, if the interface block 220-c receives an indication of an error associated with the counter 380-b-4 corresponding to the row 405-a-4, the interface block 220-c may issue refresh commands for the row 405-a-2, the row 405-a-3, the row 405-a-5, and the row 405-a-6.

[0092] The interface block 220-c may use the counter 385-b (e.g., instead of or in addition to the counter 380-b) to track the number of access operations to the first row 405-a and may transmit refresh signaling to the interface block 245-c based on the value of the counter 385-b (e.g., based on comparing the value to one or more thresholds). For example, the counter 385-b may include a portion 425-a-2 that the interface block 220-c may use to determine whether the value of the counter 385-b satisfies a first threshold. If the value of the counter 385-b satisfies the first threshold, the interface block 220-c may transmit the refresh signaling 420, e.g., just as the interface block 220-c received the alarm signaling 415 indicating the first alarm type. For example, the interface block 220-c may include in the refresh signaling 420 a refresh command, such as to refresh a first number of rows 405-a adjacent to the first row 405-a. In addition, the counter 385-b may include a portion 425-b-2 that the interface block 220-c may use to determine whether the value of the counter 385-b satisfies a second threshold (e.g., is greater than the first threshold). If the value of the counter 385-b satisfies the second threshold, the interface block 220-c may transmit refresh signaling 420, e.g., as if the interface block 220-c received the alarm signaling 415 indicating the second alarm type. For example, the interface block 220-c may include in the refresh signaling 420 a second number of refresh commands greater than the first number, e.g., to refresh both adjacent and non-directly adjacent rows 405-a. In some examples, the counter 385-b may include a portion 425-c, e.g., to support identification of errors associated with the counter 385-b.

[0093] The counter 385-b may allow the interface block 220-c to transmit refresh signaling 420 independent of the counter 380-b. For example, the interface block 220-c may transmit refresh signaling based on the value of the counter 385-b satisfying the threshold when the value of the counter 380-b fails to satisfy the threshold, e.g., due to an error (e.g., a persistent error, a previous error) (e.g., for row hammer mitigation). In some examples, the interface block 220-c may deactivate (e.g., deallocate, remove) a relatively unused counter 385-b (e.g., a counter 385-b whose value fails to satisfy the threshold for a duration), e.g., to support reallocation of memory for the counter 385-b for other uses. For example, the counter 385-b may be activated, but the row 405-a associated with the counter 385-b may not have experienced enough access operations to cause the value of the counter 385-b to satisfy the threshold for a duration. Thus, interface block 220 - c may deactivate counter 385 - b , and system 400 may resume using counter 380 - b to detect row hammer attacks.

[0094] Figure 5An example of a process 500 is shown for supporting row hammer mitigation reliability in a stacked memory architecture according to examples disclosed herein. In some examples, the process 500 can be implemented by components of the system 100, the system 200, the interface architecture 300, or the system 400. For example, one or more aspects of the process 500 can be implemented by an interface block 220 (e.g., of the die 205). The process 500 can be an example of allocating a spare counter (e.g., the counter 385) in a system that can use the spare counter to improve the reliability of a row hammer mitigation procedure.

[0095] At 505, process 500 may include receiving error signaling (e.g., from interface block 245). Error signaling (e.g., alert signaling 415) may be in response to access signaling (e.g., an ACT command) transmitted by interface block 220. Error signaling may include indicating to interface block 220 an error associated with a counter (e.g., counter 380) that tracks the number of access operations (e.g., row activations) to a row (e.g., an address) of a memory array (e.g., memory array 250 of die 240). For example, error signaling may be associated with a particular row of the memory array whose corresponding counter in the memory has an error. In some examples, the timing of error signaling may be deterministic, such that interface block 220 may determine that error signaling corresponds to a row and counter. For example, error signaling may be transmitted to interface block 220 within a deterministic duration (e.g., a certain number of clock cycles, e.g., 13 command clock cycles) after access signaling is transmitted by interface block 220. Thus, the interface block 220 may determine the row whose error signaling indicates an associated counter for an error caused by access signaling issued to the row, such as the number of clock cycles before error signaling was received.

[0096] At 510, process 500 may include determining whether a spare counter is allocated (e.g., at interface block 220) for tracking access operations to the row. In some examples, if a spare counter is allocated for the row, process 500 may continue to 535 and end. For example, a spare counter may have been allocated for the row (e.g., may have been previously allocated) and no further action is taken. Alternatively, if a spare counter is not allocated for the row, process may continue to 515.

[0097] At 515, in some examples, process 500 may include transmitting refresh signaling (e.g., from interface block 220 to interface block 245) based on receiving error signaling. Because the error signaling indicates an error associated with a counter for a row, it is not possible to determine whether the true value of the counter indicates that row hammer mitigation is to be performed on one or more second rows that are adjacent to (e.g., adjacent to) the first row. Thus, in some examples, interface block 220 may transmit (e.g., to interface block 245) refresh signaling to refresh the one or more second rows adjacent to the first row (e.g., as a precautionary measure). In some examples, the one or more second rows may include at least four rows adjacent to the row. For example, the one or more second rows may include a second row adjacent to the row on both sides of the row and a row that is not directly adjacent to the row itself but is adjacent to the adjacent row (e.g., the one or more second rows may include the two rows that are physically closest to the row on each side of the row or some other number of rows on each side of the row).

[0098] At 520, process 500 may include determining whether resources (e.g., space in a memory) are available to allocate (e.g., activate) a backup counter (e.g., at interface block 220). If sufficient resources are available to allocate a backup counter, process 500 may continue to 530. If insufficient resources are available to allocate a backup counter, process 500 may continue to 525.

[0099] At 525, process 500 may include allocating resources (e.g., content addressable memory (CAM) entries, a portion of volatile memory, one or more latches) for the backup counter. In some examples, the number of resources for the backup counter at interface block 220 (e.g., or die 205 including interface block 220) may be limited (e.g., less than a second number of resources for the counter at interface block 245). Thus, in order to allocate sufficient resources to the backup counter, interface block 220 may remove (e.g., deallocate, reallocate) other resources (e.g., other backup counters, other CAM entries) from a certain number of resources. Interface block 220 may determine which entry (e.g., or entries) to remove based on a policy (e.g., a least recently used (LRU) policy) in which the least recently used entry is removed to free up resources for the backup counter. Other policies for selecting reallocation of resources for the backup counter may be implemented.

[0100] At 530, process 500 may include allocating a standby counter to track (e.g., count) access activations of a row. For example, interface block 220 may allocate (e.g., activate) a portion of a memory array (e.g., of die 205) for the standby counter. The resources for the standby counter may be the resources allocated from 525. In some examples, interface block 220 may associate the standby counter with an address (e.g., a row) of one or more memory arrays (e.g., of die 240) associated with a counter (e.g., an error counter). For example, interface block 220 may associate the standby counter with a row for which error signaling has indicated an error of its associated counter. In some examples, to associate the standby counter with the row, interface block 220 may store the address of the row to, for example, indicate a pseudo channel used to access the row, a memory bank comprising the row, and a row address of the row. Interface block 220 may associate the standby counter with a storage address. In some examples, the portion of the memory array may operate as a CAM, a volatile memory (e.g., an SRAM), a latch, or some other type of memory. In some examples, if the portion of the memory array is operable as a CAM, the interface block 220 may activate the standby counter by adding an entry to the CAM, identified, for example, by the address of the row and whose contents are the value of the standby counter. After allocating the standby counter, the process may continue to 535 and end.

[0101] Figure 6 An example of a process 600 is shown to support reliability of row hammer mitigation in a stacked memory architecture according to examples disclosed herein. In some examples, the process 600 may be implemented by components of the system 100, the system 200, the interface architecture 300, or the system 400. For example, one or more aspects of the process 600 may be implemented by an interface block 220 (e.g., of the die 205). The process 600 may be an example of adjusting (e.g., manipulating, incrementing, resetting) a standby counter (e.g., counter 385, CAM entry) in a system, which may achieve reliability improvements for a row hammer mitigation procedure.

[0102] At 605, process 600 may include transmitting access signaling (eg, from interface block 220 to interface block 245). The access signaling may include a command (eg, an ACT command) to activate a row of a memory array (eg, of die 240).

[0103] At 610, based on the transport access signaling, process 600 may include determining whether a spare counter is allocated for the row (e.g., in a CAM of interface block 220, in die 205). If a spare counter is not allocated for the row, the process may continue to 630 and end. If a spare counter is allocated for the row, process 600 may continue to 615.

[0104] At 615, process 600 may include incrementing a standby counter based on the transmission access signaling at 605. For example, the standby counter may be used to count the number of activations of rows indicated by the access signaling, and interface block 220 may increment the standby counter to count the activations of rows caused by the transmission access signaling.

[0105] At 620, the process 600 may include reading the value of the backup counter and determining whether the value satisfies one or more thresholds (e.g., for row hammer mitigation). For example, the interface block 220 may compare the value to a first threshold, a second threshold (e.g., greater than the first threshold), or both and determine whether the value satisfies the first threshold, the second threshold, or both. If the value of the backup counter fails to satisfy the one or more thresholds, the process 600 may continue to 630 and end. If the value of the backup counter satisfies at least one of the one or more thresholds, the process 600 may continue to 625.

[0106] At 625, process 600 may include transmitting refresh signaling (e.g., via interface block 220 to interface block 245) and resetting one or more portions (e.g., or all portions) of the standby counter based on the value of the standby counter satisfying one or more thresholds. For example, the value of the counter may satisfy a first threshold. Thus, interface block 220 may transmit refresh signaling including refresh commands for a first number of rows (e.g., two rows) proximate to the row associated with the access signaling (e.g., two rows adjacent to the row, one row on each side) and reset a first portion (e.g., portion 425-a) of the standby counter. Additionally or alternatively, the value of the counter may satisfy a second threshold. Thus, interface block 220 may transmit refresh signaling including refresh commands for a second number of rows (e.g., four rows) proximate to the row associated with the access signaling (e.g., four rows adjacent to the row, two rows on each side) and may reset at least a second portion (e.g., portion 425-b) of the standby counter. Process 600 may continue to 630 and end.

[0107] Fig. 7A An example of a process 700-a is shown to support row hammer mitigation reliability in a stacked memory architecture according to examples disclosed herein. In some examples, the process 700-a can be implemented by components of the system 100, the system 200, the interface architecture 300, or the system 400. For example, one or more aspects of the process 700-a can be implemented by an interface block 220 (e.g., of the die 205). The process 700-a can be an example of a first process for deactivating (e.g., deleting, deallocating, removing) a standby counter (e.g., counter 385, CAM entry) from a system.

[0108] At 705, process 700-a may include receiving alarm signaling (e.g., from interface block 245, such as alarm signaling 415). The alarm signaling may indicate that a value of a counter associated with a row of a memory array (e.g., a counter at a memory array of die 240 that is different from a spare counter) meets a threshold. In some examples, interface block 220 may have (e.g., previously) received error signaling associated with a counter and assigned a spare counter to a row corresponding to the counter (e.g., as described in reference to FIG. 4 ). Figure 5 However, receipt of the alert signaling may indicate to the interface block 220 that the counter is no longer associated with the error (eg, the error may be a transient error) and thus the standby counter may be deactivated.

[0109] At 710, process 700-a may include determining whether a spare counter is allocated for the row (e.g., in a CAM of interface block 220, in die 205). If a spare counter is not allocated for the row, process 700-a may continue to 720 and end. If a spare counter is allocated for the row, process 700-a may continue to 715.

[0110] At 715, process 700-a may include deactivating the standby counter (e.g., based on receiving the alert signaling). In some examples, the standby counter may be associated with a portion of memory at die 205 and interface block 220 may deallocate the portion for the standby counter. In some examples, interface block 220 may further disassociate the standby counter from an address (e.g., row) of one or more memory arrays (e.g., at die 240) associated with the counter (e.g., at die 240). In some examples, interface block 220 may deallocate the portion and disassociate the standby counter from the address by deleting a CAM entry corresponding to the address and whose contents represent the value of the standby counter.

[0111] Figure 7B An example of a process 700-b is shown to support row hammer mitigation reliability in a stacked memory architecture according to examples disclosed herein. In some examples, the process 700-b may be implemented by components of the system 100, the system 200, the interface architecture 300, or the system 400. For example, one or more aspects of the process 700-b may be implemented by an interface block 220 (e.g., of the die 205). The process 700-b may be an example of a second process for deactivating (e.g., deleting, deallocating, removing) a standby counter (e.g., counter 385, CAM entry) from the system.

[0112] At 725, process 700-b may include transmitting (e.g., to interface block 245) access signaling. The access signaling may include a command (e.g., an ACT command) to activate a row of a memory array (e.g., of die 240). Based on transmitting the access signaling, interface block 220 may increment a value of a standby counter (e.g., as described in reference to FIG. 245). Figure 6 describe).

[0113] At 730, process 700-b may include determining whether a standby counter is assigned to the row (e.g., in a CAM of interface block 220, in die 205) and whether the value of the standby counter satisfies a threshold for a duration. If a standby counter is not assigned or the value of the standby counter satisfies (e.g., is greater than, greater than, or equal to) the threshold for the duration, process 700-b may continue to 740 and end. If a standby counter is assigned to the row and the value of the standby counter fails to satisfy the threshold for the duration, process 700-b may continue to 735.

[0114] At 735, process 700-b may include deactivating a standby counter (e.g., based on a failure of the value of the standby counter to satisfy a threshold for a duration). For example, a failure of the value of the standby counter to satisfy a threshold for a duration may indicate that an associated row is not frequently accessed. Thus, resources may be de-allocated for the standby counter and used for other purposes. In some instances, the standby counter may be associated with a portion of a memory at die 205 and interface block 220 may de-allocate the portion for the standby counter. In some instances, interface block 220 may further de-associate the standby counter from an address (e.g., a row) of one or more memory arrays (e.g., at die 240) associated with the counter (e.g., at die 240). In some instances, interface block 220 may de-allocate the portion and de-associate the standby counter from the address by deleting a CAM entry corresponding to the address and whose contents represent the value of the standby counter.

[0115] Figure 8 A block diagram 800 is shown of a logic die 820 (eg, die 205) that supports row hammer mitigation reliability in a stacked memory architecture according to examples disclosed herein. The logic die 820 may be a reference Figures 1 to 7B820 or its various components (e.g., interface block 220, circuitry of interface block 220) may be examples of means for performing various aspects of row hammer mitigation reliability in stacked memory architectures described herein. For example, logic die 820 (e.g., interface block 220) may include access signaling component 825, error signaling component 830, counter operation component 835, refresh signaling component 840, counter allocation component 845, alarm signaling component 850, or any combination thereof. Each of these components or components of its subcomponents (e.g., one or more processors, one or more memories) may communicate directly or indirectly with each other (e.g., via one or more buses).

[0116] The access signaling component 825 may be configured as or otherwise support means for transmitting first signaling (e.g., one or more signals, one or more indications) including a first command to activate a row of a memory array of the second semiconductor die from a first interface (e.g., interface block 220) of a first semiconductor die (e.g., logic die 820) to a second interface (e.g., interface block 245) of a second semiconductor die (e.g., array die, die 240) coupled to the first semiconductor die. The error signaling component 830 may be configured as or otherwise support means for receiving, at the first interface from the second interface, second signaling indicating an error associated with a first counter of the second semiconductor die for counting activations of rows of the memory array based on transmitting the first signaling. The counter operation component 835 may be configured as or otherwise support means for activating, at the first interface, a second counter of the first semiconductor die for counting activations of rows of the memory array based on receiving the second signaling indicating an error. The refresh signaling component 840 can be configured as or otherwise support means for transmitting third signaling from the first interface to the second interface including a second command to refresh one or more rows of the memory array different from the row based on the indication of the error or the value of the second counter.

[0117] In some examples, to support activation of the second counter, the counter allocation component 845 may be configured as or otherwise support means for allocating a portion of the second memory array of the first semiconductor die for the second counter. In some examples, to support activation of the second counter, the counter allocation component 845 may be configured as or otherwise support means for associating the second counter with a row.

[0118] In some examples, the access signaling component 825 may be configured or otherwise support means for transmitting a fourth signaling including a third command to activate a row from the first interface to the second interface after activating the second counter. In some examples, the counter operation component 835 may be configured or otherwise support means for incrementing the value of the second counter at the first interface based on transmitting the fourth signaling. In some examples, the refresh signaling component 840 may be configured or otherwise support means for transmitting a third signaling from the first interface to the second interface based on the value of the second counter satisfying one or more thresholds. In some examples, the counter operation component 835 may be configured or otherwise support means for resetting one or more portions of the second counter at the first interface based on transmitting the third signaling.

[0119] In some examples, the alarm signaling component 850 may be configured or otherwise support a means for receiving, at the first interface, from the second interface, a fourth signaling indicating that the value of the first counter satisfies a threshold value after receiving the second signaling. In some examples, the counter operation component 835 may be configured or otherwise support a means for deactivating the second counter at the first interface based on receiving the fourth signaling.

[0120] In some examples, the counter operation component 835 can be configured or otherwise support means for deactivating the second counter at the first interface based on the value of the second counter failing to satisfy a threshold value for a duration of time.

[0121] In some examples, the first interface can include a second counter.

[0122] In some examples, to support transmitting a third signaling, the refresh signaling component 840 may be configured to or otherwise support means for transmitting a third signaling in response to receiving a second signaling indicating an error, wherein the one or more rows of the memory array different from the rows include a first group of rows and a second group of rows different from the first group of rows based on the second signaling indicating the error.

[0123] In some examples, the described functionality of the logic die 820 or its various components may be supported by or may refer to at least a portion of at least one processor, where such at least one processor may include one or more processing elements (e.g., a controller, a microprocessor, a microcontroller, a digital signal processor, a state machine, discrete gate logic, discrete transistor logic, discrete hardware components, or any combination of one or more of such elements). In some examples, the described functionality of the logic die 820 or its various components may be implemented at least in part by instructions (e.g., stored in a memory, a non-transitory computer-readable medium) that are executable by such at least one processor.

[0124] Fig. 9 A block diagram 900 is shown of an array die 920 (eg, die 240) that supports row hammer mitigation reliability in a stacked memory architecture according to examples disclosed herein. The array die 920 may be a reference Figure 1 7. Array die 920 or its various components (e.g., interface block 245, circuitry of interface block 245) may be examples of means for performing various aspects of row hammer mitigation reliability in stacked memory architectures described herein. For example, array die 920 (e.g., interface block 245) may include access signaling component 925, error detection component 930, error signaling component 935, refresh signaling component 940, or any combination thereof. Components of each of these components or subcomponents thereof (e.g., one or more processors, one or more memories) may communicate directly or indirectly with each other (e.g., via one or more buses).

[0125] The access signaling component 925 may be configured as or otherwise support means for receiving, at a second interface (e.g., interface block 245) of a second semiconductor die (e.g., array die 920, die 240), from a first interface (e.g., interface block 220) of a first semiconductor die (e.g., logic die, die 205), first signaling including a first command to activate a row of a memory array of the second semiconductor die. The error detection component 930 may be configured as or otherwise support means for identifying, at the second interface, an error associated with a counter of the second semiconductor die for counting activations of rows of the memory array based on the first signaling. The error signaling component 935 may be configured as or otherwise support means for transmitting, from the second interface to the first interface, second signaling including an indication of the error based on identifying the error. The refresh signaling component 940 may be configured as or otherwise support means for receiving, from the first interface, third signaling including a second command to refresh one or more second rows of the memory array different from the row based on transmitting the second signaling.

[0126] In some examples, error detection component 930 can be configured or otherwise support means for resetting the value of the counter based on transmitting the second signaling to the first interface.

[0127] In some examples, refresh signaling component 940 can be configured or otherwise support means for receiving fourth signaling based on transmitting the second signaling and after receiving the third signaling including a third command to refresh one or more second rows when the value of the counter fails to satisfy a threshold.

[0128] In some examples, to support identifying errors, error detection component 930 may be configured or otherwise support means for identifying errors based on one or more parity bits of a counter, one or more error detection bits of a counter, a CRC operation based on an indication of a counter, or any combination thereof.

[0129] In some examples, the described functionality of array die 920 or its various components may be supported by or may refer to at least a portion of at least one processor, where such at least one processor may include one or more processing elements (e.g., a controller, a microprocessor, a microcontroller, a digital signal processor, a state machine, discrete gate logic, discrete transistor logic, discrete hardware components, or any combination of one or more of such elements). In some examples, the described functionality of array die 920 or its various components may be implemented at least in part by instructions (e.g., stored in a memory, a non-transitory computer-readable medium) that are executable by such at least one processor.

[0130] Fig.10 A flow chart illustrating a method 1000 for supporting row hammer mitigation reliability in a stacked memory architecture according to examples disclosed herein is shown. The operations of the method 1000 may be implemented by a logic die (e.g., die 205) or a component thereof (e.g., interface block 220) described herein. For example, the operations of the method 1000 may be implemented by reference to Figures 1 to 8 The logic die described herein performs. In some examples, the logic die may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the logic die may use dedicated hardware to perform aspects of the described functions.

[0131] At 1005, the method may include transmitting, from a first interface of a first semiconductor die to a second interface of a second semiconductor die coupled to the first semiconductor die, first signaling including a first command to activate a row of a memory array of the second semiconductor die. For example, the die 205 may include an interface block 220 that transmits an access signaling 410 (e.g., via bus 301) including an ACT command to an interface block 245 of the die 240. The access signaling 410 may instruct the interface block 245 to activate a row 405-a of a memory array 250 included in the die 240. In some examples, aspects of operation 1005 may be referred to as Figure 8 The access signaling component 825 described above performs the above.

[0132] At 1010, the method may include receiving, at the first interface from the second interface, second signaling indicating an error associated with a first counter of a second semiconductor die for counting activations of a row of a memory array based on transmitting the first signaling. For example, the interface block 220 may receive the alarm signaling 415 from the interface block 245 (e.g., via the bus 301) based on transmitting the access signaling. The alarm signaling 415 may indicate an error associated with the counter 380 of the die 240, wherein the counter 380 counts activations of the row 405-a of the memory array 250 at the die 240. In some examples, aspects of operation 1010 may be referred to as Figure 8 The error signaling component 830 described above performs the above.

[0133] At 1015, the method may include activating a second counter of the first semiconductor die for counting activations of a row of the memory array at the first interface based on receiving the second signaling indicating the error. For example, based on receiving the error signaling from the interface block 245, the interface block 220 may activate (e.g., allocate) a counter 385 (e.g., a spare counter) at the die 205, wherein the spare counter counts activations of the row 405-a of the memory array 250 at the die 240. In some examples, aspects of operation 1015 may be described with reference to Figure 8 The counter operation component 835 described above performs the above.

[0134] At 1020, the method may include transmitting, from the first interface to the second interface, third signaling including a second command to refresh one or more rows of the memory array different from the row based on the indication of the error or the value of the second counter. For example, the interface block 220 may transmit the refresh signaling 420 to the interface block 245 based on receiving the error signaling from the interface block 245. The refresh signaling 420 may include a refresh command to refresh one or more rows 405-a of the memory array 250 different from the row 405-a associated with the error signaling. In some examples, aspects of operation 1020 may be referred to as Figure 8 The refresh signaling component 840 described above performs.

[0135] In some examples, the apparatus described herein may perform one or several methods, such as method 1000. The apparatus may include features, circuitry, logic, means, or instructions (such as a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following aspects of the present disclosure, or any combination thereof:

[0136] Aspect 1: A method, apparatus, or non-transitory computer-readable medium comprising operations, features, circuit systems, logic, means, or instructions, or any combination thereof, for: transmitting, from a first interface of a first semiconductor die to a second interface of a second semiconductor die coupled to the first semiconductor die, first signaling comprising a first command to activate a row of a memory array of the second semiconductor die; receiving, at the first interface from the second interface based on transmitting the first signaling, second signaling indicating an error associated with a first counter of the second semiconductor die for counting activations of the rows of the memory array; activating, at the first interface, a second counter of the first semiconductor die for counting activations of the rows of the memory array based on receiving the second signaling indicating the error; and transmitting, from the first interface to the second interface, third signaling comprising a second command to refresh one or more rows of the memory array different from the row based on the indication of the error or the value of the second counter.

[0137] Aspect 2: A method, apparatus, or non-transitory computer-readable medium according to aspect 1, wherein activating the second counter includes operations, features, circuit systems, logic, means, or instructions or any combination thereof for: allocating a portion of a second memory array of the first semiconductor die to the second counter; and associating the second counter with the row.

[0138] Aspect 3: A method, apparatus or non-transitory computer-readable medium according to any one of Aspects 1 to 2, further comprising the following operations, features, circuit systems, logic, components or instructions or any combination thereof: transmitting a fourth signaling including a third command to activate the row from the first interface to the second interface after activating the second counter; incrementing the value of the second counter at the first interface based on transmitting the fourth signaling; transmitting the third signaling from the first interface to the second interface based on the value of the second counter satisfying one or more thresholds; and resetting one or more parts of the second counter at the first interface based on transmitting the third signaling.

[0139] Aspect 4: The method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 3, further comprising the following operations, features, circuit systems, logic, components, or instructions, or any combination thereof: receiving, at the first interface, a fourth signaling from the second interface indicating that the value of the first counter satisfies a threshold after receiving the second signaling; and deactivating the second counter at the first interface based on receiving the fourth signaling.

[0140] Aspect 5: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 4, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: deactivating the second counter at the first interface based on the value of the second counter failing to meet a threshold within a duration.

[0141] Fig.11 A flow chart illustrating a method 1100 for supporting row hammer mitigation reliability in a stacked memory architecture according to examples disclosed herein is shown. The operations of the method 1100 may be implemented by an array die (e.g., die 240) or a component thereof (e.g., interface block 245) described herein. For example, the operations of the method 1100 may be implemented by reference to Figure 1 7 and 9. In some examples, the array die may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the array die may use dedicated hardware to perform aspects of the described functions.

[0142] At 1105, the method may include receiving, at a second interface of the second semiconductor die, from a first interface of the first semiconductor die, first signaling including a first command to activate a row of a memory array of the second semiconductor die. For example, the die 240 may include an interface block 245 that receives access signaling 410 (e.g., via bus 301) including an ACT command from the interface block 220 of the die 205. The access signaling 410 may instruct the interface block 245 to activate a row 405-a of a memory array 250 included in the die 240. In some examples, aspects of operation 1105 may be referred to as Fig. 9 The access signaling component 925 described above performs the above.

[0143] At 1110, the method may include identifying, at the second interface based on the first signaling, an error associated with a counter of the second semiconductor die for counting activations of a row of a memory array. For example, the interface block 245 may identify an error associated with the counter 380 of the die 240 based on receiving the access signaling 410 from the interface block 220. The counter 380 may count activations of the row 405-a of the memory array 250 at the die 240. In some examples, aspects of operation 1110 may be referred to as Fig. 9 The error detection component 930 described above performs the above.

[0144] At 1115, the method may include transmitting, from the second interface to the first interface, second signaling including an indication of the error based on identifying the error. For example, the interface block 245 may transmit the alarm signaling 415 to the interface block 220 (e.g., via the bus 301) based on identifying the error associated with the counter 380. The alarm signaling 415 may include an indication of the identified error. In some examples, aspects of operation 1115 may be referred to as Fig. 9 The error signaling component 935 described above performs the above.

[0145] At 1120, the method may include receiving, from the first interface, third signaling including a second command to refresh one or more second rows of the memory array different from the row based on transmitting the second signaling. For example, the interface block 245 may receive the refresh signaling 420 from the interface block 220 based on transmitting the alert signaling 415 to the interface block 220. The refresh signaling 420 may include a refresh command to refresh one or more rows 405-a of the memory array 250 different from the row 405-a associated with the alert signaling. In some examples, aspects of operation 1120 may be described with reference to FIG. Fig. 9 The refresh signaling component 940 described above performs.

[0146] In some examples, the apparatus described herein may perform one or several methods, such as method 1100. The apparatus may include features, circuitry, logic, means, or instructions (such as a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following aspects of the present disclosure, or any combination thereof:

[0147] Aspect 6: A method, apparatus, or non-transitory computer-readable medium comprising operations, features, circuit systems, logic, components, or instructions or any combination thereof for: receiving first signaling including a first command to activate a row of a memory array of a second semiconductor die from a first interface of a first semiconductor die at a second interface of a second semiconductor die; identifying an error associated with a counter of the second semiconductor die for counting activations of the row of the memory array at the second interface based on the first signaling; transmitting second signaling including an indication of the error from the second interface to the first interface based on identifying the error; and receiving third signaling including a second command to refresh one or more second rows of the memory array different from the row based on transmitting the second signaling from the first interface.

[0148] It should be noted that the methods described herein describe possible implementations, and that the operations and steps may be rearranged or otherwise modified and other implementations are possible. Furthermore, portions from two or more of the methods may be combined.

[0149] An apparatus is described. The following provides an overview of aspects of the apparatus described herein:

[0150] Aspect 7: An apparatus (e.g., a system) comprising: a first semiconductor die comprising: a first interface, the first interface comprising a first circuit system operable to transmit access signaling; and a first counter; and a second semiconductor die coupled to the first semiconductor die, the second semiconductor die comprising: one or more memory arrays; a second counter; and a second interface coupled to the first interface, the one or more memory arrays, and the second counter, the second interface comprising a second circuit system operable to access the one or more memory arrays based on receiving the access signaling, wherein the first circuit system of the first interface is operable to transmit refresh signaling indicating refresh operations associated with one or more addresses of the one or more memory arrays to the second interface based on the number of access operations to the one or more memory arrays indicated by the first counter or by the second counter.

[0151] Aspect 8: An apparatus according to Aspect 7, wherein: the second circuit system of the second interface is further operable to transmit a first signaling to the first interface based on receiving the access signaling, the first signaling indicating an error associated with the second counter; and the first circuit system of the first interface is further operable to activate the first counter based on receiving the first signaling.

[0152] Aspect 9: An apparatus according to Aspect 8, wherein, in order to activate the first counter, the first circuit system of the first interface is operable to: allocate a portion of a memory array of the first semiconductor die to the first counter; and associate the first counter with addresses of the one or more memory arrays associated with the second counter.

[0153] Aspect 10: The apparatus of aspect 9, wherein the portion of the memory array is operable as a content addressable memory.

[0154] Aspect 11: An apparatus according to any one of Aspects 8 to 10, wherein the first circuit system of the first interface is further operable to: transmit a second access signaling to the second interface to the second interface after receiving the first signaling; increment the value of the first counter based on transmitting the second access signaling; transmit the refresh signaling to the second interface based on the value of the first counter satisfying one or more thresholds; and reset one or more parts of the first counter based on transmitting the refresh signaling.

[0155] Aspect 12: An apparatus according to any one of Aspects 8 to 11, wherein: the second circuit system of the second interface is further operable to transmit a second signaling to the first interface indicating that the value of the second counter meets a threshold after transmitting the first signaling; and the first circuit system of the first interface is further operable to deactivate the first counter based on receiving the second signaling.

[0156] Aspect 13: The apparatus of any of aspects 8 to 12, wherein the first circuitry of the first interface is further operable to: deactivate the first counter based on a value of the first counter failing to satisfy a threshold for a duration of time.

[0157] Aspect 14: An apparatus according to Aspect 13, wherein, in order to deactivate the first counter, the first circuit system of the first interface is operable to: de-allocate a portion of the memory array of the first semiconductor die for the first counter; and disassociate the first counter from the addresses of the one or more memory arrays associated with the second counter.

[0158] Aspect 15: The apparatus of any one of aspects 8 to 14, wherein the first circuitry of the first interface is further operable to: transmit the refresh signaling based on the first signaling indicating the error associated with the second counter.

[0159] Aspect 16: The apparatus of aspect 15, wherein the second circuitry of the second interface is further operable to: reset one or more portions of the second counter based on the error associated with the second counter.

[0160] Aspect 17: An apparatus according to any one of Aspects 7 to 16, wherein the second circuit system of the second interface is further operable to: read the value of the second counter based on accessing the one or more memory arrays; identify an error associated with the second counter based on reading the value of the second counter; and transmit a first signaling to the first interface based on identifying the error, the first signaling indicating the error associated with the second counter.

[0161] Aspect 18: An apparatus according to Aspect 17, wherein the second circuit system of the second interface is operable to identify the error based on one or more parity bits of the second counter, one or more error detection bits of the second counter, a cyclic redundancy check operation based on an indication of the second counter, or any combination thereof.

[0162] Aspect 19: The apparatus of any of aspects 7 to 18, wherein the first interface comprises the first counter of the first semiconductor die.

[0163] Aspect 20: The apparatus of any one of aspects 7 to 19, wherein the refresh operation is for a set of one or more addresses different from addresses of the one or more memory arrays associated with the first counter or the second counter.

[0164] An apparatus is described. The following provides an overview of aspects of the apparatus described herein:

[0165] Aspect 21: A device comprising: a first semiconductor die comprising a first interface, the first interface comprising a circuit system, the circuit system being operable to: transmit a first signaling comprising a first command to activate a row of a memory array of the second semiconductor die to a second interface of a second semiconductor die coupled to the first semiconductor die; receive a second signaling indicating an error associated with a first counter of the second semiconductor die for counting activations of the rows of the memory array from the second interface based on transmitting the first signaling; activate a second counter of the first semiconductor die for counting activations of the rows of the memory array based on receiving the second signaling indicating the error; and transmit a third signaling comprising a second command to refresh one or more rows of the memory array different from the row to the second interface based on a value of the second counter or the second signaling indicating the error.

[0166] Aspect 22: The apparatus of aspect 21, wherein to activate the second counter, the circuitry is operable to: allocate a portion of a second memory array of the first semiconductor die for the second counter; and associate the second counter with the row.

[0167] Aspect 23: An apparatus according to any one of Aspects 21 to 22, wherein the circuit system is further operable to: transmit a fourth signaling including a third command to activate the row to the second interface after activating the second counter; increment the value of the second counter based on transmitting the fourth signaling from the second interface; transmit the third signaling to the second interface based on the value of the second counter satisfying one or more thresholds; and reset one or more parts of the second counter based on transmitting the third signaling.

[0168] Aspect 24: An apparatus according to any one of Aspects 21 to 23, wherein the circuit system is further operable to: receive fourth signaling from the second interface indicating that the value of the first counter meets a threshold after receiving the second signaling; and deactivate the second counter based on receiving the fourth signaling.

[0169] Aspect 25: The apparatus of any of aspects 21 to 24, wherein the circuitry is further operable to: deactivate the second counter based on the value of the second counter failing to satisfy a threshold for a duration of time.

[0170] Aspect 26: The apparatus according to any one of aspects 21 to 25, wherein the first interface includes the second counter.

[0171] Aspect 27: An apparatus according to any one of Aspects 21 to 26, wherein the circuit system is operable to transmit the third signaling in response to receiving the second signaling indicating the error, and the one or more rows of the memory array different from the row include a first group of rows and a second group of rows different from the first group of rows based on the second signaling indicating the error.

[0172] An apparatus is described. The following provides an overview of aspects of the apparatus described herein:

[0173] Aspect 28: A device comprising: a second semiconductor die comprising a second interface, the second interface comprising a circuit system, the circuit system being operable to: receive first signaling including a first command to activate a row of a memory array of the second semiconductor die from a first interface of a first semiconductor die; identify an error associated with a counter of the second semiconductor die for counting activations of the row of the memory array based on the first signaling; transmit second signaling including an indication of the error to the first interface based on identifying the error; and receive third signaling including a second command to refresh one or more second rows of the memory array different from the row based on transmitting the second signaling from the first interface.

[0174] Aspect 29: The apparatus of aspect 28, wherein the circuit system is further operable to: reset the value of the counter based on transmitting the second signaling to the first interface.

[0175] Aspect 30: An apparatus according to any one of Aspects 28 to 29, wherein the circuit system is further operable to: based on transmitting the second signaling and after receiving the third signaling, receive a fourth signaling comprising a third command to refresh the one or more second rows when the value of the counter fails to meet a threshold.

[0176] Aspect 31: An apparatus according to any one of Aspects 28 to 30, wherein the circuit system is operable to identify the error based on one or more parity bits of the counter, one or more error detection bits of the counter, a cyclic redundancy check operation based on the indication of the counter, or any combination thereof.

[0177] The information and signals described herein may be represented using any of a variety of different techniques and technologies. For example, data, instructions, commands, information, signals, bits, or signaling symbols that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some figures may illustrate a signal as a single signal; however, a signal may represent a signal bus, where the bus may have various bit widths.

[0178] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports the flow of signals between the components. Components are considered to be in electronic communication (e.g., conductive contact, connection, coupling) with each other if there is any electrical path (e.g., conductive path) between the components that can support the flow of signals (e.g., charge, current, voltage) between the components at any time. At any given time, the conductive path between components that are in electronic communication (e.g., conductive contact, connection, coupling) with each other may be an open circuit or a closed circuit based on the operation of the device that includes the connected components. The conductive path between the connected components may be a direct conductive path between the components, or the conductive path between the connected components may be an indirect conductive path that may include intermediate components (e.g., switches, transistors, or other components). In some examples, the flow of signals between the connected components may be interrupted for a period of time, for example, using one or more intermediate components (e.g., switches or transistors).

[0179] The term "coupled" (e.g., "electrically coupled") may refer to a condition that transitions from an open-circuit relationship between components, where signals cannot currently be communicated between the components (e.g., via conductive paths), to a closed-circuit relationship between the components, where signals can be communicated between the components (e.g., via conductive paths). When a component, such as a controller, couples other components together, the component causes a change that allows signals to flow between the other components via conductive paths that previously did not allow signals to flow.

[0180] The term "isolation" refers to a relationship between components where a signal cannot currently flow between the components. Components are isolated from one another if an open circuit exists between the components. For example, when a switch positioned between two components is opened, the components separated by the switch are isolated from one another. When a controller isolates two components, the controller causes a change that prevents a signal from flowing between the components using a conductive path that previously permitted the signal to flow.

[0181] As used herein (including in the claims), the article "a" before a noun is open-ended and should be understood to refer to "at least one" of those nouns or "one or more" of those nouns. Therefore, the terms "one", "at least one", "one or more", and "at least one of one or more" are interchangeable. For example, if a claim recites "a component" that performs one or more functions, each of the individual functions may be performed by a single component or any combination of multiple components. Therefore, the term "a component" having a characteristic or performing a function may refer to "at least one of one or more components" having a specific characteristic or performing a specific function. The subsequent use of the term "the / said" to refer to a component introduced with the article "a" may refer to any or all of the one or more components. For example, a component introduced with the article "a" may be understood to mean "one or more components", and then referring to "the component" in the claim may be understood to be equivalent to referring to "at least one of one or more components".

[0182] The description set forth herein describes example configurations in conjunction with the accompanying drawings and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" rather than "preferred" or "superior to other examples". The "Detailed Description" includes specific details for providing an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some examples, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0183] In the accompanying drawings, similar components or features may have the same reference label. In addition, various components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label, regardless of the second reference label.

[0184] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored as one or more instructions (e.g., code) on a computer-readable medium or transmitted via a computer-readable medium. Other examples and implementations are within the scope of the present disclosure and the appended claims. For example, due to the nature of software, the functions described herein may be implemented using software executed by a processor, hardware, firmware, hardwiring, or a combination of any of these. Features implementing the functions may also be physically located at various locations, including being distributed so that portions of the functions are implemented at different physical locations.

[0185] For example, the various descriptive blocks and modules described in connection with the present disclosure may be implemented or executed with a processor designed to perform the functions described herein, such as a DSP, ASIC, FPGA, discrete gate logic, discrete transistor logic, discrete hardware components, other programmable logic devices, or any combination thereof. A processor may be an example of a microprocessor, a controller, a microcontroller, a state machine, or any type of processor. A processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0186] As used herein (including in the claims), "or" used in a list of items (e.g., a list of items preceded by a phrase such as "at least one of" or "one or more of") indicates an inclusive list, so that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Moreover, as used herein, the phrase "based on" should not be interpreted as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

[0187] Computer-readable media include both non-transitory computer storage media and communication media, including any media that facilitates the transfer of a computer program from one location to another. Non-transitory storage media may be any available media that can be accessed by a computer. For example, but not limited to, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk (CD) ROM or other optical disk storage devices, magnetic disk storage devices or other magnetic storage devices or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and can be accessed by a computer or processor. Moreover, any connection is appropriately referred to as computer-readable media. For example, if the software is transmitted from a website, server or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technology (such as infrared, radio and microwave), then coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technology (such as infrared, radio and microwave) are included in the definition of media. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0188] The description herein is provided to enable persons skilled in the art to make or use the present disclosure. Persons skilled in the art will appreciate various modifications of the present disclosure, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but should be given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A system comprising: A first semiconductor die comprising: a first interface comprising first circuitry operable to transmit access signaling; and a first counter; and a second semiconductor die coupled to the first semiconductor die, the second semiconductor die comprising: one or more memory arrays; a second counter; and a second interface coupled to the first interface, the one or more memory arrays, and the second counter, the second interface comprising second circuitry operable to access the one or more memory arrays based on receiving the access signaling, The first circuit system of the first interface is operable to transmit refresh signaling indicating a refresh operation associated with one or more addresses of the one or more memory arrays to the second interface based on the number of access operations to the one or more memory arrays indicated by the first counter or by the second counter.

2. The system of claim 1, wherein: The second circuitry of the second interface is further operable to transmit first signaling to the first interface based on receiving the access signaling, the first signaling indicating an error associated with the second counter; and The first circuitry of the first interface is further operable to activate the first counter based on receiving the first signaling.

3. The system of claim 2, wherein to activate the first counter, the first circuitry of the first interface is operable to: allocating a portion of a memory array of the first semiconductor die to the first counter; and The first counter is associated with an address of the one or more memory arrays associated with the second counter.

4. The system of claim 3, wherein the portion of the memory array is operable as a content addressable memory.

5. The system of claim 2, wherein the first circuitry of the first interface is further operable to: transmitting to the second interface a second access signaling to the second interface after receiving the first signaling; incrementing the value of the first counter based on transmitting the second access signaling; transmitting the refresh signaling to the second interface based on the value of the first counter satisfying one or more thresholds; and One or more portions of the first counter are reset based on transmitting the refresh signaling.

6. The system of claim 2, wherein: The second circuitry of the second interface is further operable to transmit, after transmitting the first signaling, second signaling to the first interface indicating that the value of the second counter satisfies a threshold; and The first circuitry of the first interface is further operable to deactivate the first counter based on receiving the second signaling.

7. The system of claim 2, wherein the first circuitry of the first interface is further operable to: The first counter is deactivated based on a value of the first counter failing to satisfy a threshold for a duration of time.

8. The system of claim 7, wherein to deactivate the first counter, the first circuitry of the first interface is operable to: de-allocating a portion of a memory array of the first semiconductor die from the first counter; and The first counter is disassociated from addresses of the one or more memory arrays associated with the second counter.

9. The system of claim 2, wherein the first circuitry of the first interface is further operable to: The refresh signaling is transmitted based on the first signaling indicating the error associated with the second counter.

10. The system of claim 9, wherein the second circuitry of the second interface is further operable to: One or more portions of the second counter are reset based on the error associated with the second counter.

11. The system of claim 1 , wherein the second circuitry of the second interface is further operable to: reading a value of the second counter based on accessing the one or more memory arrays; identifying an error associated with the second counter based on reading the value of the second counter; and Based on identifying the error, first signaling is transmitted to the first interface, the first signaling indicating the error associated with the second counter.

12. The system of claim 11, wherein the second circuit system of the second interface is operable to identify the error based on one or more parity bits of the second counter, one or more error detection bits of the second counter, a cyclic redundancy check operation based on an indication of the second counter, or any combination thereof.

13. The system of claim 1, wherein the first interface comprises the first counter of the first semiconductor die.

14. The system of claim 1, wherein the refresh operation is for a set of one or more addresses that is different from addresses of the one or more memory arrays associated with the first counter or the second counter.

15. An apparatus comprising: A first semiconductor die comprising a first interface, the first interface comprising circuitry operable to: transmitting, to a second interface of a second semiconductor die coupled to the first semiconductor die, first signaling including a first command to activate a row of a memory array of the second semiconductor die; receiving, from the second interface based on transmitting the first signaling, second signaling indicating an error associated with a first counter of the second semiconductor die for counting activations of the row of the memory array; activating a second counter of the first semiconductor die for counting activations of the row of the memory array based on receiving the second signaling indicating the error; and Third signaling including a second command to refresh one or more rows of the memory array different from the row is transmitted to the second interface based on the value of the second counter or the second signaling indicating the error.

16. The apparatus of claim 15, wherein to activate the second counter, the circuit system is operable to: allocating a portion of a second memory array of the first semiconductor die to the second counter; and The second counter is associated with the row.

17. The apparatus of claim 15, wherein the circuit system is further operable to: transmitting, to the second interface after activating the second counter, fourth signaling including a third command to activate the row; incrementing the value of the second counter based on transmitting the fourth signaling from the second interface; transmitting the third signaling to the second interface based on the value of the second counter satisfying one or more thresholds; and One or more portions of the second counter are reset based on transmitting the third signaling.

18. The apparatus of claim 15, wherein the circuit system is further operable to: receiving, after receiving the second signaling, fourth signaling from the second interface indicating that the value of the first counter satisfies a threshold; and The second counter is deactivated based on receiving the fourth signaling.

19. The apparatus of claim 15, wherein the circuit system is further operable to: The second counter is deactivated based on the value of the second counter failing to satisfy a threshold for a duration of time.

20. The apparatus of claim 15, wherein the first interface comprises the second counter.

21. An apparatus according to claim 15, wherein the circuit system is operable to transmit the third signaling in response to receiving the second signaling indicating the error, and the one or more rows of the memory array different from the row include a first group of rows and a second group of rows different from the first group of rows based on the second signaling indicating the error.

22. A method comprising: transmitting, from a first interface of a first semiconductor die to a second interface of a second semiconductor die coupled to the first semiconductor die, first signaling including a first command to activate a row of a memory array of the second semiconductor die; receiving, at the first interface from the second interface, second signaling indicating an error associated with a first counter of the second semiconductor die for counting activations of the row of the memory array based on transmitting the first signaling; activating, at the first interface, a second counter of the first semiconductor die for counting activations of the row of the memory array based on receiving the second signaling indicating the error; and Third signaling including a second command to refresh one or more rows of the memory array different from the row is transmitted from the first interface to the second interface based on the indication of the error or the value of the second counter.

23. The method of claim 22, wherein activating the second counter comprises: allocating a portion of a second memory array of the first semiconductor die to the second counter; and The second counter is associated with the row.

24. The method of claim 22, further comprising: transmitting, from the first interface to the second interface, fourth signaling including a third command to activate the row after activating the second counter; incrementing the value of the second counter at the first interface based on transmitting the fourth signaling; transmitting the third signaling from the first interface to the second interface based on the value of the second counter satisfying one or more thresholds; and One or more portions of the second counter are reset at the first interface based on transmitting the third signaling.

25. The method of claim 22, further comprising: receiving, at the first interface, from the second interface, fourth signaling indicating that the value of the first counter satisfies a threshold value after receiving the second signaling; and The second counter is deactivated at the first interface based on receiving the fourth signaling.

26. The method of claim 22, further comprising: The second counter is deactivated at the first interface based on the value of the second counter failing to satisfy a threshold for a duration of time.

27. An apparatus comprising: a second semiconductor die comprising a second interface, the second interface comprising circuitry operable to: receiving, from a first interface of a first semiconductor die, first signaling including a first command to activate a row of a memory array of the second semiconductor die; identifying, based on the first signaling, an error associated with a counter of the second semiconductor die used to count activations of the row of the memory array; transmitting, based on identifying the error, second signaling to the first interface including an indication of the error; and Based on transmitting the second signaling, third signaling including a second command to refresh one or more second rows of the memory array different from the row is received from the first interface.

28. The apparatus of claim 27, wherein the circuit system is further operable to: The value of the counter is reset based on transmitting the second signaling to the first interface.

29. The apparatus of claim 27, wherein the circuit system is further operable to: Based on transmitting the second signaling and after receiving the third signaling, receiving fourth signaling including a third command to refresh the one or more second rows when the value of the counter fails to satisfy a threshold.

30. The apparatus of claim 27, wherein the circuitry is operable to identify the error based on one or more parity bits of the counter, one or more error detection bits of the counter, a cyclic redundancy check operation based on an indication of the counter, or any combination thereof.

31. A method comprising: receiving, at a second interface of a second semiconductor die from a first interface of a first semiconductor die, first signaling including a first command to activate a row of a memory array of the second semiconductor die; identifying, at the second interface based on the first signaling, an error associated with a counter of the second semiconductor die used to count activations of the row of the memory array; transmitting, from the second interface to the first interface, second signaling including an indication of the error based on identifying the error; and Based on transmitting the second signaling, third signaling including a second command to refresh one or more second rows of the memory array different from the row is received from the first interface.

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